src/mesa/drivers/dri/i965/brw_compiler.h

   1 /*
   2  * Copyright © 2010 - 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #pragma once
  25
  26 #include <stdio.h>
  27 #include "brw_device_info.h"
  28 #include "main/mtypes.h"
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 struct ra_regs;
  35 struct nir_shader;
  36 struct brw_geometry_program;
  37 union gl_constant_value;
  38
  39 struct brw_compiler {
  40    const struct brw_device_info *devinfo;
  41
  42    struct {
  43       struct ra_regs *regs;
  44
  45       /**
  46        * Array of the ra classes for the unaligned contiguous register
  47        * block sizes used.
  48        */
  49       int *classes;
  50
  51       /**
  52        * Mapping for register-allocated objects in *regs to the first
  53        * GRF for that object.
  54        */
  55       uint8_t *ra_reg_to_grf;
  56    } vec4_reg_set;
  57
  58    struct {
  59       struct ra_regs *regs;
  60
  61       /**
  62        * Array of the ra classes for the unaligned contiguous register
  63        * block sizes used, indexed by register size.
  64        */
  65       int classes[16];
  66
  67       /**
  68        * Mapping from classes to ra_reg ranges.  Each of the per-size
  69        * classes corresponds to a range of ra_reg nodes.  This array stores
  70        * those ranges in the form of first ra_reg in each class and the
  71        * total number of ra_reg elements in the last array element.  This
  72        * way the range of the i'th class is given by:
  73        * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
  74        */
  75       int class_to_ra_reg_range[17];
  76
  77       /**
  78        * Mapping for register-allocated objects in *regs to the first
  79        * GRF for that object.
  80        */
  81       uint8_t *ra_reg_to_grf;
  82
  83       /**
  84        * ra class for the aligned pairs we use for PLN, which doesn't
  85        * appear in *classes.
  86        */
  87       int aligned_pairs_class;
  88    } fs_reg_sets[2];
  89
  90    void (*shader_debug_log)(void *, const char *str, ...) PRINTFLIKE(2, 3);
  91    void (*shader_perf_log)(void *, const char *str, ...) PRINTFLIKE(2, 3);
  92
  93    bool scalar_stage[MESA_SHADER_STAGES];
  94    struct gl_shader_compiler_options glsl_compiler_options[MESA_SHADER_STAGES];
  95 };
  96
  97 struct brw_compiler *
  98 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo);
  99
 100
 101 /**
 102  * Program key structures.
 103  *
 104  * When drawing, we look for the currently bound shaders in the program
 105  * cache.  This is essentially a hash table lookup, and these are the keys.
 106  *
 107  * Sometimes OpenGL features specified as state need to be simulated via
 108  * shader code, due to a mismatch between the API and the hardware.  This
 109  * is often referred to as "non-orthagonal state" or "NOS".  We store NOS
 110  * in the program key so it's considered when searching for a program.  If
 111  * we haven't seen a particular combination before, we have to recompile a
 112  * new specialized version.
 113  *
 114  * Shader compilation should not look up state in gl_context directly, but
 115  * instead use the copy in the program key.  This guarantees recompiles will
 116  * happen correctly.
 117  *
 118  *  @{
 119  */
 120
 121 enum PACKED gen6_gather_sampler_wa {
 122    WA_SIGN = 1,      /* whether we need to sign extend */
 123    WA_8BIT = 2,      /* if we have an 8bit format needing wa */
 124    WA_16BIT = 4,     /* if we have a 16bit format needing wa */
 125 };
 126
 127 /**
 128  * Sampler information needed by VS, WM, and GS program cache keys.
 129  */
 130 struct brw_sampler_prog_key_data {
 131    /**
 132     * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
 133     */
 134    uint16_t swizzles[MAX_SAMPLERS];
 135
 136    uint32_t gl_clamp_mask[3];
 137
 138    /**
 139     * For RG32F, gather4's channel select is broken.
 140     */
 141    uint32_t gather_channel_quirk_mask;
 142
 143    /**
 144     * Whether this sampler uses the compressed multisample surface layout.
 145     */
 146    uint32_t compressed_multisample_layout_mask;
 147
 148    /**
 149     * Whether this sampler is using 16x multisampling. If so fetching from
 150     * this sampler will be handled with a different instruction, ld2dms_w
 151     * instead of ld2dms.
 152     */
 153    uint32_t msaa_16;
 154
 155    /**
 156     * For Sandybridge, which shader w/a we need for gather quirks.
 157     */
 158    enum gen6_gather_sampler_wa gen6_gather_wa[MAX_SAMPLERS];
 159 };
 160
 161
 162 /** The program key for Vertex Shaders. */
 163 struct brw_vs_prog_key {
 164    unsigned program_string_id;
 165
 166    /*
 167     * Per-attribute workaround flags
 168     */
 169    uint8_t gl_attrib_wa_flags[VERT_ATTRIB_MAX];
 170
 171    bool copy_edgeflag:1;
 172
 173    bool clamp_vertex_color:1;
 174
 175    /**
 176     * How many user clipping planes are being uploaded to the vertex shader as
 177     * push constants.
 178     *
 179     * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
 180     * clip distances.
 181     */
 182    unsigned nr_userclip_plane_consts:4;
 183
 184    /**
 185     * For pre-Gen6 hardware, a bitfield indicating which texture coordinates
 186     * are going to be replaced with point coordinates (as a consequence of a
 187     * call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)).  Because
 188     * our SF thread requires exact matching between VS outputs and FS inputs,
 189     * these texture coordinates will need to be unconditionally included in
 190     * the VUE, even if they aren't written by the vertex shader.
 191     */
 192    uint8_t point_coord_replace;
 193
 194    struct brw_sampler_prog_key_data tex;
 195 };
 196
 197 /** The program key for Tessellation Control Shaders. */
 198 struct brw_tcs_prog_key
 199 {
 200    unsigned program_string_id;
 201
 202    GLenum tes_primitive_mode;
 203
 204    unsigned input_vertices;
 205
 206    /** A bitfield of per-patch outputs written. */
 207    uint32_t patch_outputs_written;
 208
 209    /** A bitfield of per-vertex outputs written. */
 210    uint64_t outputs_written;
 211
 212    struct brw_sampler_prog_key_data tex;
 213 };
 214
 215 /** The program key for Tessellation Evaluation Shaders. */
 216 struct brw_tes_prog_key
 217 {
 218    unsigned program_string_id;
 219
 220    /** A bitfield of per-patch inputs read. */
 221    uint32_t patch_inputs_read;
 222
 223    /** A bitfield of per-vertex inputs read. */
 224    uint64_t inputs_read;
 225
 226    struct brw_sampler_prog_key_data tex;
 227 };
 228
 229 /** The program key for Geometry Shaders. */
 230 struct brw_gs_prog_key
 231 {
 232    unsigned program_string_id;
 233
 234    struct brw_sampler_prog_key_data tex;
 235 };
 236
 237 /** The program key for Fragment/Pixel Shaders. */
 238 struct brw_wm_prog_key {
 239    uint8_t iz_lookup;
 240    bool stats_wm:1;
 241    bool flat_shade:1;
 242    bool persample_shading:1;
 243    bool persample_2x:1;
 244    unsigned nr_color_regions:5;
 245    bool replicate_alpha:1;
 246    bool render_to_fbo:1;
 247    bool clamp_fragment_color:1;
 248    bool compute_pos_offset:1;
 249    bool compute_sample_id:1;
 250    unsigned line_aa:2;
 251    bool high_quality_derivatives:1;
 252
 253    uint16_t drawable_height;
 254    uint64_t input_slots_valid;
 255    unsigned program_string_id;
 256    GLenum alpha_test_func;          /* < For Gen4/5 MRT alpha test */
 257    float alpha_test_ref;
 258
 259    struct brw_sampler_prog_key_data tex;
 260 };
 261
 262 struct brw_cs_prog_key {
 263    uint32_t program_string_id;
 264    struct brw_sampler_prog_key_data tex;
 265 };
 266
 267 /*
 268  * Image metadata structure as laid out in the shader parameter
 269  * buffer.  Entries have to be 16B-aligned for the vec4 back-end to be
 270  * able to use them.  That's okay because the padding and any unused
 271  * entries [most of them except when we're doing untyped surface
 272  * access] will be removed by the uniform packing pass.
 273  */
 274 #define BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET      0
 275 #define BRW_IMAGE_PARAM_OFFSET_OFFSET           4
 276 #define BRW_IMAGE_PARAM_SIZE_OFFSET             8
 277 #define BRW_IMAGE_PARAM_STRIDE_OFFSET           12
 278 #define BRW_IMAGE_PARAM_TILING_OFFSET           16
 279 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET        20
 280 #define BRW_IMAGE_PARAM_SIZE                    24
 281
 282 struct brw_image_param {
 283    /** Surface binding table index. */
 284    uint32_t surface_idx;
 285
 286    /** Offset applied to the X and Y surface coordinates. */
 287    uint32_t offset[2];
 288
 289    /** Surface X, Y and Z dimensions. */
 290    uint32_t size[3];
 291
 292    /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
 293     * pixels, vertical slice stride in pixels.
 294     */
 295    uint32_t stride[4];
 296
 297    /** Log2 of the tiling modulus in the X, Y and Z dimension. */
 298    uint32_t tiling[3];
 299
 300    /**
 301     * Right shift to apply for bit 6 address swizzling.  Two different
 302     * swizzles can be specified and will be applied one after the other.  The
 303     * resulting address will be:
 304     *
 305     *  addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
 306     *                              (addr >> swizzling[1])))
 307     *
 308     * Use \c 0xff if any of the swizzles is not required.
 309     */
 310    uint32_t swizzling[2];
 311 };
 312
 313 struct brw_stage_prog_data {
 314    struct {
 315       /** size of our binding table. */
 316       uint32_t size_bytes;
 317
 318       /** @{
 319        * surface indices for the various groups of surfaces
 320        */
 321       uint32_t pull_constants_start;
 322       uint32_t texture_start;
 323       uint32_t gather_texture_start;
 324       uint32_t ubo_start;
 325       uint32_t ssbo_start;
 326       uint32_t abo_start;
 327       uint32_t image_start;
 328       uint32_t shader_time_start;
 329       /** @} */
 330    } binding_table;
 331
 332    GLuint nr_params;       /**< number of float params/constants */
 333    GLuint nr_pull_params;
 334    unsigned nr_image_params;
 335
 336    unsigned curb_read_length;
 337    unsigned total_scratch;
 338    unsigned total_shared;
 339
 340    /**
 341     * Register where the thread expects to find input data from the URB
 342     * (typically uniforms, followed by vertex or fragment attributes).
 343     */
 344    unsigned dispatch_grf_start_reg;
 345
 346    bool use_alt_mode; /**< Use ALT floating point mode?  Otherwise, IEEE. */
 347
 348    /* Pointers to tracked values (only valid once
 349     * _mesa_load_state_parameters has been called at runtime).
 350     */
 351    const union gl_constant_value **param;
 352    const union gl_constant_value **pull_param;
 353
 354    /** Image metadata passed to the shader as uniforms. */
 355    struct brw_image_param *image_param;
 356 };
 357
 358 /* Data about a particular attempt to compile a program.  Note that
 359  * there can be many of these, each in a different GL state
 360  * corresponding to a different brw_wm_prog_key struct, with different
 361  * compiled programs.
 362  */
 363 struct brw_wm_prog_data {
 364    struct brw_stage_prog_data base;
 365
 366    GLuint num_varying_inputs;
 367
 368    GLuint dispatch_grf_start_reg_16;
 369    GLuint reg_blocks;
 370    GLuint reg_blocks_16;
 371
 372    struct {
 373       /** @{
 374        * surface indices the WM-specific surfaces
 375        */
 376       uint32_t render_target_start;
 377       /** @} */
 378    } binding_table;
 379
 380    uint8_t computed_depth_mode;
 381    bool computed_stencil;
 382
 383    bool early_fragment_tests;
 384    bool no_8;
 385    bool dual_src_blend;
 386    bool uses_pos_offset;
 387    bool uses_omask;
 388    bool uses_kill;
 389    bool pulls_bary;
 390    uint32_t prog_offset_16;
 391
 392    /**
 393     * Mask of which interpolation modes are required by the fragment shader.
 394     * Used in hardware setup on gen6+.
 395     */
 396    uint32_t barycentric_interp_modes;
 397
 398    /**
 399     * Map from gl_varying_slot to the position within the FS setup data
 400     * payload where the varying's attribute vertex deltas should be delivered.
 401     * For varying slots that are not used by the FS, the value is -1.
 402     */
 403    int urb_setup[VARYING_SLOT_MAX];
 404 };
 405
 406 struct brw_cs_prog_data {
 407    struct brw_stage_prog_data base;
 408
 409    GLuint dispatch_grf_start_reg_16;
 410    unsigned local_size[3];
 411    unsigned simd_size;
 412    bool uses_barrier;
 413    bool uses_num_work_groups;
 414    unsigned local_invocation_id_regs;
 415
 416    struct {
 417       /** @{
 418        * surface indices the CS-specific surfaces
 419        */
 420       uint32_t work_groups_start;
 421       /** @} */
 422    } binding_table;
 423 };
 424
 425 /**
 426  * Enum representing the i965-specific vertex results that don't correspond
 427  * exactly to any element of gl_varying_slot.  The values of this enum are
 428  * assigned such that they don't conflict with gl_varying_slot.
 429  */
 430 typedef enum
 431 {
 432    BRW_VARYING_SLOT_NDC = VARYING_SLOT_MAX,
 433    BRW_VARYING_SLOT_PAD,
 434    /**
 435     * Technically this is not a varying but just a placeholder that
 436     * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
 437     * builtin variable to be compiled correctly. see compile_sf_prog() for
 438     * more info.
 439     */
 440    BRW_VARYING_SLOT_PNTC,
 441    BRW_VARYING_SLOT_COUNT
 442 } brw_varying_slot;
 443
 444 /**
 445  * Data structure recording the relationship between the gl_varying_slot enum
 446  * and "slots" within the vertex URB entry (VUE).  A "slot" is defined as a
 447  * single octaword within the VUE (128 bits).
 448  *
 449  * Note that each BRW register contains 256 bits (2 octawords), so when
 450  * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
 451  * consecutive VUE slots.  When accessing the VUE in URB_INTERLEAVED mode (as
 452  * in a vertex shader), each register corresponds to a single VUE slot, since
 453  * it contains data for two separate vertices.
 454  */
 455 struct brw_vue_map {
 456    /**
 457     * Bitfield representing all varying slots that are (a) stored in this VUE
 458     * map, and (b) actually written by the shader.  Does not include any of
 459     * the additional varying slots defined in brw_varying_slot.
 460     */
 461    GLbitfield64 slots_valid;
 462
 463    /**
 464     * Is this VUE map for a separate shader pipeline?
 465     *
 466     * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
 467     * without the linker having a chance to dead code eliminate unused varyings.
 468     *
 469     * This means that we have to use a fixed slot layout, based on the output's
 470     * location field, rather than assigning slots in a compact contiguous block.
 471     */
 472    bool separate;
 473
 474    /**
 475     * Map from gl_varying_slot value to VUE slot.  For gl_varying_slots that are
 476     * not stored in a slot (because they are not written, or because
 477     * additional processing is applied before storing them in the VUE), the
 478     * value is -1.
 479     */
 480    signed char varying_to_slot[VARYING_SLOT_TESS_MAX];
 481
 482    /**
 483     * Map from VUE slot to gl_varying_slot value.  For slots that do not
 484     * directly correspond to a gl_varying_slot, the value comes from
 485     * brw_varying_slot.
 486     *
 487     * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
 488     */
 489    signed char slot_to_varying[VARYING_SLOT_TESS_MAX];
 490
 491    /**
 492     * Total number of VUE slots in use
 493     */
 494    int num_slots;
 495
 496    /**
 497     * Number of per-patch VUE slots. Only valid for tessellation control
 498     * shader outputs and tessellation evaluation shader inputs.
 499     */
 500    int num_per_patch_slots;
 501
 502    /**
 503     * Number of per-vertex VUE slots. Only valid for tessellation control
 504     * shader outputs and tessellation evaluation shader inputs.
 505     */
 506    int num_per_vertex_slots;
 507 };
 508
 509 void brw_print_vue_map(FILE *fp, const struct brw_vue_map *vue_map);
 510
 511 /**
 512  * Convert a VUE slot number into a byte offset within the VUE.
 513  */
 514 static inline GLuint brw_vue_slot_to_offset(GLuint slot)
 515 {
 516    return 16*slot;
 517 }
 518
 519 /**
 520  * Convert a vertex output (brw_varying_slot) into a byte offset within the
 521  * VUE.
 522  */
 523 static inline
 524 GLuint brw_varying_to_offset(const struct brw_vue_map *vue_map, GLuint varying)
 525 {
 526    return brw_vue_slot_to_offset(vue_map->varying_to_slot[varying]);
 527 }
 528
 529 void brw_compute_vue_map(const struct brw_device_info *devinfo,
 530                          struct brw_vue_map *vue_map,
 531                          GLbitfield64 slots_valid,
 532                          bool separate_shader);
 533
 534 void brw_compute_tess_vue_map(struct brw_vue_map *const vue_map,
 535                               const GLbitfield64 slots_valid,
 536                               const GLbitfield is_patch);
 537
 538 enum shader_dispatch_mode {
 539    DISPATCH_MODE_4X1_SINGLE = 0,
 540    DISPATCH_MODE_4X2_DUAL_INSTANCE = 1,
 541    DISPATCH_MODE_4X2_DUAL_OBJECT = 2,
 542    DISPATCH_MODE_SIMD8 = 3,
 543 };
 544
 545 /**
 546  * @defgroup Tessellator parameter enumerations.
 547  *
 548  * These correspond to the hardware values in 3DSTATE_TE, and are provided
 549  * as part of the tessellation evaluation shader.
 550  *
 551  * @{
 552  */
 553 enum brw_tess_partitioning {
 554    BRW_TESS_PARTITIONING_INTEGER         = 0,
 555    BRW_TESS_PARTITIONING_ODD_FRACTIONAL  = 1,
 556    BRW_TESS_PARTITIONING_EVEN_FRACTIONAL = 2,
 557 };
 558
 559 enum brw_tess_output_topology {
 560    BRW_TESS_OUTPUT_TOPOLOGY_POINT   = 0,
 561    BRW_TESS_OUTPUT_TOPOLOGY_LINE    = 1,
 562    BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW  = 2,
 563    BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW = 3,
 564 };
 565
 566 enum brw_tess_domain {
 567    BRW_TESS_DOMAIN_QUAD    = 0,
 568    BRW_TESS_DOMAIN_TRI     = 1,
 569    BRW_TESS_DOMAIN_ISOLINE = 2,
 570 };
 571 /** @} */
 572
 573 struct brw_vue_prog_data {
 574    struct brw_stage_prog_data base;
 575    struct brw_vue_map vue_map;
 576
 577    /** Should the hardware deliver input VUE handles for URB pull loads? */
 578    bool include_vue_handles;
 579
 580    GLuint urb_read_length;
 581    GLuint total_grf;
 582
 583    /* Used for calculating urb partitions.  In the VS, this is the size of the
 584     * URB entry used for both input and output to the thread.  In the GS, this
 585     * is the size of the URB entry used for output.
 586     */
 587    GLuint urb_entry_size;
 588
 589    enum shader_dispatch_mode dispatch_mode;
 590 };
 591
 592 struct brw_vs_prog_data {
 593    struct brw_vue_prog_data base;
 594
 595    GLbitfield64 inputs_read;
 596
 597    unsigned nr_attributes;
 598
 599    bool uses_vertexid;
 600    bool uses_instanceid;
 601    bool uses_basevertex;
 602    bool uses_baseinstance;
 603    bool uses_drawid;
 604 };
 605
 606 struct brw_tcs_prog_data
 607 {
 608    struct brw_vue_prog_data base;
 609
 610    /** Number vertices in output patch */
 611    int instances;
 612 };
 613
 614
 615 struct brw_tes_prog_data
 616 {
 617    struct brw_vue_prog_data base;
 618
 619    enum brw_tess_partitioning partitioning;
 620    enum brw_tess_output_topology output_topology;
 621    enum brw_tess_domain domain;
 622 };
 623
 624 struct brw_gs_prog_data
 625 {
 626    struct brw_vue_prog_data base;
 627
 628    /**
 629     * Size of an output vertex, measured in HWORDS (32 bytes).
 630     */
 631    unsigned output_vertex_size_hwords;
 632
 633    unsigned output_topology;
 634
 635    /**
 636     * Size of the control data (cut bits or StreamID bits), in hwords (32
 637     * bytes).  0 if there is no control data.
 638     */
 639    unsigned control_data_header_size_hwords;
 640
 641    /**
 642     * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
 643     * if the control data is StreamID bits, or
 644     * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
 645     * Ignored if control_data_header_size is 0.
 646     */
 647    unsigned control_data_format;
 648
 649    bool include_primitive_id;
 650
 651    /**
 652     * The number of vertices emitted, if constant - otherwise -1.
 653     */
 654    int static_vertex_count;
 655
 656    int invocations;
 657
 658    /**
 659     * Gen6 transform feedback enabled flag.
 660     */
 661    bool gen6_xfb_enabled;
 662
 663    /**
 664     * Gen6: Provoking vertex convention for odd-numbered triangles
 665     * in tristrips.
 666     */
 667    GLuint pv_first:1;
 668
 669    /**
 670     * Gen6: Number of varyings that are output to transform feedback.
 671     */
 672    GLuint num_transform_feedback_bindings:7; /* 0-BRW_MAX_SOL_BINDINGS */
 673
 674    /**
 675     * Gen6: Map from the index of a transform feedback binding table entry to the
 676     * gl_varying_slot that should be streamed out through that binding table
 677     * entry.
 678     */
 679    unsigned char transform_feedback_bindings[64 /* BRW_MAX_SOL_BINDINGS */];
 680
 681    /**
 682     * Gen6: Map from the index of a transform feedback binding table entry to the
 683     * swizzles that should be used when streaming out data through that
 684     * binding table entry.
 685     */
 686    unsigned char transform_feedback_swizzles[64 /* BRW_MAX_SOL_BINDINGS */];
 687 };
 688
 689
 690 /** @} */
 691
 692 /**
 693  * Compile a vertex shader.
 694  *
 695  * Returns the final assembly and the program's size.
 696  */
 697 const unsigned *
 698 brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
 699                void *mem_ctx,
 700                const struct brw_vs_prog_key *key,
 701                struct brw_vs_prog_data *prog_data,
 702                const struct nir_shader *shader,
 703                gl_clip_plane *clip_planes,
 704                bool use_legacy_snorm_formula,
 705                int shader_time_index,
 706                unsigned *final_assembly_size,
 707                char **error_str);
 708
 709 /**
 710  * Compile a tessellation control shader.
 711  *
 712  * Returns the final assembly and the program's size.
 713  */
 714 const unsigned *
 715 brw_compile_tcs(const struct brw_compiler *compiler,
 716                 void *log_data,
 717                 void *mem_ctx,
 718                 const struct brw_tcs_prog_key *key,
 719                 struct brw_tcs_prog_data *prog_data,
 720                 const struct nir_shader *nir,
 721                 int shader_time_index,
 722                 unsigned *final_assembly_size,
 723                 char **error_str);
 724
 725 /**
 726  * Compile a tessellation evaluation shader.
 727  *
 728  * Returns the final assembly and the program's size.
 729  */
 730 const unsigned *
 731 brw_compile_tes(const struct brw_compiler *compiler, void *log_data,
 732                 void *mem_ctx,
 733                 const struct brw_tes_prog_key *key,
 734                 struct brw_tes_prog_data *prog_data,
 735                 const struct nir_shader *shader,
 736                 struct gl_shader_program *shader_prog,
 737                 int shader_time_index,
 738                 unsigned *final_assembly_size,
 739                 char **error_str);
 740
 741 /**
 742  * Compile a vertex shader.
 743  *
 744  * Returns the final assembly and the program's size.
 745  */
 746 const unsigned *
 747 brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
 748                void *mem_ctx,
 749                const struct brw_gs_prog_key *key,
 750                struct brw_gs_prog_data *prog_data,
 751                const struct nir_shader *shader,
 752                struct gl_shader_program *shader_prog,
 753                int shader_time_index,
 754                unsigned *final_assembly_size,
 755                char **error_str);
 756
 757 /**
 758  * Compile a fragment shader.
 759  *
 760  * Returns the final assembly and the program's size.
 761  */
 762 const unsigned *
 763 brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
 764                void *mem_ctx,
 765                const struct brw_wm_prog_key *key,
 766                struct brw_wm_prog_data *prog_data,
 767                const struct nir_shader *shader,
 768                struct gl_program *prog,
 769                int shader_time_index8,
 770                int shader_time_index16,
 771                bool use_rep_send,
 772                unsigned *final_assembly_size,
 773                char **error_str);
 774
 775 /**
 776  * Compile a compute shader.
 777  *
 778  * Returns the final assembly and the program's size.
 779  */
 780 const unsigned *
 781 brw_compile_cs(const struct brw_compiler *compiler, void *log_data,
 782                void *mem_ctx,
 783                const struct brw_cs_prog_key *key,
 784                struct brw_cs_prog_data *prog_data,
 785                const struct nir_shader *shader,
 786                int shader_time_index,
 787                unsigned *final_assembly_size,
 788                char **error_str);
 789
 790 /**
 791  * Fill out local id payload for compute shader according to cs_prog_data.
 792  */
 793 void
 794 brw_cs_fill_local_id_payload(const struct brw_cs_prog_data *cs_prog_data,
 795                              void *buffer, uint32_t threads, uint32_t stride);
 796
 797 #ifdef __cplusplus
 798 } /* extern "C" */
 799 #endif