src/mesa/drivers/dri/i965/brw_compiler.h

   1 /*
   2  * Copyright © 2010 - 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #pragma once
  25
  26 #include <stdio.h>
  27 #include "brw_device_info.h"
  28 #include "main/mtypes.h"
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 struct ra_regs;
  35 struct nir_shader;
  36 struct brw_geometry_program;
  37 union gl_constant_value;
  38
  39 struct brw_compiler {
  40    const struct brw_device_info *devinfo;
  41
  42    struct {
  43       struct ra_regs *regs;
  44
  45       /**
  46        * Array of the ra classes for the unaligned contiguous register
  47        * block sizes used.
  48        */
  49       int *classes;
  50
  51       /**
  52        * Mapping for register-allocated objects in *regs to the first
  53        * GRF for that object.
  54        */
  55       uint8_t *ra_reg_to_grf;
  56    } vec4_reg_set;
  57
  58    struct {
  59       struct ra_regs *regs;
  60
  61       /**
  62        * Array of the ra classes for the unaligned contiguous register
  63        * block sizes used, indexed by register size.
  64        */
  65       int classes[16];
  66
  67       /**
  68        * Mapping from classes to ra_reg ranges.  Each of the per-size
  69        * classes corresponds to a range of ra_reg nodes.  This array stores
  70        * those ranges in the form of first ra_reg in each class and the
  71        * total number of ra_reg elements in the last array element.  This
  72        * way the range of the i'th class is given by:
  73        * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
  74        */
  75       int class_to_ra_reg_range[17];
  76
  77       /**
  78        * Mapping for register-allocated objects in *regs to the first
  79        * GRF for that object.
  80        */
  81       uint8_t *ra_reg_to_grf;
  82
  83       /**
  84        * ra class for the aligned pairs we use for PLN, which doesn't
  85        * appear in *classes.
  86        */
  87       int aligned_pairs_class;
  88    } fs_reg_sets[2];
  89
  90    void (*shader_debug_log)(void *, const char *str, ...) PRINTFLIKE(2, 3);
  91    void (*shader_perf_log)(void *, const char *str, ...) PRINTFLIKE(2, 3);
  92
  93    bool scalar_stage[MESA_SHADER_STAGES];
  94    struct gl_shader_compiler_options glsl_compiler_options[MESA_SHADER_STAGES];
  95 };
  96
  97
  98 /**
  99  * Program key structures.
 100  *
 101  * When drawing, we look for the currently bound shaders in the program
 102  * cache.  This is essentially a hash table lookup, and these are the keys.
 103  *
 104  * Sometimes OpenGL features specified as state need to be simulated via
 105  * shader code, due to a mismatch between the API and the hardware.  This
 106  * is often referred to as "non-orthagonal state" or "NOS".  We store NOS
 107  * in the program key so it's considered when searching for a program.  If
 108  * we haven't seen a particular combination before, we have to recompile a
 109  * new specialized version.
 110  *
 111  * Shader compilation should not look up state in gl_context directly, but
 112  * instead use the copy in the program key.  This guarantees recompiles will
 113  * happen correctly.
 114  *
 115  *  @{
 116  */
 117
 118 enum PACKED gen6_gather_sampler_wa {
 119    WA_SIGN = 1,      /* whether we need to sign extend */
 120    WA_8BIT = 2,      /* if we have an 8bit format needing wa */
 121    WA_16BIT = 4,     /* if we have a 16bit format needing wa */
 122 };
 123
 124 /**
 125  * Sampler information needed by VS, WM, and GS program cache keys.
 126  */
 127 struct brw_sampler_prog_key_data {
 128    /**
 129     * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
 130     */
 131    uint16_t swizzles[MAX_SAMPLERS];
 132
 133    uint32_t gl_clamp_mask[3];
 134
 135    /**
 136     * For RG32F, gather4's channel select is broken.
 137     */
 138    uint32_t gather_channel_quirk_mask;
 139
 140    /**
 141     * Whether this sampler uses the compressed multisample surface layout.
 142     */
 143    uint32_t compressed_multisample_layout_mask;
 144
 145    /**
 146     * Whether this sampler is using 16x multisampling. If so fetching from
 147     * this sampler will be handled with a different instruction, ld2dms_w
 148     * instead of ld2dms.
 149     */
 150    uint32_t msaa_16;
 151
 152    /**
 153     * For Sandybridge, which shader w/a we need for gather quirks.
 154     */
 155    enum gen6_gather_sampler_wa gen6_gather_wa[MAX_SAMPLERS];
 156 };
 157
 158
 159 /** The program key for Vertex Shaders. */
 160 struct brw_vs_prog_key {
 161    unsigned program_string_id;
 162
 163    /*
 164     * Per-attribute workaround flags
 165     */
 166    uint8_t gl_attrib_wa_flags[VERT_ATTRIB_MAX];
 167
 168    bool copy_edgeflag:1;
 169
 170    bool clamp_vertex_color:1;
 171
 172    /**
 173     * How many user clipping planes are being uploaded to the vertex shader as
 174     * push constants.
 175     *
 176     * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
 177     * clip distances.
 178     */
 179    unsigned nr_userclip_plane_consts:4;
 180
 181    /**
 182     * For pre-Gen6 hardware, a bitfield indicating which texture coordinates
 183     * are going to be replaced with point coordinates (as a consequence of a
 184     * call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)).  Because
 185     * our SF thread requires exact matching between VS outputs and FS inputs,
 186     * these texture coordinates will need to be unconditionally included in
 187     * the VUE, even if they aren't written by the vertex shader.
 188     */
 189    uint8_t point_coord_replace;
 190
 191    struct brw_sampler_prog_key_data tex;
 192 };
 193
 194 /** The program key for Tessellation Control Shaders. */
 195 struct brw_tcs_prog_key
 196 {
 197    unsigned program_string_id;
 198
 199    GLenum tes_primitive_mode;
 200
 201    unsigned input_vertices;
 202
 203    /** A bitfield of per-patch outputs written. */
 204    uint32_t patch_outputs_written;
 205
 206    /** A bitfield of per-vertex outputs written. */
 207    uint64_t outputs_written;
 208
 209    struct brw_sampler_prog_key_data tex;
 210 };
 211
 212 /** The program key for Tessellation Evaluation Shaders. */
 213 struct brw_tes_prog_key
 214 {
 215    unsigned program_string_id;
 216
 217    /** A bitfield of per-patch inputs read. */
 218    uint32_t patch_inputs_read;
 219
 220    /** A bitfield of per-vertex inputs read. */
 221    uint64_t inputs_read;
 222
 223    struct brw_sampler_prog_key_data tex;
 224 };
 225
 226 /** The program key for Geometry Shaders. */
 227 struct brw_gs_prog_key
 228 {
 229    unsigned program_string_id;
 230
 231    struct brw_sampler_prog_key_data tex;
 232 };
 233
 234 /** The program key for Fragment/Pixel Shaders. */
 235 struct brw_wm_prog_key {
 236    uint8_t iz_lookup;
 237    bool stats_wm:1;
 238    bool flat_shade:1;
 239    bool persample_shading:1;
 240    bool persample_2x:1;
 241    unsigned nr_color_regions:5;
 242    bool replicate_alpha:1;
 243    bool render_to_fbo:1;
 244    bool clamp_fragment_color:1;
 245    bool compute_pos_offset:1;
 246    bool compute_sample_id:1;
 247    unsigned line_aa:2;
 248    bool high_quality_derivatives:1;
 249
 250    uint16_t drawable_height;
 251    uint64_t input_slots_valid;
 252    unsigned program_string_id;
 253    GLenum alpha_test_func;          /* < For Gen4/5 MRT alpha test */
 254    float alpha_test_ref;
 255
 256    struct brw_sampler_prog_key_data tex;
 257 };
 258
 259 struct brw_cs_prog_key {
 260    uint32_t program_string_id;
 261    struct brw_sampler_prog_key_data tex;
 262 };
 263
 264 /*
 265  * Image metadata structure as laid out in the shader parameter
 266  * buffer.  Entries have to be 16B-aligned for the vec4 back-end to be
 267  * able to use them.  That's okay because the padding and any unused
 268  * entries [most of them except when we're doing untyped surface
 269  * access] will be removed by the uniform packing pass.
 270  */
 271 #define BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET      0
 272 #define BRW_IMAGE_PARAM_OFFSET_OFFSET           4
 273 #define BRW_IMAGE_PARAM_SIZE_OFFSET             8
 274 #define BRW_IMAGE_PARAM_STRIDE_OFFSET           12
 275 #define BRW_IMAGE_PARAM_TILING_OFFSET           16
 276 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET        20
 277 #define BRW_IMAGE_PARAM_SIZE                    24
 278
 279 struct brw_image_param {
 280    /** Surface binding table index. */
 281    uint32_t surface_idx;
 282
 283    /** Offset applied to the X and Y surface coordinates. */
 284    uint32_t offset[2];
 285
 286    /** Surface X, Y and Z dimensions. */
 287    uint32_t size[3];
 288
 289    /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
 290     * pixels, vertical slice stride in pixels.
 291     */
 292    uint32_t stride[4];
 293
 294    /** Log2 of the tiling modulus in the X, Y and Z dimension. */
 295    uint32_t tiling[3];
 296
 297    /**
 298     * Right shift to apply for bit 6 address swizzling.  Two different
 299     * swizzles can be specified and will be applied one after the other.  The
 300     * resulting address will be:
 301     *
 302     *  addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
 303     *                              (addr >> swizzling[1])))
 304     *
 305     * Use \c 0xff if any of the swizzles is not required.
 306     */
 307    uint32_t swizzling[2];
 308 };
 309
 310 struct brw_stage_prog_data {
 311    struct {
 312       /** size of our binding table. */
 313       uint32_t size_bytes;
 314
 315       /** @{
 316        * surface indices for the various groups of surfaces
 317        */
 318       uint32_t pull_constants_start;
 319       uint32_t texture_start;
 320       uint32_t gather_texture_start;
 321       uint32_t ubo_start;
 322       uint32_t ssbo_start;
 323       uint32_t abo_start;
 324       uint32_t image_start;
 325       uint32_t shader_time_start;
 326       /** @} */
 327    } binding_table;
 328
 329    GLuint nr_params;       /**< number of float params/constants */
 330    GLuint nr_pull_params;
 331    unsigned nr_image_params;
 332
 333    unsigned curb_read_length;
 334    unsigned total_scratch;
 335    unsigned total_shared;
 336
 337    /**
 338     * Register where the thread expects to find input data from the URB
 339     * (typically uniforms, followed by vertex or fragment attributes).
 340     */
 341    unsigned dispatch_grf_start_reg;
 342
 343    bool use_alt_mode; /**< Use ALT floating point mode?  Otherwise, IEEE. */
 344
 345    /* Pointers to tracked values (only valid once
 346     * _mesa_load_state_parameters has been called at runtime).
 347     */
 348    const union gl_constant_value **param;
 349    const union gl_constant_value **pull_param;
 350
 351    /** Image metadata passed to the shader as uniforms. */
 352    struct brw_image_param *image_param;
 353 };
 354
 355 /* Data about a particular attempt to compile a program.  Note that
 356  * there can be many of these, each in a different GL state
 357  * corresponding to a different brw_wm_prog_key struct, with different
 358  * compiled programs.
 359  */
 360 struct brw_wm_prog_data {
 361    struct brw_stage_prog_data base;
 362
 363    GLuint num_varying_inputs;
 364
 365    GLuint dispatch_grf_start_reg_16;
 366    GLuint reg_blocks;
 367    GLuint reg_blocks_16;
 368
 369    struct {
 370       /** @{
 371        * surface indices the WM-specific surfaces
 372        */
 373       uint32_t render_target_start;
 374       /** @} */
 375    } binding_table;
 376
 377    uint8_t computed_depth_mode;
 378    bool computed_stencil;
 379
 380    bool early_fragment_tests;
 381    bool no_8;
 382    bool dual_src_blend;
 383    bool uses_pos_offset;
 384    bool uses_omask;
 385    bool uses_kill;
 386    bool pulls_bary;
 387    uint32_t prog_offset_16;
 388
 389    /**
 390     * Mask of which interpolation modes are required by the fragment shader.
 391     * Used in hardware setup on gen6+.
 392     */
 393    uint32_t barycentric_interp_modes;
 394
 395    /**
 396     * Map from gl_varying_slot to the position within the FS setup data
 397     * payload where the varying's attribute vertex deltas should be delivered.
 398     * For varying slots that are not used by the FS, the value is -1.
 399     */
 400    int urb_setup[VARYING_SLOT_MAX];
 401 };
 402
 403 struct brw_cs_prog_data {
 404    struct brw_stage_prog_data base;
 405
 406    GLuint dispatch_grf_start_reg_16;
 407    unsigned local_size[3];
 408    unsigned simd_size;
 409    bool uses_barrier;
 410    bool uses_num_work_groups;
 411    unsigned local_invocation_id_regs;
 412
 413    struct {
 414       /** @{
 415        * surface indices the CS-specific surfaces
 416        */
 417       uint32_t work_groups_start;
 418       /** @} */
 419    } binding_table;
 420 };
 421
 422 /**
 423  * Enum representing the i965-specific vertex results that don't correspond
 424  * exactly to any element of gl_varying_slot.  The values of this enum are
 425  * assigned such that they don't conflict with gl_varying_slot.
 426  */
 427 typedef enum
 428 {
 429    BRW_VARYING_SLOT_NDC = VARYING_SLOT_MAX,
 430    BRW_VARYING_SLOT_PAD,
 431    /**
 432     * Technically this is not a varying but just a placeholder that
 433     * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
 434     * builtin variable to be compiled correctly. see compile_sf_prog() for
 435     * more info.
 436     */
 437    BRW_VARYING_SLOT_PNTC,
 438    BRW_VARYING_SLOT_COUNT
 439 } brw_varying_slot;
 440
 441 /**
 442  * Data structure recording the relationship between the gl_varying_slot enum
 443  * and "slots" within the vertex URB entry (VUE).  A "slot" is defined as a
 444  * single octaword within the VUE (128 bits).
 445  *
 446  * Note that each BRW register contains 256 bits (2 octawords), so when
 447  * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
 448  * consecutive VUE slots.  When accessing the VUE in URB_INTERLEAVED mode (as
 449  * in a vertex shader), each register corresponds to a single VUE slot, since
 450  * it contains data for two separate vertices.
 451  */
 452 struct brw_vue_map {
 453    /**
 454     * Bitfield representing all varying slots that are (a) stored in this VUE
 455     * map, and (b) actually written by the shader.  Does not include any of
 456     * the additional varying slots defined in brw_varying_slot.
 457     */
 458    GLbitfield64 slots_valid;
 459
 460    /**
 461     * Is this VUE map for a separate shader pipeline?
 462     *
 463     * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
 464     * without the linker having a chance to dead code eliminate unused varyings.
 465     *
 466     * This means that we have to use a fixed slot layout, based on the output's
 467     * location field, rather than assigning slots in a compact contiguous block.
 468     */
 469    bool separate;
 470
 471    /**
 472     * Map from gl_varying_slot value to VUE slot.  For gl_varying_slots that are
 473     * not stored in a slot (because they are not written, or because
 474     * additional processing is applied before storing them in the VUE), the
 475     * value is -1.
 476     */
 477    signed char varying_to_slot[VARYING_SLOT_TESS_MAX];
 478
 479    /**
 480     * Map from VUE slot to gl_varying_slot value.  For slots that do not
 481     * directly correspond to a gl_varying_slot, the value comes from
 482     * brw_varying_slot.
 483     *
 484     * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
 485     */
 486    signed char slot_to_varying[VARYING_SLOT_TESS_MAX];
 487
 488    /**
 489     * Total number of VUE slots in use
 490     */
 491    int num_slots;
 492
 493    /**
 494     * Number of per-patch VUE slots. Only valid for tessellation control
 495     * shader outputs and tessellation evaluation shader inputs.
 496     */
 497    int num_per_patch_slots;
 498
 499    /**
 500     * Number of per-vertex VUE slots. Only valid for tessellation control
 501     * shader outputs and tessellation evaluation shader inputs.
 502     */
 503    int num_per_vertex_slots;
 504 };
 505
 506 void brw_print_vue_map(FILE *fp, const struct brw_vue_map *vue_map);
 507
 508 /**
 509  * Convert a VUE slot number into a byte offset within the VUE.
 510  */
 511 static inline GLuint brw_vue_slot_to_offset(GLuint slot)
 512 {
 513    return 16*slot;
 514 }
 515
 516 /**
 517  * Convert a vertex output (brw_varying_slot) into a byte offset within the
 518  * VUE.
 519  */
 520 static inline
 521 GLuint brw_varying_to_offset(const struct brw_vue_map *vue_map, GLuint varying)
 522 {
 523    return brw_vue_slot_to_offset(vue_map->varying_to_slot[varying]);
 524 }
 525
 526 void brw_compute_vue_map(const struct brw_device_info *devinfo,
 527                          struct brw_vue_map *vue_map,
 528                          GLbitfield64 slots_valid,
 529                          bool separate_shader);
 530
 531 void brw_compute_tess_vue_map(struct brw_vue_map *const vue_map,
 532                               const GLbitfield64 slots_valid,
 533                               const GLbitfield is_patch);
 534
 535 enum shader_dispatch_mode {
 536    DISPATCH_MODE_4X1_SINGLE = 0,
 537    DISPATCH_MODE_4X2_DUAL_INSTANCE = 1,
 538    DISPATCH_MODE_4X2_DUAL_OBJECT = 2,
 539    DISPATCH_MODE_SIMD8 = 3,
 540 };
 541
 542 /**
 543  * @defgroup Tessellator parameter enumerations.
 544  *
 545  * These correspond to the hardware values in 3DSTATE_TE, and are provided
 546  * as part of the tessellation evaluation shader.
 547  *
 548  * @{
 549  */
 550 enum brw_tess_partitioning {
 551    BRW_TESS_PARTITIONING_INTEGER         = 0,
 552    BRW_TESS_PARTITIONING_ODD_FRACTIONAL  = 1,
 553    BRW_TESS_PARTITIONING_EVEN_FRACTIONAL = 2,
 554 };
 555
 556 enum brw_tess_output_topology {
 557    BRW_TESS_OUTPUT_TOPOLOGY_POINT   = 0,
 558    BRW_TESS_OUTPUT_TOPOLOGY_LINE    = 1,
 559    BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW  = 2,
 560    BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW = 3,
 561 };
 562
 563 enum brw_tess_domain {
 564    BRW_TESS_DOMAIN_QUAD    = 0,
 565    BRW_TESS_DOMAIN_TRI     = 1,
 566    BRW_TESS_DOMAIN_ISOLINE = 2,
 567 };
 568 /** @} */
 569
 570 struct brw_vue_prog_data {
 571    struct brw_stage_prog_data base;
 572    struct brw_vue_map vue_map;
 573
 574    /** Should the hardware deliver input VUE handles for URB pull loads? */
 575    bool include_vue_handles;
 576
 577    GLuint urb_read_length;
 578    GLuint total_grf;
 579
 580    /* Used for calculating urb partitions.  In the VS, this is the size of the
 581     * URB entry used for both input and output to the thread.  In the GS, this
 582     * is the size of the URB entry used for output.
 583     */
 584    GLuint urb_entry_size;
 585
 586    enum shader_dispatch_mode dispatch_mode;
 587 };
 588
 589 struct brw_vs_prog_data {
 590    struct brw_vue_prog_data base;
 591
 592    GLbitfield64 inputs_read;
 593
 594    unsigned nr_attributes;
 595
 596    bool uses_vertexid;
 597    bool uses_instanceid;
 598    bool uses_basevertex;
 599    bool uses_baseinstance;
 600    bool uses_drawid;
 601 };
 602
 603 struct brw_tcs_prog_data
 604 {
 605    struct brw_vue_prog_data base;
 606
 607    /** Number vertices in output patch */
 608    int instances;
 609 };
 610
 611
 612 struct brw_tes_prog_data
 613 {
 614    struct brw_vue_prog_data base;
 615
 616    enum brw_tess_partitioning partitioning;
 617    enum brw_tess_output_topology output_topology;
 618    enum brw_tess_domain domain;
 619 };
 620
 621 struct brw_gs_prog_data
 622 {
 623    struct brw_vue_prog_data base;
 624
 625    /**
 626     * Size of an output vertex, measured in HWORDS (32 bytes).
 627     */
 628    unsigned output_vertex_size_hwords;
 629
 630    unsigned output_topology;
 631
 632    /**
 633     * Size of the control data (cut bits or StreamID bits), in hwords (32
 634     * bytes).  0 if there is no control data.
 635     */
 636    unsigned control_data_header_size_hwords;
 637
 638    /**
 639     * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
 640     * if the control data is StreamID bits, or
 641     * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
 642     * Ignored if control_data_header_size is 0.
 643     */
 644    unsigned control_data_format;
 645
 646    bool include_primitive_id;
 647
 648    /**
 649     * The number of vertices emitted, if constant - otherwise -1.
 650     */
 651    int static_vertex_count;
 652
 653    int invocations;
 654
 655    /**
 656     * Gen6 transform feedback enabled flag.
 657     */
 658    bool gen6_xfb_enabled;
 659
 660    /**
 661     * Gen6: Provoking vertex convention for odd-numbered triangles
 662     * in tristrips.
 663     */
 664    GLuint pv_first:1;
 665
 666    /**
 667     * Gen6: Number of varyings that are output to transform feedback.
 668     */
 669    GLuint num_transform_feedback_bindings:7; /* 0-BRW_MAX_SOL_BINDINGS */
 670
 671    /**
 672     * Gen6: Map from the index of a transform feedback binding table entry to the
 673     * gl_varying_slot that should be streamed out through that binding table
 674     * entry.
 675     */
 676    unsigned char transform_feedback_bindings[64 /* BRW_MAX_SOL_BINDINGS */];
 677
 678    /**
 679     * Gen6: Map from the index of a transform feedback binding table entry to the
 680     * swizzles that should be used when streaming out data through that
 681     * binding table entry.
 682     */
 683    unsigned char transform_feedback_swizzles[64 /* BRW_MAX_SOL_BINDINGS */];
 684 };
 685
 686
 687 /** @} */
 688
 689 /**
 690  * Compile a vertex shader.
 691  *
 692  * Returns the final assembly and the program's size.
 693  */
 694 const unsigned *
 695 brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
 696                void *mem_ctx,
 697                const struct brw_vs_prog_key *key,
 698                struct brw_vs_prog_data *prog_data,
 699                const struct nir_shader *shader,
 700                gl_clip_plane *clip_planes,
 701                bool use_legacy_snorm_formula,
 702                int shader_time_index,
 703                unsigned *final_assembly_size,
 704                char **error_str);
 705
 706 /**
 707  * Compile a tessellation control shader.
 708  *
 709  * Returns the final assembly and the program's size.
 710  */
 711 const unsigned *
 712 brw_compile_tcs(const struct brw_compiler *compiler,
 713                 void *log_data,
 714                 void *mem_ctx,
 715                 const struct brw_tcs_prog_key *key,
 716                 struct brw_tcs_prog_data *prog_data,
 717                 const struct nir_shader *nir,
 718                 int shader_time_index,
 719                 unsigned *final_assembly_size,
 720                 char **error_str);
 721
 722 /**
 723  * Compile a tessellation evaluation shader.
 724  *
 725  * Returns the final assembly and the program's size.
 726  */
 727 const unsigned *
 728 brw_compile_tes(const struct brw_compiler *compiler, void *log_data,
 729                 void *mem_ctx,
 730                 const struct brw_tes_prog_key *key,
 731                 struct brw_tes_prog_data *prog_data,
 732                 const struct nir_shader *shader,
 733                 struct gl_shader_program *shader_prog,
 734                 int shader_time_index,
 735                 unsigned *final_assembly_size,
 736                 char **error_str);
 737
 738 /**
 739  * Compile a vertex shader.
 740  *
 741  * Returns the final assembly and the program's size.
 742  */
 743 const unsigned *
 744 brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
 745                void *mem_ctx,
 746                const struct brw_gs_prog_key *key,
 747                struct brw_gs_prog_data *prog_data,
 748                const struct nir_shader *shader,
 749                struct gl_shader_program *shader_prog,
 750                int shader_time_index,
 751                unsigned *final_assembly_size,
 752                char **error_str);
 753
 754 /**
 755  * Compile a fragment shader.
 756  *
 757  * Returns the final assembly and the program's size.
 758  */
 759 const unsigned *
 760 brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
 761                void *mem_ctx,
 762                const struct brw_wm_prog_key *key,
 763                struct brw_wm_prog_data *prog_data,
 764                const struct nir_shader *shader,
 765                struct gl_program *prog,
 766                int shader_time_index8,
 767                int shader_time_index16,
 768                bool use_rep_send,
 769                unsigned *final_assembly_size,
 770                char **error_str);
 771
 772 /**
 773  * Compile a compute shader.
 774  *
 775  * Returns the final assembly and the program's size.
 776  */
 777 const unsigned *
 778 brw_compile_cs(const struct brw_compiler *compiler, void *log_data,
 779                void *mem_ctx,
 780                const struct brw_cs_prog_key *key,
 781                struct brw_cs_prog_data *prog_data,
 782                const struct nir_shader *shader,
 783                int shader_time_index,
 784                unsigned *final_assembly_size,
 785                char **error_str);
 786
 787 /**
 788  * Fill out local id payload for compute shader according to cs_prog_data.
 789  */
 790 void
 791 brw_cs_fill_local_id_payload(const struct brw_cs_prog_data *cs_prog_data,
 792                              void *buffer, uint32_t threads, uint32_t stride);
 793
 794 #ifdef __cplusplus
 795 } /* extern "C" */
 796 #endif