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27 #include "brw_device_info.h"
28 #include "main/mtypes.h"
36 struct brw_geometry_program
;
37 union gl_constant_value
;
40 const struct brw_device_info
*devinfo
;
46 * Array of the ra classes for the unaligned contiguous register
52 * Mapping for register-allocated objects in *regs to the first
53 * GRF for that object.
55 uint8_t *ra_reg_to_grf
;
62 * Array of the ra classes for the unaligned contiguous register
63 * block sizes used, indexed by register size.
68 * Mapping from classes to ra_reg ranges. Each of the per-size
69 * classes corresponds to a range of ra_reg nodes. This array stores
70 * those ranges in the form of first ra_reg in each class and the
71 * total number of ra_reg elements in the last array element. This
72 * way the range of the i'th class is given by:
73 * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
75 int class_to_ra_reg_range
[17];
78 * Mapping for register-allocated objects in *regs to the first
79 * GRF for that object.
81 uint8_t *ra_reg_to_grf
;
84 * ra class for the aligned pairs we use for PLN, which doesn't
87 int aligned_pairs_class
;
90 void (*shader_debug_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
91 void (*shader_perf_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
93 bool scalar_stage
[MESA_SHADER_STAGES
];
94 struct gl_shader_compiler_options glsl_compiler_options
[MESA_SHADER_STAGES
];
97 * Apply workarounds for SIN and COS output range problems.
98 * This can negatively impact performance.
105 * Program key structures.
107 * When drawing, we look for the currently bound shaders in the program
108 * cache. This is essentially a hash table lookup, and these are the keys.
110 * Sometimes OpenGL features specified as state need to be simulated via
111 * shader code, due to a mismatch between the API and the hardware. This
112 * is often referred to as "non-orthagonal state" or "NOS". We store NOS
113 * in the program key so it's considered when searching for a program. If
114 * we haven't seen a particular combination before, we have to recompile a
115 * new specialized version.
117 * Shader compilation should not look up state in gl_context directly, but
118 * instead use the copy in the program key. This guarantees recompiles will
124 enum PACKED gen6_gather_sampler_wa
{
125 WA_SIGN
= 1, /* whether we need to sign extend */
126 WA_8BIT
= 2, /* if we have an 8bit format needing wa */
127 WA_16BIT
= 4, /* if we have a 16bit format needing wa */
131 * Sampler information needed by VS, WM, and GS program cache keys.
133 struct brw_sampler_prog_key_data
{
135 * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
137 uint16_t swizzles
[MAX_SAMPLERS
];
139 uint32_t gl_clamp_mask
[3];
142 * For RG32F, gather4's channel select is broken.
144 uint32_t gather_channel_quirk_mask
;
147 * Whether this sampler uses the compressed multisample surface layout.
149 uint32_t compressed_multisample_layout_mask
;
152 * Whether this sampler is using 16x multisampling. If so fetching from
153 * this sampler will be handled with a different instruction, ld2dms_w
159 * For Sandybridge, which shader w/a we need for gather quirks.
161 enum gen6_gather_sampler_wa gen6_gather_wa
[MAX_SAMPLERS
];
164 * Texture units that have a YUV image bound.
166 uint32_t y_u_v_image_mask
;
167 uint32_t y_uv_image_mask
;
168 uint32_t yx_xuxv_image_mask
;
172 /** The program key for Vertex Shaders. */
173 struct brw_vs_prog_key
{
174 unsigned program_string_id
;
177 * Per-attribute workaround flags
179 uint8_t gl_attrib_wa_flags
[VERT_ATTRIB_MAX
];
181 bool copy_edgeflag
:1;
183 bool clamp_vertex_color
:1;
186 * How many user clipping planes are being uploaded to the vertex shader as
189 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
192 unsigned nr_userclip_plane_consts
:4;
195 * For pre-Gen6 hardware, a bitfield indicating which texture coordinates
196 * are going to be replaced with point coordinates (as a consequence of a
197 * call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)). Because
198 * our SF thread requires exact matching between VS outputs and FS inputs,
199 * these texture coordinates will need to be unconditionally included in
200 * the VUE, even if they aren't written by the vertex shader.
202 uint8_t point_coord_replace
;
204 struct brw_sampler_prog_key_data tex
;
207 /** The program key for Tessellation Control Shaders. */
208 struct brw_tcs_prog_key
210 unsigned program_string_id
;
212 GLenum tes_primitive_mode
;
214 unsigned input_vertices
;
216 /** A bitfield of per-patch outputs written. */
217 uint32_t patch_outputs_written
;
219 /** A bitfield of per-vertex outputs written. */
220 uint64_t outputs_written
;
222 struct brw_sampler_prog_key_data tex
;
225 /** The program key for Tessellation Evaluation Shaders. */
226 struct brw_tes_prog_key
228 unsigned program_string_id
;
230 /** A bitfield of per-patch inputs read. */
231 uint32_t patch_inputs_read
;
233 /** A bitfield of per-vertex inputs read. */
234 uint64_t inputs_read
;
236 struct brw_sampler_prog_key_data tex
;
239 /** The program key for Geometry Shaders. */
240 struct brw_gs_prog_key
242 unsigned program_string_id
;
244 struct brw_sampler_prog_key_data tex
;
247 /** The program key for Fragment/Pixel Shaders. */
248 struct brw_wm_prog_key
{
252 unsigned nr_color_regions
:5;
253 bool replicate_alpha
:1;
254 bool clamp_fragment_color
:1;
255 bool persample_interp
:1;
256 bool multisample_fbo
:1;
258 bool high_quality_derivatives
:1;
259 bool force_dual_color_blend
:1;
261 uint16_t drawable_height
;
262 uint64_t input_slots_valid
;
263 unsigned program_string_id
;
264 GLenum alpha_test_func
; /* < For Gen4/5 MRT alpha test */
265 float alpha_test_ref
;
267 struct brw_sampler_prog_key_data tex
;
270 struct brw_cs_prog_key
{
271 uint32_t program_string_id
;
272 struct brw_sampler_prog_key_data tex
;
276 * Image metadata structure as laid out in the shader parameter
277 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
278 * able to use them. That's okay because the padding and any unused
279 * entries [most of them except when we're doing untyped surface
280 * access] will be removed by the uniform packing pass.
282 #define BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET 0
283 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 4
284 #define BRW_IMAGE_PARAM_SIZE_OFFSET 8
285 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 12
286 #define BRW_IMAGE_PARAM_TILING_OFFSET 16
287 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 20
288 #define BRW_IMAGE_PARAM_SIZE 24
290 struct brw_image_param
{
291 /** Surface binding table index. */
292 uint32_t surface_idx
;
294 /** Offset applied to the X and Y surface coordinates. */
297 /** Surface X, Y and Z dimensions. */
300 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
301 * pixels, vertical slice stride in pixels.
305 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
309 * Right shift to apply for bit 6 address swizzling. Two different
310 * swizzles can be specified and will be applied one after the other. The
311 * resulting address will be:
313 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
314 * (addr >> swizzling[1])))
316 * Use \c 0xff if any of the swizzles is not required.
318 uint32_t swizzling
[2];
321 struct brw_stage_prog_data
{
323 /** size of our binding table. */
327 * surface indices for the various groups of surfaces
329 uint32_t pull_constants_start
;
330 uint32_t texture_start
;
331 uint32_t gather_texture_start
;
335 uint32_t image_start
;
336 uint32_t shader_time_start
;
337 uint32_t plane_start
[3];
341 GLuint nr_params
; /**< number of float params/constants */
342 GLuint nr_pull_params
;
343 unsigned nr_image_params
;
345 unsigned curb_read_length
;
346 unsigned total_scratch
;
347 unsigned total_shared
;
350 * Register where the thread expects to find input data from the URB
351 * (typically uniforms, followed by vertex or fragment attributes).
353 unsigned dispatch_grf_start_reg
;
355 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
357 /* Pointers to tracked values (only valid once
358 * _mesa_load_state_parameters has been called at runtime).
360 const union gl_constant_value
**param
;
361 const union gl_constant_value
**pull_param
;
363 /** Image metadata passed to the shader as uniforms. */
364 struct brw_image_param
*image_param
;
367 /* Data about a particular attempt to compile a program. Note that
368 * there can be many of these, each in a different GL state
369 * corresponding to a different brw_wm_prog_key struct, with different
372 struct brw_wm_prog_data
{
373 struct brw_stage_prog_data base
;
375 GLuint num_varying_inputs
;
377 uint8_t reg_blocks_0
;
378 uint8_t reg_blocks_2
;
380 uint8_t dispatch_grf_start_reg_2
;
381 uint32_t prog_offset_2
;
385 * surface indices the WM-specific surfaces
387 uint32_t render_target_start
;
391 uint8_t computed_depth_mode
;
392 bool computed_stencil
;
394 bool early_fragment_tests
;
398 bool persample_dispatch
;
399 bool uses_pos_offset
;
404 bool uses_sample_mask
;
408 * Mask of which interpolation modes are required by the fragment shader.
409 * Used in hardware setup on gen6+.
411 uint32_t barycentric_interp_modes
;
414 * Mask of which FS inputs are marked flat by the shader source. This is
415 * needed for setting up 3DSTATE_SF/SBE.
417 uint32_t flat_inputs
;
420 * Map from gl_varying_slot to the position within the FS setup data
421 * payload where the varying's attribute vertex deltas should be delivered.
422 * For varying slots that are not used by the FS, the value is -1.
424 int urb_setup
[VARYING_SLOT_MAX
];
427 struct brw_push_const_block
{
428 unsigned dwords
; /* Dword count, not reg aligned */
430 unsigned size
; /* Bytes, register aligned */
433 struct brw_cs_prog_data
{
434 struct brw_stage_prog_data base
;
436 GLuint dispatch_grf_start_reg_16
;
437 unsigned local_size
[3];
441 bool uses_num_work_groups
;
442 unsigned local_invocation_id_regs
;
443 int thread_local_id_index
;
446 struct brw_push_const_block cross_thread
;
447 struct brw_push_const_block per_thread
;
448 struct brw_push_const_block total
;
453 * surface indices the CS-specific surfaces
455 uint32_t work_groups_start
;
461 * Enum representing the i965-specific vertex results that don't correspond
462 * exactly to any element of gl_varying_slot. The values of this enum are
463 * assigned such that they don't conflict with gl_varying_slot.
467 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
468 BRW_VARYING_SLOT_PAD
,
470 * Technically this is not a varying but just a placeholder that
471 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
472 * builtin variable to be compiled correctly. see compile_sf_prog() for
475 BRW_VARYING_SLOT_PNTC
,
476 BRW_VARYING_SLOT_COUNT
480 * Data structure recording the relationship between the gl_varying_slot enum
481 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
482 * single octaword within the VUE (128 bits).
484 * Note that each BRW register contains 256 bits (2 octawords), so when
485 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
486 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
487 * in a vertex shader), each register corresponds to a single VUE slot, since
488 * it contains data for two separate vertices.
492 * Bitfield representing all varying slots that are (a) stored in this VUE
493 * map, and (b) actually written by the shader. Does not include any of
494 * the additional varying slots defined in brw_varying_slot.
496 GLbitfield64 slots_valid
;
499 * Is this VUE map for a separate shader pipeline?
501 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
502 * without the linker having a chance to dead code eliminate unused varyings.
504 * This means that we have to use a fixed slot layout, based on the output's
505 * location field, rather than assigning slots in a compact contiguous block.
510 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
511 * not stored in a slot (because they are not written, or because
512 * additional processing is applied before storing them in the VUE), the
515 signed char varying_to_slot
[VARYING_SLOT_TESS_MAX
];
518 * Map from VUE slot to gl_varying_slot value. For slots that do not
519 * directly correspond to a gl_varying_slot, the value comes from
522 * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
524 signed char slot_to_varying
[VARYING_SLOT_TESS_MAX
];
527 * Total number of VUE slots in use
532 * Number of per-patch VUE slots. Only valid for tessellation control
533 * shader outputs and tessellation evaluation shader inputs.
535 int num_per_patch_slots
;
538 * Number of per-vertex VUE slots. Only valid for tessellation control
539 * shader outputs and tessellation evaluation shader inputs.
541 int num_per_vertex_slots
;
544 void brw_print_vue_map(FILE *fp
, const struct brw_vue_map
*vue_map
);
547 * Convert a VUE slot number into a byte offset within the VUE.
549 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
555 * Convert a vertex output (brw_varying_slot) into a byte offset within the
559 GLuint
brw_varying_to_offset(const struct brw_vue_map
*vue_map
, GLuint varying
)
561 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
564 void brw_compute_vue_map(const struct brw_device_info
*devinfo
,
565 struct brw_vue_map
*vue_map
,
566 GLbitfield64 slots_valid
,
567 bool separate_shader
);
569 void brw_compute_tess_vue_map(struct brw_vue_map
*const vue_map
,
570 const GLbitfield64 slots_valid
,
571 const GLbitfield is_patch
);
573 enum shader_dispatch_mode
{
574 DISPATCH_MODE_4X1_SINGLE
= 0,
575 DISPATCH_MODE_4X2_DUAL_INSTANCE
= 1,
576 DISPATCH_MODE_4X2_DUAL_OBJECT
= 2,
577 DISPATCH_MODE_SIMD8
= 3,
581 * @defgroup Tessellator parameter enumerations.
583 * These correspond to the hardware values in 3DSTATE_TE, and are provided
584 * as part of the tessellation evaluation shader.
588 enum brw_tess_partitioning
{
589 BRW_TESS_PARTITIONING_INTEGER
= 0,
590 BRW_TESS_PARTITIONING_ODD_FRACTIONAL
= 1,
591 BRW_TESS_PARTITIONING_EVEN_FRACTIONAL
= 2,
594 enum brw_tess_output_topology
{
595 BRW_TESS_OUTPUT_TOPOLOGY_POINT
= 0,
596 BRW_TESS_OUTPUT_TOPOLOGY_LINE
= 1,
597 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
= 2,
598 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
= 3,
601 enum brw_tess_domain
{
602 BRW_TESS_DOMAIN_QUAD
= 0,
603 BRW_TESS_DOMAIN_TRI
= 1,
604 BRW_TESS_DOMAIN_ISOLINE
= 2,
608 struct brw_vue_prog_data
{
609 struct brw_stage_prog_data base
;
610 struct brw_vue_map vue_map
;
612 /** Should the hardware deliver input VUE handles for URB pull loads? */
613 bool include_vue_handles
;
615 GLuint urb_read_length
;
618 uint32_t cull_distance_mask
;
620 /* Used for calculating urb partitions. In the VS, this is the size of the
621 * URB entry used for both input and output to the thread. In the GS, this
622 * is the size of the URB entry used for output.
624 GLuint urb_entry_size
;
626 enum shader_dispatch_mode dispatch_mode
;
629 struct brw_vs_prog_data
{
630 struct brw_vue_prog_data base
;
632 GLbitfield64 inputs_read
;
634 unsigned nr_attributes
;
635 unsigned nr_attribute_slots
;
638 bool uses_instanceid
;
639 bool uses_basevertex
;
640 bool uses_baseinstance
;
644 struct brw_tcs_prog_data
646 struct brw_vue_prog_data base
;
648 /** Number vertices in output patch */
653 struct brw_tes_prog_data
655 struct brw_vue_prog_data base
;
657 enum brw_tess_partitioning partitioning
;
658 enum brw_tess_output_topology output_topology
;
659 enum brw_tess_domain domain
;
662 struct brw_gs_prog_data
664 struct brw_vue_prog_data base
;
666 unsigned vertices_in
;
669 * Size of an output vertex, measured in HWORDS (32 bytes).
671 unsigned output_vertex_size_hwords
;
673 unsigned output_topology
;
676 * Size of the control data (cut bits or StreamID bits), in hwords (32
677 * bytes). 0 if there is no control data.
679 unsigned control_data_header_size_hwords
;
682 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
683 * if the control data is StreamID bits, or
684 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
685 * Ignored if control_data_header_size is 0.
687 unsigned control_data_format
;
689 bool include_primitive_id
;
692 * The number of vertices emitted, if constant - otherwise -1.
694 int static_vertex_count
;
699 * Gen6 transform feedback enabled flag.
701 bool gen6_xfb_enabled
;
704 * Gen6: Provoking vertex convention for odd-numbered triangles
710 * Gen6: Number of varyings that are output to transform feedback.
712 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
715 * Gen6: Map from the index of a transform feedback binding table entry to the
716 * gl_varying_slot that should be streamed out through that binding table
719 unsigned char transform_feedback_bindings
[64 /* BRW_MAX_SOL_BINDINGS */];
722 * Gen6: Map from the index of a transform feedback binding table entry to the
723 * swizzles that should be used when streaming out data through that
724 * binding table entry.
726 unsigned char transform_feedback_swizzles
[64 /* BRW_MAX_SOL_BINDINGS */];
732 struct brw_compiler
*
733 brw_compiler_create(void *mem_ctx
, const struct brw_device_info
*devinfo
);
736 * Compile a vertex shader.
738 * Returns the final assembly and the program's size.
741 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
743 const struct brw_vs_prog_key
*key
,
744 struct brw_vs_prog_data
*prog_data
,
745 const struct nir_shader
*shader
,
746 gl_clip_plane
*clip_planes
,
747 bool use_legacy_snorm_formula
,
748 int shader_time_index
,
749 unsigned *final_assembly_size
,
753 * Compile a tessellation control shader.
755 * Returns the final assembly and the program's size.
758 brw_compile_tcs(const struct brw_compiler
*compiler
,
761 const struct brw_tcs_prog_key
*key
,
762 struct brw_tcs_prog_data
*prog_data
,
763 const struct nir_shader
*nir
,
764 int shader_time_index
,
765 unsigned *final_assembly_size
,
769 * Compile a tessellation evaluation shader.
771 * Returns the final assembly and the program's size.
774 brw_compile_tes(const struct brw_compiler
*compiler
, void *log_data
,
776 const struct brw_tes_prog_key
*key
,
777 struct brw_tes_prog_data
*prog_data
,
778 const struct nir_shader
*shader
,
779 struct gl_shader_program
*shader_prog
,
780 int shader_time_index
,
781 unsigned *final_assembly_size
,
785 * Compile a vertex shader.
787 * Returns the final assembly and the program's size.
790 brw_compile_gs(const struct brw_compiler
*compiler
, void *log_data
,
792 const struct brw_gs_prog_key
*key
,
793 struct brw_gs_prog_data
*prog_data
,
794 const struct nir_shader
*shader
,
795 struct gl_shader_program
*shader_prog
,
796 int shader_time_index
,
797 unsigned *final_assembly_size
,
801 * Compile a fragment shader.
803 * Returns the final assembly and the program's size.
806 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
808 const struct brw_wm_prog_key
*key
,
809 struct brw_wm_prog_data
*prog_data
,
810 const struct nir_shader
*shader
,
811 struct gl_program
*prog
,
812 int shader_time_index8
,
813 int shader_time_index16
,
816 unsigned *final_assembly_size
,
820 * Compile a compute shader.
822 * Returns the final assembly and the program's size.
825 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
827 const struct brw_cs_prog_key
*key
,
828 struct brw_cs_prog_data
*prog_data
,
829 const struct nir_shader
*shader
,
830 int shader_time_index
,
831 unsigned *final_assembly_size
,
835 * Fill out local id payload for compute shader according to cs_prog_data.
838 brw_cs_fill_local_id_payload(const struct brw_cs_prog_data
*cs_prog_data
,
839 void *buffer
, uint32_t threads
, uint32_t stride
);