src/mesa/drivers/dri/i965/brw_context.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/api_exec.h"
  34 #include "main/imports.h"
  35 #include "main/macros.h"
  36 #include "main/simple_list.h"
  37 #include "main/version.h"
  38 #include "main/vtxfmt.h"
  39
  40 #include "vbo/vbo_context.h"
  41
  42 #include "brw_context.h"
  43 #include "brw_defines.h"
  44 #include "brw_draw.h"
  45 #include "brw_state.h"
  46
  47 #include "intel_fbo.h"
  48 #include "intel_mipmap_tree.h"
  49 #include "intel_regions.h"
  50 #include "intel_span.h"
  51 #include "intel_tex.h"
  52 #include "intel_tex_obj.h"
  53
  54 #include "tnl/t_pipeline.h"
  55 #include "glsl/ralloc.h"
  56
  57 /***************************************
  58  * Mesa's Driver Functions
  59  ***************************************/
  60
  61 static size_t
  62 brw_query_samples_for_format(struct gl_context *ctx, GLenum target,
  63                              GLenum internalFormat, int samples[16])
  64 {
  65    struct intel_context *intel = intel_context(ctx);
  66
  67    (void) target;
  68
  69    switch (intel->gen) {
  70    case 7:
  71       samples[0] = 8;
  72       samples[1] = 4;
  73       return 2;
  74
  75    case 6:
  76       samples[0] = 4;
  77       return 1;
  78
  79    default:
  80       samples[0] = 1;
  81       return 1;
  82    }
  83 }
  84
  85 static void brwInitDriverFunctions(struct intel_screen *screen,
  86                                    struct dd_function_table *functions)
  87 {
  88    intelInitDriverFunctions( functions );
  89
  90    brwInitFragProgFuncs( functions );
  91    brw_init_queryobj_functions(functions);
  92
  93    functions->QuerySamplesForFormat = brw_query_samples_for_format;
  94    functions->BeginTransformFeedback = brw_begin_transform_feedback;
  95
  96    if (screen->gen >= 7)
  97       functions->EndTransformFeedback = gen7_end_transform_feedback;
  98    else
  99       functions->EndTransformFeedback = brw_end_transform_feedback;
 100
 101    if (screen->gen >= 6)
 102       functions->GetSamplePosition = gen6_get_sample_position;
 103 }
 104
 105 bool
 106 brwCreateContext(int api,
 107                  const struct gl_config *mesaVis,
 108                  __DRIcontext *driContextPriv,
 109                  unsigned major_version,
 110                  unsigned minor_version,
 111                  uint32_t flags,
 112                  unsigned *error,
 113                  void *sharedContextPrivate)
 114 {
 115    __DRIscreen *sPriv = driContextPriv->driScreenPriv;
 116    struct intel_screen *screen = sPriv->driverPrivate;
 117    struct dd_function_table functions;
 118    unsigned i;
 119
 120    struct brw_context *brw = rzalloc(NULL, struct brw_context);
 121    if (!brw) {
 122       printf("%s: failed to alloc context\n", __FUNCTION__);
 123       *error = __DRI_CTX_ERROR_NO_MEMORY;
 124       return false;
 125    }
 126
 127    /* brwInitVtbl needs to know the chipset generation so that it can set the
 128     * right pointers.
 129     */
 130    brw->intel.gen = screen->gen;
 131
 132    brwInitVtbl( brw );
 133
 134    brwInitDriverFunctions(screen, &functions);
 135
 136    struct intel_context *intel = &brw->intel;
 137    struct gl_context *ctx = &intel->ctx;
 138
 139    if (!intelInitContext( intel, api, major_version, minor_version,
 140                           mesaVis, driContextPriv,
 141                           sharedContextPrivate, &functions,
 142                           error)) {
 143       ralloc_free(brw);
 144       return false;
 145    }
 146
 147    brw_init_surface_formats(brw);
 148
 149    /* Initialize swrast, tnl driver tables: */
 150    intelInitSpanFuncs(ctx);
 151
 152    TNLcontext *tnl = TNL_CONTEXT(ctx);
 153    if (tnl)
 154       tnl->Driver.RunPipeline = _tnl_run_pipeline;
 155
 156    ctx->DriverFlags.NewTransformFeedback = BRW_NEW_TRANSFORM_FEEDBACK;
 157
 158    ctx->Const.MaxDualSourceDrawBuffers = 1;
 159    ctx->Const.MaxDrawBuffers = BRW_MAX_DRAW_BUFFERS;
 160    ctx->Const.MaxTextureImageUnits = BRW_MAX_TEX_UNIT;
 161    ctx->Const.MaxTextureCoordUnits = 8; /* Mesa limit */
 162    ctx->Const.MaxTextureUnits = MIN2(ctx->Const.MaxTextureCoordUnits,
 163                                      ctx->Const.MaxTextureImageUnits);
 164    ctx->Const.MaxVertexTextureImageUnits = BRW_MAX_TEX_UNIT;
 165    ctx->Const.MaxCombinedTextureImageUnits =
 166       ctx->Const.MaxVertexTextureImageUnits +
 167       ctx->Const.MaxTextureImageUnits;
 168
 169    ctx->Const.MaxTextureLevels = 14; /* 8192 */
 170    if (ctx->Const.MaxTextureLevels > MAX_TEXTURE_LEVELS)
 171            ctx->Const.MaxTextureLevels = MAX_TEXTURE_LEVELS;
 172    ctx->Const.Max3DTextureLevels = 9;
 173    ctx->Const.MaxCubeTextureLevels = 12;
 174
 175    if (intel->gen >= 7)
 176       ctx->Const.MaxArrayTextureLayers = 2048;
 177    else
 178       ctx->Const.MaxArrayTextureLayers = 512;
 179
 180    ctx->Const.MaxTextureRectSize = (1<<12);
 181
 182    ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 183
 184    /* Hardware only supports a limited number of transform feedback buffers.
 185     * So we need to override the Mesa default (which is based only on software
 186     * limits).
 187     */
 188    ctx->Const.MaxTransformFeedbackBuffers = BRW_MAX_SOL_BUFFERS;
 189
 190    /* On Gen6, in the worst case, we use up one binding table entry per
 191     * transform feedback component (see comments above the definition of
 192     * BRW_MAX_SOL_BINDINGS, in brw_context.h), so we need to advertise a value
 193     * for MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS equal to
 194     * BRW_MAX_SOL_BINDINGS.
 195     *
 196     * In "separate components" mode, we need to divide this value by
 197     * BRW_MAX_SOL_BUFFERS, so that the total number of binding table entries
 198     * used up by all buffers will not exceed BRW_MAX_SOL_BINDINGS.
 199     */
 200    ctx->Const.MaxTransformFeedbackInterleavedComponents = BRW_MAX_SOL_BINDINGS;
 201    ctx->Const.MaxTransformFeedbackSeparateComponents =
 202       BRW_MAX_SOL_BINDINGS / BRW_MAX_SOL_BUFFERS;
 203
 204    if (intel->gen == 6) {
 205       ctx->Const.MaxSamples = 4;
 206       ctx->Const.MaxColorTextureSamples = 4;
 207       ctx->Const.MaxDepthTextureSamples = 4;
 208       ctx->Const.MaxIntegerSamples = 4;
 209    }
 210    else if (intel->gen >= 7) {
 211       ctx->Const.MaxSamples = 8;
 212       ctx->Const.MaxColorTextureSamples = 8;
 213       ctx->Const.MaxDepthTextureSamples = 8;
 214       ctx->Const.MaxIntegerSamples = 8;
 215    }
 216
 217    /* if conformance mode is set, swrast can handle any size AA point */
 218    ctx->Const.MaxPointSizeAA = 255.0;
 219
 220    /* We want the GLSL compiler to emit code that uses condition codes */
 221    for (i = 0; i <= MESA_SHADER_FRAGMENT; i++) {
 222       ctx->ShaderCompilerOptions[i].MaxIfDepth = intel->gen < 6 ? 16 : UINT_MAX;
 223       ctx->ShaderCompilerOptions[i].EmitCondCodes = true;
 224       ctx->ShaderCompilerOptions[i].EmitNoNoise = true;
 225       ctx->ShaderCompilerOptions[i].EmitNoMainReturn = true;
 226       ctx->ShaderCompilerOptions[i].EmitNoIndirectInput = true;
 227       ctx->ShaderCompilerOptions[i].EmitNoIndirectOutput = true;
 228
 229       ctx->ShaderCompilerOptions[i].EmitNoIndirectUniform =
 230          (i == MESA_SHADER_FRAGMENT);
 231       ctx->ShaderCompilerOptions[i].EmitNoIndirectTemp =
 232          (i == MESA_SHADER_FRAGMENT);
 233       ctx->ShaderCompilerOptions[i].LowerClipDistance = true;
 234    }
 235
 236    ctx->Const.VertexProgram.MaxNativeInstructions = (16 * 1024);
 237    ctx->Const.VertexProgram.MaxAluInstructions = 0;
 238    ctx->Const.VertexProgram.MaxTexInstructions = 0;
 239    ctx->Const.VertexProgram.MaxTexIndirections = 0;
 240    ctx->Const.VertexProgram.MaxNativeAluInstructions = 0;
 241    ctx->Const.VertexProgram.MaxNativeTexInstructions = 0;
 242    ctx->Const.VertexProgram.MaxNativeTexIndirections = 0;
 243    ctx->Const.VertexProgram.MaxNativeAttribs = 16;
 244    ctx->Const.VertexProgram.MaxNativeTemps = 256;
 245    ctx->Const.VertexProgram.MaxNativeAddressRegs = 1;
 246    ctx->Const.VertexProgram.MaxNativeParameters = 1024;
 247    ctx->Const.VertexProgram.MaxEnvParams =
 248       MIN2(ctx->Const.VertexProgram.MaxNativeParameters,
 249            ctx->Const.VertexProgram.MaxEnvParams);
 250
 251    ctx->Const.FragmentProgram.MaxNativeInstructions = (1 * 1024);
 252    ctx->Const.FragmentProgram.MaxNativeAluInstructions = (1 * 1024);
 253    ctx->Const.FragmentProgram.MaxNativeTexInstructions = (1 * 1024);
 254    ctx->Const.FragmentProgram.MaxNativeTexIndirections = (1 * 1024);
 255    ctx->Const.FragmentProgram.MaxNativeAttribs = 12;
 256    ctx->Const.FragmentProgram.MaxNativeTemps = 256;
 257    ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
 258    ctx->Const.FragmentProgram.MaxNativeParameters = 1024;
 259    ctx->Const.FragmentProgram.MaxEnvParams =
 260       MIN2(ctx->Const.FragmentProgram.MaxNativeParameters,
 261            ctx->Const.FragmentProgram.MaxEnvParams);
 262
 263    /* Fragment shaders use real, 32-bit twos-complement integers for all
 264     * integer types.
 265     */
 266    ctx->Const.FragmentProgram.LowInt.RangeMin = 31;
 267    ctx->Const.FragmentProgram.LowInt.RangeMax = 30;
 268    ctx->Const.FragmentProgram.LowInt.Precision = 0;
 269    ctx->Const.FragmentProgram.HighInt = ctx->Const.FragmentProgram.MediumInt
 270       = ctx->Const.FragmentProgram.LowInt;
 271
 272    /* Gen6 converts quads to polygon in beginning of 3D pipeline,
 273       but we're not sure how it's actually done for vertex order,
 274       that affect provoking vertex decision. Always use last vertex
 275       convention for quad primitive which works as expected for now. */
 276    if (intel->gen >= 6)
 277        ctx->Const.QuadsFollowProvokingVertexConvention = false;
 278
 279    ctx->Const.QueryCounterBits.Timestamp = 36;
 280
 281    if (intel->is_g4x || intel->gen >= 5) {
 282       brw->CMD_VF_STATISTICS = GM45_3DSTATE_VF_STATISTICS;
 283       brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_GM45;
 284       brw->has_surface_tile_offset = true;
 285       if (intel->gen < 6)
 286           brw->has_compr4 = true;
 287       brw->has_aa_line_parameters = true;
 288       brw->has_pln = true;
 289   } else {
 290       brw->CMD_VF_STATISTICS = GEN4_3DSTATE_VF_STATISTICS;
 291       brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_965;
 292    }
 293
 294    /* WM maximum threads is number of EUs times number of threads per EU. */
 295    assert(intel->gen <= 7);
 296
 297    if (intel->is_haswell) {
 298       if (intel->gt == 1) {
 299          brw->max_wm_threads = 102;
 300          brw->max_vs_threads = 70;
 301          brw->urb.size = 128;
 302          brw->urb.max_vs_entries = 640;
 303          brw->urb.max_gs_entries = 256;
 304       } else if (intel->gt == 2) {
 305          brw->max_wm_threads = 204;
 306          brw->max_vs_threads = 280;
 307          brw->urb.size = 256;
 308          brw->urb.max_vs_entries = 1664;
 309          brw->urb.max_gs_entries = 640;
 310       }
 311    } else if (intel->gen == 7) {
 312       if (intel->gt == 1) {
 313          brw->max_wm_threads = 48;
 314          brw->max_vs_threads = 36;
 315          brw->max_gs_threads = 36;
 316          brw->urb.size = 128;
 317          brw->urb.max_vs_entries = 512;
 318          brw->urb.max_gs_entries = 192;
 319       } else if (intel->gt == 2) {
 320          brw->max_wm_threads = 172;
 321          brw->max_vs_threads = 128;
 322          brw->max_gs_threads = 128;
 323          brw->urb.size = 256;
 324          brw->urb.max_vs_entries = 704;
 325          brw->urb.max_gs_entries = 320;
 326       } else {
 327          assert(!"Unknown gen7 device.");
 328       }
 329    } else if (intel->gen == 6) {
 330       if (intel->gt == 2) {
 331          brw->max_wm_threads = 80;
 332          brw->max_vs_threads = 60;
 333          brw->max_gs_threads = 60;
 334          brw->urb.size = 64;            /* volume 5c.5 section 5.1 */
 335          brw->urb.max_vs_entries = 256; /* volume 2a (see 3DSTATE_URB) */
 336          brw->urb.max_gs_entries = 256;
 337       } else {
 338          brw->max_wm_threads = 40;
 339          brw->max_vs_threads = 24;
 340          brw->max_gs_threads = 21; /* conservative; 24 if rendering disabled */
 341          brw->urb.size = 32;            /* volume 5c.5 section 5.1 */
 342          brw->urb.max_vs_entries = 256; /* volume 2a (see 3DSTATE_URB) */
 343          brw->urb.max_gs_entries = 256;
 344       }
 345       brw->urb.gen6_gs_previously_active = false;
 346    } else if (intel->gen == 5) {
 347       brw->urb.size = 1024;
 348       brw->max_vs_threads = 72;
 349       brw->max_gs_threads = 32;
 350       brw->max_wm_threads = 12 * 6;
 351    } else if (intel->is_g4x) {
 352       brw->urb.size = 384;
 353       brw->max_vs_threads = 32;
 354       brw->max_gs_threads = 2;
 355       brw->max_wm_threads = 10 * 5;
 356    } else if (intel->gen < 6) {
 357       brw->urb.size = 256;
 358       brw->max_vs_threads = 16;
 359       brw->max_gs_threads = 2;
 360       brw->max_wm_threads = 8 * 4;
 361       brw->has_negative_rhw_bug = true;
 362    }
 363
 364    if (intel->gen <= 7) {
 365       brw->needs_unlit_centroid_workaround = true;
 366    }
 367
 368    brw->prim_restart.in_progress = false;
 369    brw->prim_restart.enable_cut_index = false;
 370    intel->hw_ctx = drm_intel_gem_context_create(intel->bufmgr);
 371
 372    brw_init_state( brw );
 373
 374    brw->curbe.last_buf = calloc(1, 4096);
 375    brw->curbe.next_buf = calloc(1, 4096);
 376
 377    brw->state.dirty.mesa = ~0;
 378    brw->state.dirty.brw = ~0;
 379
 380    brw->emit_state_always = 0;
 381
 382    intel->batch.need_workaround_flush = true;
 383
 384    ctx->VertexProgram._MaintainTnlProgram = true;
 385    ctx->FragmentProgram._MaintainTexEnvProgram = true;
 386
 387    brw_draw_init( brw );
 388
 389    brw->precompile = driQueryOptionb(&intel->optionCache, "shader_precompile");
 390
 391    ctx->Const.NativeIntegers = true;
 392    ctx->Const.UniformBooleanTrue = 1;
 393    ctx->Const.UniformBufferOffsetAlignment = 16;
 394
 395    ctx->Const.ForceGLSLExtensionsWarn = driQueryOptionb(&intel->optionCache, "force_glsl_extensions_warn");
 396
 397    ctx->Const.DisableGLSLLineContinuations = driQueryOptionb(&intel->optionCache, "disable_glsl_line_continuations");
 398
 399    ctx->Const.ContextFlags = 0;
 400    if ((flags & __DRI_CTX_FLAG_FORWARD_COMPATIBLE) != 0)
 401       ctx->Const.ContextFlags |= GL_CONTEXT_FLAG_FORWARD_COMPATIBLE_BIT;
 402
 403    if ((flags & __DRI_CTX_FLAG_DEBUG) != 0) {
 404       ctx->Const.ContextFlags |= GL_CONTEXT_FLAG_DEBUG_BIT;
 405
 406       /* Turn on some extra GL_ARB_debug_output generation. */
 407       intel->perf_debug = true;
 408    }
 409
 410    brw_fs_alloc_reg_sets(brw);
 411
 412    if (INTEL_DEBUG & DEBUG_SHADER_TIME)
 413       brw_init_shader_time(brw);
 414
 415    _mesa_compute_version(ctx);
 416
 417    _mesa_initialize_dispatch_tables(ctx);
 418    _mesa_initialize_vbo_vtxfmt(ctx);
 419
 420    return true;
 421 }
 422