src/mesa/drivers/dri/i965/brw_context.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/imports.h"
  34 #include "main/macros.h"
  35 #include "main/simple_list.h"
  36
  37 #include "vbo/vbo_context.h"
  38
  39 #include "brw_context.h"
  40 #include "brw_defines.h"
  41 #include "brw_draw.h"
  42 #include "brw_state.h"
  43
  44 #include "gen6_hiz.h"
  45
  46 #include "intel_fbo.h"
  47 #include "intel_mipmap_tree.h"
  48 #include "intel_regions.h"
  49 #include "intel_span.h"
  50 #include "intel_tex.h"
  51 #include "intel_tex_obj.h"
  52
  53 #include "tnl/t_pipeline.h"
  54 #include "glsl/ralloc.h"
  55
  56 /***************************************
  57  * Mesa's Driver Functions
  58  ***************************************/
  59
  60 /**
  61  * \brief Prepare for entry into glBegin/glEnd block.
  62  *
  63  * Resolve buffers before entering a glBegin/glEnd block. This is
  64  * necessary to prevent recursive calls to FLUSH_VERTICES.
  65  *
  66  * This resolves the depth buffer of each enabled depth texture and the HiZ
  67  * buffer of the attached depth renderbuffer.
  68  *
  69  * Details
  70  * -------
  71  * When vertices are queued during a glBegin/glEnd block, those vertices must
  72  * be drawn before any rendering state changes. To ensure this, Mesa calls
  73  * FLUSH_VERTICES as a prehook to such state changes. Therefore,
  74  * FLUSH_VERTICES itself cannot change rendering state without falling into a
  75  * recursive trap.
  76  *
  77  * This precludes meta-ops, namely buffer resolves, from occurring while any
  78  * vertices are queued. To prevent that situation, we resolve some buffers on
  79  * entering a glBegin/glEnd
  80  *
  81  * \see brwCleanupExecEnd()
  82  */
  83 static void brwPrepareExecBegin(struct gl_context *ctx)
  84 {
  85    struct brw_context *brw = brw_context(ctx);
  86    struct intel_context *intel = &brw->intel;
  87    struct intel_renderbuffer *draw_irb;
  88    struct intel_texture_object *tex_obj;
  89
  90    if (!intel->has_hiz) {
  91       /* The context uses no feature that requires buffer resolves. */
  92       return;
  93    }
  94
  95    /* Resolve each enabled texture. */
  96    for (int i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
  97       if (!ctx->Texture.Unit[i]._ReallyEnabled)
  98          continue;
  99       tex_obj = intel_texture_object(ctx->Texture.Unit[i]._Current);
 100       if (!tex_obj || !tex_obj->mt)
 101          continue;
 102       intel_miptree_all_slices_resolve_depth(intel, tex_obj->mt);
 103    }
 104
 105    /* Resolve the attached depth buffer. */
 106    draw_irb = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);
 107    if (draw_irb) {
 108       intel_renderbuffer_resolve_hiz(intel, draw_irb);
 109    }
 110 }
 111
 112 static void brwInitDriverFunctions( struct dd_function_table *functions )
 113 {
 114    intelInitDriverFunctions( functions );
 115
 116    brwInitFragProgFuncs( functions );
 117    brw_init_queryobj_functions(functions);
 118
 119    functions->PrepareExecBegin = brwPrepareExecBegin;
 120    functions->BeginTransformFeedback = brw_begin_transform_feedback;
 121    functions->EndTransformFeedback = brw_end_transform_feedback;
 122 }
 123
 124 bool
 125 brwCreateContext(int api,
 126                  const struct gl_config *mesaVis,
 127                  __DRIcontext *driContextPriv,
 128                  void *sharedContextPrivate)
 129 {
 130    struct dd_function_table functions;
 131    struct brw_context *brw = rzalloc(NULL, struct brw_context);
 132    struct intel_context *intel = &brw->intel;
 133    struct gl_context *ctx = &intel->ctx;
 134    unsigned i;
 135
 136    if (!brw) {
 137       printf("%s: failed to alloc context\n", __FUNCTION__);
 138       return false;
 139    }
 140
 141    brwInitDriverFunctions( &functions );
 142
 143    if (!intelInitContext( intel, api, mesaVis, driContextPriv,
 144                           sharedContextPrivate, &functions )) {
 145       printf("%s: failed to init intel context\n", __FUNCTION__);
 146       FREE(brw);
 147       return false;
 148    }
 149
 150    brwInitVtbl( brw );
 151
 152    brw_init_surface_formats(brw);
 153
 154    /* Initialize swrast, tnl driver tables: */
 155    intelInitSpanFuncs(ctx);
 156
 157    TNL_CONTEXT(ctx)->Driver.RunPipeline = _tnl_run_pipeline;
 158
 159    ctx->Const.MaxDrawBuffers = BRW_MAX_DRAW_BUFFERS;
 160    ctx->Const.MaxTextureImageUnits = BRW_MAX_TEX_UNIT;
 161    ctx->Const.MaxTextureCoordUnits = 8; /* Mesa limit */
 162    ctx->Const.MaxTextureUnits = MIN2(ctx->Const.MaxTextureCoordUnits,
 163                                      ctx->Const.MaxTextureImageUnits);
 164    ctx->Const.MaxVertexTextureImageUnits = BRW_MAX_TEX_UNIT;
 165    ctx->Const.MaxCombinedTextureImageUnits =
 166       ctx->Const.MaxVertexTextureImageUnits +
 167       ctx->Const.MaxTextureImageUnits;
 168
 169    ctx->Const.MaxTextureLevels = 14; /* 8192 */
 170    if (ctx->Const.MaxTextureLevels > MAX_TEXTURE_LEVELS)
 171            ctx->Const.MaxTextureLevels = MAX_TEXTURE_LEVELS;
 172    ctx->Const.Max3DTextureLevels = 9;
 173    ctx->Const.MaxCubeTextureLevels = 12;
 174    /* minimum maximum.  Users are likely to run into memory problems
 175     * even at this size, since 64 * 2048 * 2048 * 4 = 1GB and we can't
 176     * address that much.
 177     */
 178    ctx->Const.MaxArrayTextureLayers = 64;
 179    ctx->Const.MaxTextureRectSize = (1<<12);
 180
 181    ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 182
 183    /* Hardware only supports a limited number of transform feedback buffers.
 184     * So we need to override the Mesa default (which is based only on software
 185     * limits).
 186     */
 187    ctx->Const.MaxTransformFeedbackSeparateAttribs = BRW_MAX_SOL_BUFFERS;
 188
 189    /* On Gen6, in the worst case, we use up one binding table entry per
 190     * transform feedback component (see comments above the definition of
 191     * BRW_MAX_SOL_BINDINGS, in brw_context.h), so we need to advertise a value
 192     * for MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS equal to
 193     * BRW_MAX_SOL_BINDINGS.
 194     *
 195     * In "separate components" mode, we need to divide this value by
 196     * BRW_MAX_SOL_BUFFERS, so that the total number of binding table entries
 197     * used up by all buffers will not exceed BRW_MAX_SOL_BINDINGS.
 198     */
 199    ctx->Const.MaxTransformFeedbackInterleavedComponents = BRW_MAX_SOL_BINDINGS;
 200    ctx->Const.MaxTransformFeedbackSeparateComponents =
 201       BRW_MAX_SOL_BINDINGS / BRW_MAX_SOL_BUFFERS;
 202
 203    /* if conformance mode is set, swrast can handle any size AA point */
 204    ctx->Const.MaxPointSizeAA = 255.0;
 205
 206    /* We want the GLSL compiler to emit code that uses condition codes */
 207    for (i = 0; i <= MESA_SHADER_FRAGMENT; i++) {
 208       ctx->ShaderCompilerOptions[i].MaxIfDepth = intel->gen < 6 ? 16 : UINT_MAX;
 209       ctx->ShaderCompilerOptions[i].EmitCondCodes = true;
 210       ctx->ShaderCompilerOptions[i].EmitNVTempInitialization = true;
 211       ctx->ShaderCompilerOptions[i].EmitNoNoise = true;
 212       ctx->ShaderCompilerOptions[i].EmitNoMainReturn = true;
 213       ctx->ShaderCompilerOptions[i].EmitNoIndirectInput = true;
 214       ctx->ShaderCompilerOptions[i].EmitNoIndirectOutput = true;
 215
 216       ctx->ShaderCompilerOptions[i].EmitNoIndirectUniform =
 217          (i == MESA_SHADER_FRAGMENT);
 218       ctx->ShaderCompilerOptions[i].EmitNoIndirectTemp =
 219          (i == MESA_SHADER_FRAGMENT);
 220       ctx->ShaderCompilerOptions[i].LowerClipDistance = true;
 221    }
 222
 223    ctx->Const.VertexProgram.MaxNativeInstructions = (16 * 1024);
 224    ctx->Const.VertexProgram.MaxAluInstructions = 0;
 225    ctx->Const.VertexProgram.MaxTexInstructions = 0;
 226    ctx->Const.VertexProgram.MaxTexIndirections = 0;
 227    ctx->Const.VertexProgram.MaxNativeAluInstructions = 0;
 228    ctx->Const.VertexProgram.MaxNativeTexInstructions = 0;
 229    ctx->Const.VertexProgram.MaxNativeTexIndirections = 0;
 230    ctx->Const.VertexProgram.MaxNativeAttribs = 16;
 231    ctx->Const.VertexProgram.MaxNativeTemps = 256;
 232    ctx->Const.VertexProgram.MaxNativeAddressRegs = 1;
 233    ctx->Const.VertexProgram.MaxNativeParameters = 1024;
 234    ctx->Const.VertexProgram.MaxEnvParams =
 235       MIN2(ctx->Const.VertexProgram.MaxNativeParameters,
 236            ctx->Const.VertexProgram.MaxEnvParams);
 237
 238    ctx->Const.FragmentProgram.MaxNativeInstructions = (16 * 1024);
 239    ctx->Const.FragmentProgram.MaxNativeAluInstructions = (16 * 1024);
 240    ctx->Const.FragmentProgram.MaxNativeTexInstructions = (16 * 1024);
 241    ctx->Const.FragmentProgram.MaxNativeTexIndirections = (16 * 1024);
 242    ctx->Const.FragmentProgram.MaxNativeAttribs = 12;
 243    ctx->Const.FragmentProgram.MaxNativeTemps = 256;
 244    ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
 245    ctx->Const.FragmentProgram.MaxNativeParameters = 1024;
 246    ctx->Const.FragmentProgram.MaxEnvParams =
 247       MIN2(ctx->Const.FragmentProgram.MaxNativeParameters,
 248            ctx->Const.FragmentProgram.MaxEnvParams);
 249
 250    /* Fragment shaders use real, 32-bit twos-complement integers for all
 251     * integer types.
 252     */
 253    ctx->Const.FragmentProgram.LowInt.RangeMin = 31;
 254    ctx->Const.FragmentProgram.LowInt.RangeMax = 30;
 255    ctx->Const.FragmentProgram.LowInt.Precision = 0;
 256    ctx->Const.FragmentProgram.HighInt = ctx->Const.FragmentProgram.MediumInt
 257       = ctx->Const.FragmentProgram.LowInt;
 258
 259    /* Gen6 converts quads to polygon in beginning of 3D pipeline,
 260       but we're not sure how it's actually done for vertex order,
 261       that affect provoking vertex decision. Always use last vertex
 262       convention for quad primitive which works as expected for now. */
 263    if (intel->gen >= 6)
 264        ctx->Const.QuadsFollowProvokingVertexConvention = false;
 265
 266    if (intel->is_g4x || intel->gen >= 5) {
 267       brw->CMD_VF_STATISTICS = GM45_3DSTATE_VF_STATISTICS;
 268       brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_GM45;
 269       brw->has_surface_tile_offset = true;
 270       if (intel->gen < 6)
 271           brw->has_compr4 = true;
 272       brw->has_aa_line_parameters = true;
 273       brw->has_pln = true;
 274   } else {
 275       brw->CMD_VF_STATISTICS = GEN4_3DSTATE_VF_STATISTICS;
 276       brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_965;
 277    }
 278
 279    /* WM maximum threads is number of EUs times number of threads per EU. */
 280    if (intel->gen >= 7) {
 281       if (intel->gt == 1) {
 282          brw->max_wm_threads = 86;
 283          brw->max_vs_threads = 36;
 284          brw->max_gs_threads = 36;
 285          brw->urb.size = 128;
 286          brw->urb.max_vs_entries = 512;
 287          brw->urb.max_gs_entries = 192;
 288       } else if (intel->gt == 2) {
 289          brw->max_wm_threads = 86;
 290          brw->max_vs_threads = 128;
 291          brw->max_gs_threads = 128;
 292          brw->urb.size = 256;
 293          brw->urb.max_vs_entries = 704;
 294          brw->urb.max_gs_entries = 320;
 295       } else {
 296          assert(!"Unknown gen7 device.");
 297       }
 298    } else if (intel->gen == 6) {
 299       if (intel->gt == 2) {
 300          /* This could possibly be 80, but is supposed to require
 301           * disabling of WIZ hashing (bit 6 of GT_MODE, 0x20d0) and a
 302           * GPU reset to change.
 303           */
 304          brw->max_wm_threads = 40;
 305          brw->max_vs_threads = 60;
 306          brw->max_gs_threads = 60;
 307          brw->urb.size = 64;            /* volume 5c.5 section 5.1 */
 308          brw->urb.max_vs_entries = 256; /* volume 2a (see 3DSTATE_URB) */
 309          brw->urb.max_gs_entries = 256;
 310       } else {
 311          brw->max_wm_threads = 40;
 312          brw->max_vs_threads = 24;
 313          brw->max_gs_threads = 21; /* conservative; 24 if rendering disabled */
 314          brw->urb.size = 32;            /* volume 5c.5 section 5.1 */
 315          brw->urb.max_vs_entries = 128; /* volume 2a (see 3DSTATE_URB) */
 316          brw->urb.max_gs_entries = 256;
 317       }
 318       brw->urb.gen6_gs_previously_active = false;
 319    } else if (intel->gen == 5) {
 320       brw->urb.size = 1024;
 321       brw->max_vs_threads = 72;
 322       brw->max_gs_threads = 32;
 323       brw->max_wm_threads = 12 * 6;
 324    } else if (intel->is_g4x) {
 325       brw->urb.size = 384;
 326       brw->max_vs_threads = 32;
 327       brw->max_gs_threads = 2;
 328       brw->max_wm_threads = 10 * 5;
 329    } else if (intel->gen < 6) {
 330       brw->urb.size = 256;
 331       brw->max_vs_threads = 16;
 332       brw->max_gs_threads = 2;
 333       brw->max_wm_threads = 8 * 4;
 334       brw->has_negative_rhw_bug = true;
 335    }
 336
 337    brw_init_state( brw );
 338
 339    brw->curbe.last_buf = calloc(1, 4096);
 340    brw->curbe.next_buf = calloc(1, 4096);
 341
 342    brw->state.dirty.mesa = ~0;
 343    brw->state.dirty.brw = ~0;
 344
 345    brw->emit_state_always = 0;
 346
 347    intel->batch.need_workaround_flush = true;
 348
 349    ctx->VertexProgram._MaintainTnlProgram = true;
 350    ctx->FragmentProgram._MaintainTexEnvProgram = true;
 351
 352    brw_draw_init( brw );
 353
 354    brw->new_vs_backend = (getenv("INTEL_OLD_VS") == NULL);
 355    brw->precompile = driQueryOptionb(&intel->optionCache, "shader_precompile");
 356
 357    /* If we're using the new shader backend, we require integer uniforms
 358     * stored as actual integers.
 359     */
 360    if (brw->new_vs_backend) {
 361       ctx->Const.NativeIntegers = true;
 362       ctx->Const.UniformBooleanTrue = 1;
 363    }
 364
 365    return true;
 366 }
 367