src/mesa/drivers/dri/i965/brw_context.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/imports.h"
  34 #include "main/macros.h"
  35 #include "main/simple_list.h"
  36
  37 #include "vbo/vbo_context.h"
  38
  39 #include "brw_context.h"
  40 #include "brw_defines.h"
  41 #include "brw_draw.h"
  42 #include "brw_state.h"
  43
  44 #include "intel_fbo.h"
  45 #include "intel_mipmap_tree.h"
  46 #include "intel_regions.h"
  47 #include "intel_span.h"
  48 #include "intel_tex.h"
  49 #include "intel_tex_obj.h"
  50
  51 #include "tnl/t_pipeline.h"
  52 #include "glsl/ralloc.h"
  53
  54 /***************************************
  55  * Mesa's Driver Functions
  56  ***************************************/
  57
  58 static void brwInitDriverFunctions(struct intel_screen *screen,
  59                                    struct dd_function_table *functions)
  60 {
  61    intelInitDriverFunctions( functions );
  62
  63    brwInitFragProgFuncs( functions );
  64    brw_init_queryobj_functions(functions);
  65
  66    functions->BeginTransformFeedback = brw_begin_transform_feedback;
  67
  68    if (screen->gen >= 7)
  69       functions->EndTransformFeedback = gen7_end_transform_feedback;
  70    else
  71       functions->EndTransformFeedback = brw_end_transform_feedback;
  72 }
  73
  74 bool
  75 brwCreateContext(int api,
  76                  const struct gl_config *mesaVis,
  77                  __DRIcontext *driContextPriv,
  78                  void *sharedContextPrivate)
  79 {
  80    __DRIscreen *sPriv = driContextPriv->driScreenPriv;
  81    struct intel_screen *screen = sPriv->driverPrivate;
  82    struct dd_function_table functions;
  83    struct brw_context *brw = rzalloc(NULL, struct brw_context);
  84    struct intel_context *intel = &brw->intel;
  85    struct gl_context *ctx = &intel->ctx;
  86    unsigned i;
  87
  88    if (!brw) {
  89       printf("%s: failed to alloc context\n", __FUNCTION__);
  90       return false;
  91    }
  92
  93    brwInitDriverFunctions(screen, &functions);
  94
  95    if (!intelInitContext( intel, api, mesaVis, driContextPriv,
  96                           sharedContextPrivate, &functions )) {
  97       printf("%s: failed to init intel context\n", __FUNCTION__);
  98       FREE(brw);
  99       return false;
 100    }
 101
 102    brwInitVtbl( brw );
 103
 104    brw_init_surface_formats(brw);
 105
 106    /* Initialize swrast, tnl driver tables: */
 107    intelInitSpanFuncs(ctx);
 108
 109    TNL_CONTEXT(ctx)->Driver.RunPipeline = _tnl_run_pipeline;
 110
 111    ctx->Const.MaxDualSourceDrawBuffers = 1;
 112    ctx->Const.MaxDrawBuffers = BRW_MAX_DRAW_BUFFERS;
 113    ctx->Const.MaxTextureImageUnits = BRW_MAX_TEX_UNIT;
 114    ctx->Const.MaxTextureCoordUnits = 8; /* Mesa limit */
 115    ctx->Const.MaxTextureUnits = MIN2(ctx->Const.MaxTextureCoordUnits,
 116                                      ctx->Const.MaxTextureImageUnits);
 117    ctx->Const.MaxVertexTextureImageUnits = BRW_MAX_TEX_UNIT;
 118    ctx->Const.MaxCombinedTextureImageUnits =
 119       ctx->Const.MaxVertexTextureImageUnits +
 120       ctx->Const.MaxTextureImageUnits;
 121
 122    ctx->Const.MaxTextureLevels = 14; /* 8192 */
 123    if (ctx->Const.MaxTextureLevels > MAX_TEXTURE_LEVELS)
 124            ctx->Const.MaxTextureLevels = MAX_TEXTURE_LEVELS;
 125    ctx->Const.Max3DTextureLevels = 9;
 126    ctx->Const.MaxCubeTextureLevels = 12;
 127
 128    if (intel->gen >= 7)
 129       ctx->Const.MaxArrayTextureLayers = 2048;
 130    else
 131       ctx->Const.MaxArrayTextureLayers = 512;
 132
 133    ctx->Const.MaxTextureRectSize = (1<<12);
 134
 135    ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 136
 137    /* Hardware only supports a limited number of transform feedback buffers.
 138     * So we need to override the Mesa default (which is based only on software
 139     * limits).
 140     */
 141    ctx->Const.MaxTransformFeedbackBuffers = BRW_MAX_SOL_BUFFERS;
 142
 143    /* On Gen6, in the worst case, we use up one binding table entry per
 144     * transform feedback component (see comments above the definition of
 145     * BRW_MAX_SOL_BINDINGS, in brw_context.h), so we need to advertise a value
 146     * for MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS equal to
 147     * BRW_MAX_SOL_BINDINGS.
 148     *
 149     * In "separate components" mode, we need to divide this value by
 150     * BRW_MAX_SOL_BUFFERS, so that the total number of binding table entries
 151     * used up by all buffers will not exceed BRW_MAX_SOL_BINDINGS.
 152     */
 153    ctx->Const.MaxTransformFeedbackInterleavedComponents = BRW_MAX_SOL_BINDINGS;
 154    ctx->Const.MaxTransformFeedbackSeparateComponents =
 155       BRW_MAX_SOL_BINDINGS / BRW_MAX_SOL_BUFFERS;
 156
 157    /* Claim to support 4 multisamples, even though we don't.  This is a
 158     * requirement for GL 3.0 that we missed until the last minute.  Go ahead and
 159     * claim the limit, so that usage of the 4 multisample-based API that is
 160     * guaranteed in 3.0 succeeds, even though we only rasterize a single sample.
 161     */
 162    if (intel->gen >= 6)
 163       ctx->Const.MaxSamples = 4;
 164
 165    /* if conformance mode is set, swrast can handle any size AA point */
 166    ctx->Const.MaxPointSizeAA = 255.0;
 167
 168    /* We want the GLSL compiler to emit code that uses condition codes */
 169    for (i = 0; i <= MESA_SHADER_FRAGMENT; i++) {
 170       ctx->ShaderCompilerOptions[i].MaxIfDepth = intel->gen < 6 ? 16 : UINT_MAX;
 171       ctx->ShaderCompilerOptions[i].EmitCondCodes = true;
 172       ctx->ShaderCompilerOptions[i].EmitNVTempInitialization = true;
 173       ctx->ShaderCompilerOptions[i].EmitNoNoise = true;
 174       ctx->ShaderCompilerOptions[i].EmitNoMainReturn = true;
 175       ctx->ShaderCompilerOptions[i].EmitNoIndirectInput = true;
 176       ctx->ShaderCompilerOptions[i].EmitNoIndirectOutput = true;
 177
 178       ctx->ShaderCompilerOptions[i].EmitNoIndirectUniform =
 179          (i == MESA_SHADER_FRAGMENT);
 180       ctx->ShaderCompilerOptions[i].EmitNoIndirectTemp =
 181          (i == MESA_SHADER_FRAGMENT);
 182       ctx->ShaderCompilerOptions[i].LowerClipDistance = true;
 183    }
 184
 185    ctx->Const.VertexProgram.MaxNativeInstructions = (16 * 1024);
 186    ctx->Const.VertexProgram.MaxAluInstructions = 0;
 187    ctx->Const.VertexProgram.MaxTexInstructions = 0;
 188    ctx->Const.VertexProgram.MaxTexIndirections = 0;
 189    ctx->Const.VertexProgram.MaxNativeAluInstructions = 0;
 190    ctx->Const.VertexProgram.MaxNativeTexInstructions = 0;
 191    ctx->Const.VertexProgram.MaxNativeTexIndirections = 0;
 192    ctx->Const.VertexProgram.MaxNativeAttribs = 16;
 193    ctx->Const.VertexProgram.MaxNativeTemps = 256;
 194    ctx->Const.VertexProgram.MaxNativeAddressRegs = 1;
 195    ctx->Const.VertexProgram.MaxNativeParameters = 1024;
 196    ctx->Const.VertexProgram.MaxEnvParams =
 197       MIN2(ctx->Const.VertexProgram.MaxNativeParameters,
 198            ctx->Const.VertexProgram.MaxEnvParams);
 199
 200    ctx->Const.FragmentProgram.MaxNativeInstructions = (16 * 1024);
 201    ctx->Const.FragmentProgram.MaxNativeAluInstructions = (16 * 1024);
 202    ctx->Const.FragmentProgram.MaxNativeTexInstructions = (16 * 1024);
 203    ctx->Const.FragmentProgram.MaxNativeTexIndirections = (16 * 1024);
 204    ctx->Const.FragmentProgram.MaxNativeAttribs = 12;
 205    ctx->Const.FragmentProgram.MaxNativeTemps = 256;
 206    ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
 207    ctx->Const.FragmentProgram.MaxNativeParameters = 1024;
 208    ctx->Const.FragmentProgram.MaxEnvParams =
 209       MIN2(ctx->Const.FragmentProgram.MaxNativeParameters,
 210            ctx->Const.FragmentProgram.MaxEnvParams);
 211
 212    /* Fragment shaders use real, 32-bit twos-complement integers for all
 213     * integer types.
 214     */
 215    ctx->Const.FragmentProgram.LowInt.RangeMin = 31;
 216    ctx->Const.FragmentProgram.LowInt.RangeMax = 30;
 217    ctx->Const.FragmentProgram.LowInt.Precision = 0;
 218    ctx->Const.FragmentProgram.HighInt = ctx->Const.FragmentProgram.MediumInt
 219       = ctx->Const.FragmentProgram.LowInt;
 220
 221    /* Gen6 converts quads to polygon in beginning of 3D pipeline,
 222       but we're not sure how it's actually done for vertex order,
 223       that affect provoking vertex decision. Always use last vertex
 224       convention for quad primitive which works as expected for now. */
 225    if (intel->gen >= 6)
 226        ctx->Const.QuadsFollowProvokingVertexConvention = false;
 227
 228    if (intel->is_g4x || intel->gen >= 5) {
 229       brw->CMD_VF_STATISTICS = GM45_3DSTATE_VF_STATISTICS;
 230       brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_GM45;
 231       brw->has_surface_tile_offset = true;
 232       if (intel->gen < 6)
 233           brw->has_compr4 = true;
 234       brw->has_aa_line_parameters = true;
 235       brw->has_pln = true;
 236   } else {
 237       brw->CMD_VF_STATISTICS = GEN4_3DSTATE_VF_STATISTICS;
 238       brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_965;
 239    }
 240
 241    /* WM maximum threads is number of EUs times number of threads per EU. */
 242    if (intel->gen >= 7) {
 243       if (intel->gt == 1) {
 244          brw->max_wm_threads = 86;
 245          brw->max_vs_threads = 36;
 246          brw->max_gs_threads = 36;
 247          brw->urb.size = 128;
 248          brw->urb.max_vs_entries = 512;
 249          brw->urb.max_gs_entries = 192;
 250       } else if (intel->gt == 2) {
 251          brw->max_wm_threads = 86;
 252          brw->max_vs_threads = 128;
 253          brw->max_gs_threads = 128;
 254          brw->urb.size = 256;
 255          brw->urb.max_vs_entries = 704;
 256          brw->urb.max_gs_entries = 320;
 257       } else {
 258          assert(!"Unknown gen7 device.");
 259       }
 260    } else if (intel->gen == 6) {
 261       if (intel->gt == 2) {
 262          /* This could possibly be 80, but is supposed to require
 263           * disabling of WIZ hashing (bit 6 of GT_MODE, 0x20d0) and a
 264           * GPU reset to change.
 265           */
 266          brw->max_wm_threads = 40;
 267          brw->max_vs_threads = 60;
 268          brw->max_gs_threads = 60;
 269          brw->urb.size = 64;            /* volume 5c.5 section 5.1 */
 270          brw->urb.max_vs_entries = 256; /* volume 2a (see 3DSTATE_URB) */
 271          brw->urb.max_gs_entries = 256;
 272       } else {
 273          brw->max_wm_threads = 40;
 274          brw->max_vs_threads = 24;
 275          brw->max_gs_threads = 21; /* conservative; 24 if rendering disabled */
 276          brw->urb.size = 32;            /* volume 5c.5 section 5.1 */
 277          brw->urb.max_vs_entries = 256; /* volume 2a (see 3DSTATE_URB) */
 278          brw->urb.max_gs_entries = 256;
 279       }
 280       brw->urb.gen6_gs_previously_active = false;
 281    } else if (intel->gen == 5) {
 282       brw->urb.size = 1024;
 283       brw->max_vs_threads = 72;
 284       brw->max_gs_threads = 32;
 285       brw->max_wm_threads = 12 * 6;
 286    } else if (intel->is_g4x) {
 287       brw->urb.size = 384;
 288       brw->max_vs_threads = 32;
 289       brw->max_gs_threads = 2;
 290       brw->max_wm_threads = 10 * 5;
 291    } else if (intel->gen < 6) {
 292       brw->urb.size = 256;
 293       brw->max_vs_threads = 16;
 294       brw->max_gs_threads = 2;
 295       brw->max_wm_threads = 8 * 4;
 296       brw->has_negative_rhw_bug = true;
 297    }
 298
 299    brw->prim_restart.in_progress = false;
 300    brw->prim_restart.enable_cut_index = false;
 301
 302    brw_init_state( brw );
 303
 304    brw->curbe.last_buf = calloc(1, 4096);
 305    brw->curbe.next_buf = calloc(1, 4096);
 306
 307    brw->state.dirty.mesa = ~0;
 308    brw->state.dirty.brw = ~0;
 309
 310    brw->emit_state_always = 0;
 311
 312    intel->batch.need_workaround_flush = true;
 313
 314    ctx->VertexProgram._MaintainTnlProgram = true;
 315    ctx->FragmentProgram._MaintainTexEnvProgram = true;
 316
 317    brw_draw_init( brw );
 318
 319    brw->precompile = driQueryOptionb(&intel->optionCache, "shader_precompile");
 320
 321    ctx->Const.NativeIntegers = true;
 322    ctx->Const.UniformBooleanTrue = 1;
 323
 324    ctx->Const.ForceGLSLExtensionsWarn = driQueryOptionb(&intel->optionCache, "force_glsl_extensions_warn");
 325
 326    return true;
 327 }
 328