2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #include "main/api_exec.h"
34 #include "main/imports.h"
35 #include "main/macros.h"
36 #include "main/simple_list.h"
37 #include "main/version.h"
38 #include "main/vtxfmt.h"
40 #include "vbo/vbo_context.h"
42 #include "brw_context.h"
43 #include "brw_defines.h"
45 #include "brw_state.h"
47 #include "intel_fbo.h"
48 #include "intel_mipmap_tree.h"
49 #include "intel_regions.h"
50 #include "intel_span.h"
51 #include "intel_tex.h"
52 #include "intel_tex_obj.h"
54 #include "tnl/t_pipeline.h"
55 #include "glsl/ralloc.h"
57 /***************************************
58 * Mesa's Driver Functions
59 ***************************************/
62 brw_query_samples_for_format(struct gl_context
*ctx
, GLenum internalFormat
,
65 struct intel_context
*intel
= intel_context(ctx
);
83 static void brwInitDriverFunctions(struct intel_screen
*screen
,
84 struct dd_function_table
*functions
)
86 intelInitDriverFunctions( functions
);
88 brwInitFragProgFuncs( functions
);
89 brw_init_queryobj_functions(functions
);
91 functions
->QuerySamplesForFormat
= brw_query_samples_for_format
;
92 functions
->BeginTransformFeedback
= brw_begin_transform_feedback
;
95 functions
->EndTransformFeedback
= gen7_end_transform_feedback
;
97 functions
->EndTransformFeedback
= brw_end_transform_feedback
;
100 functions
->GetSamplePosition
= gen6_get_sample_position
;
104 brwCreateContext(int api
,
105 const struct gl_config
*mesaVis
,
106 __DRIcontext
*driContextPriv
,
107 unsigned major_version
,
108 unsigned minor_version
,
111 void *sharedContextPrivate
)
113 __DRIscreen
*sPriv
= driContextPriv
->driScreenPriv
;
114 struct intel_screen
*screen
= sPriv
->driverPrivate
;
115 struct dd_function_table functions
;
118 struct brw_context
*brw
= rzalloc(NULL
, struct brw_context
);
120 printf("%s: failed to alloc context\n", __FUNCTION__
);
121 *error
= __DRI_CTX_ERROR_NO_MEMORY
;
125 /* brwInitVtbl needs to know the chipset generation so that it can set the
128 brw
->intel
.gen
= screen
->gen
;
132 brwInitDriverFunctions(screen
, &functions
);
134 struct intel_context
*intel
= &brw
->intel
;
135 struct gl_context
*ctx
= &intel
->ctx
;
137 if (!intelInitContext( intel
, api
, major_version
, minor_version
,
138 mesaVis
, driContextPriv
,
139 sharedContextPrivate
, &functions
,
145 brw_init_surface_formats(brw
);
147 /* Initialize swrast, tnl driver tables: */
148 intelInitSpanFuncs(ctx
);
150 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
152 tnl
->Driver
.RunPipeline
= _tnl_run_pipeline
;
154 ctx
->Const
.MaxDualSourceDrawBuffers
= 1;
155 ctx
->Const
.MaxDrawBuffers
= BRW_MAX_DRAW_BUFFERS
;
156 ctx
->Const
.MaxTextureImageUnits
= BRW_MAX_TEX_UNIT
;
157 ctx
->Const
.MaxTextureCoordUnits
= 8; /* Mesa limit */
158 ctx
->Const
.MaxTextureUnits
= MIN2(ctx
->Const
.MaxTextureCoordUnits
,
159 ctx
->Const
.MaxTextureImageUnits
);
160 ctx
->Const
.MaxVertexTextureImageUnits
= BRW_MAX_TEX_UNIT
;
161 ctx
->Const
.MaxCombinedTextureImageUnits
=
162 ctx
->Const
.MaxVertexTextureImageUnits
+
163 ctx
->Const
.MaxTextureImageUnits
;
165 ctx
->Const
.MaxTextureLevels
= 14; /* 8192 */
166 if (ctx
->Const
.MaxTextureLevels
> MAX_TEXTURE_LEVELS
)
167 ctx
->Const
.MaxTextureLevels
= MAX_TEXTURE_LEVELS
;
168 ctx
->Const
.Max3DTextureLevels
= 9;
169 ctx
->Const
.MaxCubeTextureLevels
= 12;
172 ctx
->Const
.MaxArrayTextureLayers
= 2048;
174 ctx
->Const
.MaxArrayTextureLayers
= 512;
176 ctx
->Const
.MaxTextureRectSize
= (1<<12);
178 ctx
->Const
.MaxTextureMaxAnisotropy
= 16.0;
180 /* Hardware only supports a limited number of transform feedback buffers.
181 * So we need to override the Mesa default (which is based only on software
184 ctx
->Const
.MaxTransformFeedbackBuffers
= BRW_MAX_SOL_BUFFERS
;
186 /* On Gen6, in the worst case, we use up one binding table entry per
187 * transform feedback component (see comments above the definition of
188 * BRW_MAX_SOL_BINDINGS, in brw_context.h), so we need to advertise a value
189 * for MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS equal to
190 * BRW_MAX_SOL_BINDINGS.
192 * In "separate components" mode, we need to divide this value by
193 * BRW_MAX_SOL_BUFFERS, so that the total number of binding table entries
194 * used up by all buffers will not exceed BRW_MAX_SOL_BINDINGS.
196 ctx
->Const
.MaxTransformFeedbackInterleavedComponents
= BRW_MAX_SOL_BINDINGS
;
197 ctx
->Const
.MaxTransformFeedbackSeparateComponents
=
198 BRW_MAX_SOL_BINDINGS
/ BRW_MAX_SOL_BUFFERS
;
200 if (intel
->gen
== 6) {
201 ctx
->Const
.MaxSamples
= 4;
202 ctx
->Const
.MaxColorTextureSamples
= 4;
203 ctx
->Const
.MaxDepthTextureSamples
= 1;
204 ctx
->Const
.MaxIntegerSamples
= 4;
206 else if (intel
->gen
>= 7) {
207 ctx
->Const
.MaxSamples
= 8;
208 ctx
->Const
.MaxColorTextureSamples
= 8;
209 ctx
->Const
.MaxDepthTextureSamples
= 1;
210 ctx
->Const
.MaxIntegerSamples
= 8;
213 /* if conformance mode is set, swrast can handle any size AA point */
214 ctx
->Const
.MaxPointSizeAA
= 255.0;
216 /* We want the GLSL compiler to emit code that uses condition codes */
217 for (i
= 0; i
<= MESA_SHADER_FRAGMENT
; i
++) {
218 ctx
->ShaderCompilerOptions
[i
].MaxIfDepth
= intel
->gen
< 6 ? 16 : UINT_MAX
;
219 ctx
->ShaderCompilerOptions
[i
].EmitCondCodes
= true;
220 ctx
->ShaderCompilerOptions
[i
].EmitNoNoise
= true;
221 ctx
->ShaderCompilerOptions
[i
].EmitNoMainReturn
= true;
222 ctx
->ShaderCompilerOptions
[i
].EmitNoIndirectInput
= true;
223 ctx
->ShaderCompilerOptions
[i
].EmitNoIndirectOutput
= true;
225 ctx
->ShaderCompilerOptions
[i
].EmitNoIndirectUniform
=
226 (i
== MESA_SHADER_FRAGMENT
);
227 ctx
->ShaderCompilerOptions
[i
].EmitNoIndirectTemp
=
228 (i
== MESA_SHADER_FRAGMENT
);
229 ctx
->ShaderCompilerOptions
[i
].LowerClipDistance
= true;
232 ctx
->Const
.VertexProgram
.MaxNativeInstructions
= (16 * 1024);
233 ctx
->Const
.VertexProgram
.MaxAluInstructions
= 0;
234 ctx
->Const
.VertexProgram
.MaxTexInstructions
= 0;
235 ctx
->Const
.VertexProgram
.MaxTexIndirections
= 0;
236 ctx
->Const
.VertexProgram
.MaxNativeAluInstructions
= 0;
237 ctx
->Const
.VertexProgram
.MaxNativeTexInstructions
= 0;
238 ctx
->Const
.VertexProgram
.MaxNativeTexIndirections
= 0;
239 ctx
->Const
.VertexProgram
.MaxNativeAttribs
= 16;
240 ctx
->Const
.VertexProgram
.MaxNativeTemps
= 256;
241 ctx
->Const
.VertexProgram
.MaxNativeAddressRegs
= 1;
242 ctx
->Const
.VertexProgram
.MaxNativeParameters
= 1024;
243 ctx
->Const
.VertexProgram
.MaxEnvParams
=
244 MIN2(ctx
->Const
.VertexProgram
.MaxNativeParameters
,
245 ctx
->Const
.VertexProgram
.MaxEnvParams
);
247 ctx
->Const
.FragmentProgram
.MaxNativeInstructions
= (1 * 1024);
248 ctx
->Const
.FragmentProgram
.MaxNativeAluInstructions
= (1 * 1024);
249 ctx
->Const
.FragmentProgram
.MaxNativeTexInstructions
= (1 * 1024);
250 ctx
->Const
.FragmentProgram
.MaxNativeTexIndirections
= (1 * 1024);
251 ctx
->Const
.FragmentProgram
.MaxNativeAttribs
= 12;
252 ctx
->Const
.FragmentProgram
.MaxNativeTemps
= 256;
253 ctx
->Const
.FragmentProgram
.MaxNativeAddressRegs
= 0;
254 ctx
->Const
.FragmentProgram
.MaxNativeParameters
= 1024;
255 ctx
->Const
.FragmentProgram
.MaxEnvParams
=
256 MIN2(ctx
->Const
.FragmentProgram
.MaxNativeParameters
,
257 ctx
->Const
.FragmentProgram
.MaxEnvParams
);
259 /* Fragment shaders use real, 32-bit twos-complement integers for all
262 ctx
->Const
.FragmentProgram
.LowInt
.RangeMin
= 31;
263 ctx
->Const
.FragmentProgram
.LowInt
.RangeMax
= 30;
264 ctx
->Const
.FragmentProgram
.LowInt
.Precision
= 0;
265 ctx
->Const
.FragmentProgram
.HighInt
= ctx
->Const
.FragmentProgram
.MediumInt
266 = ctx
->Const
.FragmentProgram
.LowInt
;
268 /* Gen6 converts quads to polygon in beginning of 3D pipeline,
269 but we're not sure how it's actually done for vertex order,
270 that affect provoking vertex decision. Always use last vertex
271 convention for quad primitive which works as expected for now. */
273 ctx
->Const
.QuadsFollowProvokingVertexConvention
= false;
275 ctx
->Const
.QueryCounterBits
.Timestamp
= 36;
277 if (intel
->is_g4x
|| intel
->gen
>= 5) {
278 brw
->CMD_VF_STATISTICS
= GM45_3DSTATE_VF_STATISTICS
;
279 brw
->CMD_PIPELINE_SELECT
= CMD_PIPELINE_SELECT_GM45
;
280 brw
->has_surface_tile_offset
= true;
282 brw
->has_compr4
= true;
283 brw
->has_aa_line_parameters
= true;
286 brw
->CMD_VF_STATISTICS
= GEN4_3DSTATE_VF_STATISTICS
;
287 brw
->CMD_PIPELINE_SELECT
= CMD_PIPELINE_SELECT_965
;
290 /* WM maximum threads is number of EUs times number of threads per EU. */
291 assert(intel
->gen
<= 7);
293 if (intel
->is_haswell
) {
294 if (intel
->gt
== 1) {
295 brw
->max_wm_threads
= 102;
296 brw
->max_vs_threads
= 70;
298 brw
->urb
.max_vs_entries
= 640;
299 brw
->urb
.max_gs_entries
= 256;
300 } else if (intel
->gt
== 2) {
301 brw
->max_wm_threads
= 204;
302 brw
->max_vs_threads
= 280;
304 brw
->urb
.max_vs_entries
= 1664;
305 brw
->urb
.max_gs_entries
= 640;
307 } else if (intel
->gen
== 7) {
308 if (intel
->gt
== 1) {
309 brw
->max_wm_threads
= 48;
310 brw
->max_vs_threads
= 36;
311 brw
->max_gs_threads
= 36;
313 brw
->urb
.max_vs_entries
= 512;
314 brw
->urb
.max_gs_entries
= 192;
315 } else if (intel
->gt
== 2) {
316 brw
->max_wm_threads
= 172;
317 brw
->max_vs_threads
= 128;
318 brw
->max_gs_threads
= 128;
320 brw
->urb
.max_vs_entries
= 704;
321 brw
->urb
.max_gs_entries
= 320;
323 assert(!"Unknown gen7 device.");
325 } else if (intel
->gen
== 6) {
326 if (intel
->gt
== 2) {
327 brw
->max_wm_threads
= 80;
328 brw
->max_vs_threads
= 60;
329 brw
->max_gs_threads
= 60;
330 brw
->urb
.size
= 64; /* volume 5c.5 section 5.1 */
331 brw
->urb
.max_vs_entries
= 256; /* volume 2a (see 3DSTATE_URB) */
332 brw
->urb
.max_gs_entries
= 256;
334 brw
->max_wm_threads
= 40;
335 brw
->max_vs_threads
= 24;
336 brw
->max_gs_threads
= 21; /* conservative; 24 if rendering disabled */
337 brw
->urb
.size
= 32; /* volume 5c.5 section 5.1 */
338 brw
->urb
.max_vs_entries
= 256; /* volume 2a (see 3DSTATE_URB) */
339 brw
->urb
.max_gs_entries
= 256;
341 brw
->urb
.gen6_gs_previously_active
= false;
342 } else if (intel
->gen
== 5) {
343 brw
->urb
.size
= 1024;
344 brw
->max_vs_threads
= 72;
345 brw
->max_gs_threads
= 32;
346 brw
->max_wm_threads
= 12 * 6;
347 } else if (intel
->is_g4x
) {
349 brw
->max_vs_threads
= 32;
350 brw
->max_gs_threads
= 2;
351 brw
->max_wm_threads
= 10 * 5;
352 } else if (intel
->gen
< 6) {
354 brw
->max_vs_threads
= 16;
355 brw
->max_gs_threads
= 2;
356 brw
->max_wm_threads
= 8 * 4;
357 brw
->has_negative_rhw_bug
= true;
360 if (intel
->gen
<= 7) {
361 brw
->needs_unlit_centroid_workaround
= true;
364 brw
->prim_restart
.in_progress
= false;
365 brw
->prim_restart
.enable_cut_index
= false;
366 intel
->hw_ctx
= drm_intel_gem_context_create(intel
->bufmgr
);
368 brw_init_state( brw
);
370 brw
->curbe
.last_buf
= calloc(1, 4096);
371 brw
->curbe
.next_buf
= calloc(1, 4096);
373 brw
->state
.dirty
.mesa
= ~0;
374 brw
->state
.dirty
.brw
= ~0;
376 brw
->emit_state_always
= 0;
378 intel
->batch
.need_workaround_flush
= true;
380 ctx
->VertexProgram
._MaintainTnlProgram
= true;
381 ctx
->FragmentProgram
._MaintainTexEnvProgram
= true;
383 brw_draw_init( brw
);
385 brw
->precompile
= driQueryOptionb(&intel
->optionCache
, "shader_precompile");
387 ctx
->Const
.NativeIntegers
= true;
388 ctx
->Const
.UniformBooleanTrue
= 1;
389 ctx
->Const
.UniformBufferOffsetAlignment
= 16;
391 ctx
->Const
.ForceGLSLExtensionsWarn
= driQueryOptionb(&intel
->optionCache
, "force_glsl_extensions_warn");
393 ctx
->Const
.DisableGLSLLineContinuations
= driQueryOptionb(&intel
->optionCache
, "disable_glsl_line_continuations");
395 ctx
->Const
.ContextFlags
= 0;
396 if ((flags
& __DRI_CTX_FLAG_FORWARD_COMPATIBLE
) != 0)
397 ctx
->Const
.ContextFlags
|= GL_CONTEXT_FLAG_FORWARD_COMPATIBLE_BIT
;
399 if ((flags
& __DRI_CTX_FLAG_DEBUG
) != 0) {
400 ctx
->Const
.ContextFlags
|= GL_CONTEXT_FLAG_DEBUG_BIT
;
402 /* Turn on some extra GL_ARB_debug_output generation. */
403 intel
->perf_debug
= true;
406 brw_fs_alloc_reg_sets(brw
);
408 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
409 brw_init_shader_time(brw
);
411 _mesa_compute_version(ctx
);
413 _mesa_initialize_dispatch_tables(ctx
);
414 _mesa_initialize_vbo_vtxfmt(ctx
);