src/mesa/drivers/dri/i965/brw_context.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/imports.h"
  34 #include "main/macros.h"
  35 #include "main/simple_list.h"
  36
  37 #include "vbo/vbo_context.h"
  38
  39 #include "brw_context.h"
  40 #include "brw_defines.h"
  41 #include "brw_draw.h"
  42 #include "brw_state.h"
  43
  44 #include "gen6_hiz.h"
  45
  46 #include "intel_fbo.h"
  47 #include "intel_mipmap_tree.h"
  48 #include "intel_regions.h"
  49 #include "intel_span.h"
  50 #include "intel_tex.h"
  51 #include "intel_tex_obj.h"
  52
  53 #include "tnl/t_pipeline.h"
  54 #include "glsl/ralloc.h"
  55
  56 /***************************************
  57  * Mesa's Driver Functions
  58  ***************************************/
  59
  60 /**
  61  * \brief Prepare for entry into glBegin/glEnd block.
  62  *
  63  * Resolve buffers before entering a glBegin/glEnd block. This is
  64  * necessary to prevent recursive calls to FLUSH_VERTICES.
  65  *
  66  * This resolves the depth buffer of each enabled depth texture and the HiZ
  67  * buffer of the attached depth renderbuffer.
  68  *
  69  * Details
  70  * -------
  71  * When vertices are queued during a glBegin/glEnd block, those vertices must
  72  * be drawn before any rendering state changes. To ensure this, Mesa calls
  73  * FLUSH_VERTICES as a prehook to such state changes. Therefore,
  74  * FLUSH_VERTICES itself cannot change rendering state without falling into a
  75  * recursive trap.
  76  *
  77  * This precludes meta-ops, namely buffer resolves, from occurring while any
  78  * vertices are queued. To prevent that situation, we resolve some buffers on
  79  * entering a glBegin/glEnd
  80  *
  81  * \see brwCleanupExecEnd()
  82  */
  83 static void brwPrepareExecBegin(struct gl_context *ctx)
  84 {
  85    struct brw_context *brw = brw_context(ctx);
  86    struct intel_context *intel = &brw->intel;
  87    struct intel_renderbuffer *draw_irb;
  88    struct intel_texture_object *tex_obj;
  89
  90    if (!intel->has_hiz) {
  91       /* The context uses no feature that requires buffer resolves. */
  92       return;
  93    }
  94
  95    /* Resolve each enabled texture. */
  96    for (int i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
  97       if (!ctx->Texture.Unit[i]._ReallyEnabled)
  98          continue;
  99       tex_obj = intel_texture_object(ctx->Texture.Unit[i]._Current);
 100       if (!tex_obj || !tex_obj->mt)
 101          continue;
 102       intel_miptree_all_slices_resolve_depth(intel, tex_obj->mt);
 103    }
 104
 105    /* Resolve the attached depth buffer. */
 106    draw_irb = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);
 107    if (draw_irb) {
 108       intel_renderbuffer_resolve_hiz(intel, draw_irb);
 109    }
 110 }
 111
 112 static void brwInitDriverFunctions( struct dd_function_table *functions )
 113 {
 114    intelInitDriverFunctions( functions );
 115
 116    brwInitFragProgFuncs( functions );
 117    brw_init_queryobj_functions(functions);
 118
 119    functions->PrepareExecBegin = brwPrepareExecBegin;
 120 }
 121
 122 bool
 123 brwCreateContext(int api,
 124                  const struct gl_config *mesaVis,
 125                  __DRIcontext *driContextPriv,
 126                  void *sharedContextPrivate)
 127 {
 128    struct dd_function_table functions;
 129    struct brw_context *brw = rzalloc(NULL, struct brw_context);
 130    struct intel_context *intel = &brw->intel;
 131    struct gl_context *ctx = &intel->ctx;
 132    unsigned i;
 133
 134    if (!brw) {
 135       printf("%s: failed to alloc context\n", __FUNCTION__);
 136       return false;
 137    }
 138
 139    brwInitDriverFunctions( &functions );
 140
 141    if (!intelInitContext( intel, api, mesaVis, driContextPriv,
 142                           sharedContextPrivate, &functions )) {
 143       printf("%s: failed to init intel context\n", __FUNCTION__);
 144       FREE(brw);
 145       return false;
 146    }
 147
 148    brwInitVtbl( brw );
 149
 150    /* Initialize swrast, tnl driver tables: */
 151    intelInitSpanFuncs(ctx);
 152
 153    TNL_CONTEXT(ctx)->Driver.RunPipeline = _tnl_run_pipeline;
 154
 155    ctx->Const.MaxDrawBuffers = BRW_MAX_DRAW_BUFFERS;
 156    ctx->Const.MaxTextureImageUnits = BRW_MAX_TEX_UNIT;
 157    ctx->Const.MaxTextureCoordUnits = 8; /* Mesa limit */
 158    ctx->Const.MaxTextureUnits = MIN2(ctx->Const.MaxTextureCoordUnits,
 159                                      ctx->Const.MaxTextureImageUnits);
 160    ctx->Const.MaxVertexTextureImageUnits = 0; /* no vertex shader textures */
 161    ctx->Const.MaxCombinedTextureImageUnits =
 162       ctx->Const.MaxVertexTextureImageUnits +
 163       ctx->Const.MaxTextureImageUnits;
 164
 165    ctx->Const.MaxTextureLevels = 14; /* 8192 */
 166    if (ctx->Const.MaxTextureLevels > MAX_TEXTURE_LEVELS)
 167            ctx->Const.MaxTextureLevels = MAX_TEXTURE_LEVELS;
 168    ctx->Const.Max3DTextureLevels = 9;
 169    ctx->Const.MaxCubeTextureLevels = 12;
 170    /* minimum maximum.  Users are likely to run into memory problems
 171     * even at this size, since 64 * 2048 * 2048 * 4 = 1GB and we can't
 172     * address that much.
 173     */
 174    ctx->Const.MaxArrayTextureLayers = 64;
 175    ctx->Const.MaxTextureRectSize = (1<<12);
 176
 177    ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 178
 179    /* if conformance mode is set, swrast can handle any size AA point */
 180    ctx->Const.MaxPointSizeAA = 255.0;
 181
 182    /* We want the GLSL compiler to emit code that uses condition codes */
 183    for (i = 0; i <= MESA_SHADER_FRAGMENT; i++) {
 184       ctx->ShaderCompilerOptions[i].MaxIfDepth = intel->gen < 6 ? 16 : UINT_MAX;
 185       ctx->ShaderCompilerOptions[i].EmitCondCodes = true;
 186       ctx->ShaderCompilerOptions[i].EmitNVTempInitialization = true;
 187       ctx->ShaderCompilerOptions[i].EmitNoNoise = true;
 188       ctx->ShaderCompilerOptions[i].EmitNoMainReturn = true;
 189       ctx->ShaderCompilerOptions[i].EmitNoIndirectInput = true;
 190       ctx->ShaderCompilerOptions[i].EmitNoIndirectOutput = true;
 191
 192       ctx->ShaderCompilerOptions[i].EmitNoIndirectUniform =
 193          (i == MESA_SHADER_FRAGMENT);
 194       ctx->ShaderCompilerOptions[i].EmitNoIndirectTemp =
 195          (i == MESA_SHADER_FRAGMENT);
 196       ctx->ShaderCompilerOptions[i].LowerClipDistance = true;
 197    }
 198
 199    ctx->Const.VertexProgram.MaxNativeInstructions = (16 * 1024);
 200    ctx->Const.VertexProgram.MaxAluInstructions = 0;
 201    ctx->Const.VertexProgram.MaxTexInstructions = 0;
 202    ctx->Const.VertexProgram.MaxTexIndirections = 0;
 203    ctx->Const.VertexProgram.MaxNativeAluInstructions = 0;
 204    ctx->Const.VertexProgram.MaxNativeTexInstructions = 0;
 205    ctx->Const.VertexProgram.MaxNativeTexIndirections = 0;
 206    ctx->Const.VertexProgram.MaxNativeAttribs = 16;
 207    ctx->Const.VertexProgram.MaxNativeTemps = 256;
 208    ctx->Const.VertexProgram.MaxNativeAddressRegs = 1;
 209    ctx->Const.VertexProgram.MaxNativeParameters = 1024;
 210    ctx->Const.VertexProgram.MaxEnvParams =
 211       MIN2(ctx->Const.VertexProgram.MaxNativeParameters,
 212            ctx->Const.VertexProgram.MaxEnvParams);
 213
 214    ctx->Const.FragmentProgram.MaxNativeInstructions = (16 * 1024);
 215    ctx->Const.FragmentProgram.MaxNativeAluInstructions = (16 * 1024);
 216    ctx->Const.FragmentProgram.MaxNativeTexInstructions = (16 * 1024);
 217    ctx->Const.FragmentProgram.MaxNativeTexIndirections = (16 * 1024);
 218    ctx->Const.FragmentProgram.MaxNativeAttribs = 12;
 219    ctx->Const.FragmentProgram.MaxNativeTemps = 256;
 220    ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
 221    ctx->Const.FragmentProgram.MaxNativeParameters = 1024;
 222    ctx->Const.FragmentProgram.MaxEnvParams =
 223       MIN2(ctx->Const.FragmentProgram.MaxNativeParameters,
 224            ctx->Const.FragmentProgram.MaxEnvParams);
 225
 226    /* Fragment shaders use real, 32-bit twos-complement integers for all
 227     * integer types.
 228     */
 229    ctx->Const.FragmentProgram.LowInt.RangeMin = 31;
 230    ctx->Const.FragmentProgram.LowInt.RangeMax = 30;
 231    ctx->Const.FragmentProgram.LowInt.Precision = 0;
 232    ctx->Const.FragmentProgram.HighInt = ctx->Const.FragmentProgram.MediumInt
 233       = ctx->Const.FragmentProgram.LowInt;
 234
 235    /* Gen6 converts quads to polygon in beginning of 3D pipeline,
 236       but we're not sure how it's actually done for vertex order,
 237       that affect provoking vertex decision. Always use last vertex
 238       convention for quad primitive which works as expected for now. */
 239    if (intel->gen >= 6)
 240        ctx->Const.QuadsFollowProvokingVertexConvention = false;
 241
 242    if (intel->is_g4x || intel->gen >= 5) {
 243       brw->CMD_VF_STATISTICS = GM45_3DSTATE_VF_STATISTICS;
 244       brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_GM45;
 245       brw->has_surface_tile_offset = true;
 246       if (intel->gen < 6)
 247           brw->has_compr4 = true;
 248       brw->has_aa_line_parameters = true;
 249       brw->has_pln = true;
 250   } else {
 251       brw->CMD_VF_STATISTICS = GEN4_3DSTATE_VF_STATISTICS;
 252       brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_965;
 253    }
 254
 255    /* WM maximum threads is number of EUs times number of threads per EU. */
 256    if (intel->gen >= 7) {
 257       if (intel->gt == 1) {
 258          brw->max_wm_threads = 86;
 259          brw->max_vs_threads = 36;
 260          brw->max_gs_threads = 36;
 261          brw->urb.size = 128;
 262          brw->urb.max_vs_entries = 512;
 263          brw->urb.max_gs_entries = 192;
 264       } else if (intel->gt == 2) {
 265          brw->max_wm_threads = 86;
 266          brw->max_vs_threads = 128;
 267          brw->max_gs_threads = 128;
 268          brw->urb.size = 256;
 269          brw->urb.max_vs_entries = 704;
 270          brw->urb.max_gs_entries = 320;
 271       } else {
 272          assert(!"Unknown gen7 device.");
 273       }
 274    } else if (intel->gen == 6) {
 275       if (intel->gt == 2) {
 276          /* This could possibly be 80, but is supposed to require
 277           * disabling of WIZ hashing (bit 6 of GT_MODE, 0x20d0) and a
 278           * GPU reset to change.
 279           */
 280          brw->max_wm_threads = 40;
 281          brw->max_vs_threads = 60;
 282          brw->max_gs_threads = 60;
 283          brw->urb.size = 64;            /* volume 5c.5 section 5.1 */
 284          brw->urb.max_vs_entries = 256; /* volume 2a (see 3DSTATE_URB) */
 285       } else {
 286          brw->max_wm_threads = 40;
 287          brw->max_vs_threads = 24;
 288          brw->max_gs_threads = 21; /* conservative; 24 if rendering disabled */
 289          brw->urb.size = 32;            /* volume 5c.5 section 5.1 */
 290          brw->urb.max_vs_entries = 128; /* volume 2a (see 3DSTATE_URB) */
 291       }
 292    } else if (intel->gen == 5) {
 293       brw->urb.size = 1024;
 294       brw->max_vs_threads = 72;
 295       brw->max_gs_threads = 32;
 296       brw->max_wm_threads = 12 * 6;
 297    } else if (intel->is_g4x) {
 298       brw->urb.size = 384;
 299       brw->max_vs_threads = 32;
 300       brw->max_gs_threads = 2;
 301       brw->max_wm_threads = 10 * 5;
 302    } else if (intel->gen < 6) {
 303       brw->urb.size = 256;
 304       brw->max_vs_threads = 16;
 305       brw->max_gs_threads = 2;
 306       brw->max_wm_threads = 8 * 4;
 307       brw->has_negative_rhw_bug = true;
 308    }
 309
 310    brw_init_state( brw );
 311
 312    brw->curbe.last_buf = calloc(1, 4096);
 313    brw->curbe.next_buf = calloc(1, 4096);
 314
 315    brw->state.dirty.mesa = ~0;
 316    brw->state.dirty.brw = ~0;
 317
 318    brw->emit_state_always = 0;
 319
 320    intel->batch.need_workaround_flush = true;
 321
 322    ctx->VertexProgram._MaintainTnlProgram = true;
 323    ctx->FragmentProgram._MaintainTexEnvProgram = true;
 324
 325    brw_draw_init( brw );
 326
 327    brw->new_vs_backend = (getenv("INTEL_OLD_VS") == NULL);
 328
 329    /* If we're using the new shader backend, we require integer uniforms
 330     * stored as actual integers.
 331     */
 332    if (brw->new_vs_backend) {
 333       ctx->Const.NativeIntegers = true;
 334       ctx->Const.UniformBooleanTrue = 1;
 335    }
 336
 337    return true;
 338 }
 339