src/mesa/drivers/dri/i965/brw_context.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/imports.h"
  34 #include "main/macros.h"
  35 #include "main/simple_list.h"
  36
  37 #include "vbo/vbo_context.h"
  38
  39 #include "brw_context.h"
  40 #include "brw_defines.h"
  41 #include "brw_draw.h"
  42 #include "brw_state.h"
  43
  44 #include "gen6_hiz.h"
  45
  46 #include "intel_fbo.h"
  47 #include "intel_mipmap_tree.h"
  48 #include "intel_regions.h"
  49 #include "intel_span.h"
  50 #include "intel_tex.h"
  51 #include "intel_tex_obj.h"
  52
  53 #include "tnl/t_pipeline.h"
  54 #include "glsl/ralloc.h"
  55
  56 /***************************************
  57  * Mesa's Driver Functions
  58  ***************************************/
  59
  60 /**
  61  * \brief Prepare for entry into glBegin/glEnd block.
  62  *
  63  * Resolve buffers before entering a glBegin/glEnd block. This is
  64  * necessary to prevent recursive calls to FLUSH_VERTICES.
  65  *
  66  * This resolves the depth buffer of each enabled depth texture and the HiZ
  67  * buffer of the attached depth renderbuffer.
  68  *
  69  * Details
  70  * -------
  71  * When vertices are queued during a glBegin/glEnd block, those vertices must
  72  * be drawn before any rendering state changes. To ensure this, Mesa calls
  73  * FLUSH_VERTICES as a prehook to such state changes. Therefore,
  74  * FLUSH_VERTICES itself cannot change rendering state without falling into a
  75  * recursive trap.
  76  *
  77  * This precludes meta-ops, namely buffer resolves, from occurring while any
  78  * vertices are queued. To prevent that situation, we resolve some buffers on
  79  * entering a glBegin/glEnd
  80  *
  81  * \see brwCleanupExecEnd()
  82  */
  83 static void brwPrepareExecBegin(struct gl_context *ctx)
  84 {
  85    struct brw_context *brw = brw_context(ctx);
  86    struct intel_context *intel = &brw->intel;
  87    struct intel_renderbuffer *draw_irb;
  88    struct intel_texture_object *tex_obj;
  89
  90    if (!intel->has_hiz) {
  91       /* The context uses no feature that requires buffer resolves. */
  92       return;
  93    }
  94
  95    /* Resolve each enabled texture. */
  96    for (int i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
  97       if (!ctx->Texture.Unit[i]._ReallyEnabled)
  98          continue;
  99       tex_obj = intel_texture_object(ctx->Texture.Unit[i]._Current);
 100       if (!tex_obj || !tex_obj->mt)
 101          continue;
 102       intel_miptree_all_slices_resolve_depth(intel, tex_obj->mt);
 103    }
 104
 105    /* Resolve the attached depth buffer. */
 106    draw_irb = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);
 107    if (draw_irb) {
 108       intel_renderbuffer_resolve_hiz(intel, draw_irb);
 109    }
 110 }
 111
 112 static void brwInitDriverFunctions( struct dd_function_table *functions )
 113 {
 114    intelInitDriverFunctions( functions );
 115
 116    brwInitFragProgFuncs( functions );
 117    brw_init_queryobj_functions(functions);
 118
 119    functions->PrepareExecBegin = brwPrepareExecBegin;
 120    functions->EndTransformFeedback = brw_end_transform_feedback;
 121 }
 122
 123 bool
 124 brwCreateContext(int api,
 125                  const struct gl_config *mesaVis,
 126                  __DRIcontext *driContextPriv,
 127                  void *sharedContextPrivate)
 128 {
 129    struct dd_function_table functions;
 130    struct brw_context *brw = rzalloc(NULL, struct brw_context);
 131    struct intel_context *intel = &brw->intel;
 132    struct gl_context *ctx = &intel->ctx;
 133    unsigned i;
 134
 135    if (!brw) {
 136       printf("%s: failed to alloc context\n", __FUNCTION__);
 137       return false;
 138    }
 139
 140    brwInitDriverFunctions( &functions );
 141
 142    if (!intelInitContext( intel, api, mesaVis, driContextPriv,
 143                           sharedContextPrivate, &functions )) {
 144       printf("%s: failed to init intel context\n", __FUNCTION__);
 145       FREE(brw);
 146       return false;
 147    }
 148
 149    brwInitVtbl( brw );
 150
 151    brw_init_surface_formats(brw);
 152
 153    /* Initialize swrast, tnl driver tables: */
 154    intelInitSpanFuncs(ctx);
 155
 156    TNL_CONTEXT(ctx)->Driver.RunPipeline = _tnl_run_pipeline;
 157
 158    ctx->Const.MaxDrawBuffers = BRW_MAX_DRAW_BUFFERS;
 159    ctx->Const.MaxTextureImageUnits = BRW_MAX_TEX_UNIT;
 160    ctx->Const.MaxTextureCoordUnits = 8; /* Mesa limit */
 161    ctx->Const.MaxTextureUnits = MIN2(ctx->Const.MaxTextureCoordUnits,
 162                                      ctx->Const.MaxTextureImageUnits);
 163    ctx->Const.MaxVertexTextureImageUnits = BRW_MAX_TEX_UNIT;
 164    ctx->Const.MaxCombinedTextureImageUnits =
 165       ctx->Const.MaxVertexTextureImageUnits +
 166       ctx->Const.MaxTextureImageUnits;
 167
 168    ctx->Const.MaxTextureLevels = 14; /* 8192 */
 169    if (ctx->Const.MaxTextureLevels > MAX_TEXTURE_LEVELS)
 170            ctx->Const.MaxTextureLevels = MAX_TEXTURE_LEVELS;
 171    ctx->Const.Max3DTextureLevels = 9;
 172    ctx->Const.MaxCubeTextureLevels = 12;
 173    /* minimum maximum.  Users are likely to run into memory problems
 174     * even at this size, since 64 * 2048 * 2048 * 4 = 1GB and we can't
 175     * address that much.
 176     */
 177    ctx->Const.MaxArrayTextureLayers = 64;
 178    ctx->Const.MaxTextureRectSize = (1<<12);
 179
 180    ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 181
 182    /* Hardware only supports a limited number of transform feedback buffers.
 183     * So we need to override the Mesa default (which is based only on software
 184     * limits).
 185     */
 186    ctx->Const.MaxTransformFeedbackSeparateAttribs = BRW_MAX_SOL_BUFFERS;
 187
 188    /* On Gen6, in the worst case, we use up one binding table entry per
 189     * transform feedback component (see comments above the definition of
 190     * BRW_MAX_SOL_BINDINGS, in brw_context.h), so we need to advertise a value
 191     * for MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS equal to
 192     * BRW_MAX_SOL_BINDINGS.
 193     *
 194     * In "separate components" mode, we need to divide this value by
 195     * BRW_MAX_SOL_BUFFERS, so that the total number of binding table entries
 196     * used up by all buffers will not exceed BRW_MAX_SOL_BINDINGS.
 197     */
 198    ctx->Const.MaxTransformFeedbackInterleavedComponents = BRW_MAX_SOL_BINDINGS;
 199    ctx->Const.MaxTransformFeedbackSeparateComponents =
 200       BRW_MAX_SOL_BINDINGS / BRW_MAX_SOL_BUFFERS;
 201
 202    /* if conformance mode is set, swrast can handle any size AA point */
 203    ctx->Const.MaxPointSizeAA = 255.0;
 204
 205    /* We want the GLSL compiler to emit code that uses condition codes */
 206    for (i = 0; i <= MESA_SHADER_FRAGMENT; i++) {
 207       ctx->ShaderCompilerOptions[i].MaxIfDepth = intel->gen < 6 ? 16 : UINT_MAX;
 208       ctx->ShaderCompilerOptions[i].EmitCondCodes = true;
 209       ctx->ShaderCompilerOptions[i].EmitNVTempInitialization = true;
 210       ctx->ShaderCompilerOptions[i].EmitNoNoise = true;
 211       ctx->ShaderCompilerOptions[i].EmitNoMainReturn = true;
 212       ctx->ShaderCompilerOptions[i].EmitNoIndirectInput = true;
 213       ctx->ShaderCompilerOptions[i].EmitNoIndirectOutput = true;
 214
 215       ctx->ShaderCompilerOptions[i].EmitNoIndirectUniform =
 216          (i == MESA_SHADER_FRAGMENT);
 217       ctx->ShaderCompilerOptions[i].EmitNoIndirectTemp =
 218          (i == MESA_SHADER_FRAGMENT);
 219       ctx->ShaderCompilerOptions[i].LowerClipDistance = true;
 220    }
 221
 222    ctx->Const.VertexProgram.MaxNativeInstructions = (16 * 1024);
 223    ctx->Const.VertexProgram.MaxAluInstructions = 0;
 224    ctx->Const.VertexProgram.MaxTexInstructions = 0;
 225    ctx->Const.VertexProgram.MaxTexIndirections = 0;
 226    ctx->Const.VertexProgram.MaxNativeAluInstructions = 0;
 227    ctx->Const.VertexProgram.MaxNativeTexInstructions = 0;
 228    ctx->Const.VertexProgram.MaxNativeTexIndirections = 0;
 229    ctx->Const.VertexProgram.MaxNativeAttribs = 16;
 230    ctx->Const.VertexProgram.MaxNativeTemps = 256;
 231    ctx->Const.VertexProgram.MaxNativeAddressRegs = 1;
 232    ctx->Const.VertexProgram.MaxNativeParameters = 1024;
 233    ctx->Const.VertexProgram.MaxEnvParams =
 234       MIN2(ctx->Const.VertexProgram.MaxNativeParameters,
 235            ctx->Const.VertexProgram.MaxEnvParams);
 236
 237    ctx->Const.FragmentProgram.MaxNativeInstructions = (16 * 1024);
 238    ctx->Const.FragmentProgram.MaxNativeAluInstructions = (16 * 1024);
 239    ctx->Const.FragmentProgram.MaxNativeTexInstructions = (16 * 1024);
 240    ctx->Const.FragmentProgram.MaxNativeTexIndirections = (16 * 1024);
 241    ctx->Const.FragmentProgram.MaxNativeAttribs = 12;
 242    ctx->Const.FragmentProgram.MaxNativeTemps = 256;
 243    ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
 244    ctx->Const.FragmentProgram.MaxNativeParameters = 1024;
 245    ctx->Const.FragmentProgram.MaxEnvParams =
 246       MIN2(ctx->Const.FragmentProgram.MaxNativeParameters,
 247            ctx->Const.FragmentProgram.MaxEnvParams);
 248
 249    /* Fragment shaders use real, 32-bit twos-complement integers for all
 250     * integer types.
 251     */
 252    ctx->Const.FragmentProgram.LowInt.RangeMin = 31;
 253    ctx->Const.FragmentProgram.LowInt.RangeMax = 30;
 254    ctx->Const.FragmentProgram.LowInt.Precision = 0;
 255    ctx->Const.FragmentProgram.HighInt = ctx->Const.FragmentProgram.MediumInt
 256       = ctx->Const.FragmentProgram.LowInt;
 257
 258    /* Gen6 converts quads to polygon in beginning of 3D pipeline,
 259       but we're not sure how it's actually done for vertex order,
 260       that affect provoking vertex decision. Always use last vertex
 261       convention for quad primitive which works as expected for now. */
 262    if (intel->gen >= 6)
 263        ctx->Const.QuadsFollowProvokingVertexConvention = false;
 264
 265    if (intel->is_g4x || intel->gen >= 5) {
 266       brw->CMD_VF_STATISTICS = GM45_3DSTATE_VF_STATISTICS;
 267       brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_GM45;
 268       brw->has_surface_tile_offset = true;
 269       if (intel->gen < 6)
 270           brw->has_compr4 = true;
 271       brw->has_aa_line_parameters = true;
 272       brw->has_pln = true;
 273   } else {
 274       brw->CMD_VF_STATISTICS = GEN4_3DSTATE_VF_STATISTICS;
 275       brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_965;
 276    }
 277
 278    /* WM maximum threads is number of EUs times number of threads per EU. */
 279    if (intel->gen >= 7) {
 280       if (intel->gt == 1) {
 281          brw->max_wm_threads = 86;
 282          brw->max_vs_threads = 36;
 283          brw->max_gs_threads = 36;
 284          brw->urb.size = 128;
 285          brw->urb.max_vs_entries = 512;
 286          brw->urb.max_gs_entries = 192;
 287       } else if (intel->gt == 2) {
 288          brw->max_wm_threads = 86;
 289          brw->max_vs_threads = 128;
 290          brw->max_gs_threads = 128;
 291          brw->urb.size = 256;
 292          brw->urb.max_vs_entries = 704;
 293          brw->urb.max_gs_entries = 320;
 294       } else {
 295          assert(!"Unknown gen7 device.");
 296       }
 297    } else if (intel->gen == 6) {
 298       if (intel->gt == 2) {
 299          /* This could possibly be 80, but is supposed to require
 300           * disabling of WIZ hashing (bit 6 of GT_MODE, 0x20d0) and a
 301           * GPU reset to change.
 302           */
 303          brw->max_wm_threads = 40;
 304          brw->max_vs_threads = 60;
 305          brw->max_gs_threads = 60;
 306          brw->urb.size = 64;            /* volume 5c.5 section 5.1 */
 307          brw->urb.max_vs_entries = 256; /* volume 2a (see 3DSTATE_URB) */
 308          brw->urb.max_gs_entries = 256;
 309       } else {
 310          brw->max_wm_threads = 40;
 311          brw->max_vs_threads = 24;
 312          brw->max_gs_threads = 21; /* conservative; 24 if rendering disabled */
 313          brw->urb.size = 32;            /* volume 5c.5 section 5.1 */
 314          brw->urb.max_vs_entries = 128; /* volume 2a (see 3DSTATE_URB) */
 315          brw->urb.max_gs_entries = 256;
 316       }
 317       brw->urb.gen6_gs_previously_active = false;
 318    } else if (intel->gen == 5) {
 319       brw->urb.size = 1024;
 320       brw->max_vs_threads = 72;
 321       brw->max_gs_threads = 32;
 322       brw->max_wm_threads = 12 * 6;
 323    } else if (intel->is_g4x) {
 324       brw->urb.size = 384;
 325       brw->max_vs_threads = 32;
 326       brw->max_gs_threads = 2;
 327       brw->max_wm_threads = 10 * 5;
 328    } else if (intel->gen < 6) {
 329       brw->urb.size = 256;
 330       brw->max_vs_threads = 16;
 331       brw->max_gs_threads = 2;
 332       brw->max_wm_threads = 8 * 4;
 333       brw->has_negative_rhw_bug = true;
 334    }
 335
 336    brw_init_state( brw );
 337
 338    brw->curbe.last_buf = calloc(1, 4096);
 339    brw->curbe.next_buf = calloc(1, 4096);
 340
 341    brw->state.dirty.mesa = ~0;
 342    brw->state.dirty.brw = ~0;
 343
 344    brw->emit_state_always = 0;
 345
 346    intel->batch.need_workaround_flush = true;
 347
 348    ctx->VertexProgram._MaintainTnlProgram = true;
 349    ctx->FragmentProgram._MaintainTexEnvProgram = true;
 350
 351    brw_draw_init( brw );
 352
 353    brw->new_vs_backend = (getenv("INTEL_OLD_VS") == NULL);
 354    brw->precompile = driQueryOptionb(&intel->optionCache, "shader_precompile");
 355
 356    /* If we're using the new shader backend, we require integer uniforms
 357     * stored as actual integers.
 358     */
 359    if (brw->new_vs_backend) {
 360       ctx->Const.NativeIntegers = true;
 361       ctx->Const.UniformBooleanTrue = 1;
 362    }
 363
 364    return true;
 365 }
 366