src/mesa/drivers/dri/i965/brw_context.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/api_exec.h"
  34 #include "main/imports.h"
  35 #include "main/macros.h"
  36 #include "main/simple_list.h"
  37 #include "main/version.h"
  38 #include "main/vtxfmt.h"
  39
  40 #include "vbo/vbo_context.h"
  41
  42 #include "brw_context.h"
  43 #include "brw_defines.h"
  44 #include "brw_draw.h"
  45 #include "brw_state.h"
  46
  47 #include "intel_fbo.h"
  48 #include "intel_mipmap_tree.h"
  49 #include "intel_regions.h"
  50 #include "intel_tex.h"
  51 #include "intel_tex_obj.h"
  52
  53 #include "tnl/t_pipeline.h"
  54 #include "glsl/ralloc.h"
  55
  56 /***************************************
  57  * Mesa's Driver Functions
  58  ***************************************/
  59
  60 static size_t
  61 brw_query_samples_for_format(struct gl_context *ctx, GLenum target,
  62                              GLenum internalFormat, int samples[16])
  63 {
  64    struct intel_context *intel = intel_context(ctx);
  65
  66    (void) target;
  67
  68    switch (intel->gen) {
  69    case 7:
  70       samples[0] = 8;
  71       samples[1] = 4;
  72       return 2;
  73
  74    case 6:
  75       samples[0] = 4;
  76       return 1;
  77
  78    default:
  79       samples[0] = 1;
  80       return 1;
  81    }
  82 }
  83
  84 static void brwInitDriverFunctions(struct intel_screen *screen,
  85                                    struct dd_function_table *functions)
  86 {
  87    intelInitDriverFunctions( functions );
  88
  89    brwInitFragProgFuncs( functions );
  90    brw_init_queryobj_functions(functions);
  91
  92    functions->QuerySamplesForFormat = brw_query_samples_for_format;
  93    functions->BeginTransformFeedback = brw_begin_transform_feedback;
  94
  95    if (screen->gen >= 7)
  96       functions->EndTransformFeedback = gen7_end_transform_feedback;
  97    else
  98       functions->EndTransformFeedback = brw_end_transform_feedback;
  99
 100    if (screen->gen >= 6)
 101       functions->GetSamplePosition = gen6_get_sample_position;
 102 }
 103
 104 bool
 105 brwCreateContext(int api,
 106                  const struct gl_config *mesaVis,
 107                  __DRIcontext *driContextPriv,
 108                  unsigned major_version,
 109                  unsigned minor_version,
 110                  uint32_t flags,
 111                  unsigned *error,
 112                  void *sharedContextPrivate)
 113 {
 114    __DRIscreen *sPriv = driContextPriv->driScreenPriv;
 115    struct intel_screen *screen = sPriv->driverPrivate;
 116    struct dd_function_table functions;
 117    unsigned i;
 118
 119    struct brw_context *brw = rzalloc(NULL, struct brw_context);
 120    if (!brw) {
 121       printf("%s: failed to alloc context\n", __FUNCTION__);
 122       *error = __DRI_CTX_ERROR_NO_MEMORY;
 123       return false;
 124    }
 125
 126    /* brwInitVtbl needs to know the chipset generation so that it can set the
 127     * right pointers.
 128     */
 129    brw->intel.gen = screen->gen;
 130
 131    brwInitVtbl( brw );
 132
 133    brwInitDriverFunctions(screen, &functions);
 134
 135    struct intel_context *intel = &brw->intel;
 136    struct gl_context *ctx = &intel->ctx;
 137
 138    if (!intelInitContext( intel, api, major_version, minor_version,
 139                           mesaVis, driContextPriv,
 140                           sharedContextPrivate, &functions,
 141                           error)) {
 142       ralloc_free(brw);
 143       return false;
 144    }
 145
 146    if (intel->gen >= 6) {
 147       /* Create a new hardware context.  Using a hardware context means that
 148        * our GPU state will be saved/restored on context switch, allowing us
 149        * to assume that the GPU is in the same state we left it in.
 150        *
 151        * This is required for transform feedback buffer offsets, query objects,
 152        * and also allows us to reduce how much state we have to emit.
 153        */
 154       intel->hw_ctx = drm_intel_gem_context_create(intel->bufmgr);
 155
 156       if (!intel->hw_ctx) {
 157          fprintf(stderr, "Gen6+ requires Kernel 3.6 or later.\n");
 158          ralloc_free(brw);
 159          return false;
 160       }
 161    }
 162
 163    brw_init_surface_formats(brw);
 164
 165    /* Initialize swrast, tnl driver tables: */
 166    TNLcontext *tnl = TNL_CONTEXT(ctx);
 167    if (tnl)
 168       tnl->Driver.RunPipeline = _tnl_run_pipeline;
 169
 170    ctx->DriverFlags.NewTransformFeedback = BRW_NEW_TRANSFORM_FEEDBACK;
 171    ctx->DriverFlags.NewRasterizerDiscard = BRW_NEW_RASTERIZER_DISCARD;
 172    ctx->DriverFlags.NewUniformBuffer = BRW_NEW_UNIFORM_BUFFER;
 173
 174    ctx->Const.MaxDualSourceDrawBuffers = 1;
 175    ctx->Const.MaxDrawBuffers = BRW_MAX_DRAW_BUFFERS;
 176    ctx->Const.FragmentProgram.MaxTextureImageUnits = BRW_MAX_TEX_UNIT;
 177    ctx->Const.MaxTextureCoordUnits = 8; /* Mesa limit */
 178    ctx->Const.MaxTextureUnits = MIN2(ctx->Const.MaxTextureCoordUnits,
 179                                      ctx->Const.FragmentProgram.MaxTextureImageUnits);
 180    ctx->Const.VertexProgram.MaxTextureImageUnits = BRW_MAX_TEX_UNIT;
 181    ctx->Const.MaxCombinedTextureImageUnits =
 182       ctx->Const.VertexProgram.MaxTextureImageUnits +
 183       ctx->Const.FragmentProgram.MaxTextureImageUnits;
 184
 185    ctx->Const.MaxTextureLevels = 14; /* 8192 */
 186    if (ctx->Const.MaxTextureLevels > MAX_TEXTURE_LEVELS)
 187            ctx->Const.MaxTextureLevels = MAX_TEXTURE_LEVELS;
 188    ctx->Const.Max3DTextureLevels = 9;
 189    ctx->Const.MaxCubeTextureLevels = 12;
 190
 191    if (intel->gen >= 7)
 192       ctx->Const.MaxArrayTextureLayers = 2048;
 193    else
 194       ctx->Const.MaxArrayTextureLayers = 512;
 195
 196    ctx->Const.MaxTextureRectSize = (1<<12);
 197
 198    ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 199
 200    /* Hardware only supports a limited number of transform feedback buffers.
 201     * So we need to override the Mesa default (which is based only on software
 202     * limits).
 203     */
 204    ctx->Const.MaxTransformFeedbackBuffers = BRW_MAX_SOL_BUFFERS;
 205
 206    /* On Gen6, in the worst case, we use up one binding table entry per
 207     * transform feedback component (see comments above the definition of
 208     * BRW_MAX_SOL_BINDINGS, in brw_context.h), so we need to advertise a value
 209     * for MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS equal to
 210     * BRW_MAX_SOL_BINDINGS.
 211     *
 212     * In "separate components" mode, we need to divide this value by
 213     * BRW_MAX_SOL_BUFFERS, so that the total number of binding table entries
 214     * used up by all buffers will not exceed BRW_MAX_SOL_BINDINGS.
 215     */
 216    ctx->Const.MaxTransformFeedbackInterleavedComponents = BRW_MAX_SOL_BINDINGS;
 217    ctx->Const.MaxTransformFeedbackSeparateComponents =
 218       BRW_MAX_SOL_BINDINGS / BRW_MAX_SOL_BUFFERS;
 219
 220    if (intel->gen == 6) {
 221       ctx->Const.MaxSamples = 4;
 222       ctx->Const.MaxColorTextureSamples = 4;
 223       ctx->Const.MaxDepthTextureSamples = 4;
 224       ctx->Const.MaxIntegerSamples = 4;
 225    }
 226    else if (intel->gen >= 7) {
 227       ctx->Const.MaxSamples = 8;
 228       ctx->Const.MaxColorTextureSamples = 8;
 229       ctx->Const.MaxDepthTextureSamples = 8;
 230       ctx->Const.MaxIntegerSamples = 8;
 231    }
 232
 233    /* if conformance mode is set, swrast can handle any size AA point */
 234    ctx->Const.MaxPointSizeAA = 255.0;
 235
 236    /* We want the GLSL compiler to emit code that uses condition codes */
 237    for (i = 0; i <= MESA_SHADER_FRAGMENT; i++) {
 238       ctx->ShaderCompilerOptions[i].MaxIfDepth = intel->gen < 6 ? 16 : UINT_MAX;
 239       ctx->ShaderCompilerOptions[i].EmitCondCodes = true;
 240       ctx->ShaderCompilerOptions[i].EmitNoNoise = true;
 241       ctx->ShaderCompilerOptions[i].EmitNoMainReturn = true;
 242       ctx->ShaderCompilerOptions[i].EmitNoIndirectInput = true;
 243       ctx->ShaderCompilerOptions[i].EmitNoIndirectOutput = true;
 244
 245       ctx->ShaderCompilerOptions[i].EmitNoIndirectUniform =
 246          (i == MESA_SHADER_FRAGMENT);
 247       ctx->ShaderCompilerOptions[i].EmitNoIndirectTemp =
 248          (i == MESA_SHADER_FRAGMENT);
 249       ctx->ShaderCompilerOptions[i].LowerClipDistance = true;
 250    }
 251
 252    ctx->ShaderCompilerOptions[MESA_SHADER_VERTEX].PreferDP4 = true;
 253
 254    ctx->Const.VertexProgram.MaxNativeInstructions = (16 * 1024);
 255    ctx->Const.VertexProgram.MaxAluInstructions = 0;
 256    ctx->Const.VertexProgram.MaxTexInstructions = 0;
 257    ctx->Const.VertexProgram.MaxTexIndirections = 0;
 258    ctx->Const.VertexProgram.MaxNativeAluInstructions = 0;
 259    ctx->Const.VertexProgram.MaxNativeTexInstructions = 0;
 260    ctx->Const.VertexProgram.MaxNativeTexIndirections = 0;
 261    ctx->Const.VertexProgram.MaxNativeAttribs = 16;
 262    ctx->Const.VertexProgram.MaxNativeTemps = 256;
 263    ctx->Const.VertexProgram.MaxNativeAddressRegs = 1;
 264    ctx->Const.VertexProgram.MaxNativeParameters = 1024;
 265    ctx->Const.VertexProgram.MaxEnvParams =
 266       MIN2(ctx->Const.VertexProgram.MaxNativeParameters,
 267            ctx->Const.VertexProgram.MaxEnvParams);
 268
 269    ctx->Const.FragmentProgram.MaxNativeInstructions = (1 * 1024);
 270    ctx->Const.FragmentProgram.MaxNativeAluInstructions = (1 * 1024);
 271    ctx->Const.FragmentProgram.MaxNativeTexInstructions = (1 * 1024);
 272    ctx->Const.FragmentProgram.MaxNativeTexIndirections = (1 * 1024);
 273    ctx->Const.FragmentProgram.MaxNativeAttribs = 12;
 274    ctx->Const.FragmentProgram.MaxNativeTemps = 256;
 275    ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
 276    ctx->Const.FragmentProgram.MaxNativeParameters = 1024;
 277    ctx->Const.FragmentProgram.MaxEnvParams =
 278       MIN2(ctx->Const.FragmentProgram.MaxNativeParameters,
 279            ctx->Const.FragmentProgram.MaxEnvParams);
 280
 281    /* Fragment shaders use real, 32-bit twos-complement integers for all
 282     * integer types.
 283     */
 284    ctx->Const.FragmentProgram.LowInt.RangeMin = 31;
 285    ctx->Const.FragmentProgram.LowInt.RangeMax = 30;
 286    ctx->Const.FragmentProgram.LowInt.Precision = 0;
 287    ctx->Const.FragmentProgram.HighInt = ctx->Const.FragmentProgram.MediumInt
 288       = ctx->Const.FragmentProgram.LowInt;
 289
 290    /* Gen6 converts quads to polygon in beginning of 3D pipeline,
 291       but we're not sure how it's actually done for vertex order,
 292       that affect provoking vertex decision. Always use last vertex
 293       convention for quad primitive which works as expected for now. */
 294    if (intel->gen >= 6)
 295        ctx->Const.QuadsFollowProvokingVertexConvention = false;
 296
 297    ctx->Const.QueryCounterBits.Timestamp = 36;
 298
 299    if (intel->is_g4x || intel->gen >= 5) {
 300       brw->CMD_VF_STATISTICS = GM45_3DSTATE_VF_STATISTICS;
 301       brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_GM45;
 302       brw->has_surface_tile_offset = true;
 303       if (intel->gen < 6)
 304           brw->has_compr4 = true;
 305       brw->has_aa_line_parameters = true;
 306       brw->has_pln = true;
 307   } else {
 308       brw->CMD_VF_STATISTICS = GEN4_3DSTATE_VF_STATISTICS;
 309       brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_965;
 310    }
 311
 312    /* WM maximum threads is number of EUs times number of threads per EU. */
 313    assert(intel->gen <= 7);
 314
 315    if (intel->is_haswell) {
 316       if (intel->gt == 1) {
 317          brw->max_wm_threads = 102;
 318          brw->max_vs_threads = 70;
 319          brw->urb.size = 128;
 320          brw->urb.max_vs_entries = 640;
 321          brw->urb.max_gs_entries = 256;
 322       } else if (intel->gt == 2) {
 323          brw->max_wm_threads = 204;
 324          brw->max_vs_threads = 280;
 325          brw->urb.size = 256;
 326          brw->urb.max_vs_entries = 1664;
 327          brw->urb.max_gs_entries = 640;
 328       } else if (intel->gt == 3) {
 329          brw->max_wm_threads = 408;
 330          brw->max_vs_threads = 280;
 331          brw->urb.size = 512;
 332          brw->urb.max_vs_entries = 1664;
 333          brw->urb.max_gs_entries = 640;
 334       }
 335    } else if (intel->gen == 7) {
 336       if (intel->gt == 1) {
 337          brw->max_wm_threads = 48;
 338          brw->max_vs_threads = 36;
 339          brw->max_gs_threads = 36;
 340          brw->urb.size = 128;
 341          brw->urb.max_vs_entries = 512;
 342          brw->urb.max_gs_entries = 192;
 343       } else if (intel->gt == 2) {
 344          brw->max_wm_threads = 172;
 345          brw->max_vs_threads = 128;
 346          brw->max_gs_threads = 128;
 347          brw->urb.size = 256;
 348          brw->urb.max_vs_entries = 704;
 349          brw->urb.max_gs_entries = 320;
 350       } else {
 351          assert(!"Unknown gen7 device.");
 352       }
 353    } else if (intel->gen == 6) {
 354       if (intel->gt == 2) {
 355          brw->max_wm_threads = 80;
 356          brw->max_vs_threads = 60;
 357          brw->max_gs_threads = 60;
 358          brw->urb.size = 64;            /* volume 5c.5 section 5.1 */
 359          brw->urb.max_vs_entries = 256; /* volume 2a (see 3DSTATE_URB) */
 360          brw->urb.max_gs_entries = 256;
 361       } else {
 362          brw->max_wm_threads = 40;
 363          brw->max_vs_threads = 24;
 364          brw->max_gs_threads = 21; /* conservative; 24 if rendering disabled */
 365          brw->urb.size = 32;            /* volume 5c.5 section 5.1 */
 366          brw->urb.max_vs_entries = 256; /* volume 2a (see 3DSTATE_URB) */
 367          brw->urb.max_gs_entries = 256;
 368       }
 369       brw->urb.gen6_gs_previously_active = false;
 370    } else if (intel->gen == 5) {
 371       brw->urb.size = 1024;
 372       brw->max_vs_threads = 72;
 373       brw->max_gs_threads = 32;
 374       brw->max_wm_threads = 12 * 6;
 375    } else if (intel->is_g4x) {
 376       brw->urb.size = 384;
 377       brw->max_vs_threads = 32;
 378       brw->max_gs_threads = 2;
 379       brw->max_wm_threads = 10 * 5;
 380    } else if (intel->gen < 6) {
 381       brw->urb.size = 256;
 382       brw->max_vs_threads = 16;
 383       brw->max_gs_threads = 2;
 384       brw->max_wm_threads = 8 * 4;
 385       brw->has_negative_rhw_bug = true;
 386    }
 387
 388    if (intel->gen <= 7) {
 389       brw->needs_unlit_centroid_workaround = true;
 390    }
 391
 392    brw->prim_restart.in_progress = false;
 393    brw->prim_restart.enable_cut_index = false;
 394
 395    brw_init_state( brw );
 396
 397    brw->curbe.last_buf = calloc(1, 4096);
 398    brw->curbe.next_buf = calloc(1, 4096);
 399
 400    brw->state.dirty.mesa = ~0;
 401    brw->state.dirty.brw = ~0;
 402
 403    brw->emit_state_always = 0;
 404
 405    intel->batch.need_workaround_flush = true;
 406
 407    ctx->VertexProgram._MaintainTnlProgram = true;
 408    ctx->FragmentProgram._MaintainTexEnvProgram = true;
 409
 410    brw_draw_init( brw );
 411
 412    brw->precompile = driQueryOptionb(&intel->optionCache, "shader_precompile");
 413
 414    ctx->Const.NativeIntegers = true;
 415    ctx->Const.UniformBooleanTrue = 1;
 416    ctx->Const.UniformBufferOffsetAlignment = 16;
 417
 418    ctx->Const.ForceGLSLExtensionsWarn = driQueryOptionb(&intel->optionCache, "force_glsl_extensions_warn");
 419
 420    ctx->Const.DisableGLSLLineContinuations = driQueryOptionb(&intel->optionCache, "disable_glsl_line_continuations");
 421
 422    ctx->Const.ContextFlags = 0;
 423    if ((flags & __DRI_CTX_FLAG_FORWARD_COMPATIBLE) != 0)
 424       ctx->Const.ContextFlags |= GL_CONTEXT_FLAG_FORWARD_COMPATIBLE_BIT;
 425
 426    if ((flags & __DRI_CTX_FLAG_DEBUG) != 0) {
 427       ctx->Const.ContextFlags |= GL_CONTEXT_FLAG_DEBUG_BIT;
 428
 429       /* Turn on some extra GL_ARB_debug_output generation. */
 430       intel->perf_debug = true;
 431    }
 432
 433    brw_fs_alloc_reg_sets(brw);
 434
 435    if (INTEL_DEBUG & DEBUG_SHADER_TIME)
 436       brw_init_shader_time(brw);
 437
 438    _mesa_compute_version(ctx);
 439
 440    _mesa_initialize_dispatch_tables(ctx);
 441    _mesa_initialize_vbo_vtxfmt(ctx);
 442
 443    return true;
 444 }
 445