2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
38 #include "main/imports.h"
39 #include "main/macros.h"
41 #include "main/mtypes.h"
42 #include "brw_structs.h"
43 #include "intel_aub.h"
44 #include "program/prog_parameter.h"
48 /* Evil hack for using libdrm in a c++ compiler. */
53 #include <intel_bufmgr.h>
63 #include "intel_debug.h"
64 #include "intel_screen.h"
65 #include "intel_tex_obj.h"
66 #include "intel_resolve_map.h"
70 * URB - uniform resource buffer. A mid-sized buffer which is
71 * partitioned between the fixed function units and used for passing
72 * values (vertices, primitives, constants) between them.
74 * CURBE - constant URB entry. An urb region (entry) used to hold
75 * constant values which the fixed function units can be instructed to
76 * preload into the GRF when spawning a thread.
78 * VUE - vertex URB entry. An urb entry holding a vertex and usually
79 * a vertex header. The header contains control information and
80 * things like primitive type, Begin/end flags and clip codes.
82 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
83 * unit holding rasterization and interpolation parameters.
85 * GRF - general register file. One of several register files
86 * addressable by programmed threads. The inputs (r0, payload, curbe,
87 * urb) of the thread are preloaded to this area before the thread is
88 * spawned. The registers are individually 8 dwords wide and suitable
89 * for general usage. Registers holding thread input values are not
90 * special and may be overwritten.
92 * MRF - message register file. Threads communicate (and terminate)
93 * by sending messages. Message parameters are placed in contiguous
94 * MRF registers. All program output is via these messages. URB
95 * entries are populated by sending a message to the shared URB
96 * function containing the new data, together with a control word,
97 * often an unmodified copy of R0.
99 * R0 - GRF register 0. Typically holds control information used when
100 * sending messages to other threads.
102 * EU or GEN4 EU: The name of the programmable subsystem of the
103 * i965 hardware. Threads are executed by the EU, the registers
104 * described above are part of the EU architecture.
106 * Fixed function units:
108 * CS - Command streamer. Notional first unit, little software
109 * interaction. Holds the URB entries used for constant data, ie the
112 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
113 * this unit is responsible for pulling vertices out of vertex buffers
114 * in vram and injecting them into the processing pipe as VUEs. If
115 * enabled, it first passes them to a VS thread which is a good place
116 * for the driver to implement any active vertex shader.
118 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
119 * enabled, incoming strips etc are passed to GS threads in individual
120 * line/triangle/point units. The GS thread may perform arbitary
121 * computation and emit whatever primtives with whatever vertices it
122 * chooses. This makes GS an excellent place to implement GL's
123 * unfilled polygon modes, though of course it is capable of much
124 * more. Additionally, GS is used to translate away primitives not
125 * handled by latter units, including Quads and Lineloops.
127 * CS - Clipper. Mesa's clipping algorithms are imported to run on
128 * this unit. The fixed function part performs cliptesting against
129 * the 6 fixed clipplanes and makes descisions on whether or not the
130 * incoming primitive needs to be passed to a thread for clipping.
131 * User clip planes are handled via cooperation with the VS thread.
133 * SF - Strips Fans or Setup: Triangles are prepared for
134 * rasterization. Interpolation coefficients are calculated.
135 * Flatshading and two-side lighting usually performed here.
137 * WM - Windower. Interpolation of vertex attributes performed here.
138 * Fragment shader implemented here. SIMD aspects of EU taken full
139 * advantage of, as pixels are processed in blocks of 16.
141 * CC - Color Calculator. No EU threads associated with this unit.
142 * Handles blending and (presumably) depth and stencil testing.
147 struct brw_vs_prog_key
;
148 struct brw_vue_prog_key
;
149 struct brw_wm_prog_key
;
150 struct brw_wm_prog_data
;
151 struct brw_cs_prog_key
;
152 struct brw_cs_prog_data
;
156 BRW_COMPUTE_PIPELINE
,
163 BRW_CACHE_BLORP_BLIT_PROG
,
166 BRW_CACHE_FF_GS_PROG
,
175 /* brw_cache_ids must come first - see brw_state_cache.c */
176 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
177 BRW_STATE_FRAGMENT_PROGRAM
,
178 BRW_STATE_GEOMETRY_PROGRAM
,
179 BRW_STATE_VERTEX_PROGRAM
,
180 BRW_STATE_CURBE_OFFSETS
,
181 BRW_STATE_REDUCED_PRIMITIVE
,
186 BRW_STATE_VS_BINDING_TABLE
,
187 BRW_STATE_GS_BINDING_TABLE
,
188 BRW_STATE_PS_BINDING_TABLE
,
192 BRW_STATE_INDEX_BUFFER
,
193 BRW_STATE_VS_CONSTBUF
,
194 BRW_STATE_GS_CONSTBUF
,
195 BRW_STATE_PROGRAM_CACHE
,
196 BRW_STATE_STATE_BASE_ADDRESS
,
197 BRW_STATE_VUE_MAP_VS
,
198 BRW_STATE_VUE_MAP_GEOM_OUT
,
199 BRW_STATE_TRANSFORM_FEEDBACK
,
200 BRW_STATE_RASTERIZER_DISCARD
,
202 BRW_STATE_UNIFORM_BUFFER
,
203 BRW_STATE_ATOMIC_BUFFER
,
204 BRW_STATE_IMAGE_UNITS
,
205 BRW_STATE_META_IN_PROGRESS
,
206 BRW_STATE_INTERPOLATION_MAP
,
207 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
208 BRW_STATE_NUM_SAMPLES
,
209 BRW_STATE_TEXTURE_BUFFER
,
210 BRW_STATE_GEN4_UNIT_STATE
,
214 BRW_STATE_SAMPLER_STATE_TABLE
,
215 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
216 BRW_STATE_COMPUTE_PROGRAM
,
221 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
223 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
224 * When the currently bound shader program differs from the previous draw
225 * call, these will be flagged. They cover brw->{stage}_program and
226 * ctx->{Stage}Program->_Current.
228 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
229 * driver perspective. Even if the same shader is bound at the API level,
230 * we may need to switch between multiple versions of that shader to handle
231 * changes in non-orthagonal state.
233 * Additionally, multiple shader programs may have identical vertex shaders
234 * (for example), or compile down to the same code in the backend. We combine
235 * those into a single program cache entry.
237 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
238 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
240 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
241 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
242 * use the normal state upload paths), but the cache is still used. To avoid
243 * polluting the brw_state_cache code with special cases, we retain the dirty
244 * bit for now. It should eventually be removed.
246 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_BLIT_PROG)
247 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
248 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
249 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
250 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
251 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
252 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
253 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
254 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
255 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
256 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
257 #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
258 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
259 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
260 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
261 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
262 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
263 #define BRW_NEW_VS_BINDING_TABLE (1ull << BRW_STATE_VS_BINDING_TABLE)
264 #define BRW_NEW_GS_BINDING_TABLE (1ull << BRW_STATE_GS_BINDING_TABLE)
265 #define BRW_NEW_PS_BINDING_TABLE (1ull << BRW_STATE_PS_BINDING_TABLE)
266 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
267 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
269 * Used for any batch entry with a relocated pointer that will be used
270 * by any 3D rendering.
272 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
273 /** \see brw.state.depth_region */
274 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
275 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
276 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
277 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
278 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
279 #define BRW_NEW_VUE_MAP_VS (1ull << BRW_STATE_VUE_MAP_VS)
280 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
281 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
282 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
283 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
284 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
285 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
286 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
287 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
288 #define BRW_NEW_INTERPOLATION_MAP (1ull << BRW_STATE_INTERPOLATION_MAP)
289 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
290 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
291 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
292 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
293 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
294 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
295 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
296 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
297 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
298 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
300 struct brw_state_flags
{
301 /** State update flags signalled by mesa internals */
304 * State update flags signalled as the result of brw_tracked_state updates
309 /** Subclass of Mesa vertex program */
310 struct brw_vertex_program
{
311 struct gl_vertex_program program
;
316 /** Subclass of Mesa geometry program */
317 struct brw_geometry_program
{
318 struct gl_geometry_program program
;
319 unsigned id
; /**< serial no. to identify geom progs, never re-used */
323 /** Subclass of Mesa fragment program */
324 struct brw_fragment_program
{
325 struct gl_fragment_program program
;
326 GLuint id
; /**< serial no. to identify frag progs, never re-used */
330 /** Subclass of Mesa compute program */
331 struct brw_compute_program
{
332 struct gl_compute_program program
;
333 unsigned id
; /**< serial no. to identify compute progs, never re-used */
338 struct gl_shader base
;
343 /* Note: If adding fields that need anything besides a normal memcmp() for
344 * comparing them, be sure to go fix brw_stage_prog_data_compare().
346 struct brw_stage_prog_data
{
348 /** size of our binding table. */
352 * surface indices for the various groups of surfaces
354 uint32_t pull_constants_start
;
355 uint32_t texture_start
;
356 uint32_t gather_texture_start
;
359 uint32_t image_start
;
360 uint32_t shader_time_start
;
364 GLuint nr_params
; /**< number of float params/constants */
365 GLuint nr_pull_params
;
366 unsigned nr_image_params
;
368 unsigned curb_read_length
;
369 unsigned total_scratch
;
372 * Register where the thread expects to find input data from the URB
373 * (typically uniforms, followed by vertex or fragment attributes).
375 unsigned dispatch_grf_start_reg
;
377 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
379 /* Pointers to tracked values (only valid once
380 * _mesa_load_state_parameters has been called at runtime).
382 * These must be the last fields of the struct (see
383 * brw_stage_prog_data_compare()).
385 const gl_constant_value
**param
;
386 const gl_constant_value
**pull_param
;
389 * Image metadata passed to the shader as uniforms. This is deliberately
390 * ignored by brw_stage_prog_data_compare() because its contents don't have
391 * any influence on program compilation.
393 struct brw_image_param
*image_param
;
397 * Image metadata structure as laid out in the shader parameter
398 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
399 * able to use them. That's okay because the padding and any unused
400 * entries [most of them except when we're doing untyped surface
401 * access] will be removed by the uniform packing pass.
403 #define BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET 0
404 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 4
405 #define BRW_IMAGE_PARAM_SIZE_OFFSET 8
406 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 12
407 #define BRW_IMAGE_PARAM_TILING_OFFSET 16
408 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 20
409 #define BRW_IMAGE_PARAM_SIZE 24
411 struct brw_image_param
{
412 /** Surface binding table index. */
413 uint32_t surface_idx
;
415 /** Offset applied to the X and Y surface coordinates. */
418 /** Surface X, Y and Z dimensions. */
421 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
422 * pixels, vertical slice stride in pixels.
426 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
430 * Right shift to apply for bit 6 address swizzling. Two different
431 * swizzles can be specified and will be applied one after the other. The
432 * resulting address will be:
434 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
435 * (addr >> swizzling[1])))
437 * Use \c 0xff if any of the swizzles is not required.
439 uint32_t swizzling
[2];
442 /* Data about a particular attempt to compile a program. Note that
443 * there can be many of these, each in a different GL state
444 * corresponding to a different brw_wm_prog_key struct, with different
447 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
450 struct brw_wm_prog_data
{
451 struct brw_stage_prog_data base
;
453 GLuint num_varying_inputs
;
455 GLuint dispatch_grf_start_reg_16
;
457 GLuint reg_blocks_16
;
461 * surface indices the WM-specific surfaces
463 uint32_t render_target_start
;
467 uint8_t computed_depth_mode
;
469 bool early_fragment_tests
;
472 bool uses_pos_offset
;
476 uint32_t prog_offset_16
;
479 * Mask of which interpolation modes are required by the fragment shader.
480 * Used in hardware setup on gen6+.
482 uint32_t barycentric_interp_modes
;
485 * Map from gl_varying_slot to the position within the FS setup data
486 * payload where the varying's attribute vertex deltas should be delivered.
487 * For varying slots that are not used by the FS, the value is -1.
489 int urb_setup
[VARYING_SLOT_MAX
];
492 /* Note: brw_cs_prog_data_compare() must be updated when adding fields to this
495 struct brw_cs_prog_data
{
496 struct brw_stage_prog_data base
;
498 GLuint dispatch_grf_start_reg_16
;
499 unsigned local_size
[3];
505 * Enum representing the i965-specific vertex results that don't correspond
506 * exactly to any element of gl_varying_slot. The values of this enum are
507 * assigned such that they don't conflict with gl_varying_slot.
511 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
512 BRW_VARYING_SLOT_PAD
,
514 * Technically this is not a varying but just a placeholder that
515 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
516 * builtin variable to be compiled correctly. see compile_sf_prog() for
519 BRW_VARYING_SLOT_PNTC
,
520 BRW_VARYING_SLOT_COUNT
525 * Data structure recording the relationship between the gl_varying_slot enum
526 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
527 * single octaword within the VUE (128 bits).
529 * Note that each BRW register contains 256 bits (2 octawords), so when
530 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
531 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
532 * in a vertex shader), each register corresponds to a single VUE slot, since
533 * it contains data for two separate vertices.
537 * Bitfield representing all varying slots that are (a) stored in this VUE
538 * map, and (b) actually written by the shader. Does not include any of
539 * the additional varying slots defined in brw_varying_slot.
541 GLbitfield64 slots_valid
;
544 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
545 * not stored in a slot (because they are not written, or because
546 * additional processing is applied before storing them in the VUE), the
549 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
552 * Map from VUE slot to gl_varying_slot value. For slots that do not
553 * directly correspond to a gl_varying_slot, the value comes from
556 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
557 * simplifies code that uses the value stored in slot_to_varying to
558 * create a bit mask).
560 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
563 * Total number of VUE slots in use
569 * Convert a VUE slot number into a byte offset within the VUE.
571 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
577 * Convert a vertex output (brw_varying_slot) into a byte offset within the
580 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
583 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
586 void brw_compute_vue_map(const struct brw_device_info
*devinfo
,
587 struct brw_vue_map
*vue_map
,
588 GLbitfield64 slots_valid
);
592 * Bitmask indicating which fragment shader inputs represent varyings (and
593 * hence have to be delivered to the fragment shader by the SF/SBE stage).
595 #define BRW_FS_VARYING_INPUT_MASK \
596 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
597 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
601 * Mapping of VUE map slots to interpolation modes.
603 struct interpolation_mode_map
{
604 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
607 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
609 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
610 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
616 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
618 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
619 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
626 struct brw_sf_prog_data
{
627 GLuint urb_read_length
;
630 /* Each vertex may have upto 12 attributes, 4 components each,
631 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
634 * Actually we use 4 for each, so call it 12 rows.
636 GLuint urb_entry_size
;
641 * We always program SF to start reading at an offset of 1 (2 varying slots)
642 * from the start of the vertex URB entry. This causes it to skip:
643 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
644 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
646 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
649 struct brw_clip_prog_data
{
650 GLuint curb_read_length
; /* user planes? */
652 GLuint urb_read_length
;
656 struct brw_ff_gs_prog_data
{
657 GLuint urb_read_length
;
661 * Gen6 transform feedback: Amount by which the streaming vertex buffer
662 * indices should be incremented each time the GS is invoked.
664 unsigned svbi_postincrement_value
;
667 enum shader_dispatch_mode
{
668 DISPATCH_MODE_4X1_SINGLE
= 0,
669 DISPATCH_MODE_4X2_DUAL_INSTANCE
= 1,
670 DISPATCH_MODE_4X2_DUAL_OBJECT
= 2,
671 DISPATCH_MODE_SIMD8
= 3,
674 /* Note: brw_vue_prog_data_compare() must be updated when adding fields to
677 struct brw_vue_prog_data
{
678 struct brw_stage_prog_data base
;
679 struct brw_vue_map vue_map
;
681 GLuint urb_read_length
;
684 /* Used for calculating urb partitions. In the VS, this is the size of the
685 * URB entry used for both input and output to the thread. In the GS, this
686 * is the size of the URB entry used for output.
688 GLuint urb_entry_size
;
690 enum shader_dispatch_mode dispatch_mode
;
694 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
697 struct brw_vs_prog_data
{
698 struct brw_vue_prog_data base
;
700 GLbitfield64 inputs_read
;
703 bool uses_instanceid
;
706 /** Number of texture sampler units */
707 #define BRW_MAX_TEX_UNIT 32
709 /** Max number of render targets in a shader */
710 #define BRW_MAX_DRAW_BUFFERS 8
712 /** Max number of atomic counter buffer objects in a shader */
713 #define BRW_MAX_ABO 16
715 /** Max number of image uniforms in a shader */
716 #define BRW_MAX_IMAGES 32
719 * Max number of binding table entries used for stream output.
721 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
722 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
724 * On Gen6, the size of transform feedback data is limited not by the number
725 * of components but by the number of binding table entries we set aside. We
726 * use one binding table entry for a float, one entry for a vector, and one
727 * entry per matrix column. Since the only way we can communicate our
728 * transform feedback capabilities to the client is via
729 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
730 * worst case, in which all the varyings are floats, so we use up one binding
731 * table entry per component. Therefore we need to set aside at least 64
732 * binding table entries for use by transform feedback.
734 * Note: since we don't currently pack varyings, it is currently impossible
735 * for the client to actually use up all of these binding table entries--if
736 * all of their varyings were floats, they would run out of varying slots and
737 * fail to link. But that's a bug, so it seems prudent to go ahead and
738 * allocate the number of binding table entries we will need once the bug is
741 #define BRW_MAX_SOL_BINDINGS 64
743 /** Maximum number of actual buffers used for stream output */
744 #define BRW_MAX_SOL_BUFFERS 4
746 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
747 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
751 2 /* shader time, pull constants */)
753 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
755 /* Note: brw_gs_prog_data_compare() must be updated when adding fields to
758 struct brw_gs_prog_data
760 struct brw_vue_prog_data base
;
763 * Size of an output vertex, measured in HWORDS (32 bytes).
765 unsigned output_vertex_size_hwords
;
767 unsigned output_topology
;
770 * Size of the control data (cut bits or StreamID bits), in hwords (32
771 * bytes). 0 if there is no control data.
773 unsigned control_data_header_size_hwords
;
776 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
777 * if the control data is StreamID bits, or
778 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
779 * Ignored if control_data_header_size is 0.
781 unsigned control_data_format
;
783 bool include_primitive_id
;
788 * Gen6 transform feedback enabled flag.
790 bool gen6_xfb_enabled
;
793 * Gen6: Provoking vertex convention for odd-numbered triangles
799 * Gen6: Number of varyings that are output to transform feedback.
801 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
804 * Gen6: Map from the index of a transform feedback binding table entry to the
805 * gl_varying_slot that should be streamed out through that binding table
808 unsigned char transform_feedback_bindings
[BRW_MAX_SOL_BINDINGS
];
811 * Gen6: Map from the index of a transform feedback binding table entry to the
812 * swizzles that should be used when streaming out data through that
813 * binding table entry.
815 unsigned char transform_feedback_swizzles
[BRW_MAX_SOL_BINDINGS
];
819 * Stride in bytes between shader_time entries.
821 * We separate entries by a cacheline to reduce traffic between EUs writing to
824 #define SHADER_TIME_STRIDE 64
826 struct brw_cache_item
{
828 * Effectively part of the key, cache_id identifies what kind of state
829 * buffer is involved, and also which dirty flag should set.
831 enum brw_cache_id cache_id
;
832 /** 32-bit hash of the key data */
834 GLuint key_size
; /* for variable-sized keys */
841 struct brw_cache_item
*next
;
845 typedef bool (*cache_aux_compare_func
)(const void *a
, const void *b
);
846 typedef void (*cache_aux_free_func
)(const void *aux
);
849 struct brw_context
*brw
;
851 struct brw_cache_item
**items
;
853 GLuint size
, n_items
;
855 uint32_t next_offset
;
859 * Optional functions used in determining whether the prog_data for a new
860 * cache item matches an existing cache item (in case there's relevant data
861 * outside of the prog_data). If NULL, a plain memcmp is done.
863 cache_aux_compare_func aux_compare
[BRW_MAX_CACHE
];
864 /** Optional functions for freeing other pointers attached to a prog_data. */
865 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
869 /* Considered adding a member to this struct to document which flags
870 * an update might raise so that ordering of the state atoms can be
871 * checked or derived at runtime. Dropped the idea in favor of having
872 * a debug mode where the state is monitored for flags which are
873 * raised that have already been tested against.
875 struct brw_tracked_state
{
876 struct brw_state_flags dirty
;
877 void (*emit
)( struct brw_context
*brw
);
880 enum shader_time_shader_type
{
889 struct brw_vertex_buffer
{
890 /** Buffer object containing the uploaded vertex data */
893 /** Byte stride between elements in the uploaded array */
897 struct brw_vertex_element
{
898 const struct gl_client_array
*glarray
;
902 /** Offset of the first element within the buffer object */
906 struct brw_query_object
{
907 struct gl_query_object Base
;
909 /** Last query BO associated with this query. */
912 /** Last index in bo with query data for this object. */
915 /** True if we know the batch has been flushed since we ended the query. */
925 struct intel_batchbuffer
{
926 /** Current batchbuffer being queued up. */
928 /** Last BO submitted to the hardware. Used for glFinish(). */
929 drm_intel_bo
*last_bo
;
932 uint16_t emit
, total
;
934 uint16_t reserved_space
;
938 #define BATCH_SZ (8192*sizeof(uint32_t))
940 uint32_t state_batch_offset
;
941 enum brw_gpu_ring ring
;
942 bool needs_sol_reset
;
950 #define BRW_MAX_XFB_STREAMS 4
952 struct brw_transform_feedback_object
{
953 struct gl_transform_feedback_object base
;
955 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
956 drm_intel_bo
*offset_bo
;
958 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
961 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
962 GLenum primitive_mode
;
965 * Count of primitives generated during this transform feedback operation.
968 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
969 drm_intel_bo
*prim_count_bo
;
970 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
974 * Number of vertices written between last Begin/EndTransformFeedback().
976 * Used to implement DrawTransformFeedback().
978 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
979 bool vertices_written_valid
;
983 * Data shared between each programmable stage in the pipeline (vs, gs, and
986 struct brw_stage_state
988 gl_shader_stage stage
;
989 struct brw_stage_prog_data
*prog_data
;
992 * Optional scratch buffer used to store spilled register values and
993 * variably-indexed GRF arrays.
995 drm_intel_bo
*scratch_bo
;
997 /** Offset in the program cache to the program */
998 uint32_t prog_offset
;
1000 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
1001 uint32_t state_offset
;
1003 uint32_t push_const_offset
; /* Offset in the batchbuffer */
1004 int push_const_size
; /* in 256-bit register increments */
1006 /* Binding table: pointers to SURFACE_STATE entries. */
1007 uint32_t bind_bo_offset
;
1008 uint32_t surf_offset
[BRW_MAX_SURFACES
];
1010 /** SAMPLER_STATE count and table offset */
1011 uint32_t sampler_count
;
1012 uint32_t sampler_offset
;
1015 enum brw_predicate_state
{
1016 /* The first two states are used if we can determine whether to draw
1017 * without having to look at the values in the query object buffer. This
1018 * will happen if there is no conditional render in progress, if the query
1019 * object is already completed or if something else has already added
1020 * samples to the preliminary result such as via a BLT command.
1022 BRW_PREDICATE_STATE_RENDER
,
1023 BRW_PREDICATE_STATE_DONT_RENDER
,
1024 /* In this case whether to draw or not depends on the result of an
1025 * MI_PREDICATE command so the predicate enable bit needs to be checked.
1027 BRW_PREDICATE_STATE_USE_BIT
1030 struct shader_times
;
1033 * brw_context is derived from gl_context.
1037 struct gl_context ctx
; /**< base class, must be first field */
1041 void (*update_texture_surface
)(struct gl_context
*ctx
,
1043 uint32_t *surf_offset
,
1045 uint32_t (*update_renderbuffer_surface
)(struct brw_context
*brw
,
1046 struct gl_renderbuffer
*rb
,
1047 bool layered
, unsigned unit
,
1048 uint32_t surf_index
);
1050 void (*emit_texture_surface_state
)(struct brw_context
*brw
,
1051 struct intel_mipmap_tree
*mt
,
1059 uint32_t *surf_offset
,
1060 bool rw
, bool for_gather
);
1061 void (*emit_buffer_surface_state
)(struct brw_context
*brw
,
1062 uint32_t *out_offset
,
1064 unsigned buffer_offset
,
1065 unsigned surface_format
,
1066 unsigned buffer_size
,
1069 void (*emit_null_surface_state
)(struct brw_context
*brw
,
1073 uint32_t *out_offset
);
1076 * Send the appropriate state packets to configure depth, stencil, and
1077 * HiZ buffers (i965+ only)
1079 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
1080 struct intel_mipmap_tree
*depth_mt
,
1081 uint32_t depth_offset
,
1082 uint32_t depthbuffer_format
,
1083 uint32_t depth_surface_type
,
1084 struct intel_mipmap_tree
*stencil_mt
,
1085 bool hiz
, bool separate_stencil
,
1086 uint32_t width
, uint32_t height
,
1087 uint32_t tile_x
, uint32_t tile_y
);
1093 drm_intel_context
*hw_ctx
;
1095 /** BO for post-sync nonzero writes for gen6 workaround. */
1096 drm_intel_bo
*workaround_bo
;
1097 uint8_t pipe_controls_since_last_cs_stall
;
1100 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
1101 * and would need flushing before being used from another cache domain that
1102 * isn't coherent with it (i.e. the sampler).
1104 struct set
*render_cache
;
1107 * Number of resets observed in the system at context creation.
1109 * This is tracked in the context so that we can determine that another
1110 * reset has occurred.
1112 uint32_t reset_count
;
1114 struct intel_batchbuffer batch
;
1119 uint32_t next_offset
;
1123 * Set if rendering has occurred to the drawable's front buffer.
1125 * This is used in the DRI2 case to detect that glFlush should also copy
1126 * the contents of the fake front buffer to the real front buffer.
1128 bool front_buffer_dirty
;
1130 /** Framerate throttling: @{ */
1131 drm_intel_bo
*throttle_batch
[2];
1133 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
1134 * frame of rendering to complete. This gives a very precise cap to the
1135 * latency between input and output such that rendering never gets more
1136 * than a frame behind the user. (With the caveat that we technically are
1137 * not using the SwapBuffers itself as a barrier but the first batch
1138 * submitted afterwards, which may be immediately prior to the next
1141 bool need_swap_throttle
;
1143 /** General throttling, not caught by throttling between SwapBuffers */
1144 bool need_flush_throttle
;
1154 bool always_flush_batch
;
1155 bool always_flush_cache
;
1156 bool disable_throttling
;
1159 driOptionCache optionCache
;
1162 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
1164 GLenum reduced_primitive
;
1167 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
1168 * variable is set, this is the flag indicating to do expensive work that
1169 * might lead to a perf_debug() call.
1173 uint32_t max_gtt_map_object_size
;
1185 bool has_separate_stencil
;
1186 bool must_use_separate_stencil
;
1189 bool has_surface_tile_offset
;
1191 bool has_negative_rhw_bug
;
1195 bool use_resource_streamer
;
1198 * Some versions of Gen hardware don't do centroid interpolation correctly
1199 * on unlit pixels, causing incorrect values for derivatives near triangle
1200 * edges. Enabling this flag causes the fragment shader to use
1201 * non-centroid interpolation for unlit pixels, at the expense of two extra
1202 * fragment shader instructions.
1204 bool needs_unlit_centroid_workaround
;
1208 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
1211 enum brw_pipeline last_pipeline
;
1213 struct brw_cache cache
;
1215 /** IDs for meta stencil blit shader programs. */
1216 unsigned meta_stencil_blit_programs
[2];
1218 /* Whether a meta-operation is in progress. */
1219 bool meta_in_progress
;
1221 /* Whether the last depth/stencil packets were both NULL. */
1222 bool no_depth_or_stencil
;
1224 /* The last PMA stall bits programmed. */
1225 uint32_t pma_stall_bits
;
1228 /** The value of gl_BaseVertex for the current _mesa_prim. */
1232 * Buffer and offset used for GL_ARB_shader_draw_parameters
1233 * (for now, only gl_BaseVertex).
1235 drm_intel_bo
*draw_params_bo
;
1236 uint32_t draw_params_offset
;
1240 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
1241 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
1243 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
1247 /* Summary of size and varying of active arrays, so we can check
1248 * for changes to this state:
1250 unsigned int min_index
, max_index
;
1252 /* Offset from start of vertex buffer so we can avoid redefining
1253 * the same VB packed over and over again.
1255 unsigned int start_vertex_bias
;
1258 * Certain vertex attribute formats aren't natively handled by the
1259 * hardware and require special VS code to fix up their values.
1261 * These bitfields indicate which workarounds are needed.
1263 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
1268 * Index buffer for this draw_prims call.
1270 * Updates are signaled by BRW_NEW_INDICES.
1272 const struct _mesa_index_buffer
*ib
;
1274 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
1278 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
1279 * avoid re-uploading the IB packet over and over if we're actually
1280 * referencing the same index buffer.
1282 unsigned int start_vertex_offset
;
1285 /* Active vertex program:
1287 const struct gl_vertex_program
*vertex_program
;
1288 const struct gl_geometry_program
*geometry_program
;
1289 const struct gl_fragment_program
*fragment_program
;
1290 const struct gl_compute_program
*compute_program
;
1293 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
1294 * that we don't have to reemit that state every time we change FBOs.
1299 * Platform specific constants containing the maximum number of threads
1300 * for each pipeline stage.
1302 unsigned max_vs_threads
;
1303 unsigned max_hs_threads
;
1304 unsigned max_ds_threads
;
1305 unsigned max_gs_threads
;
1306 unsigned max_wm_threads
;
1307 unsigned max_cs_threads
;
1309 /* BRW_NEW_URB_ALLOCATIONS:
1312 GLuint vsize
; /* vertex size plus header in urb registers */
1313 GLuint gsize
; /* GS output size in urb registers */
1314 GLuint csize
; /* constant buffer size in urb registers */
1315 GLuint sfsize
; /* setup data size in urb registers */
1319 GLuint min_vs_entries
; /* Minimum number of VS entries */
1320 GLuint max_vs_entries
; /* Maximum number of VS entries */
1321 GLuint max_hs_entries
; /* Maximum number of HS entries */
1322 GLuint max_ds_entries
; /* Maximum number of DS entries */
1323 GLuint max_gs_entries
; /* Maximum number of GS entries */
1325 GLuint nr_vs_entries
;
1326 GLuint nr_gs_entries
;
1327 GLuint nr_clip_entries
;
1328 GLuint nr_sf_entries
;
1329 GLuint nr_cs_entries
;
1336 GLuint size
; /* Hardware URB size, in KB. */
1338 /* True if the most recently sent _3DSTATE_URB message allocated
1339 * URB space for the GS.
1345 /* BRW_NEW_CURBE_OFFSETS:
1348 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1349 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1357 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1358 * for upload to the CURBE.
1360 drm_intel_bo
*curbe_bo
;
1361 /** Offset within curbe_bo of space for current curbe entry */
1362 GLuint curbe_offset
;
1366 * Layout of vertex data exiting the vertex shader.
1368 * BRW_NEW_VUE_MAP_VS is flagged when this VUE map changes.
1370 struct brw_vue_map vue_map_vs
;
1373 * Layout of vertex data exiting the geometry portion of the pipleine.
1374 * This comes from the geometry shader if one exists, otherwise from the
1377 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1379 struct brw_vue_map vue_map_geom_out
;
1382 struct brw_stage_state base
;
1383 struct brw_vs_prog_data
*prog_data
;
1387 struct brw_stage_state base
;
1388 struct brw_gs_prog_data
*prog_data
;
1391 * True if the 3DSTATE_GS command most recently emitted to the 3D
1392 * pipeline enabled the GS; false otherwise.
1398 struct brw_ff_gs_prog_data
*prog_data
;
1401 /** Offset in the program cache to the CLIP program pre-gen6 */
1402 uint32_t prog_offset
;
1403 uint32_t state_offset
;
1405 uint32_t bind_bo_offset
;
1407 * Surface offsets for the binding table. We only need surfaces to
1408 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1409 * need in this case.
1411 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1415 struct brw_clip_prog_data
*prog_data
;
1417 /** Offset in the program cache to the CLIP program pre-gen6 */
1418 uint32_t prog_offset
;
1420 /* Offset in the batch to the CLIP state on pre-gen6. */
1421 uint32_t state_offset
;
1423 /* As of gen6, this is the offset in the batch to the CLIP VP,
1431 struct brw_sf_prog_data
*prog_data
;
1433 /** Offset in the program cache to the CLIP program pre-gen6 */
1434 uint32_t prog_offset
;
1435 uint32_t state_offset
;
1437 bool viewport_transform_enable
;
1441 struct brw_stage_state base
;
1442 struct brw_wm_prog_data
*prog_data
;
1447 * Buffer object used in place of multisampled null render targets on
1448 * Gen6. See brw_emit_null_surface_state().
1450 drm_intel_bo
*multisampled_null_render_target_bo
;
1451 uint32_t fast_clear_op
;
1455 struct brw_stage_state base
;
1456 struct brw_cs_prog_data
*prog_data
;
1459 /* RS hardware binding table */
1462 uint32_t next_offset
;
1466 uint32_t state_offset
;
1467 uint32_t blend_state_offset
;
1468 uint32_t depth_stencil_state_offset
;
1473 struct brw_query_object
*obj
;
1478 enum brw_predicate_state state
;
1483 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1484 const int *statistics_registers
;
1486 /** The number of active monitors using OA counters. */
1490 * A buffer object storing OA counter snapshots taken at the start and
1491 * end of each batch (creating "bookends" around the batch).
1493 drm_intel_bo
*bookend_bo
;
1495 /** The number of snapshots written to bookend_bo. */
1496 int bookend_snapshots
;
1499 * An array of monitors whose results haven't yet been assembled based on
1500 * the data in buffer objects.
1502 * These may be active, or have already ended. However, the results
1503 * have not been requested.
1505 struct brw_perf_monitor_object
**unresolved
;
1506 int unresolved_elements
;
1507 int unresolved_array_size
;
1510 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1511 * the counter which MI_REPORT_PERF_COUNT stores there.
1513 const int *oa_snapshot_layout
;
1515 /** Number of 32-bit entries in a hardware counter snapshot. */
1516 int entries_per_oa_snapshot
;
1519 int num_atoms
[BRW_NUM_PIPELINES
];
1520 const struct brw_tracked_state render_atoms
[60];
1521 const struct brw_tracked_state compute_atoms
[6];
1523 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1527 enum aub_state_struct_type type
;
1529 } *state_batch_list
;
1530 int state_batch_count
;
1532 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1533 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1535 /* Interpolation modes, one byte per vue slot.
1536 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1538 struct interpolation_mode_map interpolation_mode
;
1540 /* PrimitiveRestart */
1543 bool enable_cut_index
;
1546 /** Computed depth/stencil/hiz state from the current attached
1547 * renderbuffers, valid only during the drawing state upload loop after
1548 * brw_workaround_depthstencil_alignment().
1551 struct intel_mipmap_tree
*depth_mt
;
1552 struct intel_mipmap_tree
*stencil_mt
;
1554 /* Inter-tile (page-aligned) byte offsets. */
1555 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1556 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1557 uint32_t tile_x
, tile_y
;
1560 uint32_t num_instances
;
1567 enum shader_time_shader_type
*types
;
1568 struct shader_times
*cumulative
;
1574 struct brw_fast_clear_state
*fast_clear_state
;
1576 __DRIcontext
*driContext
;
1577 struct intel_screen
*intelScreen
;
1580 /*======================================================================
1583 void brwInitVtbl( struct brw_context
*brw
);
1586 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1588 /*======================================================================
1591 extern const char *const brw_vendor_string
;
1593 extern const char *brw_get_renderer_string(unsigned deviceID
);
1596 DRI_CONF_BO_REUSE_DISABLED
,
1597 DRI_CONF_BO_REUSE_ALL
1600 void intel_update_renderbuffers(__DRIcontext
*context
,
1601 __DRIdrawable
*drawable
);
1602 void intel_prepare_render(struct brw_context
*brw
);
1604 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1605 __DRIdrawable
*drawable
);
1607 GLboolean
brwCreateContext(gl_api api
,
1608 const struct gl_config
*mesaVis
,
1609 __DRIcontext
*driContextPriv
,
1610 unsigned major_version
,
1611 unsigned minor_version
,
1615 void *sharedContextPrivate
);
1617 /*======================================================================
1620 GLuint
brw_get_rb_for_slice(struct brw_context
*brw
,
1621 struct intel_mipmap_tree
*mt
,
1622 unsigned level
, unsigned layer
, bool flat
);
1624 void brw_meta_updownsample(struct brw_context
*brw
,
1625 struct intel_mipmap_tree
*src
,
1626 struct intel_mipmap_tree
*dst
);
1628 void brw_meta_fbo_stencil_blit(struct brw_context
*brw
,
1629 struct gl_framebuffer
*read_fb
,
1630 struct gl_framebuffer
*draw_fb
,
1631 GLfloat srcX0
, GLfloat srcY0
,
1632 GLfloat srcX1
, GLfloat srcY1
,
1633 GLfloat dstX0
, GLfloat dstY0
,
1634 GLfloat dstX1
, GLfloat dstY1
);
1636 void brw_meta_stencil_updownsample(struct brw_context
*brw
,
1637 struct intel_mipmap_tree
*src
,
1638 struct intel_mipmap_tree
*dst
);
1640 bool brw_meta_fast_clear(struct brw_context
*brw
,
1641 struct gl_framebuffer
*fb
,
1643 bool partial_clear
);
1646 brw_meta_resolve_color(struct brw_context
*brw
,
1647 struct intel_mipmap_tree
*mt
);
1649 brw_meta_fast_clear_free(struct brw_context
*brw
);
1652 /*======================================================================
1655 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1656 uint32_t depth_level
,
1657 uint32_t depth_layer
,
1658 struct intel_mipmap_tree
*stencil_mt
,
1659 uint32_t *out_tile_mask_x
,
1660 uint32_t *out_tile_mask_y
);
1661 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1662 GLbitfield clear_mask
);
1664 /* brw_object_purgeable.c */
1665 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1667 /*======================================================================
1670 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1671 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1672 void brw_emit_query_begin(struct brw_context
*brw
);
1673 void brw_emit_query_end(struct brw_context
*brw
);
1675 /** gen6_queryobj.c */
1676 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1677 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1678 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1679 void brw_store_register_mem64(struct brw_context
*brw
,
1680 drm_intel_bo
*bo
, uint32_t reg
, int idx
);
1682 /** brw_conditional_render.c */
1683 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1684 bool brw_check_conditional_render(struct brw_context
*brw
);
1686 /** intel_batchbuffer.c */
1687 void brw_load_register_mem(struct brw_context
*brw
,
1690 uint32_t read_domains
, uint32_t write_domain
,
1692 void brw_load_register_mem64(struct brw_context
*brw
,
1695 uint32_t read_domains
, uint32_t write_domain
,
1698 /*======================================================================
1701 void brw_debug_batch(struct brw_context
*brw
);
1702 void brw_annotate_aub(struct brw_context
*brw
);
1704 /*======================================================================
1707 void brw_validate_textures( struct brw_context
*brw
);
1710 /*======================================================================
1713 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1715 int brw_get_scratch_size(int size
);
1716 void brw_get_scratch_bo(struct brw_context
*brw
,
1717 drm_intel_bo
**scratch_bo
, int size
);
1718 void brw_init_shader_time(struct brw_context
*brw
);
1719 int brw_get_shader_time_index(struct brw_context
*brw
,
1720 struct gl_shader_program
*shader_prog
,
1721 struct gl_program
*prog
,
1722 enum shader_time_shader_type type
);
1723 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1724 void brw_destroy_shader_time(struct brw_context
*brw
);
1728 void brw_upload_urb_fence(struct brw_context
*brw
);
1732 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1734 /* brw_fs_reg_allocate.cpp
1736 void brw_fs_alloc_reg_sets(struct brw_compiler
*compiler
);
1738 /* brw_vec4_reg_allocate.cpp */
1739 void brw_vec4_alloc_reg_set(struct brw_compiler
*compiler
);
1742 int brw_disassemble_inst(FILE *file
, const struct brw_device_info
*devinfo
,
1743 struct brw_inst
*inst
, bool is_compacted
);
1746 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1748 /* brw_draw_upload.c */
1749 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1750 const struct gl_client_array
*glarray
);
1752 static inline unsigned
1753 brw_get_index_type(GLenum type
)
1755 assert((type
== GL_UNSIGNED_BYTE
)
1756 || (type
== GL_UNSIGNED_SHORT
)
1757 || (type
== GL_UNSIGNED_INT
));
1759 /* The possible values for type are GL_UNSIGNED_BYTE (0x1401),
1760 * GL_UNSIGNED_SHORT (0x1403), and GL_UNSIGNED_INT (0x1405) which we want
1761 * to map to scale factors of 0, 1, and 2, respectively. These scale
1762 * factors are then left-shfited by 8 to be in the correct position in the
1763 * CMD_INDEX_BUFFER packet.
1765 * Subtracting 0x1401 gives 0, 2, and 4. Shifting left by 7 afterwards
1766 * gives 0x00000000, 0x00000100, and 0x00000200. These just happen to be
1767 * the values the need to be written in the CMD_INDEX_BUFFER packet.
1769 return (type
- 0x1401) << 7;
1772 void brw_prepare_vertices(struct brw_context
*brw
);
1774 /* brw_wm_surface_state.c */
1775 void brw_init_surface_formats(struct brw_context
*brw
);
1776 void brw_create_constant_surface(struct brw_context
*brw
,
1780 uint32_t *out_offset
,
1782 void brw_create_buffer_surface(struct brw_context
*brw
,
1786 uint32_t *out_offset
,
1788 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1790 uint32_t *surf_offset
);
1792 brw_update_sol_surface(struct brw_context
*brw
,
1793 struct gl_buffer_object
*buffer_obj
,
1794 uint32_t *out_offset
, unsigned num_vector_components
,
1795 unsigned stride_dwords
, unsigned offset_dwords
);
1796 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1797 struct gl_shader
*shader
,
1798 struct brw_stage_state
*stage_state
,
1799 struct brw_stage_prog_data
*prog_data
,
1801 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1802 struct gl_shader_program
*prog
,
1803 struct brw_stage_state
*stage_state
,
1804 struct brw_stage_prog_data
*prog_data
);
1805 void brw_upload_image_surfaces(struct brw_context
*brw
,
1806 struct gl_shader
*shader
,
1807 struct brw_stage_state
*stage_state
,
1808 struct brw_stage_prog_data
*prog_data
);
1810 /* brw_surface_formats.c */
1811 bool brw_render_target_supported(struct brw_context
*brw
,
1812 struct gl_renderbuffer
*rb
);
1813 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1814 mesa_format
brw_lower_mesa_image_format(const struct brw_device_info
*devinfo
,
1815 mesa_format format
);
1817 /* brw_performance_monitor.c */
1818 void brw_init_performance_monitors(struct brw_context
*brw
);
1819 void brw_dump_perf_monitors(struct brw_context
*brw
);
1820 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1821 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1823 /* intel_buffer_objects.c */
1824 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1825 const char *bo_name
);
1826 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1827 const char *bo_name
);
1829 /* intel_extensions.c */
1830 extern void intelInitExtensions(struct gl_context
*ctx
);
1833 extern int intel_translate_shadow_compare_func(GLenum func
);
1834 extern int intel_translate_compare_func(GLenum func
);
1835 extern int intel_translate_stencil_op(GLenum op
);
1836 extern int intel_translate_logic_op(GLenum opcode
);
1838 /* intel_syncobj.c */
1839 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1842 struct gl_transform_feedback_object
*
1843 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1845 brw_delete_transform_feedback(struct gl_context
*ctx
,
1846 struct gl_transform_feedback_object
*obj
);
1848 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1849 struct gl_transform_feedback_object
*obj
);
1851 brw_end_transform_feedback(struct gl_context
*ctx
,
1852 struct gl_transform_feedback_object
*obj
);
1854 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1855 struct gl_transform_feedback_object
*obj
,
1858 /* gen7_sol_state.c */
1860 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1861 struct gl_transform_feedback_object
*obj
);
1863 gen7_end_transform_feedback(struct gl_context
*ctx
,
1864 struct gl_transform_feedback_object
*obj
);
1866 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1867 struct gl_transform_feedback_object
*obj
);
1869 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1870 struct gl_transform_feedback_object
*obj
);
1872 /* brw_blorp_blit.cpp */
1874 brw_blorp_framebuffer(struct brw_context
*brw
,
1875 struct gl_framebuffer
*readFb
,
1876 struct gl_framebuffer
*drawFb
,
1877 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1878 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1879 GLbitfield mask
, GLenum filter
);
1882 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1883 struct gl_renderbuffer
*src_rb
,
1884 struct gl_texture_image
*dst_image
,
1886 int srcX0
, int srcY0
,
1887 int dstX0
, int dstY0
,
1888 int width
, int height
);
1890 /* gen6_multisample_state.c */
1892 gen6_determine_sample_mask(struct brw_context
*brw
);
1895 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1896 unsigned num_samples
);
1898 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1900 gen6_get_sample_position(struct gl_context
*ctx
,
1901 struct gl_framebuffer
*fb
,
1905 gen6_set_sample_maps(struct gl_context
*ctx
);
1907 /* gen8_multisample_state.c */
1908 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1909 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1913 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1914 unsigned gs_size
, unsigned fs_size
);
1917 gen7_emit_urb_state(struct brw_context
*brw
,
1918 unsigned nr_vs_entries
, unsigned vs_size
,
1919 unsigned vs_start
, unsigned nr_gs_entries
,
1920 unsigned gs_size
, unsigned gs_start
);
1925 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1929 brw_init_compute_functions(struct dd_function_table
*functions
);
1931 /*======================================================================
1932 * Inline conversion functions. These are better-typed than the
1933 * macros used previously:
1935 static inline struct brw_context
*
1936 brw_context( struct gl_context
*ctx
)
1938 return (struct brw_context
*)ctx
;
1941 static inline struct brw_vertex_program
*
1942 brw_vertex_program(struct gl_vertex_program
*p
)
1944 return (struct brw_vertex_program
*) p
;
1947 static inline const struct brw_vertex_program
*
1948 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1950 return (const struct brw_vertex_program
*) p
;
1953 static inline struct brw_geometry_program
*
1954 brw_geometry_program(struct gl_geometry_program
*p
)
1956 return (struct brw_geometry_program
*) p
;
1959 static inline struct brw_fragment_program
*
1960 brw_fragment_program(struct gl_fragment_program
*p
)
1962 return (struct brw_fragment_program
*) p
;
1965 static inline const struct brw_fragment_program
*
1966 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1968 return (const struct brw_fragment_program
*) p
;
1971 static inline struct brw_compute_program
*
1972 brw_compute_program(struct gl_compute_program
*p
)
1974 return (struct brw_compute_program
*) p
;
1978 * Pre-gen6, the register file of the EUs was shared between threads,
1979 * and each thread used some subset allocated on a 16-register block
1980 * granularity. The unit states wanted these block counts.
1983 brw_register_blocks(int reg_count
)
1985 return ALIGN(reg_count
, 16) / 16 - 1;
1988 static inline uint32_t
1989 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1990 uint32_t prog_offset
)
1992 if (brw
->gen
>= 5) {
1993 /* Using state base address. */
1997 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
2001 I915_GEM_DOMAIN_INSTRUCTION
, 0);
2003 return brw
->cache
.bo
->offset64
+ prog_offset
;
2006 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
2007 bool brw_lower_texture_gradients(struct brw_context
*brw
,
2008 struct exec_list
*instructions
);
2009 bool brw_do_lower_unnormalized_offset(struct exec_list
*instructions
);
2011 struct opcode_desc
{
2017 extern const struct opcode_desc opcode_descs
[128];
2018 extern const char * const conditional_modifier
[16];
2021 brw_emit_depthbuffer(struct brw_context
*brw
);
2024 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
2025 struct intel_mipmap_tree
*depth_mt
,
2026 uint32_t depth_offset
, uint32_t depthbuffer_format
,
2027 uint32_t depth_surface_type
,
2028 struct intel_mipmap_tree
*stencil_mt
,
2029 bool hiz
, bool separate_stencil
,
2030 uint32_t width
, uint32_t height
,
2031 uint32_t tile_x
, uint32_t tile_y
);
2034 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
2035 struct intel_mipmap_tree
*depth_mt
,
2036 uint32_t depth_offset
, uint32_t depthbuffer_format
,
2037 uint32_t depth_surface_type
,
2038 struct intel_mipmap_tree
*stencil_mt
,
2039 bool hiz
, bool separate_stencil
,
2040 uint32_t width
, uint32_t height
,
2041 uint32_t tile_x
, uint32_t tile_y
);
2044 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
2045 struct intel_mipmap_tree
*depth_mt
,
2046 uint32_t depth_offset
, uint32_t depthbuffer_format
,
2047 uint32_t depth_surface_type
,
2048 struct intel_mipmap_tree
*stencil_mt
,
2049 bool hiz
, bool separate_stencil
,
2050 uint32_t width
, uint32_t height
,
2051 uint32_t tile_x
, uint32_t tile_y
);
2053 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
2054 struct intel_mipmap_tree
*depth_mt
,
2055 uint32_t depth_offset
, uint32_t depthbuffer_format
,
2056 uint32_t depth_surface_type
,
2057 struct intel_mipmap_tree
*stencil_mt
,
2058 bool hiz
, bool separate_stencil
,
2059 uint32_t width
, uint32_t height
,
2060 uint32_t tile_x
, uint32_t tile_y
);
2062 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
2063 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);
2065 uint32_t get_hw_prim_for_gl_prim(int mode
);
2068 gen6_upload_push_constants(struct brw_context
*brw
,
2069 const struct gl_program
*prog
,
2070 const struct brw_stage_prog_data
*prog_data
,
2071 struct brw_stage_state
*stage_state
,
2072 enum aub_state_struct_type type
);
2075 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
2076 const struct intel_mipmap_tree
*mt
);
2078 /* brw_pipe_control.c */
2079 int brw_init_pipe_control(struct brw_context
*brw
,
2080 const struct brw_device_info
*info
);
2081 void brw_fini_pipe_control(struct brw_context
*brw
);
2083 void brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
);
2084 void brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
2085 drm_intel_bo
*bo
, uint32_t offset
,
2086 uint32_t imm_lower
, uint32_t imm_upper
);
2087 void brw_emit_mi_flush(struct brw_context
*brw
);
2088 void brw_emit_post_sync_nonzero_flush(struct brw_context
*brw
);
2089 void brw_emit_depth_stall_flushes(struct brw_context
*brw
);
2090 void gen7_emit_vs_workaround_flush(struct brw_context
*brw
);
2091 void gen7_emit_cs_stall_flush(struct brw_context
*brw
);