2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
38 #include "main/imports.h"
39 #include "main/macros.h"
41 #include "main/mtypes.h"
42 #include "brw_structs.h"
46 /* Evil hack for using libdrm in a c++ compiler. */
51 #include <intel_bufmgr.h>
61 #include "intel_debug.h"
62 #include "intel_screen.h"
63 #include "intel_tex_obj.h"
64 #include "intel_resolve_map.h"
68 * URB - uniform resource buffer. A mid-sized buffer which is
69 * partitioned between the fixed function units and used for passing
70 * values (vertices, primitives, constants) between them.
72 * CURBE - constant URB entry. An urb region (entry) used to hold
73 * constant values which the fixed function units can be instructed to
74 * preload into the GRF when spawning a thread.
76 * VUE - vertex URB entry. An urb entry holding a vertex and usually
77 * a vertex header. The header contains control information and
78 * things like primitive type, Begin/end flags and clip codes.
80 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
81 * unit holding rasterization and interpolation parameters.
83 * GRF - general register file. One of several register files
84 * addressable by programmed threads. The inputs (r0, payload, curbe,
85 * urb) of the thread are preloaded to this area before the thread is
86 * spawned. The registers are individually 8 dwords wide and suitable
87 * for general usage. Registers holding thread input values are not
88 * special and may be overwritten.
90 * MRF - message register file. Threads communicate (and terminate)
91 * by sending messages. Message parameters are placed in contiguous
92 * MRF registers. All program output is via these messages. URB
93 * entries are populated by sending a message to the shared URB
94 * function containing the new data, together with a control word,
95 * often an unmodified copy of R0.
97 * R0 - GRF register 0. Typically holds control information used when
98 * sending messages to other threads.
100 * EU or GEN4 EU: The name of the programmable subsystem of the
101 * i965 hardware. Threads are executed by the EU, the registers
102 * described above are part of the EU architecture.
104 * Fixed function units:
106 * CS - Command streamer. Notional first unit, little software
107 * interaction. Holds the URB entries used for constant data, ie the
110 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
111 * this unit is responsible for pulling vertices out of vertex buffers
112 * in vram and injecting them into the processing pipe as VUEs. If
113 * enabled, it first passes them to a VS thread which is a good place
114 * for the driver to implement any active vertex shader.
116 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
117 * enabled, incoming strips etc are passed to GS threads in individual
118 * line/triangle/point units. The GS thread may perform arbitary
119 * computation and emit whatever primtives with whatever vertices it
120 * chooses. This makes GS an excellent place to implement GL's
121 * unfilled polygon modes, though of course it is capable of much
122 * more. Additionally, GS is used to translate away primitives not
123 * handled by latter units, including Quads and Lineloops.
125 * CS - Clipper. Mesa's clipping algorithms are imported to run on
126 * this unit. The fixed function part performs cliptesting against
127 * the 6 fixed clipplanes and makes descisions on whether or not the
128 * incoming primitive needs to be passed to a thread for clipping.
129 * User clip planes are handled via cooperation with the VS thread.
131 * SF - Strips Fans or Setup: Triangles are prepared for
132 * rasterization. Interpolation coefficients are calculated.
133 * Flatshading and two-side lighting usually performed here.
135 * WM - Windower. Interpolation of vertex attributes performed here.
136 * Fragment shader implemented here. SIMD aspects of EU taken full
137 * advantage of, as pixels are processed in blocks of 16.
139 * CC - Color Calculator. No EU threads associated with this unit.
140 * Handles blending and (presumably) depth and stencil testing.
143 #define BRW_MAX_CURBE (32*16)
146 struct brw_instruction
;
147 struct brw_vs_prog_key
;
148 struct brw_vec4_prog_key
;
149 struct brw_wm_prog_key
;
150 struct brw_wm_prog_data
;
154 BRW_STATE_FRAGMENT_PROGRAM
,
155 BRW_STATE_GEOMETRY_PROGRAM
,
156 BRW_STATE_VERTEX_PROGRAM
,
157 BRW_STATE_CURBE_OFFSETS
,
158 BRW_STATE_REDUCED_PRIMITIVE
,
163 BRW_STATE_VS_BINDING_TABLE
,
164 BRW_STATE_GS_BINDING_TABLE
,
165 BRW_STATE_PS_BINDING_TABLE
,
169 BRW_STATE_INDEX_BUFFER
,
170 BRW_STATE_VS_CONSTBUF
,
171 BRW_STATE_GS_CONSTBUF
,
172 BRW_STATE_PROGRAM_CACHE
,
173 BRW_STATE_STATE_BASE_ADDRESS
,
174 BRW_STATE_VUE_MAP_VS
,
175 BRW_STATE_VUE_MAP_GEOM_OUT
,
176 BRW_STATE_TRANSFORM_FEEDBACK
,
177 BRW_STATE_RASTERIZER_DISCARD
,
179 BRW_STATE_UNIFORM_BUFFER
,
180 BRW_STATE_ATOMIC_BUFFER
,
181 BRW_STATE_META_IN_PROGRESS
,
182 BRW_STATE_INTERPOLATION_MAP
,
183 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
184 BRW_STATE_NUM_SAMPLES
,
188 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
189 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
190 #define BRW_NEW_GEOMETRY_PROGRAM (1 << BRW_STATE_GEOMETRY_PROGRAM)
191 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
192 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
193 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
194 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
195 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
196 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
197 #define BRW_NEW_SURFACES (1 << BRW_STATE_SURFACES)
198 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
199 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
200 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
201 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
202 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
204 * Used for any batch entry with a relocated pointer that will be used
205 * by any 3D rendering.
207 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
208 /** \see brw.state.depth_region */
209 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
210 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
211 #define BRW_NEW_GS_CONSTBUF (1 << BRW_STATE_GS_CONSTBUF)
212 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
213 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
214 #define BRW_NEW_VUE_MAP_VS (1 << BRW_STATE_VUE_MAP_VS)
215 #define BRW_NEW_VUE_MAP_GEOM_OUT (1 << BRW_STATE_VUE_MAP_GEOM_OUT)
216 #define BRW_NEW_TRANSFORM_FEEDBACK (1 << BRW_STATE_TRANSFORM_FEEDBACK)
217 #define BRW_NEW_RASTERIZER_DISCARD (1 << BRW_STATE_RASTERIZER_DISCARD)
218 #define BRW_NEW_STATS_WM (1 << BRW_STATE_STATS_WM)
219 #define BRW_NEW_UNIFORM_BUFFER (1 << BRW_STATE_UNIFORM_BUFFER)
220 #define BRW_NEW_ATOMIC_BUFFER (1 << BRW_STATE_ATOMIC_BUFFER)
221 #define BRW_NEW_META_IN_PROGRESS (1 << BRW_STATE_META_IN_PROGRESS)
222 #define BRW_NEW_INTERPOLATION_MAP (1 << BRW_STATE_INTERPOLATION_MAP)
223 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1 << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
224 #define BRW_NEW_NUM_SAMPLES (1 << BRW_STATE_NUM_SAMPLES)
226 struct brw_state_flags
{
227 /** State update flags signalled by mesa internals */
230 * State update flags signalled as the result of brw_tracked_state updates
233 /** State update flags signalled by brw_state_cache.c searches */
237 #define AUB_TRACE_TYPE_MASK 0x0000ff00
238 #define AUB_TRACE_TYPE_NOTYPE (0 << 8)
239 #define AUB_TRACE_TYPE_BATCH (1 << 8)
240 #define AUB_TRACE_TYPE_VERTEX_BUFFER (5 << 8)
241 #define AUB_TRACE_TYPE_2D_MAP (6 << 8)
242 #define AUB_TRACE_TYPE_CUBE_MAP (7 << 8)
243 #define AUB_TRACE_TYPE_VOLUME_MAP (9 << 8)
244 #define AUB_TRACE_TYPE_1D_MAP (10 << 8)
245 #define AUB_TRACE_TYPE_CONSTANT_BUFFER (11 << 8)
246 #define AUB_TRACE_TYPE_CONSTANT_URB (12 << 8)
247 #define AUB_TRACE_TYPE_INDEX_BUFFER (13 << 8)
248 #define AUB_TRACE_TYPE_GENERAL (14 << 8)
249 #define AUB_TRACE_TYPE_SURFACE (15 << 8)
252 * state_struct_type enum values are encoded with the top 16 bits representing
253 * the type to be delivered to the .aub file, and the bottom 16 bits
254 * representing the subtype. This macro performs the encoding.
256 #define ENCODE_SS_TYPE(type, subtype) (((type) << 16) | (subtype))
258 enum state_struct_type
{
259 AUB_TRACE_VS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 1),
260 AUB_TRACE_GS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 2),
261 AUB_TRACE_CLIP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 3),
262 AUB_TRACE_SF_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 4),
263 AUB_TRACE_WM_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 5),
264 AUB_TRACE_CC_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 6),
265 AUB_TRACE_CLIP_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 7),
266 AUB_TRACE_SF_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 8),
267 AUB_TRACE_CC_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x9),
268 AUB_TRACE_SAMPLER_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xa),
269 AUB_TRACE_KERNEL_INSTRUCTIONS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xb),
270 AUB_TRACE_SCRATCH_SPACE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xc),
271 AUB_TRACE_SAMPLER_DEFAULT_COLOR
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xd),
273 AUB_TRACE_SCISSOR_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x15),
274 AUB_TRACE_BLEND_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x16),
275 AUB_TRACE_DEPTH_STENCIL_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x17),
277 AUB_TRACE_VERTEX_BUFFER
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_VERTEX_BUFFER
, 0),
278 AUB_TRACE_BINDING_TABLE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x100),
279 AUB_TRACE_SURFACE_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x200),
280 AUB_TRACE_VS_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 0),
281 AUB_TRACE_WM_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 1),
285 * Decode a state_struct_type value to determine the type that should be
286 * stored in the .aub file.
288 static inline uint32_t AUB_TRACE_TYPE(enum state_struct_type ss_type
)
290 return (ss_type
& 0xFFFF0000) >> 16;
294 * Decode a state_struct_type value to determine the subtype that should be
295 * stored in the .aub file.
297 static inline uint32_t AUB_TRACE_SUBTYPE(enum state_struct_type ss_type
)
299 return ss_type
& 0xFFFF;
302 /** Subclass of Mesa vertex program */
303 struct brw_vertex_program
{
304 struct gl_vertex_program program
;
309 /** Subclass of Mesa geometry program */
310 struct brw_geometry_program
{
311 struct gl_geometry_program program
;
312 unsigned id
; /**< serial no. to identify geom progs, never re-used */
316 /** Subclass of Mesa fragment program */
317 struct brw_fragment_program
{
318 struct gl_fragment_program program
;
319 GLuint id
; /**< serial no. to identify frag progs, never re-used */
323 /** Subclass of Mesa compute program */
324 struct brw_compute_program
{
325 struct gl_compute_program program
;
326 unsigned id
; /**< serial no. to identify compute progs, never re-used */
331 struct gl_shader base
;
336 /* Note: If adding fields that need anything besides a normal memcmp() for
337 * comparing them, be sure to go fix brw_stage_prog_data_compare().
339 struct brw_stage_prog_data
{
341 /** size of our binding table. */
345 * surface indices for the various groups of surfaces
347 uint32_t pull_constants_start
;
348 uint32_t texture_start
;
349 uint32_t gather_texture_start
;
352 uint32_t shader_time_start
;
356 GLuint nr_params
; /**< number of float params/constants */
357 GLuint nr_pull_params
;
359 /* Pointers to tracked values (only valid once
360 * _mesa_load_state_parameters has been called at runtime).
362 * These must be the last fields of the struct (see
363 * brw_stage_prog_data_compare()).
366 const float **pull_param
;
369 /* Data about a particular attempt to compile a program. Note that
370 * there can be many of these, each in a different GL state
371 * corresponding to a different brw_wm_prog_key struct, with different
374 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
377 struct brw_wm_prog_data
{
378 struct brw_stage_prog_data base
;
380 GLuint curb_read_length
;
381 GLuint num_varying_inputs
;
383 GLuint first_curbe_grf
;
384 GLuint first_curbe_grf_16
;
386 GLuint reg_blocks_16
;
387 GLuint total_scratch
;
391 * surface indices the WM-specific surfaces
393 uint32_t render_target_start
;
398 bool uses_pos_offset
;
400 uint32_t prog_offset_16
;
403 * Mask of which interpolation modes are required by the fragment shader.
404 * Used in hardware setup on gen6+.
406 uint32_t barycentric_interp_modes
;
409 * Map from gl_varying_slot to the position within the FS setup data
410 * payload where the varying's attribute vertex deltas should be delivered.
411 * For varying slots that are not used by the FS, the value is -1.
413 int urb_setup
[VARYING_SLOT_MAX
];
417 * Enum representing the i965-specific vertex results that don't correspond
418 * exactly to any element of gl_varying_slot. The values of this enum are
419 * assigned such that they don't conflict with gl_varying_slot.
423 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
424 BRW_VARYING_SLOT_PAD
,
426 * Technically this is not a varying but just a placeholder that
427 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
428 * builtin variable to be compiled correctly. see compile_sf_prog() for
431 BRW_VARYING_SLOT_PNTC
,
432 BRW_VARYING_SLOT_COUNT
437 * Data structure recording the relationship between the gl_varying_slot enum
438 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
439 * single octaword within the VUE (128 bits).
441 * Note that each BRW register contains 256 bits (2 octawords), so when
442 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
443 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
444 * in a vertex shader), each register corresponds to a single VUE slot, since
445 * it contains data for two separate vertices.
449 * Bitfield representing all varying slots that are (a) stored in this VUE
450 * map, and (b) actually written by the shader. Does not include any of
451 * the additional varying slots defined in brw_varying_slot.
453 GLbitfield64 slots_valid
;
456 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
457 * not stored in a slot (because they are not written, or because
458 * additional processing is applied before storing them in the VUE), the
461 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
464 * Map from VUE slot to gl_varying_slot value. For slots that do not
465 * directly correspond to a gl_varying_slot, the value comes from
468 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
469 * simplifies code that uses the value stored in slot_to_varying to
470 * create a bit mask).
472 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
475 * Total number of VUE slots in use
481 * Convert a VUE slot number into a byte offset within the VUE.
483 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
489 * Convert a vertex output (brw_varying_slot) into a byte offset within the
492 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
495 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
498 void brw_compute_vue_map(struct brw_context
*brw
, struct brw_vue_map
*vue_map
,
499 GLbitfield64 slots_valid
);
503 * Bitmask indicating which fragment shader inputs represent varyings (and
504 * hence have to be delivered to the fragment shader by the SF/SBE stage).
506 #define BRW_FS_VARYING_INPUT_MASK \
507 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
508 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
512 * Mapping of VUE map slots to interpolation modes.
514 struct interpolation_mode_map
{
515 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
518 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
520 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
521 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
527 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
529 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
530 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
537 struct brw_sf_prog_data
{
538 GLuint urb_read_length
;
541 /* Each vertex may have upto 12 attributes, 4 components each,
542 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
545 * Actually we use 4 for each, so call it 12 rows.
547 GLuint urb_entry_size
;
552 * We always program SF to start reading at an offset of 1 (2 varying slots)
553 * from the start of the vertex URB entry. This causes it to skip:
554 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
555 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
557 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
560 struct brw_clip_prog_data
{
561 GLuint curb_read_length
; /* user planes? */
563 GLuint urb_read_length
;
567 struct brw_ff_gs_prog_data
{
568 GLuint urb_read_length
;
572 * Gen6 transform feedback: Amount by which the streaming vertex buffer
573 * indices should be incremented each time the GS is invoked.
575 unsigned svbi_postincrement_value
;
579 /* Note: brw_vec4_prog_data_compare() must be updated when adding fields to
582 struct brw_vec4_prog_data
{
583 struct brw_stage_prog_data base
;
584 struct brw_vue_map vue_map
;
587 * Register where the thread expects to find input data from the URB
588 * (typically uniforms, followed by per-vertex inputs).
590 unsigned dispatch_grf_start_reg
;
592 GLuint curb_read_length
;
593 GLuint urb_read_length
;
595 GLuint total_scratch
;
597 /* Used for calculating urb partitions. In the VS, this is the size of the
598 * URB entry used for both input and output to the thread. In the GS, this
599 * is the size of the URB entry used for output.
601 GLuint urb_entry_size
;
605 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
608 struct brw_vs_prog_data
{
609 struct brw_vec4_prog_data base
;
611 GLbitfield64 inputs_read
;
617 /* Note: brw_gs_prog_data_compare() must be updated when adding fields to
620 struct brw_gs_prog_data
622 struct brw_vec4_prog_data base
;
625 * Size of an output vertex, measured in HWORDS (32 bytes).
627 unsigned output_vertex_size_hwords
;
629 unsigned output_topology
;
632 * Size of the control data (cut bits or StreamID bits), in hwords (32
633 * bytes). 0 if there is no control data.
635 unsigned control_data_header_size_hwords
;
638 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
639 * if the control data is StreamID bits, or
640 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
641 * Ignored if control_data_header_size is 0.
643 unsigned control_data_format
;
645 bool include_primitive_id
;
650 * True if the thread should be dispatched in DUAL_INSTANCE mode, false if
651 * it should be dispatched in DUAL_OBJECT mode.
653 bool dual_instanced_dispatch
;
656 /** Number of texture sampler units */
657 #define BRW_MAX_TEX_UNIT 32
659 /** Max number of render targets in a shader */
660 #define BRW_MAX_DRAW_BUFFERS 8
662 /** Max number of atomic counter buffer objects in a shader */
663 #define BRW_MAX_ABO 16
666 * Max number of binding table entries used for stream output.
668 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
669 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
671 * On Gen6, the size of transform feedback data is limited not by the number
672 * of components but by the number of binding table entries we set aside. We
673 * use one binding table entry for a float, one entry for a vector, and one
674 * entry per matrix column. Since the only way we can communicate our
675 * transform feedback capabilities to the client is via
676 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
677 * worst case, in which all the varyings are floats, so we use up one binding
678 * table entry per component. Therefore we need to set aside at least 64
679 * binding table entries for use by transform feedback.
681 * Note: since we don't currently pack varyings, it is currently impossible
682 * for the client to actually use up all of these binding table entries--if
683 * all of their varyings were floats, they would run out of varying slots and
684 * fail to link. But that's a bug, so it seems prudent to go ahead and
685 * allocate the number of binding table entries we will need once the bug is
688 #define BRW_MAX_SOL_BINDINGS 64
690 /** Maximum number of actual buffers used for stream output */
691 #define BRW_MAX_SOL_BUFFERS 4
693 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
694 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
697 2 /* shader time, pull constants */)
699 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
700 #define BRW_MAX_GEN6_GS_SURFACES SURF_INDEX_GEN6_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
703 * Stride in bytes between shader_time entries.
705 * We separate entries by a cacheline to reduce traffic between EUs writing to
708 #define SHADER_TIME_STRIDE 64
715 BRW_BLORP_CONST_COLOR_PROG
,
720 BRW_SF_UNIT
, /* scissor state on gen6 */
733 struct brw_cache_item
{
735 * Effectively part of the key, cache_id identifies what kind of state
736 * buffer is involved, and also which brw->state.dirty.cache flag should
737 * be set when this cache item is chosen.
739 enum brw_cache_id cache_id
;
740 /** 32-bit hash of the key data */
742 GLuint key_size
; /* for variable-sized keys */
749 struct brw_cache_item
*next
;
753 typedef bool (*cache_aux_compare_func
)(const void *a
, const void *b
);
754 typedef void (*cache_aux_free_func
)(const void *aux
);
757 struct brw_context
*brw
;
759 struct brw_cache_item
**items
;
761 GLuint size
, n_items
;
763 uint32_t next_offset
;
767 * Optional functions used in determining whether the prog_data for a new
768 * cache item matches an existing cache item (in case there's relevant data
769 * outside of the prog_data). If NULL, a plain memcmp is done.
771 cache_aux_compare_func aux_compare
[BRW_MAX_CACHE
];
772 /** Optional functions for freeing other pointers attached to a prog_data. */
773 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
777 /* Considered adding a member to this struct to document which flags
778 * an update might raise so that ordering of the state atoms can be
779 * checked or derived at runtime. Dropped the idea in favor of having
780 * a debug mode where the state is monitored for flags which are
781 * raised that have already been tested against.
783 struct brw_tracked_state
{
784 struct brw_state_flags dirty
;
785 void (*emit
)( struct brw_context
*brw
);
788 enum shader_time_shader_type
{
804 /* Flags for brw->state.cache.
806 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
807 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
808 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
809 #define CACHE_NEW_BLORP_BLIT_PROG (1<<BRW_BLORP_BLIT_PROG)
810 #define CACHE_NEW_BLORP_CONST_COLOR_PROG (1<<BRW_BLORP_CONST_COLOR_PROG)
811 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
812 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
813 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
814 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
815 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
816 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
817 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
818 #define CACHE_NEW_FF_GS_UNIT (1<<BRW_FF_GS_UNIT)
819 #define CACHE_NEW_FF_GS_PROG (1<<BRW_FF_GS_PROG)
820 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
821 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
822 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
823 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
825 struct brw_vertex_buffer
{
826 /** Buffer object containing the uploaded vertex data */
829 /** Byte stride between elements in the uploaded array */
833 struct brw_vertex_element
{
834 const struct gl_client_array
*glarray
;
838 /** Offset of the first element within the buffer object */
842 struct brw_query_object
{
843 struct gl_query_object Base
;
845 /** Last query BO associated with this query. */
848 /** Last index in bo with query data for this object. */
852 struct intel_sync_object
{
853 struct gl_sync_object Base
;
855 /** Batch associated with this sync object */
865 struct intel_batchbuffer
{
866 /** Current batchbuffer being queued up. */
868 /** Last BO submitted to the hardware. Used for glFinish(). */
869 drm_intel_bo
*last_bo
;
870 /** BO for post-sync nonzero writes for gen6 workaround. */
871 drm_intel_bo
*workaround_bo
;
872 bool need_workaround_flush
;
874 uint16_t emit
, total
;
875 uint16_t used
, reserved_space
;
878 #define BATCH_SZ (8192*sizeof(uint32_t))
880 uint32_t state_batch_offset
;
881 enum brw_gpu_ring ring
;
882 bool needs_sol_reset
;
890 #define BRW_MAX_XFB_STREAMS 4
892 struct brw_transform_feedback_object
{
893 struct gl_transform_feedback_object base
;
895 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
896 drm_intel_bo
*offset_bo
;
898 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
901 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
902 GLenum primitive_mode
;
905 * Count of primitives generated during this transform feedback operation.
908 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
909 drm_intel_bo
*prim_count_bo
;
910 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
914 * Number of vertices written between last Begin/EndTransformFeedback().
916 * Used to implement DrawTransformFeedback().
918 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
919 bool vertices_written_valid
;
923 * Data shared between each programmable stage in the pipeline (vs, gs, and
926 struct brw_stage_state
928 gl_shader_stage stage
;
929 struct brw_stage_prog_data
*prog_data
;
932 * Optional scratch buffer used to store spilled register values and
933 * variably-indexed GRF arrays.
935 drm_intel_bo
*scratch_bo
;
937 /** Offset in the program cache to the program */
938 uint32_t prog_offset
;
940 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
941 uint32_t state_offset
;
943 uint32_t push_const_offset
; /* Offset in the batchbuffer */
944 int push_const_size
; /* in 256-bit register increments */
946 /* Binding table: pointers to SURFACE_STATE entries. */
947 uint32_t bind_bo_offset
;
948 uint32_t surf_offset
[BRW_MAX_SURFACES
];
950 /** SAMPLER_STATE count and table offset */
951 uint32_t sampler_count
;
952 uint32_t sampler_offset
;
954 /** Offsets in the batch to sampler default colors (texture border color) */
955 uint32_t sdc_offset
[BRW_MAX_TEX_UNIT
];
960 * brw_context is derived from gl_context.
964 struct gl_context ctx
; /**< base class, must be first field */
968 void (*update_texture_surface
)(struct gl_context
*ctx
,
970 uint32_t *surf_offset
,
972 void (*update_renderbuffer_surface
)(struct brw_context
*brw
,
973 struct gl_renderbuffer
*rb
,
976 void (*update_null_renderbuffer_surface
)(struct brw_context
*brw
,
979 void (*create_raw_surface
)(struct brw_context
*brw
,
983 uint32_t *out_offset
,
985 void (*emit_buffer_surface_state
)(struct brw_context
*brw
,
986 uint32_t *out_offset
,
988 unsigned buffer_offset
,
989 unsigned surface_format
,
990 unsigned buffer_size
,
995 /** Upload a SAMPLER_STATE table. */
996 void (*upload_sampler_state_table
)(struct brw_context
*brw
,
997 struct gl_program
*prog
,
998 struct brw_stage_state
*stage_state
);
1001 * Send the appropriate state packets to configure depth, stencil, and
1002 * HiZ buffers (i965+ only)
1004 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
1005 struct intel_mipmap_tree
*depth_mt
,
1006 uint32_t depth_offset
,
1007 uint32_t depthbuffer_format
,
1008 uint32_t depth_surface_type
,
1009 struct intel_mipmap_tree
*stencil_mt
,
1010 bool hiz
, bool separate_stencil
,
1011 uint32_t width
, uint32_t height
,
1012 uint32_t tile_x
, uint32_t tile_y
);
1018 drm_intel_context
*hw_ctx
;
1021 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
1022 * and would need flushing before being used from another cache domain that
1023 * isn't coherent with it (i.e. the sampler).
1025 struct set
*render_cache
;
1028 * Number of resets observed in the system at context creation.
1030 * This is tracked in the context so that we can determine that another
1031 * reset has occured.
1033 uint32_t reset_count
;
1035 struct intel_batchbuffer batch
;
1040 uint32_t next_offset
;
1044 * Set if rendering has occured to the drawable's front buffer.
1046 * This is used in the DRI2 case to detect that glFlush should also copy
1047 * the contents of the fake front buffer to the real front buffer.
1049 bool front_buffer_dirty
;
1051 /** Framerate throttling: @{ */
1052 drm_intel_bo
*first_post_swapbuffers_batch
;
1063 bool always_flush_batch
;
1064 bool always_flush_cache
;
1065 bool disable_throttling
;
1067 bool disable_derivative_optimization
;
1069 driOptionCache optionCache
;
1072 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
1074 GLenum reduced_primitive
;
1077 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
1078 * variable is set, this is the flag indicating to do expensive work that
1079 * might lead to a perf_debug() call.
1083 uint32_t max_gtt_map_object_size
;
1093 bool has_separate_stencil
;
1094 bool must_use_separate_stencil
;
1097 bool has_surface_tile_offset
;
1099 bool has_negative_rhw_bug
;
1103 * Some versions of Gen hardware don't do centroid interpolation correctly
1104 * on unlit pixels, causing incorrect values for derivatives near triangle
1105 * edges. Enabling this flag causes the fragment shader to use
1106 * non-centroid interpolation for unlit pixels, at the expense of two extra
1107 * fragment shader instructions.
1109 bool needs_unlit_centroid_workaround
;
1113 struct brw_state_flags dirty
;
1116 struct brw_cache cache
;
1118 /* Whether a meta-operation is in progress. */
1119 bool meta_in_progress
;
1121 /* Whether the last depth/stencil packets were both NULL. */
1122 bool no_depth_or_stencil
;
1125 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
1126 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
1128 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
1132 /* Summary of size and varying of active arrays, so we can check
1133 * for changes to this state:
1135 unsigned int min_index
, max_index
;
1137 /* Offset from start of vertex buffer so we can avoid redefining
1138 * the same VB packed over and over again.
1140 unsigned int start_vertex_bias
;
1145 * Index buffer for this draw_prims call.
1147 * Updates are signaled by BRW_NEW_INDICES.
1149 const struct _mesa_index_buffer
*ib
;
1151 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
1155 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
1156 * avoid re-uploading the IB packet over and over if we're actually
1157 * referencing the same index buffer.
1159 unsigned int start_vertex_offset
;
1162 /* Active vertex program:
1164 const struct gl_vertex_program
*vertex_program
;
1165 const struct gl_geometry_program
*geometry_program
;
1166 const struct gl_fragment_program
*fragment_program
;
1169 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
1170 * that we don't have to reemit that state every time we change FBOs.
1175 * Platform specific constants containing the maximum number of threads
1176 * for each pipeline stage.
1182 /* BRW_NEW_URB_ALLOCATIONS:
1185 GLuint vsize
; /* vertex size plus header in urb registers */
1186 GLuint csize
; /* constant buffer size in urb registers */
1187 GLuint sfsize
; /* setup data size in urb registers */
1191 GLuint min_vs_entries
; /* Minimum number of VS entries */
1192 GLuint max_vs_entries
; /* Maximum number of VS entries */
1193 GLuint max_gs_entries
; /* Maximum number of GS entries */
1195 GLuint nr_vs_entries
;
1196 GLuint nr_gs_entries
;
1197 GLuint nr_clip_entries
;
1198 GLuint nr_sf_entries
;
1199 GLuint nr_cs_entries
;
1206 GLuint size
; /* Hardware URB size, in KB. */
1208 /* gen6: True if the most recently sent _3DSTATE_URB message allocated
1209 * URB space for the GS.
1211 bool gen6_gs_previously_active
;
1215 /* BRW_NEW_CURBE_OFFSETS:
1218 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1219 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1226 drm_intel_bo
*curbe_bo
;
1227 /** Offset within curbe_bo of space for current curbe entry */
1228 GLuint curbe_offset
;
1229 /** Offset within curbe_bo of space for next curbe entry */
1230 GLuint curbe_next_offset
;
1233 * Copy of the last set of CURBEs uploaded. Frequently we'll end up
1234 * in brw_curbe.c with the same set of constant data to be uploaded,
1235 * so we'd rather not upload new constants in that case (it can cause
1236 * a pipeline bubble since only up to 4 can be pipelined at a time).
1240 * Allocation for where to calculate the next set of CURBEs.
1241 * It's a hot enough path that malloc/free of that data matters.
1248 * Layout of vertex data exiting the vertex shader.
1250 * BRW_NEW_VUE_MAP_VS is flagged when this VUE map changes.
1252 struct brw_vue_map vue_map_vs
;
1255 * Layout of vertex data exiting the geometry portion of the pipleine.
1256 * This comes from the geometry shader if one exists, otherwise from the
1259 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1261 struct brw_vue_map vue_map_geom_out
;
1264 struct brw_stage_state base
;
1265 struct brw_vs_prog_data
*prog_data
;
1269 struct brw_stage_state base
;
1270 struct brw_gs_prog_data
*prog_data
;
1273 * True if the 3DSTATE_GS command most recently emitted to the 3D
1274 * pipeline enabled the GS; false otherwise.
1280 struct brw_ff_gs_prog_data
*prog_data
;
1283 /** Offset in the program cache to the CLIP program pre-gen6 */
1284 uint32_t prog_offset
;
1285 uint32_t state_offset
;
1287 uint32_t bind_bo_offset
;
1288 uint32_t surf_offset
[BRW_MAX_GEN6_GS_SURFACES
];
1292 struct brw_clip_prog_data
*prog_data
;
1294 /** Offset in the program cache to the CLIP program pre-gen6 */
1295 uint32_t prog_offset
;
1297 /* Offset in the batch to the CLIP state on pre-gen6. */
1298 uint32_t state_offset
;
1300 /* As of gen6, this is the offset in the batch to the CLIP VP,
1308 struct brw_sf_prog_data
*prog_data
;
1310 /** Offset in the program cache to the CLIP program pre-gen6 */
1311 uint32_t prog_offset
;
1312 uint32_t state_offset
;
1317 struct brw_stage_state base
;
1318 struct brw_wm_prog_data
*prog_data
;
1323 * Buffer object used in place of multisampled null render targets on
1324 * Gen6. See brw_update_null_renderbuffer_surface().
1326 drm_intel_bo
*multisampled_null_render_target_bo
;
1331 uint32_t state_offset
;
1332 uint32_t blend_state_offset
;
1333 uint32_t depth_stencil_state_offset
;
1338 struct brw_query_object
*obj
;
1343 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1344 const int *statistics_registers
;
1346 /** The number of active monitors using OA counters. */
1350 * A buffer object storing OA counter snapshots taken at the start and
1351 * end of each batch (creating "bookends" around the batch).
1353 drm_intel_bo
*bookend_bo
;
1355 /** The number of snapshots written to bookend_bo. */
1356 int bookend_snapshots
;
1359 * An array of monitors whose results haven't yet been assembled based on
1360 * the data in buffer objects.
1362 * These may be active, or have already ended. However, the results
1363 * have not been requested.
1365 struct brw_perf_monitor_object
**unresolved
;
1366 int unresolved_elements
;
1367 int unresolved_array_size
;
1370 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1371 * the counter which MI_REPORT_PERF_COUNT stores there.
1373 const int *oa_snapshot_layout
;
1375 /** Number of 32-bit entries in a hardware counter snapshot. */
1376 int entries_per_oa_snapshot
;
1380 const struct brw_tracked_state
**atoms
;
1382 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1386 enum state_struct_type type
;
1387 } *state_batch_list
;
1388 int state_batch_count
;
1390 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1391 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1393 /* Interpolation modes, one byte per vue slot.
1394 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1396 struct interpolation_mode_map interpolation_mode
;
1398 /* PrimitiveRestart */
1401 bool enable_cut_index
;
1404 /** Computed depth/stencil/hiz state from the current attached
1405 * renderbuffers, valid only during the drawing state upload loop after
1406 * brw_workaround_depthstencil_alignment().
1409 struct intel_mipmap_tree
*depth_mt
;
1410 struct intel_mipmap_tree
*stencil_mt
;
1412 /* Inter-tile (page-aligned) byte offsets. */
1413 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1414 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1415 uint32_t tile_x
, tile_y
;
1418 uint32_t num_instances
;
1423 struct gl_shader_program
**shader_programs
;
1424 struct gl_program
**programs
;
1425 enum shader_time_shader_type
*types
;
1426 uint64_t *cumulative
;
1432 __DRIcontext
*driContext
;
1433 struct intel_screen
*intelScreen
;
1436 /*======================================================================
1439 void brwInitVtbl( struct brw_context
*brw
);
1442 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1444 /*======================================================================
1447 extern const char *const brw_vendor_string
;
1449 extern const char *brw_get_renderer_string(unsigned deviceID
);
1451 extern void intelFinish(struct gl_context
* ctx
);
1454 DRI_CONF_BO_REUSE_DISABLED
,
1455 DRI_CONF_BO_REUSE_ALL
1458 void intel_update_renderbuffers(__DRIcontext
*context
,
1459 __DRIdrawable
*drawable
);
1460 void intel_prepare_render(struct brw_context
*brw
);
1462 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1463 __DRIdrawable
*drawable
);
1465 GLboolean
brwCreateContext(gl_api api
,
1466 const struct gl_config
*mesaVis
,
1467 __DRIcontext
*driContextPriv
,
1468 unsigned major_version
,
1469 unsigned minor_version
,
1473 void *sharedContextPrivate
);
1475 /*======================================================================
1478 GLuint
brw_get_rb_for_slice(struct brw_context
*brw
,
1479 struct intel_mipmap_tree
*mt
,
1480 unsigned level
, unsigned layer
, bool flat
);
1482 void brw_meta_updownsample(struct brw_context
*brw
,
1483 struct intel_mipmap_tree
*src
,
1484 struct intel_mipmap_tree
*dst
);
1486 void brw_meta_fbo_stencil_blit(struct brw_context
*brw
,
1487 GLfloat srcX0
, GLfloat srcY0
,
1488 GLfloat srcX1
, GLfloat srcY1
,
1489 GLfloat dstX0
, GLfloat dstY0
,
1490 GLfloat dstX1
, GLfloat dstY1
);
1492 void brw_meta_stencil_updownsample(struct brw_context
*brw
,
1493 struct intel_mipmap_tree
*src
,
1494 struct intel_mipmap_tree
*dst
);
1495 /*======================================================================
1498 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1499 uint32_t depth_level
,
1500 uint32_t depth_layer
,
1501 struct intel_mipmap_tree
*stencil_mt
,
1502 uint32_t *out_tile_mask_x
,
1503 uint32_t *out_tile_mask_y
);
1504 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1505 GLbitfield clear_mask
);
1507 /* brw_object_purgeable.c */
1508 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1510 /*======================================================================
1513 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1514 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1515 void brw_emit_query_begin(struct brw_context
*brw
);
1516 void brw_emit_query_end(struct brw_context
*brw
);
1518 /** gen6_queryobj.c */
1519 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1520 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1521 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1522 void brw_store_register_mem64(struct brw_context
*brw
,
1523 drm_intel_bo
*bo
, uint32_t reg
, int idx
);
1525 /** intel_batchbuffer.c */
1526 void brw_load_register_mem(struct brw_context
*brw
,
1529 uint32_t read_domains
, uint32_t write_domain
,
1532 /*======================================================================
1535 void brw_debug_batch(struct brw_context
*brw
);
1536 void brw_annotate_aub(struct brw_context
*brw
);
1538 /*======================================================================
1541 void brw_validate_textures( struct brw_context
*brw
);
1544 /*======================================================================
1547 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1549 int brw_get_scratch_size(int size
);
1550 void brw_get_scratch_bo(struct brw_context
*brw
,
1551 drm_intel_bo
**scratch_bo
, int size
);
1552 void brw_init_shader_time(struct brw_context
*brw
);
1553 int brw_get_shader_time_index(struct brw_context
*brw
,
1554 struct gl_shader_program
*shader_prog
,
1555 struct gl_program
*prog
,
1556 enum shader_time_shader_type type
);
1557 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1558 void brw_destroy_shader_time(struct brw_context
*brw
);
1562 void brw_upload_urb_fence(struct brw_context
*brw
);
1566 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1568 /* brw_fs_reg_allocate.cpp
1570 void brw_fs_alloc_reg_sets(struct intel_screen
*screen
);
1572 /* brw_vec4_reg_allocate.cpp */
1573 void brw_vec4_alloc_reg_set(struct intel_screen
*screen
);
1576 int brw_disassemble_inst(FILE *file
, struct brw_instruction
*inst
,
1577 int gen
, bool is_compacted
);
1580 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1582 /* brw_draw_upload.c */
1583 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1584 const struct gl_client_array
*glarray
);
1585 unsigned brw_get_index_type(GLenum type
);
1586 void brw_prepare_vertices(struct brw_context
*brw
);
1588 /* brw_wm_surface_state.c */
1589 void brw_init_surface_formats(struct brw_context
*brw
);
1590 void brw_create_constant_surface(struct brw_context
*brw
,
1594 uint32_t *out_offset
,
1596 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1598 uint32_t *surf_offset
);
1600 brw_update_sol_surface(struct brw_context
*brw
,
1601 struct gl_buffer_object
*buffer_obj
,
1602 uint32_t *out_offset
, unsigned num_vector_components
,
1603 unsigned stride_dwords
, unsigned offset_dwords
);
1604 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1605 struct gl_shader
*shader
,
1606 struct brw_stage_state
*stage_state
,
1607 struct brw_stage_prog_data
*prog_data
);
1608 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1609 struct gl_shader_program
*prog
,
1610 struct brw_stage_state
*stage_state
,
1611 struct brw_stage_prog_data
*prog_data
);
1613 /* brw_surface_formats.c */
1614 bool brw_is_hiz_depth_format(struct brw_context
*ctx
, mesa_format format
);
1615 bool brw_render_target_supported(struct brw_context
*brw
,
1616 struct gl_renderbuffer
*rb
);
1617 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1619 /* brw_performance_monitor.c */
1620 void brw_init_performance_monitors(struct brw_context
*brw
);
1621 void brw_dump_perf_monitors(struct brw_context
*brw
);
1622 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1623 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1625 /* intel_buffer_objects.c */
1626 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1627 const char *bo_name
);
1628 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1629 const char *bo_name
);
1631 /* intel_extensions.c */
1632 extern void intelInitExtensions(struct gl_context
*ctx
);
1635 extern int intel_translate_shadow_compare_func(GLenum func
);
1636 extern int intel_translate_compare_func(GLenum func
);
1637 extern int intel_translate_stencil_op(GLenum op
);
1638 extern int intel_translate_logic_op(GLenum opcode
);
1640 /* intel_syncobj.c */
1641 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1644 struct gl_transform_feedback_object
*
1645 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1647 brw_delete_transform_feedback(struct gl_context
*ctx
,
1648 struct gl_transform_feedback_object
*obj
);
1650 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1651 struct gl_transform_feedback_object
*obj
);
1653 brw_end_transform_feedback(struct gl_context
*ctx
,
1654 struct gl_transform_feedback_object
*obj
);
1656 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1657 struct gl_transform_feedback_object
*obj
,
1660 /* gen7_sol_state.c */
1662 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1663 struct gl_transform_feedback_object
*obj
);
1665 gen7_end_transform_feedback(struct gl_context
*ctx
,
1666 struct gl_transform_feedback_object
*obj
);
1668 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1669 struct gl_transform_feedback_object
*obj
);
1671 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1672 struct gl_transform_feedback_object
*obj
);
1674 /* brw_blorp_blit.cpp */
1676 brw_blorp_framebuffer(struct brw_context
*brw
,
1677 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1678 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1679 GLbitfield mask
, GLenum filter
);
1682 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1683 struct gl_renderbuffer
*src_rb
,
1684 struct gl_texture_image
*dst_image
,
1686 int srcX0
, int srcY0
,
1687 int dstX0
, int dstY0
,
1688 int width
, int height
);
1690 /* gen6_multisample_state.c */
1692 gen6_determine_sample_mask(struct brw_context
*brw
);
1695 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1696 unsigned num_samples
);
1698 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1700 gen6_get_sample_position(struct gl_context
*ctx
,
1701 struct gl_framebuffer
*fb
,
1705 /* gen8_multisample_state.c */
1706 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1707 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1711 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1712 unsigned gs_size
, unsigned fs_size
);
1715 gen7_emit_urb_state(struct brw_context
*brw
,
1716 unsigned nr_vs_entries
, unsigned vs_size
,
1717 unsigned vs_start
, unsigned nr_gs_entries
,
1718 unsigned gs_size
, unsigned gs_start
);
1723 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1725 /*======================================================================
1726 * Inline conversion functions. These are better-typed than the
1727 * macros used previously:
1729 static inline struct brw_context
*
1730 brw_context( struct gl_context
*ctx
)
1732 return (struct brw_context
*)ctx
;
1735 static inline struct brw_vertex_program
*
1736 brw_vertex_program(struct gl_vertex_program
*p
)
1738 return (struct brw_vertex_program
*) p
;
1741 static inline const struct brw_vertex_program
*
1742 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1744 return (const struct brw_vertex_program
*) p
;
1747 static inline struct brw_geometry_program
*
1748 brw_geometry_program(struct gl_geometry_program
*p
)
1750 return (struct brw_geometry_program
*) p
;
1753 static inline struct brw_fragment_program
*
1754 brw_fragment_program(struct gl_fragment_program
*p
)
1756 return (struct brw_fragment_program
*) p
;
1759 static inline const struct brw_fragment_program
*
1760 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1762 return (const struct brw_fragment_program
*) p
;
1766 * Pre-gen6, the register file of the EUs was shared between threads,
1767 * and each thread used some subset allocated on a 16-register block
1768 * granularity. The unit states wanted these block counts.
1771 brw_register_blocks(int reg_count
)
1773 return ALIGN(reg_count
, 16) / 16 - 1;
1776 static inline uint32_t
1777 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1778 uint32_t prog_offset
)
1780 if (brw
->gen
>= 5) {
1781 /* Using state base address. */
1785 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1789 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1791 return brw
->cache
.bo
->offset64
+ prog_offset
;
1794 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1795 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1796 struct exec_list
*instructions
);
1797 bool brw_do_lower_unnormalized_offset(struct exec_list
*instructions
);
1799 struct opcode_desc
{
1805 extern const struct opcode_desc opcode_descs
[128];
1806 extern const char * const conditional_modifier
[16];
1809 brw_emit_depthbuffer(struct brw_context
*brw
);
1812 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1813 struct intel_mipmap_tree
*depth_mt
,
1814 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1815 uint32_t depth_surface_type
,
1816 struct intel_mipmap_tree
*stencil_mt
,
1817 bool hiz
, bool separate_stencil
,
1818 uint32_t width
, uint32_t height
,
1819 uint32_t tile_x
, uint32_t tile_y
);
1822 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1823 struct intel_mipmap_tree
*depth_mt
,
1824 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1825 uint32_t depth_surface_type
,
1826 struct intel_mipmap_tree
*stencil_mt
,
1827 bool hiz
, bool separate_stencil
,
1828 uint32_t width
, uint32_t height
,
1829 uint32_t tile_x
, uint32_t tile_y
);
1831 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1832 struct intel_mipmap_tree
*depth_mt
,
1833 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1834 uint32_t depth_surface_type
,
1835 struct intel_mipmap_tree
*stencil_mt
,
1836 bool hiz
, bool separate_stencil
,
1837 uint32_t width
, uint32_t height
,
1838 uint32_t tile_x
, uint32_t tile_y
);
1840 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1841 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);
1843 extern const GLuint prim_to_hw_prim
[GL_TRIANGLE_STRIP_ADJACENCY
+1];
1846 brw_setup_vec4_key_clip_info(struct brw_context
*brw
,
1847 struct brw_vec4_prog_key
*key
,
1848 bool program_uses_clip_distance
);
1851 gen6_upload_vec4_push_constants(struct brw_context
*brw
,
1852 const struct gl_program
*prog
,
1853 const struct brw_vec4_prog_data
*prog_data
,
1854 struct brw_stage_state
*stage_state
,
1855 enum state_struct_type type
);
1857 /* ================================================================
1858 * From linux kernel i386 header files, copes with odd sizes better
1859 * than COPY_DWORDS would:
1860 * XXX Put this in src/mesa/main/imports.h ???
1862 #if defined(i386) || defined(__i386__)
1863 static inline void * __memcpy(void * to
, const void * from
, size_t n
)
1866 __asm__
__volatile__(
1871 "1:\ttestb $1,%b4\n\t"
1875 : "=&c" (d0
), "=&D" (d1
), "=&S" (d2
)
1876 :"0" (n
/4), "q" (n
),"1" ((long) to
),"2" ((long) from
)
1881 #define __memcpy(a,b,c) memcpy(a,b,c)