2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
37 #include "main/macros.h"
38 #include "main/mtypes.h"
39 #include "brw_structs.h"
40 #include "brw_compiler.h"
41 #include "intel_aub.h"
44 #include "blorp/blorp.h"
48 /* Evil hack for using libdrm in a c++ compiler. */
52 #include <intel_bufmgr.h>
61 #include "intel_debug.h"
62 #include "intel_screen.h"
63 #include "intel_tex_obj.h"
64 #include "intel_resolve_map.h"
68 * URB - uniform resource buffer. A mid-sized buffer which is
69 * partitioned between the fixed function units and used for passing
70 * values (vertices, primitives, constants) between them.
72 * CURBE - constant URB entry. An urb region (entry) used to hold
73 * constant values which the fixed function units can be instructed to
74 * preload into the GRF when spawning a thread.
76 * VUE - vertex URB entry. An urb entry holding a vertex and usually
77 * a vertex header. The header contains control information and
78 * things like primitive type, Begin/end flags and clip codes.
80 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
81 * unit holding rasterization and interpolation parameters.
83 * GRF - general register file. One of several register files
84 * addressable by programmed threads. The inputs (r0, payload, curbe,
85 * urb) of the thread are preloaded to this area before the thread is
86 * spawned. The registers are individually 8 dwords wide and suitable
87 * for general usage. Registers holding thread input values are not
88 * special and may be overwritten.
90 * MRF - message register file. Threads communicate (and terminate)
91 * by sending messages. Message parameters are placed in contiguous
92 * MRF registers. All program output is via these messages. URB
93 * entries are populated by sending a message to the shared URB
94 * function containing the new data, together with a control word,
95 * often an unmodified copy of R0.
97 * R0 - GRF register 0. Typically holds control information used when
98 * sending messages to other threads.
100 * EU or GEN4 EU: The name of the programmable subsystem of the
101 * i965 hardware. Threads are executed by the EU, the registers
102 * described above are part of the EU architecture.
104 * Fixed function units:
106 * CS - Command streamer. Notional first unit, little software
107 * interaction. Holds the URB entries used for constant data, ie the
110 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
111 * this unit is responsible for pulling vertices out of vertex buffers
112 * in vram and injecting them into the processing pipe as VUEs. If
113 * enabled, it first passes them to a VS thread which is a good place
114 * for the driver to implement any active vertex shader.
116 * HS - Hull Shader (Tessellation Control Shader)
118 * TE - Tessellation Engine (Tessellation Primitive Generation)
120 * DS - Domain Shader (Tessellation Evaluation Shader)
122 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
123 * enabled, incoming strips etc are passed to GS threads in individual
124 * line/triangle/point units. The GS thread may perform arbitary
125 * computation and emit whatever primtives with whatever vertices it
126 * chooses. This makes GS an excellent place to implement GL's
127 * unfilled polygon modes, though of course it is capable of much
128 * more. Additionally, GS is used to translate away primitives not
129 * handled by latter units, including Quads and Lineloops.
131 * CS - Clipper. Mesa's clipping algorithms are imported to run on
132 * this unit. The fixed function part performs cliptesting against
133 * the 6 fixed clipplanes and makes descisions on whether or not the
134 * incoming primitive needs to be passed to a thread for clipping.
135 * User clip planes are handled via cooperation with the VS thread.
137 * SF - Strips Fans or Setup: Triangles are prepared for
138 * rasterization. Interpolation coefficients are calculated.
139 * Flatshading and two-side lighting usually performed here.
141 * WM - Windower. Interpolation of vertex attributes performed here.
142 * Fragment shader implemented here. SIMD aspects of EU taken full
143 * advantage of, as pixels are processed in blocks of 16.
145 * CC - Color Calculator. No EU threads associated with this unit.
146 * Handles blending and (presumably) depth and stencil testing.
151 struct brw_vs_prog_key
;
152 struct brw_vue_prog_key
;
153 struct brw_wm_prog_key
;
154 struct brw_wm_prog_data
;
155 struct brw_cs_prog_key
;
156 struct brw_cs_prog_data
;
160 BRW_COMPUTE_PIPELINE
,
167 BRW_CACHE_BLORP_PROG
,
170 BRW_CACHE_FF_GS_PROG
,
181 /* brw_cache_ids must come first - see brw_program_cache.c */
182 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
183 BRW_STATE_FRAGMENT_PROGRAM
,
184 BRW_STATE_GEOMETRY_PROGRAM
,
185 BRW_STATE_TESS_PROGRAMS
,
186 BRW_STATE_VERTEX_PROGRAM
,
187 BRW_STATE_CURBE_OFFSETS
,
188 BRW_STATE_REDUCED_PRIMITIVE
,
189 BRW_STATE_PATCH_PRIMITIVE
,
194 BRW_STATE_BINDING_TABLE_POINTERS
,
197 BRW_STATE_DEFAULT_TESS_LEVELS
,
199 BRW_STATE_INDEX_BUFFER
,
200 BRW_STATE_VS_CONSTBUF
,
201 BRW_STATE_TCS_CONSTBUF
,
202 BRW_STATE_TES_CONSTBUF
,
203 BRW_STATE_GS_CONSTBUF
,
204 BRW_STATE_PROGRAM_CACHE
,
205 BRW_STATE_STATE_BASE_ADDRESS
,
206 BRW_STATE_VUE_MAP_GEOM_OUT
,
207 BRW_STATE_TRANSFORM_FEEDBACK
,
208 BRW_STATE_RASTERIZER_DISCARD
,
210 BRW_STATE_UNIFORM_BUFFER
,
211 BRW_STATE_ATOMIC_BUFFER
,
212 BRW_STATE_IMAGE_UNITS
,
213 BRW_STATE_META_IN_PROGRESS
,
214 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
215 BRW_STATE_NUM_SAMPLES
,
216 BRW_STATE_TEXTURE_BUFFER
,
217 BRW_STATE_GEN4_UNIT_STATE
,
221 BRW_STATE_SAMPLER_STATE_TABLE
,
222 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
223 BRW_STATE_COMPUTE_PROGRAM
,
224 BRW_STATE_CS_WORK_GROUPS
,
228 BRW_STATE_VIEWPORT_COUNT
,
229 BRW_STATE_CONSERVATIVE_RASTERIZATION
,
234 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
236 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
237 * When the currently bound shader program differs from the previous draw
238 * call, these will be flagged. They cover brw->{stage}_program and
239 * ctx->{Stage}Program->_Current.
241 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
242 * driver perspective. Even if the same shader is bound at the API level,
243 * we may need to switch between multiple versions of that shader to handle
244 * changes in non-orthagonal state.
246 * Additionally, multiple shader programs may have identical vertex shaders
247 * (for example), or compile down to the same code in the backend. We combine
248 * those into a single program cache entry.
250 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
251 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
253 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
254 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
255 * use the normal state upload paths), but the cache is still used. To avoid
256 * polluting the brw_program_cache code with special cases, we retain the
257 * dirty bit for now. It should eventually be removed.
259 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_PROG)
260 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
261 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
262 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
263 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
264 #define BRW_NEW_TCS_PROG_DATA (1ull << BRW_CACHE_TCS_PROG)
265 #define BRW_NEW_TES_PROG_DATA (1ull << BRW_CACHE_TES_PROG)
266 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
267 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
268 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
269 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
270 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
271 #define BRW_NEW_TESS_PROGRAMS (1ull << BRW_STATE_TESS_PROGRAMS)
272 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
273 #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
274 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
275 #define BRW_NEW_PATCH_PRIMITIVE (1ull << BRW_STATE_PATCH_PRIMITIVE)
276 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
277 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
278 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
279 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
280 #define BRW_NEW_BINDING_TABLE_POINTERS (1ull << BRW_STATE_BINDING_TABLE_POINTERS)
281 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
282 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
283 #define BRW_NEW_DEFAULT_TESS_LEVELS (1ull << BRW_STATE_DEFAULT_TESS_LEVELS)
285 * Used for any batch entry with a relocated pointer that will be used
286 * by any 3D rendering.
288 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
289 /** \see brw.state.depth_region */
290 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
291 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
292 #define BRW_NEW_TCS_CONSTBUF (1ull << BRW_STATE_TCS_CONSTBUF)
293 #define BRW_NEW_TES_CONSTBUF (1ull << BRW_STATE_TES_CONSTBUF)
294 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
295 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
296 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
297 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
298 #define BRW_NEW_VIEWPORT_COUNT (1ull << BRW_STATE_VIEWPORT_COUNT)
299 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
300 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
301 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
302 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
303 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
304 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
305 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
306 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
307 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
308 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
309 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
310 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
311 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
312 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
313 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
314 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
315 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
316 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
317 #define BRW_NEW_URB_SIZE (1ull << BRW_STATE_URB_SIZE)
318 #define BRW_NEW_CC_STATE (1ull << BRW_STATE_CC_STATE)
319 #define BRW_NEW_BLORP (1ull << BRW_STATE_BLORP)
320 #define BRW_NEW_CONSERVATIVE_RASTERIZATION (1ull << BRW_STATE_CONSERVATIVE_RASTERIZATION)
322 struct brw_state_flags
{
323 /** State update flags signalled by mesa internals */
326 * State update flags signalled as the result of brw_tracked_state updates
332 /** Subclass of Mesa program */
334 struct gl_program program
;
341 struct gen4_fragment_program
{
342 struct brw_program base
;
344 bool contains_flat_varying
;
345 bool contains_noperspective_varying
;
348 * Mapping of varying slots to interpolation modes.
349 * Used Gen4/5 by the clip|sf|wm stages.
351 unsigned char interp_mode
[BRW_VARYING_SLOT_COUNT
];
356 * Bitmask indicating which fragment shader inputs represent varyings (and
357 * hence have to be delivered to the fragment shader by the SF/SBE stage).
359 #define BRW_FS_VARYING_INPUT_MASK \
360 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
361 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
364 struct brw_sf_prog_data
{
365 GLuint urb_read_length
;
368 /* Each vertex may have upto 12 attributes, 4 components each,
369 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
372 * Actually we use 4 for each, so call it 12 rows.
374 GLuint urb_entry_size
;
379 * We always program SF to start reading at an offset of 1 (2 varying slots)
380 * from the start of the vertex URB entry. This causes it to skip:
381 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
382 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
384 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
387 struct brw_clip_prog_data
{
388 GLuint curb_read_length
; /* user planes? */
390 GLuint urb_read_length
;
394 struct brw_ff_gs_prog_data
{
395 GLuint urb_read_length
;
399 * Gen6 transform feedback: Amount by which the streaming vertex buffer
400 * indices should be incremented each time the GS is invoked.
402 unsigned svbi_postincrement_value
;
405 /** Number of texture sampler units */
406 #define BRW_MAX_TEX_UNIT 32
408 /** Max number of render targets in a shader */
409 #define BRW_MAX_DRAW_BUFFERS 8
411 /** Max number of UBOs in a shader */
412 #define BRW_MAX_UBO 14
414 /** Max number of SSBOs in a shader */
415 #define BRW_MAX_SSBO 12
417 /** Max number of atomic counter buffer objects in a shader */
418 #define BRW_MAX_ABO 16
420 /** Max number of image uniforms in a shader */
421 #define BRW_MAX_IMAGES 32
424 * Max number of binding table entries used for stream output.
426 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
427 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
429 * On Gen6, the size of transform feedback data is limited not by the number
430 * of components but by the number of binding table entries we set aside. We
431 * use one binding table entry for a float, one entry for a vector, and one
432 * entry per matrix column. Since the only way we can communicate our
433 * transform feedback capabilities to the client is via
434 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
435 * worst case, in which all the varyings are floats, so we use up one binding
436 * table entry per component. Therefore we need to set aside at least 64
437 * binding table entries for use by transform feedback.
439 * Note: since we don't currently pack varyings, it is currently impossible
440 * for the client to actually use up all of these binding table entries--if
441 * all of their varyings were floats, they would run out of varying slots and
442 * fail to link. But that's a bug, so it seems prudent to go ahead and
443 * allocate the number of binding table entries we will need once the bug is
446 #define BRW_MAX_SOL_BINDINGS 64
448 /** Maximum number of actual buffers used for stream output */
449 #define BRW_MAX_SOL_BUFFERS 4
451 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
452 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
457 2 + /* shader time, pull constants */ \
458 1 /* cs num work groups */)
460 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
463 * Stride in bytes between shader_time entries.
465 * We separate entries by a cacheline to reduce traffic between EUs writing to
468 #define SHADER_TIME_STRIDE 64
470 struct brw_cache_item
{
472 * Effectively part of the key, cache_id identifies what kind of state
473 * buffer is involved, and also which dirty flag should set.
475 enum brw_cache_id cache_id
;
476 /** 32-bit hash of the key data */
478 GLuint key_size
; /* for variable-sized keys */
485 struct brw_cache_item
*next
;
490 struct brw_context
*brw
;
492 struct brw_cache_item
**items
;
494 GLuint size
, n_items
;
496 uint32_t next_offset
;
501 /* Considered adding a member to this struct to document which flags
502 * an update might raise so that ordering of the state atoms can be
503 * checked or derived at runtime. Dropped the idea in favor of having
504 * a debug mode where the state is monitored for flags which are
505 * raised that have already been tested against.
507 struct brw_tracked_state
{
508 struct brw_state_flags dirty
;
509 void (*emit
)( struct brw_context
*brw
);
512 enum shader_time_shader_type
{
523 struct brw_vertex_buffer
{
524 /** Buffer object containing the uploaded vertex data */
528 /** Byte stride between elements in the uploaded array */
532 struct brw_vertex_element
{
533 const struct gl_vertex_array
*glarray
;
537 /** Offset of the first element within the buffer object */
541 struct brw_query_object
{
542 struct gl_query_object Base
;
544 /** Last query BO associated with this query. */
547 /** Last index in bo with query data for this object. */
550 /** True if we know the batch has been flushed since we ended the query. */
560 struct intel_batchbuffer
{
561 /** Current batchbuffer being queued up. */
563 /** Last BO submitted to the hardware. Used for glFinish(). */
564 drm_intel_bo
*last_bo
;
567 uint16_t emit
, total
;
569 uint16_t reserved_space
;
573 #define BATCH_SZ (8192*sizeof(uint32_t))
575 uint32_t state_batch_offset
;
576 enum brw_gpu_ring ring
;
577 bool needs_sol_reset
;
578 bool state_base_address_emitted
;
586 #define MAX_GS_INPUT_VERTICES 6
588 #define BRW_MAX_XFB_STREAMS 4
590 struct brw_transform_feedback_object
{
591 struct gl_transform_feedback_object base
;
593 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
594 drm_intel_bo
*offset_bo
;
596 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
599 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
600 GLenum primitive_mode
;
603 * Count of primitives generated during this transform feedback operation.
606 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
607 drm_intel_bo
*prim_count_bo
;
608 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
612 * Number of vertices written between last Begin/EndTransformFeedback().
614 * Used to implement DrawTransformFeedback().
616 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
617 bool vertices_written_valid
;
621 * Data shared between each programmable stage in the pipeline (vs, gs, and
624 struct brw_stage_state
626 gl_shader_stage stage
;
627 struct brw_stage_prog_data
*prog_data
;
630 * Optional scratch buffer used to store spilled register values and
631 * variably-indexed GRF arrays.
633 * The contents of this buffer are short-lived so the same memory can be
634 * re-used at will for multiple shader programs (executed by the same fixed
635 * function). However reusing a scratch BO for which shader invocations
636 * are still in flight with a per-thread scratch slot size other than the
637 * original can cause threads with different scratch slot size and FFTID
638 * (which may be executed in parallel depending on the shader stage and
639 * hardware generation) to map to an overlapping region of the scratch
640 * space, which can potentially lead to mutual scratch space corruption.
641 * For that reason if you borrow this scratch buffer you should only be
642 * using the slot size given by the \c per_thread_scratch member below,
643 * unless you're taking additional measures to synchronize thread execution
644 * across slot size changes.
646 drm_intel_bo
*scratch_bo
;
649 * Scratch slot size allocated for each thread in the buffer object given
652 uint32_t per_thread_scratch
;
654 /** Offset in the program cache to the program */
655 uint32_t prog_offset
;
657 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
658 uint32_t state_offset
;
660 uint32_t push_const_offset
; /* Offset in the batchbuffer */
661 int push_const_size
; /* in 256-bit register increments */
663 /* Binding table: pointers to SURFACE_STATE entries. */
664 uint32_t bind_bo_offset
;
665 uint32_t surf_offset
[BRW_MAX_SURFACES
];
667 /** SAMPLER_STATE count and table offset */
668 uint32_t sampler_count
;
669 uint32_t sampler_offset
;
672 enum brw_predicate_state
{
673 /* The first two states are used if we can determine whether to draw
674 * without having to look at the values in the query object buffer. This
675 * will happen if there is no conditional render in progress, if the query
676 * object is already completed or if something else has already added
677 * samples to the preliminary result such as via a BLT command.
679 BRW_PREDICATE_STATE_RENDER
,
680 BRW_PREDICATE_STATE_DONT_RENDER
,
681 /* In this case whether to draw or not depends on the result of an
682 * MI_PREDICATE command so the predicate enable bit needs to be checked.
684 BRW_PREDICATE_STATE_USE_BIT
689 struct gen_l3_config
;
692 * brw_context is derived from gl_context.
696 struct gl_context ctx
; /**< base class, must be first field */
700 uint32_t (*update_renderbuffer_surface
)(struct brw_context
*brw
,
701 struct gl_renderbuffer
*rb
,
702 uint32_t flags
, unsigned unit
,
703 uint32_t surf_index
);
704 void (*emit_null_surface_state
)(struct brw_context
*brw
,
708 uint32_t *out_offset
);
711 * Send the appropriate state packets to configure depth, stencil, and
712 * HiZ buffers (i965+ only)
714 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
715 struct intel_mipmap_tree
*depth_mt
,
716 uint32_t depth_offset
,
717 uint32_t depthbuffer_format
,
718 uint32_t depth_surface_type
,
719 struct intel_mipmap_tree
*stencil_mt
,
720 bool hiz
, bool separate_stencil
,
721 uint32_t width
, uint32_t height
,
722 uint32_t tile_x
, uint32_t tile_y
);
728 drm_intel_context
*hw_ctx
;
730 /** BO for post-sync nonzero writes for gen6 workaround. */
731 drm_intel_bo
*workaround_bo
;
732 uint8_t pipe_controls_since_last_cs_stall
;
735 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
736 * and would need flushing before being used from another cache domain that
737 * isn't coherent with it (i.e. the sampler).
739 struct set
*render_cache
;
742 * Number of resets observed in the system at context creation.
744 * This is tracked in the context so that we can determine that another
745 * reset has occurred.
747 uint32_t reset_count
;
749 struct intel_batchbuffer batch
;
754 uint32_t next_offset
;
758 * Set if rendering has occurred to the drawable's front buffer.
760 * This is used in the DRI2 case to detect that glFlush should also copy
761 * the contents of the fake front buffer to the real front buffer.
763 bool front_buffer_dirty
;
765 /** Framerate throttling: @{ */
766 drm_intel_bo
*throttle_batch
[2];
768 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
769 * frame of rendering to complete. This gives a very precise cap to the
770 * latency between input and output such that rendering never gets more
771 * than a frame behind the user. (With the caveat that we technically are
772 * not using the SwapBuffers itself as a barrier but the first batch
773 * submitted afterwards, which may be immediately prior to the next
776 bool need_swap_throttle
;
778 /** General throttling, not caught by throttling between SwapBuffers */
779 bool need_flush_throttle
;
789 bool always_flush_batch
;
790 bool always_flush_cache
;
791 bool disable_throttling
;
793 bool dual_color_blend_by_location
;
795 driOptionCache optionCache
;
798 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
800 GLenum reduced_primitive
;
803 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
804 * variable is set, this is the flag indicating to do expensive work that
805 * might lead to a perf_debug() call.
809 uint64_t max_gtt_map_object_size
;
821 bool has_separate_stencil
;
822 bool must_use_separate_stencil
;
825 bool has_surface_tile_offset
;
827 bool has_negative_rhw_bug
;
831 bool use_resource_streamer
;
834 * Whether LRI can be used to write register values from the batch buffer.
836 bool can_do_pipelined_register_writes
;
839 * Some versions of Gen hardware don't do centroid interpolation correctly
840 * on unlit pixels, causing incorrect values for derivatives near triangle
841 * edges. Enabling this flag causes the fragment shader to use
842 * non-centroid interpolation for unlit pixels, at the expense of two extra
843 * fragment shader instructions.
845 bool needs_unlit_centroid_workaround
;
847 struct isl_device isl_dev
;
849 struct blorp_context blorp
;
853 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
856 enum brw_pipeline last_pipeline
;
858 struct brw_cache cache
;
860 /** IDs for meta stencil blit shader programs. */
861 struct gl_shader_program
*meta_stencil_blit_programs
[2];
863 /* Whether a meta-operation is in progress. */
864 bool meta_in_progress
;
866 /* Whether the last depth/stencil packets were both NULL. */
867 bool no_depth_or_stencil
;
869 /* The last PMA stall bits programmed. */
870 uint32_t pma_stall_bits
;
874 /** The value of gl_BaseVertex for the current _mesa_prim. */
877 /** The value of gl_BaseInstance for the current _mesa_prim. */
882 * Buffer and offset used for GL_ARB_shader_draw_parameters
883 * (for now, only gl_BaseVertex).
885 drm_intel_bo
*draw_params_bo
;
886 uint32_t draw_params_offset
;
889 * The value of gl_DrawID for the current _mesa_prim. This always comes
890 * in from it's own vertex buffer since it's not part of the indirect
894 drm_intel_bo
*draw_id_bo
;
895 uint32_t draw_id_offset
;
900 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
901 * an indirect call, and num_work_groups_offset is valid. Otherwise,
902 * num_work_groups is set based on glDispatchCompute.
904 drm_intel_bo
*num_work_groups_bo
;
905 GLintptr num_work_groups_offset
;
906 const GLuint
*num_work_groups
;
910 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
911 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
913 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
917 /* Summary of size and varying of active arrays, so we can check
918 * for changes to this state:
920 bool index_bounds_valid
;
921 unsigned int min_index
, max_index
;
923 /* Offset from start of vertex buffer so we can avoid redefining
924 * the same VB packed over and over again.
926 unsigned int start_vertex_bias
;
929 * Certain vertex attribute formats aren't natively handled by the
930 * hardware and require special VS code to fix up their values.
932 * These bitfields indicate which workarounds are needed.
934 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
939 * Index buffer for this draw_prims call.
941 * Updates are signaled by BRW_NEW_INDICES.
943 const struct _mesa_index_buffer
*ib
;
945 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
950 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
951 * avoid re-uploading the IB packet over and over if we're actually
952 * referencing the same index buffer.
954 unsigned int start_vertex_offset
;
957 /* Active vertex program:
959 const struct gl_program
*vertex_program
;
960 const struct gl_program
*geometry_program
;
961 const struct gl_program
*tess_ctrl_program
;
962 const struct gl_program
*tess_eval_program
;
963 const struct gl_program
*fragment_program
;
964 const struct gl_program
*compute_program
;
967 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
968 * that we don't have to reemit that state every time we change FBOs.
972 /* BRW_NEW_URB_ALLOCATIONS:
975 GLuint vsize
; /* vertex size plus header in urb registers */
976 GLuint gsize
; /* GS output size in urb registers */
977 GLuint hsize
; /* Tessellation control output size in urb registers */
978 GLuint dsize
; /* Tessellation evaluation output size in urb registers */
979 GLuint csize
; /* constant buffer size in urb registers */
980 GLuint sfsize
; /* setup data size in urb registers */
984 GLuint nr_vs_entries
;
985 GLuint nr_hs_entries
;
986 GLuint nr_ds_entries
;
987 GLuint nr_gs_entries
;
988 GLuint nr_clip_entries
;
989 GLuint nr_sf_entries
;
990 GLuint nr_cs_entries
;
1000 * URB size in the current configuration. The units this is expressed
1001 * in are somewhat inconsistent, see gen_device_info::urb::size.
1003 * FINISHME: Represent the URB size consistently in KB on all platforms.
1007 /* True if the most recently sent _3DSTATE_URB message allocated
1008 * URB space for the GS.
1012 /* True if the most recently sent _3DSTATE_URB message allocated
1013 * URB space for the HS and DS.
1019 /* BRW_NEW_CURBE_OFFSETS:
1022 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1023 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1031 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1032 * for upload to the CURBE.
1034 drm_intel_bo
*curbe_bo
;
1035 /** Offset within curbe_bo of space for current curbe entry */
1036 GLuint curbe_offset
;
1040 * Layout of vertex data exiting the geometry portion of the pipleine.
1041 * This comes from the last enabled shader stage (GS, DS, or VS).
1043 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1045 struct brw_vue_map vue_map_geom_out
;
1048 struct brw_stage_state base
;
1052 struct brw_stage_state base
;
1055 * True if the 3DSTATE_HS command most recently emitted to the 3D
1056 * pipeline enabled the HS; false otherwise.
1062 struct brw_stage_state base
;
1065 * True if the 3DSTATE_DS command most recently emitted to the 3D
1066 * pipeline enabled the DS; false otherwise.
1072 struct brw_stage_state base
;
1075 * True if the 3DSTATE_GS command most recently emitted to the 3D
1076 * pipeline enabled the GS; false otherwise.
1082 struct brw_ff_gs_prog_data
*prog_data
;
1085 /** Offset in the program cache to the CLIP program pre-gen6 */
1086 uint32_t prog_offset
;
1087 uint32_t state_offset
;
1089 uint32_t bind_bo_offset
;
1091 * Surface offsets for the binding table. We only need surfaces to
1092 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1093 * need in this case.
1095 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1099 struct brw_clip_prog_data
*prog_data
;
1101 /** Offset in the program cache to the CLIP program pre-gen6 */
1102 uint32_t prog_offset
;
1104 /* Offset in the batch to the CLIP state on pre-gen6. */
1105 uint32_t state_offset
;
1107 /* As of gen6, this is the offset in the batch to the CLIP VP,
1113 * The number of viewports to use. If gl_ViewportIndex is written,
1114 * we can have up to ctx->Const.MaxViewports viewports. If not,
1115 * the viewport index is always 0, so we can only emit one.
1117 uint8_t viewport_count
;
1122 struct brw_sf_prog_data
*prog_data
;
1124 /** Offset in the program cache to the CLIP program pre-gen6 */
1125 uint32_t prog_offset
;
1126 uint32_t state_offset
;
1128 bool viewport_transform_enable
;
1132 struct brw_stage_state base
;
1137 * Buffer object used in place of multisampled null render targets on
1138 * Gen6. See brw_emit_null_surface_state().
1140 drm_intel_bo
*multisampled_null_render_target_bo
;
1141 uint32_t fast_clear_op
;
1147 struct brw_stage_state base
;
1150 /* RS hardware binding table */
1153 uint32_t next_offset
;
1157 uint32_t state_offset
;
1158 uint32_t blend_state_offset
;
1159 uint32_t depth_stencil_state_offset
;
1164 struct brw_query_object
*obj
;
1169 enum brw_predicate_state state
;
1174 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1175 const int *statistics_registers
;
1177 /** The number of active monitors using OA counters. */
1181 * A buffer object storing OA counter snapshots taken at the start and
1182 * end of each batch (creating "bookends" around the batch).
1184 drm_intel_bo
*bookend_bo
;
1186 /** The number of snapshots written to bookend_bo. */
1187 int bookend_snapshots
;
1190 * An array of monitors whose results haven't yet been assembled based on
1191 * the data in buffer objects.
1193 * These may be active, or have already ended. However, the results
1194 * have not been requested.
1196 struct brw_perf_monitor_object
**unresolved
;
1197 int unresolved_elements
;
1198 int unresolved_array_size
;
1201 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1202 * the counter which MI_REPORT_PERF_COUNT stores there.
1204 const int *oa_snapshot_layout
;
1206 /** Number of 32-bit entries in a hardware counter snapshot. */
1207 int entries_per_oa_snapshot
;
1210 int num_atoms
[BRW_NUM_PIPELINES
];
1211 const struct brw_tracked_state render_atoms
[76];
1212 const struct brw_tracked_state compute_atoms
[11];
1214 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1218 enum aub_state_struct_type type
;
1220 } *state_batch_list
;
1221 int state_batch_count
;
1223 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1224 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1226 /* PrimitiveRestart */
1229 bool enable_cut_index
;
1232 /** Computed depth/stencil/hiz state from the current attached
1233 * renderbuffers, valid only during the drawing state upload loop after
1234 * brw_workaround_depthstencil_alignment().
1237 struct intel_mipmap_tree
*depth_mt
;
1238 struct intel_mipmap_tree
*stencil_mt
;
1240 /* Inter-tile (page-aligned) byte offsets. */
1241 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1242 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1243 uint32_t tile_x
, tile_y
;
1246 uint32_t num_instances
;
1251 const struct gen_l3_config
*config
;
1258 enum shader_time_shader_type
*types
;
1259 struct shader_times
*cumulative
;
1265 struct brw_fast_clear_state
*fast_clear_state
;
1267 /* Array of flags telling if auxiliary buffer is disabled for corresponding
1268 * renderbuffer. If draw_aux_buffer_disabled[i] is set then use of
1269 * auxiliary buffer for gl_framebuffer::_ColorDrawBuffers[i] is
1271 * This is needed in case the same underlying buffer is also configured
1272 * to be sampled but with a format that the sampling engine can't treat
1273 * compressed or fast cleared.
1275 bool draw_aux_buffer_disabled
[MAX_DRAW_BUFFERS
];
1277 __DRIcontext
*driContext
;
1278 struct intel_screen
*screen
;
1281 /*======================================================================
1284 void brwInitVtbl( struct brw_context
*brw
);
1287 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1289 /*======================================================================
1292 extern const char *const brw_vendor_string
;
1295 brw_get_renderer_string(const struct intel_screen
*screen
);
1298 DRI_CONF_BO_REUSE_DISABLED
,
1299 DRI_CONF_BO_REUSE_ALL
1302 void intel_update_renderbuffers(__DRIcontext
*context
,
1303 __DRIdrawable
*drawable
);
1304 void intel_prepare_render(struct brw_context
*brw
);
1306 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1307 __DRIdrawable
*drawable
);
1309 GLboolean
brwCreateContext(gl_api api
,
1310 const struct gl_config
*mesaVis
,
1311 __DRIcontext
*driContextPriv
,
1312 unsigned major_version
,
1313 unsigned minor_version
,
1317 void *sharedContextPrivate
);
1319 /*======================================================================
1323 brw_meta_resolve_color(struct brw_context
*brw
,
1324 struct intel_mipmap_tree
*mt
);
1326 /*======================================================================
1329 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1330 uint32_t depth_level
,
1331 uint32_t depth_layer
,
1332 struct intel_mipmap_tree
*stencil_mt
,
1333 uint32_t *out_tile_mask_x
,
1334 uint32_t *out_tile_mask_y
);
1335 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1336 GLbitfield clear_mask
);
1338 /* brw_object_purgeable.c */
1339 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1341 /*======================================================================
1344 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1345 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1346 void brw_emit_query_begin(struct brw_context
*brw
);
1347 void brw_emit_query_end(struct brw_context
*brw
);
1348 void brw_query_counter(struct gl_context
*ctx
, struct gl_query_object
*q
);
1349 bool brw_is_query_pipelined(struct brw_query_object
*query
);
1351 /** gen6_queryobj.c */
1352 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1353 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1354 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1356 /** hsw_queryobj.c */
1357 void hsw_init_queryobj_functions(struct dd_function_table
*functions
);
1359 /** brw_conditional_render.c */
1360 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1361 bool brw_check_conditional_render(struct brw_context
*brw
);
1363 /** intel_batchbuffer.c */
1364 void brw_load_register_mem(struct brw_context
*brw
,
1367 uint32_t read_domains
, uint32_t write_domain
,
1369 void brw_load_register_mem64(struct brw_context
*brw
,
1372 uint32_t read_domains
, uint32_t write_domain
,
1374 void brw_store_register_mem32(struct brw_context
*brw
,
1375 drm_intel_bo
*bo
, uint32_t reg
, uint32_t offset
);
1376 void brw_store_register_mem64(struct brw_context
*brw
,
1377 drm_intel_bo
*bo
, uint32_t reg
, uint32_t offset
);
1378 void brw_load_register_imm32(struct brw_context
*brw
,
1379 uint32_t reg
, uint32_t imm
);
1380 void brw_load_register_imm64(struct brw_context
*brw
,
1381 uint32_t reg
, uint64_t imm
);
1382 void brw_load_register_reg(struct brw_context
*brw
, uint32_t src
,
1384 void brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
,
1386 void brw_store_data_imm32(struct brw_context
*brw
, drm_intel_bo
*bo
,
1387 uint32_t offset
, uint32_t imm
);
1388 void brw_store_data_imm64(struct brw_context
*brw
, drm_intel_bo
*bo
,
1389 uint32_t offset
, uint64_t imm
);
1391 /*======================================================================
1394 void brw_debug_batch(struct brw_context
*brw
);
1395 void brw_annotate_aub(struct brw_context
*brw
);
1397 /*======================================================================
1398 * intel_tex_validate.c
1400 void brw_validate_textures( struct brw_context
*brw
);
1403 /*======================================================================
1407 key_debug(struct brw_context
*brw
, const char *name
, int a
, int b
)
1410 perf_debug(" %s %d->%d\n", name
, a
, b
);
1416 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1418 /* Per-thread scratch space is a power-of-two multiple of 1KB. */
1420 brw_get_scratch_size(int size
)
1422 return MAX2(1024, util_next_power_of_two(size
));
1424 void brw_get_scratch_bo(struct brw_context
*brw
,
1425 drm_intel_bo
**scratch_bo
, int size
);
1426 void brw_alloc_stage_scratch(struct brw_context
*brw
,
1427 struct brw_stage_state
*stage_state
,
1428 unsigned per_thread_size
,
1429 unsigned thread_count
);
1430 void brw_init_shader_time(struct brw_context
*brw
);
1431 int brw_get_shader_time_index(struct brw_context
*brw
,
1432 struct gl_shader_program
*shader_prog
,
1433 struct gl_program
*prog
,
1434 enum shader_time_shader_type type
);
1435 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1436 void brw_destroy_shader_time(struct brw_context
*brw
);
1440 void brw_upload_urb_fence(struct brw_context
*brw
);
1444 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1446 /* brw_fs_reg_allocate.cpp
1448 void brw_fs_alloc_reg_sets(struct brw_compiler
*compiler
);
1450 /* brw_vec4_reg_allocate.cpp */
1451 void brw_vec4_alloc_reg_set(struct brw_compiler
*compiler
);
1454 int brw_disassemble_inst(FILE *file
, const struct gen_device_info
*devinfo
,
1455 struct brw_inst
*inst
, bool is_compacted
);
1458 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1460 /* brw_draw_upload.c */
1461 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1462 const struct gl_vertex_array
*glarray
);
1464 static inline unsigned
1465 brw_get_index_type(GLenum type
)
1467 assert((type
== GL_UNSIGNED_BYTE
)
1468 || (type
== GL_UNSIGNED_SHORT
)
1469 || (type
== GL_UNSIGNED_INT
));
1471 /* The possible values for type are GL_UNSIGNED_BYTE (0x1401),
1472 * GL_UNSIGNED_SHORT (0x1403), and GL_UNSIGNED_INT (0x1405) which we want
1473 * to map to scale factors of 0, 1, and 2, respectively. These scale
1474 * factors are then left-shfited by 8 to be in the correct position in the
1475 * CMD_INDEX_BUFFER packet.
1477 * Subtracting 0x1401 gives 0, 2, and 4. Shifting left by 7 afterwards
1478 * gives 0x00000000, 0x00000100, and 0x00000200. These just happen to be
1479 * the values the need to be written in the CMD_INDEX_BUFFER packet.
1481 return (type
- 0x1401) << 7;
1484 void brw_prepare_vertices(struct brw_context
*brw
);
1486 /* brw_wm_surface_state.c */
1487 void brw_init_surface_formats(struct brw_context
*brw
);
1488 void brw_create_constant_surface(struct brw_context
*brw
,
1492 uint32_t *out_offset
);
1493 void brw_create_buffer_surface(struct brw_context
*brw
,
1497 uint32_t *out_offset
);
1498 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1500 uint32_t *surf_offset
);
1502 brw_update_sol_surface(struct brw_context
*brw
,
1503 struct gl_buffer_object
*buffer_obj
,
1504 uint32_t *out_offset
, unsigned num_vector_components
,
1505 unsigned stride_dwords
, unsigned offset_dwords
);
1506 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1507 struct gl_linked_shader
*shader
,
1508 struct brw_stage_state
*stage_state
,
1509 struct brw_stage_prog_data
*prog_data
);
1510 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1511 const struct gl_program
*prog
,
1512 struct brw_stage_state
*stage_state
,
1513 struct brw_stage_prog_data
*prog_data
);
1514 void brw_upload_image_surfaces(struct brw_context
*brw
,
1515 struct gl_linked_shader
*shader
,
1516 const struct gl_program
*prog
,
1517 struct brw_stage_state
*stage_state
,
1518 struct brw_stage_prog_data
*prog_data
);
1520 /* brw_surface_formats.c */
1521 bool brw_render_target_supported(struct brw_context
*brw
,
1522 struct gl_renderbuffer
*rb
);
1523 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1525 /* brw_performance_monitor.c */
1526 void brw_init_performance_monitors(struct brw_context
*brw
);
1527 void brw_dump_perf_monitors(struct brw_context
*brw
);
1528 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1529 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1531 /* intel_buffer_objects.c */
1532 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1533 const char *bo_name
);
1534 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1535 const char *bo_name
);
1537 /* intel_extensions.c */
1538 extern void intelInitExtensions(struct gl_context
*ctx
);
1541 extern int intel_translate_shadow_compare_func(GLenum func
);
1542 extern int intel_translate_compare_func(GLenum func
);
1543 extern int intel_translate_stencil_op(GLenum op
);
1544 extern int intel_translate_logic_op(GLenum opcode
);
1547 void brw_init_syncobj_functions(struct dd_function_table
*functions
);
1550 struct gl_transform_feedback_object
*
1551 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1553 brw_delete_transform_feedback(struct gl_context
*ctx
,
1554 struct gl_transform_feedback_object
*obj
);
1556 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1557 struct gl_transform_feedback_object
*obj
);
1559 brw_end_transform_feedback(struct gl_context
*ctx
,
1560 struct gl_transform_feedback_object
*obj
);
1562 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1563 struct gl_transform_feedback_object
*obj
,
1566 /* gen7_sol_state.c */
1568 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1569 struct gl_transform_feedback_object
*obj
);
1571 gen7_end_transform_feedback(struct gl_context
*ctx
,
1572 struct gl_transform_feedback_object
*obj
);
1574 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1575 struct gl_transform_feedback_object
*obj
);
1577 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1578 struct gl_transform_feedback_object
*obj
);
1582 hsw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1583 struct gl_transform_feedback_object
*obj
);
1585 hsw_end_transform_feedback(struct gl_context
*ctx
,
1586 struct gl_transform_feedback_object
*obj
);
1588 hsw_pause_transform_feedback(struct gl_context
*ctx
,
1589 struct gl_transform_feedback_object
*obj
);
1591 hsw_resume_transform_feedback(struct gl_context
*ctx
,
1592 struct gl_transform_feedback_object
*obj
);
1594 /* brw_blorp_blit.cpp */
1596 brw_blorp_framebuffer(struct brw_context
*brw
,
1597 struct gl_framebuffer
*readFb
,
1598 struct gl_framebuffer
*drawFb
,
1599 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1600 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1601 GLbitfield mask
, GLenum filter
);
1604 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1605 struct gl_renderbuffer
*src_rb
,
1606 struct gl_texture_image
*dst_image
,
1608 int srcX0
, int srcY0
,
1609 int dstX0
, int dstY0
,
1610 int width
, int height
);
1612 /* gen6_multisample_state.c */
1614 gen6_determine_sample_mask(struct brw_context
*brw
);
1617 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1618 unsigned num_samples
);
1620 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1622 gen6_get_sample_position(struct gl_context
*ctx
,
1623 struct gl_framebuffer
*fb
,
1627 gen6_set_sample_maps(struct gl_context
*ctx
);
1629 /* gen8_multisample_state.c */
1630 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1631 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1635 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1636 unsigned hs_size
, unsigned ds_size
,
1637 unsigned gs_size
, unsigned fs_size
);
1640 gen6_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1641 bool gs_present
, unsigned gs_size
);
1643 gen7_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1644 bool gs_present
, bool tess_present
);
1648 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1650 brw_check_for_reset(struct brw_context
*brw
);
1654 brw_init_compute_functions(struct dd_function_table
*functions
);
1656 /*======================================================================
1657 * Inline conversion functions. These are better-typed than the
1658 * macros used previously:
1660 static inline struct brw_context
*
1661 brw_context( struct gl_context
*ctx
)
1663 return (struct brw_context
*)ctx
;
1666 static inline struct brw_program
*
1667 brw_program(struct gl_program
*p
)
1669 return (struct brw_program
*) p
;
1672 static inline const struct brw_program
*
1673 brw_program_const(const struct gl_program
*p
)
1675 return (const struct brw_program
*) p
;
1679 * Pre-gen6, the register file of the EUs was shared between threads,
1680 * and each thread used some subset allocated on a 16-register block
1681 * granularity. The unit states wanted these block counts.
1684 brw_register_blocks(int reg_count
)
1686 return ALIGN(reg_count
, 16) / 16 - 1;
1689 static inline uint32_t
1690 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1691 uint32_t prog_offset
)
1693 if (brw
->gen
>= 5) {
1694 /* Using state base address. */
1698 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1702 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1704 return brw
->cache
.bo
->offset64
+ prog_offset
;
1707 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1709 extern const char * const conditional_modifier
[16];
1710 extern const char *const pred_ctrl_align16
[16];
1713 brw_depth_writes_enabled(const struct brw_context
*brw
)
1715 const struct gl_context
*ctx
= &brw
->ctx
;
1717 /* We consider depth writes disabled if the depth function is GL_EQUAL,
1718 * because it would just overwrite the existing depth value with itself.
1720 * These bonus depth writes not only use bandwidth, but they also can
1721 * prevent early depth processing. For example, if the pixel shader
1722 * discards, the hardware must invoke the to determine whether or not
1723 * to do the depth write. If writes are disabled, we may still be able
1724 * to do the depth test before the shader, and skip the shader execution.
1726 * The Broadwell 3DSTATE_WM_DEPTH_STENCIL documentation also contains
1727 * a programming note saying to disable depth writes for EQUAL.
1729 return ctx
->Depth
.Test
&& ctx
->Depth
.Mask
&& ctx
->Depth
.Func
!= GL_EQUAL
;
1733 brw_emit_depthbuffer(struct brw_context
*brw
);
1736 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1737 struct intel_mipmap_tree
*depth_mt
,
1738 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1739 uint32_t depth_surface_type
,
1740 struct intel_mipmap_tree
*stencil_mt
,
1741 bool hiz
, bool separate_stencil
,
1742 uint32_t width
, uint32_t height
,
1743 uint32_t tile_x
, uint32_t tile_y
);
1746 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1747 struct intel_mipmap_tree
*depth_mt
,
1748 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1749 uint32_t depth_surface_type
,
1750 struct intel_mipmap_tree
*stencil_mt
,
1751 bool hiz
, bool separate_stencil
,
1752 uint32_t width
, uint32_t height
,
1753 uint32_t tile_x
, uint32_t tile_y
);
1756 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1757 struct intel_mipmap_tree
*depth_mt
,
1758 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1759 uint32_t depth_surface_type
,
1760 struct intel_mipmap_tree
*stencil_mt
,
1761 bool hiz
, bool separate_stencil
,
1762 uint32_t width
, uint32_t height
,
1763 uint32_t tile_x
, uint32_t tile_y
);
1765 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1766 struct intel_mipmap_tree
*depth_mt
,
1767 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1768 uint32_t depth_surface_type
,
1769 struct intel_mipmap_tree
*stencil_mt
,
1770 bool hiz
, bool separate_stencil
,
1771 uint32_t width
, uint32_t height
,
1772 uint32_t tile_x
, uint32_t tile_y
);
1774 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1775 unsigned int level
, unsigned int layer
, enum blorp_hiz_op op
);
1777 uint32_t get_hw_prim_for_gl_prim(int mode
);
1780 gen6_upload_push_constants(struct brw_context
*brw
,
1781 const struct gl_program
*prog
,
1782 const struct brw_stage_prog_data
*prog_data
,
1783 struct brw_stage_state
*stage_state
,
1784 enum aub_state_struct_type type
);
1787 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
1788 const struct intel_mipmap_tree
*mt
);
1790 /* brw_pipe_control.c */
1791 int brw_init_pipe_control(struct brw_context
*brw
,
1792 const struct gen_device_info
*info
);
1793 void brw_fini_pipe_control(struct brw_context
*brw
);
1795 void brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
);
1796 void brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
1797 drm_intel_bo
*bo
, uint32_t offset
,
1798 uint32_t imm_lower
, uint32_t imm_upper
);
1799 void brw_emit_mi_flush(struct brw_context
*brw
);
1800 void brw_emit_post_sync_nonzero_flush(struct brw_context
*brw
);
1801 void brw_emit_depth_stall_flushes(struct brw_context
*brw
);
1802 void gen7_emit_vs_workaround_flush(struct brw_context
*brw
);
1803 void gen7_emit_cs_stall_flush(struct brw_context
*brw
);
1805 /* brw_queryformat.c */
1806 void brw_query_internal_format(struct gl_context
*ctx
, GLenum target
,
1807 GLenum internalFormat
, GLenum pname
,