2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
37 #include "main/macros.h"
38 #include "main/mtypes.h"
39 #include "brw_structs.h"
40 #include "brw_compiler.h"
41 #include "intel_aub.h"
44 #include "blorp/blorp.h"
48 /* Evil hack for using libdrm in a c++ compiler. */
52 #include <intel_bufmgr.h>
61 #include "intel_debug.h"
62 #include "intel_screen.h"
63 #include "intel_tex_obj.h"
64 #include "intel_resolve_map.h"
68 * URB - uniform resource buffer. A mid-sized buffer which is
69 * partitioned between the fixed function units and used for passing
70 * values (vertices, primitives, constants) between them.
72 * CURBE - constant URB entry. An urb region (entry) used to hold
73 * constant values which the fixed function units can be instructed to
74 * preload into the GRF when spawning a thread.
76 * VUE - vertex URB entry. An urb entry holding a vertex and usually
77 * a vertex header. The header contains control information and
78 * things like primitive type, Begin/end flags and clip codes.
80 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
81 * unit holding rasterization and interpolation parameters.
83 * GRF - general register file. One of several register files
84 * addressable by programmed threads. The inputs (r0, payload, curbe,
85 * urb) of the thread are preloaded to this area before the thread is
86 * spawned. The registers are individually 8 dwords wide and suitable
87 * for general usage. Registers holding thread input values are not
88 * special and may be overwritten.
90 * MRF - message register file. Threads communicate (and terminate)
91 * by sending messages. Message parameters are placed in contiguous
92 * MRF registers. All program output is via these messages. URB
93 * entries are populated by sending a message to the shared URB
94 * function containing the new data, together with a control word,
95 * often an unmodified copy of R0.
97 * R0 - GRF register 0. Typically holds control information used when
98 * sending messages to other threads.
100 * EU or GEN4 EU: The name of the programmable subsystem of the
101 * i965 hardware. Threads are executed by the EU, the registers
102 * described above are part of the EU architecture.
104 * Fixed function units:
106 * CS - Command streamer. Notional first unit, little software
107 * interaction. Holds the URB entries used for constant data, ie the
110 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
111 * this unit is responsible for pulling vertices out of vertex buffers
112 * in vram and injecting them into the processing pipe as VUEs. If
113 * enabled, it first passes them to a VS thread which is a good place
114 * for the driver to implement any active vertex shader.
116 * HS - Hull Shader (Tessellation Control Shader)
118 * TE - Tessellation Engine (Tessellation Primitive Generation)
120 * DS - Domain Shader (Tessellation Evaluation Shader)
122 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
123 * enabled, incoming strips etc are passed to GS threads in individual
124 * line/triangle/point units. The GS thread may perform arbitary
125 * computation and emit whatever primtives with whatever vertices it
126 * chooses. This makes GS an excellent place to implement GL's
127 * unfilled polygon modes, though of course it is capable of much
128 * more. Additionally, GS is used to translate away primitives not
129 * handled by latter units, including Quads and Lineloops.
131 * CS - Clipper. Mesa's clipping algorithms are imported to run on
132 * this unit. The fixed function part performs cliptesting against
133 * the 6 fixed clipplanes and makes descisions on whether or not the
134 * incoming primitive needs to be passed to a thread for clipping.
135 * User clip planes are handled via cooperation with the VS thread.
137 * SF - Strips Fans or Setup: Triangles are prepared for
138 * rasterization. Interpolation coefficients are calculated.
139 * Flatshading and two-side lighting usually performed here.
141 * WM - Windower. Interpolation of vertex attributes performed here.
142 * Fragment shader implemented here. SIMD aspects of EU taken full
143 * advantage of, as pixels are processed in blocks of 16.
145 * CC - Color Calculator. No EU threads associated with this unit.
146 * Handles blending and (presumably) depth and stencil testing.
151 struct brw_vs_prog_key
;
152 struct brw_vue_prog_key
;
153 struct brw_wm_prog_key
;
154 struct brw_wm_prog_data
;
155 struct brw_cs_prog_key
;
156 struct brw_cs_prog_data
;
160 BRW_COMPUTE_PIPELINE
,
167 BRW_CACHE_BLORP_PROG
,
170 BRW_CACHE_FF_GS_PROG
,
181 /* brw_cache_ids must come first - see brw_program_cache.c */
182 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
183 BRW_STATE_FRAGMENT_PROGRAM
,
184 BRW_STATE_GEOMETRY_PROGRAM
,
185 BRW_STATE_TESS_PROGRAMS
,
186 BRW_STATE_VERTEX_PROGRAM
,
187 BRW_STATE_CURBE_OFFSETS
,
188 BRW_STATE_REDUCED_PRIMITIVE
,
189 BRW_STATE_PATCH_PRIMITIVE
,
194 BRW_STATE_BINDING_TABLE_POINTERS
,
197 BRW_STATE_DEFAULT_TESS_LEVELS
,
199 BRW_STATE_INDEX_BUFFER
,
200 BRW_STATE_VS_CONSTBUF
,
201 BRW_STATE_TCS_CONSTBUF
,
202 BRW_STATE_TES_CONSTBUF
,
203 BRW_STATE_GS_CONSTBUF
,
204 BRW_STATE_PROGRAM_CACHE
,
205 BRW_STATE_STATE_BASE_ADDRESS
,
206 BRW_STATE_VUE_MAP_GEOM_OUT
,
207 BRW_STATE_TRANSFORM_FEEDBACK
,
208 BRW_STATE_RASTERIZER_DISCARD
,
210 BRW_STATE_UNIFORM_BUFFER
,
211 BRW_STATE_ATOMIC_BUFFER
,
212 BRW_STATE_IMAGE_UNITS
,
213 BRW_STATE_META_IN_PROGRESS
,
214 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
215 BRW_STATE_NUM_SAMPLES
,
216 BRW_STATE_TEXTURE_BUFFER
,
217 BRW_STATE_GEN4_UNIT_STATE
,
221 BRW_STATE_SAMPLER_STATE_TABLE
,
222 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
223 BRW_STATE_COMPUTE_PROGRAM
,
224 BRW_STATE_CS_WORK_GROUPS
,
228 BRW_STATE_VIEWPORT_COUNT
,
233 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
235 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
236 * When the currently bound shader program differs from the previous draw
237 * call, these will be flagged. They cover brw->{stage}_program and
238 * ctx->{Stage}Program->_Current.
240 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
241 * driver perspective. Even if the same shader is bound at the API level,
242 * we may need to switch between multiple versions of that shader to handle
243 * changes in non-orthagonal state.
245 * Additionally, multiple shader programs may have identical vertex shaders
246 * (for example), or compile down to the same code in the backend. We combine
247 * those into a single program cache entry.
249 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
250 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
252 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
253 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
254 * use the normal state upload paths), but the cache is still used. To avoid
255 * polluting the brw_program_cache code with special cases, we retain the
256 * dirty bit for now. It should eventually be removed.
258 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_PROG)
259 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
260 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
261 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
262 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
263 #define BRW_NEW_TCS_PROG_DATA (1ull << BRW_CACHE_TCS_PROG)
264 #define BRW_NEW_TES_PROG_DATA (1ull << BRW_CACHE_TES_PROG)
265 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
266 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
267 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
268 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
269 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
270 #define BRW_NEW_TESS_PROGRAMS (1ull << BRW_STATE_TESS_PROGRAMS)
271 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
272 #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
273 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
274 #define BRW_NEW_PATCH_PRIMITIVE (1ull << BRW_STATE_PATCH_PRIMITIVE)
275 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
276 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
277 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
278 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
279 #define BRW_NEW_BINDING_TABLE_POINTERS (1ull << BRW_STATE_BINDING_TABLE_POINTERS)
280 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
281 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
282 #define BRW_NEW_DEFAULT_TESS_LEVELS (1ull << BRW_STATE_DEFAULT_TESS_LEVELS)
284 * Used for any batch entry with a relocated pointer that will be used
285 * by any 3D rendering.
287 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
288 /** \see brw.state.depth_region */
289 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
290 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
291 #define BRW_NEW_TCS_CONSTBUF (1ull << BRW_STATE_TCS_CONSTBUF)
292 #define BRW_NEW_TES_CONSTBUF (1ull << BRW_STATE_TES_CONSTBUF)
293 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
294 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
295 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
296 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
297 #define BRW_NEW_VIEWPORT_COUNT (1ull << BRW_STATE_VIEWPORT_COUNT)
298 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
299 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
300 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
301 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
302 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
303 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
304 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
305 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
306 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
307 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
308 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
309 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
310 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
311 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
312 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
313 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
314 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
315 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
316 #define BRW_NEW_URB_SIZE (1ull << BRW_STATE_URB_SIZE)
317 #define BRW_NEW_CC_STATE (1ull << BRW_STATE_CC_STATE)
318 #define BRW_NEW_BLORP (1ull << BRW_STATE_BLORP)
320 struct brw_state_flags
{
321 /** State update flags signalled by mesa internals */
324 * State update flags signalled as the result of brw_tracked_state updates
330 /** Subclass of Mesa program */
332 struct gl_program program
;
337 struct gen4_fragment_program
{
338 struct brw_program base
;
340 bool contains_flat_varying
;
341 bool contains_noperspective_varying
;
344 * Mapping of varying slots to interpolation modes.
345 * Used Gen4/5 by the clip|sf|wm stages.
347 unsigned char interp_mode
[BRW_VARYING_SLOT_COUNT
];
352 struct gl_linked_shader base
;
358 * Bitmask indicating which fragment shader inputs represent varyings (and
359 * hence have to be delivered to the fragment shader by the SF/SBE stage).
361 #define BRW_FS_VARYING_INPUT_MASK \
362 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
363 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
366 struct brw_sf_prog_data
{
367 GLuint urb_read_length
;
370 /* Each vertex may have upto 12 attributes, 4 components each,
371 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
374 * Actually we use 4 for each, so call it 12 rows.
376 GLuint urb_entry_size
;
381 * We always program SF to start reading at an offset of 1 (2 varying slots)
382 * from the start of the vertex URB entry. This causes it to skip:
383 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
384 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
386 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
389 struct brw_clip_prog_data
{
390 GLuint curb_read_length
; /* user planes? */
392 GLuint urb_read_length
;
396 struct brw_ff_gs_prog_data
{
397 GLuint urb_read_length
;
401 * Gen6 transform feedback: Amount by which the streaming vertex buffer
402 * indices should be incremented each time the GS is invoked.
404 unsigned svbi_postincrement_value
;
407 /** Number of texture sampler units */
408 #define BRW_MAX_TEX_UNIT 32
410 /** Max number of render targets in a shader */
411 #define BRW_MAX_DRAW_BUFFERS 8
413 /** Max number of UBOs in a shader */
414 #define BRW_MAX_UBO 14
416 /** Max number of SSBOs in a shader */
417 #define BRW_MAX_SSBO 12
419 /** Max number of atomic counter buffer objects in a shader */
420 #define BRW_MAX_ABO 16
422 /** Max number of image uniforms in a shader */
423 #define BRW_MAX_IMAGES 32
426 * Max number of binding table entries used for stream output.
428 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
429 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
431 * On Gen6, the size of transform feedback data is limited not by the number
432 * of components but by the number of binding table entries we set aside. We
433 * use one binding table entry for a float, one entry for a vector, and one
434 * entry per matrix column. Since the only way we can communicate our
435 * transform feedback capabilities to the client is via
436 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
437 * worst case, in which all the varyings are floats, so we use up one binding
438 * table entry per component. Therefore we need to set aside at least 64
439 * binding table entries for use by transform feedback.
441 * Note: since we don't currently pack varyings, it is currently impossible
442 * for the client to actually use up all of these binding table entries--if
443 * all of their varyings were floats, they would run out of varying slots and
444 * fail to link. But that's a bug, so it seems prudent to go ahead and
445 * allocate the number of binding table entries we will need once the bug is
448 #define BRW_MAX_SOL_BINDINGS 64
450 /** Maximum number of actual buffers used for stream output */
451 #define BRW_MAX_SOL_BUFFERS 4
453 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
454 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
459 2 + /* shader time, pull constants */ \
460 1 /* cs num work groups */)
462 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
465 * Stride in bytes between shader_time entries.
467 * We separate entries by a cacheline to reduce traffic between EUs writing to
470 #define SHADER_TIME_STRIDE 64
472 struct brw_cache_item
{
474 * Effectively part of the key, cache_id identifies what kind of state
475 * buffer is involved, and also which dirty flag should set.
477 enum brw_cache_id cache_id
;
478 /** 32-bit hash of the key data */
480 GLuint key_size
; /* for variable-sized keys */
487 struct brw_cache_item
*next
;
492 struct brw_context
*brw
;
494 struct brw_cache_item
**items
;
496 GLuint size
, n_items
;
498 uint32_t next_offset
;
503 /* Considered adding a member to this struct to document which flags
504 * an update might raise so that ordering of the state atoms can be
505 * checked or derived at runtime. Dropped the idea in favor of having
506 * a debug mode where the state is monitored for flags which are
507 * raised that have already been tested against.
509 struct brw_tracked_state
{
510 struct brw_state_flags dirty
;
511 void (*emit
)( struct brw_context
*brw
);
514 enum shader_time_shader_type
{
525 struct brw_vertex_buffer
{
526 /** Buffer object containing the uploaded vertex data */
530 /** Byte stride between elements in the uploaded array */
534 struct brw_vertex_element
{
535 const struct gl_vertex_array
*glarray
;
539 /** Offset of the first element within the buffer object */
543 struct brw_query_object
{
544 struct gl_query_object Base
;
546 /** Last query BO associated with this query. */
549 /** Last index in bo with query data for this object. */
552 /** True if we know the batch has been flushed since we ended the query. */
562 struct intel_batchbuffer
{
563 /** Current batchbuffer being queued up. */
565 /** Last BO submitted to the hardware. Used for glFinish(). */
566 drm_intel_bo
*last_bo
;
569 uint16_t emit
, total
;
571 uint16_t reserved_space
;
575 #define BATCH_SZ (8192*sizeof(uint32_t))
577 uint32_t state_batch_offset
;
578 enum brw_gpu_ring ring
;
579 bool needs_sol_reset
;
580 bool state_base_address_emitted
;
588 #define MAX_GS_INPUT_VERTICES 6
590 #define BRW_MAX_XFB_STREAMS 4
592 struct brw_transform_feedback_object
{
593 struct gl_transform_feedback_object base
;
595 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
596 drm_intel_bo
*offset_bo
;
598 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
601 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
602 GLenum primitive_mode
;
605 * Count of primitives generated during this transform feedback operation.
608 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
609 drm_intel_bo
*prim_count_bo
;
610 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
614 * Number of vertices written between last Begin/EndTransformFeedback().
616 * Used to implement DrawTransformFeedback().
618 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
619 bool vertices_written_valid
;
623 * Data shared between each programmable stage in the pipeline (vs, gs, and
626 struct brw_stage_state
628 gl_shader_stage stage
;
629 struct brw_stage_prog_data
*prog_data
;
632 * Optional scratch buffer used to store spilled register values and
633 * variably-indexed GRF arrays.
635 * The contents of this buffer are short-lived so the same memory can be
636 * re-used at will for multiple shader programs (executed by the same fixed
637 * function). However reusing a scratch BO for which shader invocations
638 * are still in flight with a per-thread scratch slot size other than the
639 * original can cause threads with different scratch slot size and FFTID
640 * (which may be executed in parallel depending on the shader stage and
641 * hardware generation) to map to an overlapping region of the scratch
642 * space, which can potentially lead to mutual scratch space corruption.
643 * For that reason if you borrow this scratch buffer you should only be
644 * using the slot size given by the \c per_thread_scratch member below,
645 * unless you're taking additional measures to synchronize thread execution
646 * across slot size changes.
648 drm_intel_bo
*scratch_bo
;
651 * Scratch slot size allocated for each thread in the buffer object given
654 uint32_t per_thread_scratch
;
656 /** Offset in the program cache to the program */
657 uint32_t prog_offset
;
659 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
660 uint32_t state_offset
;
662 uint32_t push_const_offset
; /* Offset in the batchbuffer */
663 int push_const_size
; /* in 256-bit register increments */
665 /* Binding table: pointers to SURFACE_STATE entries. */
666 uint32_t bind_bo_offset
;
667 uint32_t surf_offset
[BRW_MAX_SURFACES
];
669 /** SAMPLER_STATE count and table offset */
670 uint32_t sampler_count
;
671 uint32_t sampler_offset
;
674 enum brw_predicate_state
{
675 /* The first two states are used if we can determine whether to draw
676 * without having to look at the values in the query object buffer. This
677 * will happen if there is no conditional render in progress, if the query
678 * object is already completed or if something else has already added
679 * samples to the preliminary result such as via a BLT command.
681 BRW_PREDICATE_STATE_RENDER
,
682 BRW_PREDICATE_STATE_DONT_RENDER
,
683 /* In this case whether to draw or not depends on the result of an
684 * MI_PREDICATE command so the predicate enable bit needs to be checked.
686 BRW_PREDICATE_STATE_USE_BIT
691 struct gen_l3_config
;
694 * brw_context is derived from gl_context.
698 struct gl_context ctx
; /**< base class, must be first field */
702 uint32_t (*update_renderbuffer_surface
)(struct brw_context
*brw
,
703 struct gl_renderbuffer
*rb
,
704 uint32_t flags
, unsigned unit
,
705 uint32_t surf_index
);
706 void (*emit_null_surface_state
)(struct brw_context
*brw
,
710 uint32_t *out_offset
);
713 * Send the appropriate state packets to configure depth, stencil, and
714 * HiZ buffers (i965+ only)
716 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
717 struct intel_mipmap_tree
*depth_mt
,
718 uint32_t depth_offset
,
719 uint32_t depthbuffer_format
,
720 uint32_t depth_surface_type
,
721 struct intel_mipmap_tree
*stencil_mt
,
722 bool hiz
, bool separate_stencil
,
723 uint32_t width
, uint32_t height
,
724 uint32_t tile_x
, uint32_t tile_y
);
730 drm_intel_context
*hw_ctx
;
732 /** BO for post-sync nonzero writes for gen6 workaround. */
733 drm_intel_bo
*workaround_bo
;
734 uint8_t pipe_controls_since_last_cs_stall
;
737 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
738 * and would need flushing before being used from another cache domain that
739 * isn't coherent with it (i.e. the sampler).
741 struct set
*render_cache
;
744 * Number of resets observed in the system at context creation.
746 * This is tracked in the context so that we can determine that another
747 * reset has occurred.
749 uint32_t reset_count
;
751 struct intel_batchbuffer batch
;
756 uint32_t next_offset
;
760 * Set if rendering has occurred to the drawable's front buffer.
762 * This is used in the DRI2 case to detect that glFlush should also copy
763 * the contents of the fake front buffer to the real front buffer.
765 bool front_buffer_dirty
;
767 /** Framerate throttling: @{ */
768 drm_intel_bo
*throttle_batch
[2];
770 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
771 * frame of rendering to complete. This gives a very precise cap to the
772 * latency between input and output such that rendering never gets more
773 * than a frame behind the user. (With the caveat that we technically are
774 * not using the SwapBuffers itself as a barrier but the first batch
775 * submitted afterwards, which may be immediately prior to the next
778 bool need_swap_throttle
;
780 /** General throttling, not caught by throttling between SwapBuffers */
781 bool need_flush_throttle
;
791 bool always_flush_batch
;
792 bool always_flush_cache
;
793 bool disable_throttling
;
795 bool dual_color_blend_by_location
;
797 driOptionCache optionCache
;
800 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
802 GLenum reduced_primitive
;
805 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
806 * variable is set, this is the flag indicating to do expensive work that
807 * might lead to a perf_debug() call.
811 uint64_t max_gtt_map_object_size
;
823 bool has_separate_stencil
;
824 bool must_use_separate_stencil
;
827 bool has_surface_tile_offset
;
829 bool has_negative_rhw_bug
;
833 bool use_resource_streamer
;
836 * Whether LRI can be used to write register values from the batch buffer.
838 bool can_do_pipelined_register_writes
;
841 * Some versions of Gen hardware don't do centroid interpolation correctly
842 * on unlit pixels, causing incorrect values for derivatives near triangle
843 * edges. Enabling this flag causes the fragment shader to use
844 * non-centroid interpolation for unlit pixels, at the expense of two extra
845 * fragment shader instructions.
847 bool needs_unlit_centroid_workaround
;
849 struct isl_device isl_dev
;
851 struct blorp_context blorp
;
855 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
858 enum brw_pipeline last_pipeline
;
860 struct brw_cache cache
;
862 /** IDs for meta stencil blit shader programs. */
863 struct gl_shader_program
*meta_stencil_blit_programs
[2];
865 /* Whether a meta-operation is in progress. */
866 bool meta_in_progress
;
868 /* Whether the last depth/stencil packets were both NULL. */
869 bool no_depth_or_stencil
;
871 /* The last PMA stall bits programmed. */
872 uint32_t pma_stall_bits
;
876 /** The value of gl_BaseVertex for the current _mesa_prim. */
879 /** The value of gl_BaseInstance for the current _mesa_prim. */
884 * Buffer and offset used for GL_ARB_shader_draw_parameters
885 * (for now, only gl_BaseVertex).
887 drm_intel_bo
*draw_params_bo
;
888 uint32_t draw_params_offset
;
891 * The value of gl_DrawID for the current _mesa_prim. This always comes
892 * in from it's own vertex buffer since it's not part of the indirect
896 drm_intel_bo
*draw_id_bo
;
897 uint32_t draw_id_offset
;
902 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
903 * an indirect call, and num_work_groups_offset is valid. Otherwise,
904 * num_work_groups is set based on glDispatchCompute.
906 drm_intel_bo
*num_work_groups_bo
;
907 GLintptr num_work_groups_offset
;
908 const GLuint
*num_work_groups
;
912 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
913 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
915 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
919 /* Summary of size and varying of active arrays, so we can check
920 * for changes to this state:
922 bool index_bounds_valid
;
923 unsigned int min_index
, max_index
;
925 /* Offset from start of vertex buffer so we can avoid redefining
926 * the same VB packed over and over again.
928 unsigned int start_vertex_bias
;
931 * Certain vertex attribute formats aren't natively handled by the
932 * hardware and require special VS code to fix up their values.
934 * These bitfields indicate which workarounds are needed.
936 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
941 * Index buffer for this draw_prims call.
943 * Updates are signaled by BRW_NEW_INDICES.
945 const struct _mesa_index_buffer
*ib
;
947 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
952 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
953 * avoid re-uploading the IB packet over and over if we're actually
954 * referencing the same index buffer.
956 unsigned int start_vertex_offset
;
959 /* Active vertex program:
961 const struct gl_program
*vertex_program
;
962 const struct gl_program
*geometry_program
;
963 const struct gl_program
*tess_ctrl_program
;
964 const struct gl_program
*tess_eval_program
;
965 const struct gl_program
*fragment_program
;
966 const struct gl_program
*compute_program
;
969 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
970 * that we don't have to reemit that state every time we change FBOs.
974 /* BRW_NEW_URB_ALLOCATIONS:
977 GLuint vsize
; /* vertex size plus header in urb registers */
978 GLuint gsize
; /* GS output size in urb registers */
979 GLuint hsize
; /* Tessellation control output size in urb registers */
980 GLuint dsize
; /* Tessellation evaluation output size in urb registers */
981 GLuint csize
; /* constant buffer size in urb registers */
982 GLuint sfsize
; /* setup data size in urb registers */
986 GLuint nr_vs_entries
;
987 GLuint nr_hs_entries
;
988 GLuint nr_ds_entries
;
989 GLuint nr_gs_entries
;
990 GLuint nr_clip_entries
;
991 GLuint nr_sf_entries
;
992 GLuint nr_cs_entries
;
1002 * URB size in the current configuration. The units this is expressed
1003 * in are somewhat inconsistent, see gen_device_info::urb::size.
1005 * FINISHME: Represent the URB size consistently in KB on all platforms.
1009 /* True if the most recently sent _3DSTATE_URB message allocated
1010 * URB space for the GS.
1014 /* True if the most recently sent _3DSTATE_URB message allocated
1015 * URB space for the HS and DS.
1021 /* BRW_NEW_CURBE_OFFSETS:
1024 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1025 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1033 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1034 * for upload to the CURBE.
1036 drm_intel_bo
*curbe_bo
;
1037 /** Offset within curbe_bo of space for current curbe entry */
1038 GLuint curbe_offset
;
1042 * Layout of vertex data exiting the geometry portion of the pipleine.
1043 * This comes from the last enabled shader stage (GS, DS, or VS).
1045 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1047 struct brw_vue_map vue_map_geom_out
;
1050 struct brw_stage_state base
;
1054 struct brw_stage_state base
;
1057 * True if the 3DSTATE_HS command most recently emitted to the 3D
1058 * pipeline enabled the HS; false otherwise.
1064 struct brw_stage_state base
;
1067 * True if the 3DSTATE_DS command most recently emitted to the 3D
1068 * pipeline enabled the DS; false otherwise.
1074 struct brw_stage_state base
;
1077 * True if the 3DSTATE_GS command most recently emitted to the 3D
1078 * pipeline enabled the GS; false otherwise.
1084 struct brw_ff_gs_prog_data
*prog_data
;
1087 /** Offset in the program cache to the CLIP program pre-gen6 */
1088 uint32_t prog_offset
;
1089 uint32_t state_offset
;
1091 uint32_t bind_bo_offset
;
1093 * Surface offsets for the binding table. We only need surfaces to
1094 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1095 * need in this case.
1097 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1101 struct brw_clip_prog_data
*prog_data
;
1103 /** Offset in the program cache to the CLIP program pre-gen6 */
1104 uint32_t prog_offset
;
1106 /* Offset in the batch to the CLIP state on pre-gen6. */
1107 uint32_t state_offset
;
1109 /* As of gen6, this is the offset in the batch to the CLIP VP,
1115 * The number of viewports to use. If gl_ViewportIndex is written,
1116 * we can have up to ctx->Const.MaxViewports viewports. If not,
1117 * the viewport index is always 0, so we can only emit one.
1119 uint8_t viewport_count
;
1124 struct brw_sf_prog_data
*prog_data
;
1126 /** Offset in the program cache to the CLIP program pre-gen6 */
1127 uint32_t prog_offset
;
1128 uint32_t state_offset
;
1130 bool viewport_transform_enable
;
1134 struct brw_stage_state base
;
1139 * Buffer object used in place of multisampled null render targets on
1140 * Gen6. See brw_emit_null_surface_state().
1142 drm_intel_bo
*multisampled_null_render_target_bo
;
1143 uint32_t fast_clear_op
;
1149 struct brw_stage_state base
;
1152 /* RS hardware binding table */
1155 uint32_t next_offset
;
1159 uint32_t state_offset
;
1160 uint32_t blend_state_offset
;
1161 uint32_t depth_stencil_state_offset
;
1166 struct brw_query_object
*obj
;
1171 enum brw_predicate_state state
;
1176 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1177 const int *statistics_registers
;
1179 /** The number of active monitors using OA counters. */
1183 * A buffer object storing OA counter snapshots taken at the start and
1184 * end of each batch (creating "bookends" around the batch).
1186 drm_intel_bo
*bookend_bo
;
1188 /** The number of snapshots written to bookend_bo. */
1189 int bookend_snapshots
;
1192 * An array of monitors whose results haven't yet been assembled based on
1193 * the data in buffer objects.
1195 * These may be active, or have already ended. However, the results
1196 * have not been requested.
1198 struct brw_perf_monitor_object
**unresolved
;
1199 int unresolved_elements
;
1200 int unresolved_array_size
;
1203 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1204 * the counter which MI_REPORT_PERF_COUNT stores there.
1206 const int *oa_snapshot_layout
;
1208 /** Number of 32-bit entries in a hardware counter snapshot. */
1209 int entries_per_oa_snapshot
;
1212 int num_atoms
[BRW_NUM_PIPELINES
];
1213 const struct brw_tracked_state render_atoms
[76];
1214 const struct brw_tracked_state compute_atoms
[11];
1216 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1220 enum aub_state_struct_type type
;
1222 } *state_batch_list
;
1223 int state_batch_count
;
1225 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1226 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1228 /* PrimitiveRestart */
1231 bool enable_cut_index
;
1234 /** Computed depth/stencil/hiz state from the current attached
1235 * renderbuffers, valid only during the drawing state upload loop after
1236 * brw_workaround_depthstencil_alignment().
1239 struct intel_mipmap_tree
*depth_mt
;
1240 struct intel_mipmap_tree
*stencil_mt
;
1242 /* Inter-tile (page-aligned) byte offsets. */
1243 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1244 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1245 uint32_t tile_x
, tile_y
;
1248 uint32_t num_instances
;
1253 const struct gen_l3_config
*config
;
1260 enum shader_time_shader_type
*types
;
1261 struct shader_times
*cumulative
;
1267 struct brw_fast_clear_state
*fast_clear_state
;
1269 /* Array of flags telling if auxiliary buffer is disabled for corresponding
1270 * renderbuffer. If draw_aux_buffer_disabled[i] is set then use of
1271 * auxiliary buffer for gl_framebuffer::_ColorDrawBuffers[i] is
1273 * This is needed in case the same underlying buffer is also configured
1274 * to be sampled but with a format that the sampling engine can't treat
1275 * compressed or fast cleared.
1277 bool draw_aux_buffer_disabled
[MAX_DRAW_BUFFERS
];
1279 __DRIcontext
*driContext
;
1280 struct intel_screen
*screen
;
1283 /*======================================================================
1286 void brwInitVtbl( struct brw_context
*brw
);
1289 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1291 /*======================================================================
1294 extern const char *const brw_vendor_string
;
1297 brw_get_renderer_string(const struct intel_screen
*screen
);
1300 DRI_CONF_BO_REUSE_DISABLED
,
1301 DRI_CONF_BO_REUSE_ALL
1304 void intel_update_renderbuffers(__DRIcontext
*context
,
1305 __DRIdrawable
*drawable
);
1306 void intel_prepare_render(struct brw_context
*brw
);
1308 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1309 __DRIdrawable
*drawable
);
1311 GLboolean
brwCreateContext(gl_api api
,
1312 const struct gl_config
*mesaVis
,
1313 __DRIcontext
*driContextPriv
,
1314 unsigned major_version
,
1315 unsigned minor_version
,
1319 void *sharedContextPrivate
);
1321 /*======================================================================
1325 brw_meta_resolve_color(struct brw_context
*brw
,
1326 struct intel_mipmap_tree
*mt
);
1328 /*======================================================================
1331 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1332 uint32_t depth_level
,
1333 uint32_t depth_layer
,
1334 struct intel_mipmap_tree
*stencil_mt
,
1335 uint32_t *out_tile_mask_x
,
1336 uint32_t *out_tile_mask_y
);
1337 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1338 GLbitfield clear_mask
);
1340 /* brw_object_purgeable.c */
1341 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1343 /*======================================================================
1346 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1347 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1348 void brw_emit_query_begin(struct brw_context
*brw
);
1349 void brw_emit_query_end(struct brw_context
*brw
);
1350 void brw_query_counter(struct gl_context
*ctx
, struct gl_query_object
*q
);
1351 bool brw_is_query_pipelined(struct brw_query_object
*query
);
1353 /** gen6_queryobj.c */
1354 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1355 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1356 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1358 /** hsw_queryobj.c */
1359 void hsw_init_queryobj_functions(struct dd_function_table
*functions
);
1361 /** brw_conditional_render.c */
1362 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1363 bool brw_check_conditional_render(struct brw_context
*brw
);
1365 /** intel_batchbuffer.c */
1366 void brw_load_register_mem(struct brw_context
*brw
,
1369 uint32_t read_domains
, uint32_t write_domain
,
1371 void brw_load_register_mem64(struct brw_context
*brw
,
1374 uint32_t read_domains
, uint32_t write_domain
,
1376 void brw_store_register_mem32(struct brw_context
*brw
,
1377 drm_intel_bo
*bo
, uint32_t reg
, uint32_t offset
);
1378 void brw_store_register_mem64(struct brw_context
*brw
,
1379 drm_intel_bo
*bo
, uint32_t reg
, uint32_t offset
);
1380 void brw_load_register_imm32(struct brw_context
*brw
,
1381 uint32_t reg
, uint32_t imm
);
1382 void brw_load_register_imm64(struct brw_context
*brw
,
1383 uint32_t reg
, uint64_t imm
);
1384 void brw_load_register_reg(struct brw_context
*brw
, uint32_t src
,
1386 void brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
,
1388 void brw_store_data_imm32(struct brw_context
*brw
, drm_intel_bo
*bo
,
1389 uint32_t offset
, uint32_t imm
);
1390 void brw_store_data_imm64(struct brw_context
*brw
, drm_intel_bo
*bo
,
1391 uint32_t offset
, uint64_t imm
);
1393 /*======================================================================
1396 void brw_debug_batch(struct brw_context
*brw
);
1397 void brw_annotate_aub(struct brw_context
*brw
);
1399 /*======================================================================
1400 * intel_tex_validate.c
1402 void brw_validate_textures( struct brw_context
*brw
);
1405 /*======================================================================
1409 key_debug(struct brw_context
*brw
, const char *name
, int a
, int b
)
1412 perf_debug(" %s %d->%d\n", name
, a
, b
);
1418 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1420 /* Per-thread scratch space is a power-of-two multiple of 1KB. */
1422 brw_get_scratch_size(int size
)
1424 return MAX2(1024, util_next_power_of_two(size
));
1426 void brw_get_scratch_bo(struct brw_context
*brw
,
1427 drm_intel_bo
**scratch_bo
, int size
);
1428 void brw_alloc_stage_scratch(struct brw_context
*brw
,
1429 struct brw_stage_state
*stage_state
,
1430 unsigned per_thread_size
,
1431 unsigned thread_count
);
1432 void brw_init_shader_time(struct brw_context
*brw
);
1433 int brw_get_shader_time_index(struct brw_context
*brw
,
1434 struct gl_shader_program
*shader_prog
,
1435 struct gl_program
*prog
,
1436 enum shader_time_shader_type type
);
1437 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1438 void brw_destroy_shader_time(struct brw_context
*brw
);
1442 void brw_upload_urb_fence(struct brw_context
*brw
);
1446 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1448 /* brw_fs_reg_allocate.cpp
1450 void brw_fs_alloc_reg_sets(struct brw_compiler
*compiler
);
1452 /* brw_vec4_reg_allocate.cpp */
1453 void brw_vec4_alloc_reg_set(struct brw_compiler
*compiler
);
1456 int brw_disassemble_inst(FILE *file
, const struct gen_device_info
*devinfo
,
1457 struct brw_inst
*inst
, bool is_compacted
);
1460 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1462 /* brw_draw_upload.c */
1463 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1464 const struct gl_vertex_array
*glarray
);
1466 static inline unsigned
1467 brw_get_index_type(GLenum type
)
1469 assert((type
== GL_UNSIGNED_BYTE
)
1470 || (type
== GL_UNSIGNED_SHORT
)
1471 || (type
== GL_UNSIGNED_INT
));
1473 /* The possible values for type are GL_UNSIGNED_BYTE (0x1401),
1474 * GL_UNSIGNED_SHORT (0x1403), and GL_UNSIGNED_INT (0x1405) which we want
1475 * to map to scale factors of 0, 1, and 2, respectively. These scale
1476 * factors are then left-shfited by 8 to be in the correct position in the
1477 * CMD_INDEX_BUFFER packet.
1479 * Subtracting 0x1401 gives 0, 2, and 4. Shifting left by 7 afterwards
1480 * gives 0x00000000, 0x00000100, and 0x00000200. These just happen to be
1481 * the values the need to be written in the CMD_INDEX_BUFFER packet.
1483 return (type
- 0x1401) << 7;
1486 void brw_prepare_vertices(struct brw_context
*brw
);
1488 /* brw_wm_surface_state.c */
1489 void brw_init_surface_formats(struct brw_context
*brw
);
1490 void brw_create_constant_surface(struct brw_context
*brw
,
1494 uint32_t *out_offset
);
1495 void brw_create_buffer_surface(struct brw_context
*brw
,
1499 uint32_t *out_offset
);
1500 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1502 uint32_t *surf_offset
);
1504 brw_update_sol_surface(struct brw_context
*brw
,
1505 struct gl_buffer_object
*buffer_obj
,
1506 uint32_t *out_offset
, unsigned num_vector_components
,
1507 unsigned stride_dwords
, unsigned offset_dwords
);
1508 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1509 struct gl_linked_shader
*shader
,
1510 struct brw_stage_state
*stage_state
,
1511 struct brw_stage_prog_data
*prog_data
);
1512 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1513 struct gl_linked_shader
*shader
,
1514 struct brw_stage_state
*stage_state
,
1515 struct brw_stage_prog_data
*prog_data
);
1516 void brw_upload_image_surfaces(struct brw_context
*brw
,
1517 struct gl_linked_shader
*shader
,
1518 struct brw_stage_state
*stage_state
,
1519 struct brw_stage_prog_data
*prog_data
);
1521 /* brw_surface_formats.c */
1522 bool brw_render_target_supported(struct brw_context
*brw
,
1523 struct gl_renderbuffer
*rb
);
1524 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1526 /* brw_performance_monitor.c */
1527 void brw_init_performance_monitors(struct brw_context
*brw
);
1528 void brw_dump_perf_monitors(struct brw_context
*brw
);
1529 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1530 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1532 /* intel_buffer_objects.c */
1533 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1534 const char *bo_name
);
1535 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1536 const char *bo_name
);
1538 /* intel_extensions.c */
1539 extern void intelInitExtensions(struct gl_context
*ctx
);
1542 extern int intel_translate_shadow_compare_func(GLenum func
);
1543 extern int intel_translate_compare_func(GLenum func
);
1544 extern int intel_translate_stencil_op(GLenum op
);
1545 extern int intel_translate_logic_op(GLenum opcode
);
1548 void brw_init_syncobj_functions(struct dd_function_table
*functions
);
1551 struct gl_transform_feedback_object
*
1552 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1554 brw_delete_transform_feedback(struct gl_context
*ctx
,
1555 struct gl_transform_feedback_object
*obj
);
1557 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1558 struct gl_transform_feedback_object
*obj
);
1560 brw_end_transform_feedback(struct gl_context
*ctx
,
1561 struct gl_transform_feedback_object
*obj
);
1563 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1564 struct gl_transform_feedback_object
*obj
,
1567 /* gen7_sol_state.c */
1569 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1570 struct gl_transform_feedback_object
*obj
);
1572 gen7_end_transform_feedback(struct gl_context
*ctx
,
1573 struct gl_transform_feedback_object
*obj
);
1575 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1576 struct gl_transform_feedback_object
*obj
);
1578 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1579 struct gl_transform_feedback_object
*obj
);
1583 hsw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1584 struct gl_transform_feedback_object
*obj
);
1586 hsw_end_transform_feedback(struct gl_context
*ctx
,
1587 struct gl_transform_feedback_object
*obj
);
1589 hsw_pause_transform_feedback(struct gl_context
*ctx
,
1590 struct gl_transform_feedback_object
*obj
);
1592 hsw_resume_transform_feedback(struct gl_context
*ctx
,
1593 struct gl_transform_feedback_object
*obj
);
1595 /* brw_blorp_blit.cpp */
1597 brw_blorp_framebuffer(struct brw_context
*brw
,
1598 struct gl_framebuffer
*readFb
,
1599 struct gl_framebuffer
*drawFb
,
1600 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1601 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1602 GLbitfield mask
, GLenum filter
);
1605 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1606 struct gl_renderbuffer
*src_rb
,
1607 struct gl_texture_image
*dst_image
,
1609 int srcX0
, int srcY0
,
1610 int dstX0
, int dstY0
,
1611 int width
, int height
);
1613 /* gen6_multisample_state.c */
1615 gen6_determine_sample_mask(struct brw_context
*brw
);
1618 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1619 unsigned num_samples
);
1621 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1623 gen6_get_sample_position(struct gl_context
*ctx
,
1624 struct gl_framebuffer
*fb
,
1628 gen6_set_sample_maps(struct gl_context
*ctx
);
1630 /* gen8_multisample_state.c */
1631 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1632 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1636 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1637 unsigned hs_size
, unsigned ds_size
,
1638 unsigned gs_size
, unsigned fs_size
);
1641 gen6_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1642 bool gs_present
, unsigned gs_size
);
1644 gen7_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1645 bool gs_present
, bool tess_present
);
1649 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1651 brw_check_for_reset(struct brw_context
*brw
);
1655 brw_init_compute_functions(struct dd_function_table
*functions
);
1657 /*======================================================================
1658 * Inline conversion functions. These are better-typed than the
1659 * macros used previously:
1661 static inline struct brw_context
*
1662 brw_context( struct gl_context
*ctx
)
1664 return (struct brw_context
*)ctx
;
1667 static inline struct brw_program
*
1668 brw_program(struct gl_program
*p
)
1670 return (struct brw_program
*) p
;
1673 static inline const struct brw_program
*
1674 brw_program_const(const struct gl_program
*p
)
1676 return (const struct brw_program
*) p
;
1680 * Pre-gen6, the register file of the EUs was shared between threads,
1681 * and each thread used some subset allocated on a 16-register block
1682 * granularity. The unit states wanted these block counts.
1685 brw_register_blocks(int reg_count
)
1687 return ALIGN(reg_count
, 16) / 16 - 1;
1690 static inline uint32_t
1691 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1692 uint32_t prog_offset
)
1694 if (brw
->gen
>= 5) {
1695 /* Using state base address. */
1699 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1703 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1705 return brw
->cache
.bo
->offset64
+ prog_offset
;
1708 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1709 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1710 struct exec_list
*instructions
);
1712 extern const char * const conditional_modifier
[16];
1713 extern const char *const pred_ctrl_align16
[16];
1716 brw_emit_depthbuffer(struct brw_context
*brw
);
1719 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1720 struct intel_mipmap_tree
*depth_mt
,
1721 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1722 uint32_t depth_surface_type
,
1723 struct intel_mipmap_tree
*stencil_mt
,
1724 bool hiz
, bool separate_stencil
,
1725 uint32_t width
, uint32_t height
,
1726 uint32_t tile_x
, uint32_t tile_y
);
1729 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1730 struct intel_mipmap_tree
*depth_mt
,
1731 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1732 uint32_t depth_surface_type
,
1733 struct intel_mipmap_tree
*stencil_mt
,
1734 bool hiz
, bool separate_stencil
,
1735 uint32_t width
, uint32_t height
,
1736 uint32_t tile_x
, uint32_t tile_y
);
1739 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1740 struct intel_mipmap_tree
*depth_mt
,
1741 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1742 uint32_t depth_surface_type
,
1743 struct intel_mipmap_tree
*stencil_mt
,
1744 bool hiz
, bool separate_stencil
,
1745 uint32_t width
, uint32_t height
,
1746 uint32_t tile_x
, uint32_t tile_y
);
1748 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1749 struct intel_mipmap_tree
*depth_mt
,
1750 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1751 uint32_t depth_surface_type
,
1752 struct intel_mipmap_tree
*stencil_mt
,
1753 bool hiz
, bool separate_stencil
,
1754 uint32_t width
, uint32_t height
,
1755 uint32_t tile_x
, uint32_t tile_y
);
1757 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1758 unsigned int level
, unsigned int layer
, enum blorp_hiz_op op
);
1760 uint32_t get_hw_prim_for_gl_prim(int mode
);
1763 gen6_upload_push_constants(struct brw_context
*brw
,
1764 const struct gl_program
*prog
,
1765 const struct brw_stage_prog_data
*prog_data
,
1766 struct brw_stage_state
*stage_state
,
1767 enum aub_state_struct_type type
);
1770 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
1771 const struct intel_mipmap_tree
*mt
);
1773 /* brw_pipe_control.c */
1774 int brw_init_pipe_control(struct brw_context
*brw
,
1775 const struct gen_device_info
*info
);
1776 void brw_fini_pipe_control(struct brw_context
*brw
);
1778 void brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
);
1779 void brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
1780 drm_intel_bo
*bo
, uint32_t offset
,
1781 uint32_t imm_lower
, uint32_t imm_upper
);
1782 void brw_emit_mi_flush(struct brw_context
*brw
);
1783 void brw_emit_post_sync_nonzero_flush(struct brw_context
*brw
);
1784 void brw_emit_depth_stall_flushes(struct brw_context
*brw
);
1785 void gen7_emit_vs_workaround_flush(struct brw_context
*brw
);
1786 void gen7_emit_cs_stall_flush(struct brw_context
*brw
);
1788 /* brw_queryformat.c */
1789 void brw_query_internal_format(struct gl_context
*ctx
, GLenum target
,
1790 GLenum internalFormat
, GLenum pname
,