2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
38 #include "main/imports.h"
39 #include "main/macros.h"
41 #include "main/mtypes.h"
42 #include "brw_structs.h"
46 /* Evil hack for using libdrm in a c++ compiler. */
51 #include <intel_bufmgr.h>
61 #include "intel_debug.h"
62 #include "intel_screen.h"
63 #include "intel_tex_obj.h"
67 * URB - uniform resource buffer. A mid-sized buffer which is
68 * partitioned between the fixed function units and used for passing
69 * values (vertices, primitives, constants) between them.
71 * CURBE - constant URB entry. An urb region (entry) used to hold
72 * constant values which the fixed function units can be instructed to
73 * preload into the GRF when spawning a thread.
75 * VUE - vertex URB entry. An urb entry holding a vertex and usually
76 * a vertex header. The header contains control information and
77 * things like primitive type, Begin/end flags and clip codes.
79 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
80 * unit holding rasterization and interpolation parameters.
82 * GRF - general register file. One of several register files
83 * addressable by programmed threads. The inputs (r0, payload, curbe,
84 * urb) of the thread are preloaded to this area before the thread is
85 * spawned. The registers are individually 8 dwords wide and suitable
86 * for general usage. Registers holding thread input values are not
87 * special and may be overwritten.
89 * MRF - message register file. Threads communicate (and terminate)
90 * by sending messages. Message parameters are placed in contiguous
91 * MRF registers. All program output is via these messages. URB
92 * entries are populated by sending a message to the shared URB
93 * function containing the new data, together with a control word,
94 * often an unmodified copy of R0.
96 * R0 - GRF register 0. Typically holds control information used when
97 * sending messages to other threads.
99 * EU or GEN4 EU: The name of the programmable subsystem of the
100 * i965 hardware. Threads are executed by the EU, the registers
101 * described above are part of the EU architecture.
103 * Fixed function units:
105 * CS - Command streamer. Notional first unit, little software
106 * interaction. Holds the URB entries used for constant data, ie the
109 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
110 * this unit is responsible for pulling vertices out of vertex buffers
111 * in vram and injecting them into the processing pipe as VUEs. If
112 * enabled, it first passes them to a VS thread which is a good place
113 * for the driver to implement any active vertex shader.
115 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
116 * enabled, incoming strips etc are passed to GS threads in individual
117 * line/triangle/point units. The GS thread may perform arbitary
118 * computation and emit whatever primtives with whatever vertices it
119 * chooses. This makes GS an excellent place to implement GL's
120 * unfilled polygon modes, though of course it is capable of much
121 * more. Additionally, GS is used to translate away primitives not
122 * handled by latter units, including Quads and Lineloops.
124 * CS - Clipper. Mesa's clipping algorithms are imported to run on
125 * this unit. The fixed function part performs cliptesting against
126 * the 6 fixed clipplanes and makes descisions on whether or not the
127 * incoming primitive needs to be passed to a thread for clipping.
128 * User clip planes are handled via cooperation with the VS thread.
130 * SF - Strips Fans or Setup: Triangles are prepared for
131 * rasterization. Interpolation coefficients are calculated.
132 * Flatshading and two-side lighting usually performed here.
134 * WM - Windower. Interpolation of vertex attributes performed here.
135 * Fragment shader implemented here. SIMD aspects of EU taken full
136 * advantage of, as pixels are processed in blocks of 16.
138 * CC - Color Calculator. No EU threads associated with this unit.
139 * Handles blending and (presumably) depth and stencil testing.
142 #define INTEL_WRITE_PART 0x1
143 #define INTEL_WRITE_FULL 0x2
144 #define INTEL_READ 0x4
146 #define BRW_MAX_CURBE (32*16)
149 struct brw_instruction
;
150 struct brw_vs_prog_key
;
151 struct brw_vec4_prog_key
;
152 struct brw_wm_prog_key
;
153 struct brw_wm_prog_data
;
154 struct brw_perf_bo_layout
;
158 BRW_STATE_FRAGMENT_PROGRAM
,
159 BRW_STATE_GEOMETRY_PROGRAM
,
160 BRW_STATE_VERTEX_PROGRAM
,
161 BRW_STATE_CURBE_OFFSETS
,
162 BRW_STATE_REDUCED_PRIMITIVE
,
167 BRW_STATE_VS_BINDING_TABLE
,
168 BRW_STATE_GS_BINDING_TABLE
,
169 BRW_STATE_PS_BINDING_TABLE
,
173 BRW_STATE_INDEX_BUFFER
,
174 BRW_STATE_VS_CONSTBUF
,
175 BRW_STATE_GS_CONSTBUF
,
176 BRW_STATE_PROGRAM_CACHE
,
177 BRW_STATE_STATE_BASE_ADDRESS
,
178 BRW_STATE_VUE_MAP_VS
,
179 BRW_STATE_VUE_MAP_GEOM_OUT
,
180 BRW_STATE_TRANSFORM_FEEDBACK
,
181 BRW_STATE_RASTERIZER_DISCARD
,
183 BRW_STATE_UNIFORM_BUFFER
,
184 BRW_STATE_META_IN_PROGRESS
,
185 BRW_STATE_INTERPOLATION_MAP
,
186 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
190 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
191 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
192 #define BRW_NEW_GEOMETRY_PROGRAM (1 << BRW_STATE_GEOMETRY_PROGRAM)
193 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
194 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
195 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
196 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
197 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
198 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
199 #define BRW_NEW_SURFACES (1 << BRW_STATE_SURFACES)
200 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
201 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
202 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
203 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
204 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
206 * Used for any batch entry with a relocated pointer that will be used
207 * by any 3D rendering.
209 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
210 /** \see brw.state.depth_region */
211 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
212 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
213 #define BRW_NEW_GS_CONSTBUF (1 << BRW_STATE_GS_CONSTBUF)
214 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
215 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
216 #define BRW_NEW_VUE_MAP_VS (1 << BRW_STATE_VUE_MAP_VS)
217 #define BRW_NEW_VUE_MAP_GEOM_OUT (1 << BRW_STATE_VUE_MAP_GEOM_OUT)
218 #define BRW_NEW_TRANSFORM_FEEDBACK (1 << BRW_STATE_TRANSFORM_FEEDBACK)
219 #define BRW_NEW_RASTERIZER_DISCARD (1 << BRW_STATE_RASTERIZER_DISCARD)
220 #define BRW_NEW_STATS_WM (1 << BRW_STATE_STATS_WM)
221 #define BRW_NEW_UNIFORM_BUFFER (1 << BRW_STATE_UNIFORM_BUFFER)
222 #define BRW_NEW_META_IN_PROGRESS (1 << BRW_STATE_META_IN_PROGRESS)
223 #define BRW_NEW_INTERPOLATION_MAP (1 << BRW_STATE_INTERPOLATION_MAP)
224 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1 << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
226 struct brw_state_flags
{
227 /** State update flags signalled by mesa internals */
230 * State update flags signalled as the result of brw_tracked_state updates
233 /** State update flags signalled by brw_state_cache.c searches */
237 #define AUB_TRACE_TYPE_MASK 0x0000ff00
238 #define AUB_TRACE_TYPE_NOTYPE (0 << 8)
239 #define AUB_TRACE_TYPE_BATCH (1 << 8)
240 #define AUB_TRACE_TYPE_VERTEX_BUFFER (5 << 8)
241 #define AUB_TRACE_TYPE_2D_MAP (6 << 8)
242 #define AUB_TRACE_TYPE_CUBE_MAP (7 << 8)
243 #define AUB_TRACE_TYPE_VOLUME_MAP (9 << 8)
244 #define AUB_TRACE_TYPE_1D_MAP (10 << 8)
245 #define AUB_TRACE_TYPE_CONSTANT_BUFFER (11 << 8)
246 #define AUB_TRACE_TYPE_CONSTANT_URB (12 << 8)
247 #define AUB_TRACE_TYPE_INDEX_BUFFER (13 << 8)
248 #define AUB_TRACE_TYPE_GENERAL (14 << 8)
249 #define AUB_TRACE_TYPE_SURFACE (15 << 8)
252 * state_struct_type enum values are encoded with the top 16 bits representing
253 * the type to be delivered to the .aub file, and the bottom 16 bits
254 * representing the subtype. This macro performs the encoding.
256 #define ENCODE_SS_TYPE(type, subtype) (((type) << 16) | (subtype))
258 enum state_struct_type
{
259 AUB_TRACE_VS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 1),
260 AUB_TRACE_GS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 2),
261 AUB_TRACE_CLIP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 3),
262 AUB_TRACE_SF_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 4),
263 AUB_TRACE_WM_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 5),
264 AUB_TRACE_CC_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 6),
265 AUB_TRACE_CLIP_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 7),
266 AUB_TRACE_SF_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 8),
267 AUB_TRACE_CC_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x9),
268 AUB_TRACE_SAMPLER_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xa),
269 AUB_TRACE_KERNEL_INSTRUCTIONS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xb),
270 AUB_TRACE_SCRATCH_SPACE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xc),
271 AUB_TRACE_SAMPLER_DEFAULT_COLOR
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xd),
273 AUB_TRACE_SCISSOR_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x15),
274 AUB_TRACE_BLEND_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x16),
275 AUB_TRACE_DEPTH_STENCIL_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x17),
277 AUB_TRACE_VERTEX_BUFFER
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_VERTEX_BUFFER
, 0),
278 AUB_TRACE_BINDING_TABLE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x100),
279 AUB_TRACE_SURFACE_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x200),
280 AUB_TRACE_VS_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 0),
281 AUB_TRACE_WM_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 1),
285 * Decode a state_struct_type value to determine the type that should be
286 * stored in the .aub file.
288 static inline uint32_t AUB_TRACE_TYPE(enum state_struct_type ss_type
)
290 return (ss_type
& 0xFFFF0000) >> 16;
294 * Decode a state_struct_type value to determine the subtype that should be
295 * stored in the .aub file.
297 static inline uint32_t AUB_TRACE_SUBTYPE(enum state_struct_type ss_type
)
299 return ss_type
& 0xFFFF;
302 /** Subclass of Mesa vertex program */
303 struct brw_vertex_program
{
304 struct gl_vertex_program program
;
309 /** Subclass of Mesa geometry program */
310 struct brw_geometry_program
{
311 struct gl_geometry_program program
;
312 unsigned id
; /**< serial no. to identify geom progs, never re-used */
316 /** Subclass of Mesa fragment program */
317 struct brw_fragment_program
{
318 struct gl_fragment_program program
;
319 GLuint id
; /**< serial no. to identify frag progs, never re-used */
323 struct gl_shader base
;
327 /** Shader IR transformed for native compile, at link time. */
328 struct exec_list
*ir
;
331 /* Note: If adding fields that need anything besides a normal memcmp() for
332 * comparing them, be sure to go fix the the stage-specific
333 * prog_data_compare().
335 struct brw_stage_prog_data
{
337 /** size of our binding table. */
341 * surface indices for the various groups of surfaces
343 uint32_t pull_constants_start
;
344 uint32_t texture_start
;
345 uint32_t gather_texture_start
;
347 uint32_t shader_time_start
;
352 /* Data about a particular attempt to compile a program. Note that
353 * there can be many of these, each in a different GL state
354 * corresponding to a different brw_wm_prog_key struct, with different
357 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
360 struct brw_wm_prog_data
{
361 struct brw_stage_prog_data base
;
363 GLuint curb_read_length
;
364 GLuint num_varying_inputs
;
366 GLuint first_curbe_grf
;
367 GLuint first_curbe_grf_16
;
369 GLuint reg_blocks_16
;
370 GLuint total_scratch
;
374 * surface indices the WM-specific surfaces
376 uint32_t render_target_start
;
380 GLuint nr_params
; /**< number of float params/constants */
381 GLuint nr_pull_params
;
383 uint32_t prog_offset_16
;
386 * Mask of which interpolation modes are required by the fragment shader.
387 * Used in hardware setup on gen6+.
389 uint32_t barycentric_interp_modes
;
392 * Map from gl_varying_slot to the position within the FS setup data
393 * payload where the varying's attribute vertex deltas should be delivered.
394 * For varying slots that are not used by the FS, the value is -1.
396 int urb_setup
[VARYING_SLOT_MAX
];
398 /* Pointers to tracked values (only valid once
399 * _mesa_load_state_parameters has been called at runtime).
401 * These must be the last fields of the struct (see
402 * brw_wm_prog_data_compare()).
405 const float **pull_param
;
409 * Enum representing the i965-specific vertex results that don't correspond
410 * exactly to any element of gl_varying_slot. The values of this enum are
411 * assigned such that they don't conflict with gl_varying_slot.
415 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
416 BRW_VARYING_SLOT_PAD
,
418 * Technically this is not a varying but just a placeholder that
419 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
420 * builtin variable to be compiled correctly. see compile_sf_prog() for
423 BRW_VARYING_SLOT_PNTC
,
424 BRW_VARYING_SLOT_COUNT
429 * Data structure recording the relationship between the gl_varying_slot enum
430 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
431 * single octaword within the VUE (128 bits).
433 * Note that each BRW register contains 256 bits (2 octawords), so when
434 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
435 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
436 * in a vertex shader), each register corresponds to a single VUE slot, since
437 * it contains data for two separate vertices.
441 * Bitfield representing all varying slots that are (a) stored in this VUE
442 * map, and (b) actually written by the shader. Does not include any of
443 * the additional varying slots defined in brw_varying_slot.
445 GLbitfield64 slots_valid
;
448 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
449 * not stored in a slot (because they are not written, or because
450 * additional processing is applied before storing them in the VUE), the
453 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
456 * Map from VUE slot to gl_varying_slot value. For slots that do not
457 * directly correspond to a gl_varying_slot, the value comes from
460 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
461 * simplifies code that uses the value stored in slot_to_varying to
462 * create a bit mask).
464 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
467 * Total number of VUE slots in use
473 * Convert a VUE slot number into a byte offset within the VUE.
475 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
481 * Convert a vertex output (brw_varying_slot) into a byte offset within the
484 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
487 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
490 void brw_compute_vue_map(struct brw_context
*brw
, struct brw_vue_map
*vue_map
,
491 GLbitfield64 slots_valid
);
495 * Bitmask indicating which fragment shader inputs represent varyings (and
496 * hence have to be delivered to the fragment shader by the SF/SBE stage).
498 #define BRW_FS_VARYING_INPUT_MASK \
499 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
500 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
504 * Mapping of VUE map slots to interpolation modes.
506 struct interpolation_mode_map
{
507 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
510 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
512 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
513 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
519 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
521 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
522 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
529 struct brw_sf_prog_data
{
530 GLuint urb_read_length
;
533 /* Each vertex may have upto 12 attributes, 4 components each,
534 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
537 * Actually we use 4 for each, so call it 12 rows.
539 GLuint urb_entry_size
;
544 * We always program SF to start reading at an offset of 1 (2 varying slots)
545 * from the start of the vertex URB entry. This causes it to skip:
546 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
547 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
549 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
552 struct brw_clip_prog_data
{
553 GLuint curb_read_length
; /* user planes? */
555 GLuint urb_read_length
;
559 struct brw_ff_gs_prog_data
{
560 GLuint urb_read_length
;
564 * Gen6 transform feedback: Amount by which the streaming vertex buffer
565 * indices should be incremented each time the GS is invoked.
567 unsigned svbi_postincrement_value
;
571 /* Note: brw_vec4_prog_data_compare() must be updated when adding fields to
574 struct brw_vec4_prog_data
{
575 struct brw_stage_prog_data base
;
576 struct brw_vue_map vue_map
;
579 * Register where the thread expects to find input data from the URB
580 * (typically uniforms, followed by per-vertex inputs).
582 unsigned dispatch_grf_start_reg
;
584 GLuint curb_read_length
;
585 GLuint urb_read_length
;
587 GLuint nr_params
; /**< number of float params/constants */
588 GLuint nr_pull_params
; /**< number of dwords referenced by pull_param[] */
589 GLuint total_scratch
;
591 /* Used for calculating urb partitions. In the VS, this is the size of the
592 * URB entry used for both input and output to the thread. In the GS, this
593 * is the size of the URB entry used for output.
595 GLuint urb_entry_size
;
597 /* These pointers must appear last. See brw_vec4_prog_data_compare(). */
599 const float **pull_param
;
603 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
606 struct brw_vs_prog_data
{
607 struct brw_vec4_prog_data base
;
609 GLbitfield64 inputs_read
;
615 /* Note: brw_gs_prog_data_compare() must be updated when adding fields to
618 struct brw_gs_prog_data
620 struct brw_vec4_prog_data base
;
623 * Size of an output vertex, measured in HWORDS (32 bytes).
625 unsigned output_vertex_size_hwords
;
627 unsigned output_topology
;
630 * Size of the control data (cut bits or StreamID bits), in hwords (32
631 * bytes). 0 if there is no control data.
633 unsigned control_data_header_size_hwords
;
636 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
637 * if the control data is StreamID bits, or
638 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
639 * Ignored if control_data_header_size is 0.
641 unsigned control_data_format
;
643 bool include_primitive_id
;
646 /** Number of texture sampler units */
647 #define BRW_MAX_TEX_UNIT 16
649 /** Max number of render targets in a shader */
650 #define BRW_MAX_DRAW_BUFFERS 8
653 * Max number of binding table entries used for stream output.
655 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
656 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
658 * On Gen6, the size of transform feedback data is limited not by the number
659 * of components but by the number of binding table entries we set aside. We
660 * use one binding table entry for a float, one entry for a vector, and one
661 * entry per matrix column. Since the only way we can communicate our
662 * transform feedback capabilities to the client is via
663 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
664 * worst case, in which all the varyings are floats, so we use up one binding
665 * table entry per component. Therefore we need to set aside at least 64
666 * binding table entries for use by transform feedback.
668 * Note: since we don't currently pack varyings, it is currently impossible
669 * for the client to actually use up all of these binding table entries--if
670 * all of their varyings were floats, they would run out of varying slots and
671 * fail to link. But that's a bug, so it seems prudent to go ahead and
672 * allocate the number of binding table entries we will need once the bug is
675 #define BRW_MAX_SOL_BINDINGS 64
677 /** Maximum number of actual buffers used for stream output */
678 #define BRW_MAX_SOL_BUFFERS 4
680 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
681 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
683 2 /* shader time, pull constants */)
685 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
686 #define BRW_MAX_GEN6_GS_SURFACES SURF_INDEX_GEN6_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
689 * Stride in bytes between shader_time entries.
691 * We separate entries by a cacheline to reduce traffic between EUs writing to
694 #define SHADER_TIME_STRIDE 64
701 BRW_BLORP_CONST_COLOR_PROG
,
706 BRW_SF_UNIT
, /* scissor state on gen6 */
719 struct brw_cache_item
{
721 * Effectively part of the key, cache_id identifies what kind of state
722 * buffer is involved, and also which brw->state.dirty.cache flag should
723 * be set when this cache item is chosen.
725 enum brw_cache_id cache_id
;
726 /** 32-bit hash of the key data */
728 GLuint key_size
; /* for variable-sized keys */
735 struct brw_cache_item
*next
;
739 typedef bool (*cache_aux_compare_func
)(const void *a
, const void *b
);
740 typedef void (*cache_aux_free_func
)(const void *aux
);
743 struct brw_context
*brw
;
745 struct brw_cache_item
**items
;
747 GLuint size
, n_items
;
749 uint32_t next_offset
;
753 * Optional functions used in determining whether the prog_data for a new
754 * cache item matches an existing cache item (in case there's relevant data
755 * outside of the prog_data). If NULL, a plain memcmp is done.
757 cache_aux_compare_func aux_compare
[BRW_MAX_CACHE
];
758 /** Optional functions for freeing other pointers attached to a prog_data. */
759 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
763 /* Considered adding a member to this struct to document which flags
764 * an update might raise so that ordering of the state atoms can be
765 * checked or derived at runtime. Dropped the idea in favor of having
766 * a debug mode where the state is monitored for flags which are
767 * raised that have already been tested against.
769 struct brw_tracked_state
{
770 struct brw_state_flags dirty
;
771 void (*emit
)( struct brw_context
*brw
);
774 enum shader_time_shader_type
{
787 /* Flags for brw->state.cache.
789 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
790 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
791 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
792 #define CACHE_NEW_BLORP_BLIT_PROG (1<<BRW_BLORP_BLIT_PROG)
793 #define CACHE_NEW_BLORP_CONST_COLOR_PROG (1<<BRW_BLORP_CONST_COLOR_PROG)
794 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
795 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
796 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
797 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
798 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
799 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
800 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
801 #define CACHE_NEW_FF_GS_UNIT (1<<BRW_FF_GS_UNIT)
802 #define CACHE_NEW_FF_GS_PROG (1<<BRW_FF_GS_PROG)
803 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
804 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
805 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
806 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
808 struct brw_cached_batch_item
{
809 struct header
*header
;
811 struct brw_cached_batch_item
*next
;
814 struct brw_vertex_buffer
{
815 /** Buffer object containing the uploaded vertex data */
818 /** Byte stride between elements in the uploaded array */
822 struct brw_vertex_element
{
823 const struct gl_client_array
*glarray
;
827 /** The corresponding Mesa vertex attribute */
828 gl_vert_attrib attrib
;
829 /** Offset of the first element within the buffer object */
833 struct brw_query_object
{
834 struct gl_query_object Base
;
836 /** Last query BO associated with this query. */
839 /** Last index in bo with query data for this object. */
843 struct intel_sync_object
{
844 struct gl_sync_object Base
;
846 /** Batch associated with this sync object */
850 struct intel_batchbuffer
{
851 /** Current batchbuffer being queued up. */
853 /** Last BO submitted to the hardware. Used for glFinish(). */
854 drm_intel_bo
*last_bo
;
855 /** BO for post-sync nonzero writes for gen6 workaround. */
856 drm_intel_bo
*workaround_bo
;
857 bool need_workaround_flush
;
859 struct cached_batch_item
*cached_items
;
861 uint16_t emit
, total
;
862 uint16_t used
, reserved_space
;
865 #define BATCH_SZ (8192*sizeof(uint32_t))
867 uint32_t state_batch_offset
;
869 bool needs_sol_reset
;
878 * Data shared between each programmable stage in the pipeline (vs, gs, and
881 struct brw_stage_state
883 struct brw_stage_prog_data
*prog_data
;
886 * Optional scratch buffer used to store spilled register values and
887 * variably-indexed GRF arrays.
889 drm_intel_bo
*scratch_bo
;
891 /** Pull constant buffer */
892 drm_intel_bo
*const_bo
;
894 /** Offset in the program cache to the program */
895 uint32_t prog_offset
;
897 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
898 uint32_t state_offset
;
900 uint32_t push_const_offset
; /* Offset in the batchbuffer */
901 int push_const_size
; /* in 256-bit register increments */
903 /* Binding table: pointers to SURFACE_STATE entries. */
904 uint32_t bind_bo_offset
;
905 uint32_t surf_offset
[BRW_MAX_SURFACES
];
907 /** SAMPLER_STATE count and table offset */
908 uint32_t sampler_count
;
909 uint32_t sampler_offset
;
911 /** Offsets in the batch to sampler default colors (texture border color) */
912 uint32_t sdc_offset
[BRW_MAX_TEX_UNIT
];
917 * brw_context is derived from gl_context.
921 struct gl_context ctx
; /**< base class, must be first field */
925 void (*update_texture_surface
)(struct gl_context
*ctx
,
927 uint32_t *surf_offset
,
929 void (*update_renderbuffer_surface
)(struct brw_context
*brw
,
930 struct gl_renderbuffer
*rb
,
933 void (*update_null_renderbuffer_surface
)(struct brw_context
*brw
,
935 void (*create_constant_surface
)(struct brw_context
*brw
,
939 uint32_t *out_offset
,
942 /** Upload a SAMPLER_STATE table. */
943 void (*upload_sampler_state_table
)(struct brw_context
*brw
,
944 struct gl_program
*prog
,
945 uint32_t sampler_count
,
946 uint32_t *sst_offset
,
947 uint32_t *sdc_offset
);
950 * Send the appropriate state packets to configure depth, stencil, and
951 * HiZ buffers (i965+ only)
953 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
954 struct intel_mipmap_tree
*depth_mt
,
955 uint32_t depth_offset
,
956 uint32_t depthbuffer_format
,
957 uint32_t depth_surface_type
,
958 struct intel_mipmap_tree
*stencil_mt
,
959 bool hiz
, bool separate_stencil
,
960 uint32_t width
, uint32_t height
,
961 uint32_t tile_x
, uint32_t tile_y
);
967 drm_intel_context
*hw_ctx
;
969 struct intel_batchbuffer batch
;
976 uint32_t buffer_offset
;
981 * Set if rendering has occured to the drawable's front buffer.
983 * This is used in the DRI2 case to detect that glFlush should also copy
984 * the contents of the fake front buffer to the real front buffer.
986 bool front_buffer_dirty
;
989 * Track whether front-buffer rendering is currently enabled
991 * A separate flag is used to track this in order to support MRT more
994 bool is_front_buffer_rendering
;
997 * Track whether front-buffer is the current read target.
999 * This is closely associated with is_front_buffer_rendering, but may
1000 * be set separately. The DRI2 fake front buffer must be referenced
1003 bool is_front_buffer_reading
;
1005 /** Framerate throttling: @{ */
1006 drm_intel_bo
*first_post_swapbuffers_batch
;
1017 bool always_flush_batch
;
1018 bool always_flush_cache
;
1019 bool disable_throttling
;
1021 bool disable_derivative_optimization
;
1023 driOptionCache optionCache
;
1026 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
1028 GLenum reduced_primitive
;
1031 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
1032 * variable is set, this is the flag indicating to do expensive work that
1033 * might lead to a perf_debug() call.
1037 uint32_t max_gtt_map_object_size
;
1047 bool has_separate_stencil
;
1048 bool must_use_separate_stencil
;
1051 bool has_surface_tile_offset
;
1053 bool has_negative_rhw_bug
;
1057 * Some versions of Gen hardware don't do centroid interpolation correctly
1058 * on unlit pixels, causing incorrect values for derivatives near triangle
1059 * edges. Enabling this flag causes the fragment shader to use
1060 * non-centroid interpolation for unlit pixels, at the expense of two extra
1061 * fragment shader instructions.
1063 bool needs_unlit_centroid_workaround
;
1067 struct brw_state_flags dirty
;
1070 struct brw_cache cache
;
1071 struct brw_cached_batch_item
*cached_batch_items
;
1073 /* Whether a meta-operation is in progress. */
1074 bool meta_in_progress
;
1077 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
1078 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
1080 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
1084 /* Summary of size and varying of active arrays, so we can check
1085 * for changes to this state:
1087 unsigned int min_index
, max_index
;
1089 /* Offset from start of vertex buffer so we can avoid redefining
1090 * the same VB packed over and over again.
1092 unsigned int start_vertex_bias
;
1097 * Index buffer for this draw_prims call.
1099 * Updates are signaled by BRW_NEW_INDICES.
1101 const struct _mesa_index_buffer
*ib
;
1103 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
1107 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
1108 * avoid re-uploading the IB packet over and over if we're actually
1109 * referencing the same index buffer.
1111 unsigned int start_vertex_offset
;
1114 /* Active vertex program:
1116 const struct gl_vertex_program
*vertex_program
;
1117 const struct gl_geometry_program
*geometry_program
;
1118 const struct gl_fragment_program
*fragment_program
;
1120 /* hw-dependent 3DSTATE_VF_STATISTICS opcode */
1121 uint32_t CMD_VF_STATISTICS
;
1122 /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
1123 uint32_t CMD_PIPELINE_SELECT
;
1126 * Platform specific constants containing the maximum number of threads
1127 * for each pipeline stage.
1133 /* BRW_NEW_URB_ALLOCATIONS:
1136 GLuint vsize
; /* vertex size plus header in urb registers */
1137 GLuint csize
; /* constant buffer size in urb registers */
1138 GLuint sfsize
; /* setup data size in urb registers */
1142 GLuint min_vs_entries
; /* Minimum number of VS entries */
1143 GLuint max_vs_entries
; /* Maximum number of VS entries */
1144 GLuint max_gs_entries
; /* Maximum number of GS entries */
1146 GLuint nr_vs_entries
;
1147 GLuint nr_gs_entries
;
1148 GLuint nr_clip_entries
;
1149 GLuint nr_sf_entries
;
1150 GLuint nr_cs_entries
;
1157 GLuint size
; /* Hardware URB size, in KB. */
1159 /* gen6: True if the most recently sent _3DSTATE_URB message allocated
1160 * URB space for the GS.
1162 bool gen6_gs_previously_active
;
1166 /* BRW_NEW_CURBE_OFFSETS:
1169 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1170 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1177 drm_intel_bo
*curbe_bo
;
1178 /** Offset within curbe_bo of space for current curbe entry */
1179 GLuint curbe_offset
;
1180 /** Offset within curbe_bo of space for next curbe entry */
1181 GLuint curbe_next_offset
;
1184 * Copy of the last set of CURBEs uploaded. Frequently we'll end up
1185 * in brw_curbe.c with the same set of constant data to be uploaded,
1186 * so we'd rather not upload new constants in that case (it can cause
1187 * a pipeline bubble since only up to 4 can be pipelined at a time).
1191 * Allocation for where to calculate the next set of CURBEs.
1192 * It's a hot enough path that malloc/free of that data matters.
1199 * Layout of vertex data exiting the vertex shader.
1201 * BRW_NEW_VUE_MAP_VS is flagged when this VUE map changes.
1203 struct brw_vue_map vue_map_vs
;
1206 * Layout of vertex data exiting the geometry portion of the pipleine.
1207 * This comes from the geometry shader if one exists, otherwise from the
1210 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1212 struct brw_vue_map vue_map_geom_out
;
1215 * Data structures used by all vec4 program compiles (not specific to any
1216 * particular program).
1219 struct ra_regs
*regs
;
1222 * Array of the ra classes for the unaligned contiguous register
1228 * Mapping for register-allocated objects in *regs to the first
1229 * GRF for that object.
1231 uint8_t *ra_reg_to_grf
;
1235 struct brw_stage_state base
;
1236 struct brw_vs_prog_data
*prog_data
;
1240 struct brw_stage_state base
;
1241 struct brw_gs_prog_data
*prog_data
;
1245 struct brw_ff_gs_prog_data
*prog_data
;
1248 /** Offset in the program cache to the CLIP program pre-gen6 */
1249 uint32_t prog_offset
;
1250 uint32_t state_offset
;
1252 uint32_t bind_bo_offset
;
1253 uint32_t surf_offset
[BRW_MAX_GEN6_GS_SURFACES
];
1257 struct brw_clip_prog_data
*prog_data
;
1259 /** Offset in the program cache to the CLIP program pre-gen6 */
1260 uint32_t prog_offset
;
1262 /* Offset in the batch to the CLIP state on pre-gen6. */
1263 uint32_t state_offset
;
1265 /* As of gen6, this is the offset in the batch to the CLIP VP,
1273 struct brw_sf_prog_data
*prog_data
;
1275 /** Offset in the program cache to the CLIP program pre-gen6 */
1276 uint32_t prog_offset
;
1277 uint32_t state_offset
;
1282 struct brw_stage_state base
;
1283 struct brw_wm_prog_data
*prog_data
;
1288 * Buffer object used in place of multisampled null render targets on
1289 * Gen6. See brw_update_null_renderbuffer_surface().
1291 drm_intel_bo
*multisampled_null_render_target_bo
;
1294 struct ra_regs
*regs
;
1297 * Array of the ra classes for the unaligned contiguous register
1298 * block sizes used, indexed by register size.
1303 * Mapping for register-allocated objects in *regs to the first
1304 * GRF for that object.
1306 uint8_t *ra_reg_to_grf
;
1309 * ra class for the aligned pairs we use for PLN, which doesn't
1310 * appear in *classes.
1312 int aligned_pairs_class
;
1318 uint32_t state_offset
;
1319 uint32_t blend_state_offset
;
1320 uint32_t depth_stencil_state_offset
;
1325 struct brw_query_object
*obj
;
1330 /* A map describing which counters are stored at a particular 32-bit
1331 * offset in the buffer object.
1333 const struct brw_perf_bo_layout
*bo_layout
;
1335 /* Number of 32-bit entries in the buffer object. */
1340 const struct brw_tracked_state
**atoms
;
1342 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1346 enum state_struct_type type
;
1347 } *state_batch_list
;
1348 int state_batch_count
;
1350 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1351 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1353 /* Interpolation modes, one byte per vue slot.
1354 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1356 struct interpolation_mode_map interpolation_mode
;
1358 /* PrimitiveRestart */
1361 bool enable_cut_index
;
1364 /** Computed depth/stencil/hiz state from the current attached
1365 * renderbuffers, valid only during the drawing state upload loop after
1366 * brw_workaround_depthstencil_alignment().
1369 struct intel_mipmap_tree
*depth_mt
;
1370 struct intel_mipmap_tree
*stencil_mt
;
1372 /* Inter-tile (page-aligned) byte offsets. */
1373 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1374 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1375 uint32_t tile_x
, tile_y
;
1378 uint32_t num_instances
;
1383 struct gl_shader_program
**shader_programs
;
1384 struct gl_program
**programs
;
1385 enum shader_time_shader_type
*types
;
1386 uint64_t *cumulative
;
1392 __DRIcontext
*driContext
;
1393 struct intel_screen
*intelScreen
;
1394 void (*saved_viewport
)(struct gl_context
*ctx
,
1395 GLint x
, GLint y
, GLsizei width
, GLsizei height
);
1399 is_power_of_two(uint32_t value
)
1401 return (value
& (value
- 1)) == 0;
1404 /*======================================================================
1407 void brwInitVtbl( struct brw_context
*brw
);
1410 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1412 /*======================================================================
1415 extern void intelFinish(struct gl_context
* ctx
);
1418 DRI_CONF_BO_REUSE_DISABLED
,
1419 DRI_CONF_BO_REUSE_ALL
1422 void intel_update_renderbuffers(__DRIcontext
*context
,
1423 __DRIdrawable
*drawable
);
1424 void intel_prepare_render(struct brw_context
*brw
);
1426 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1427 __DRIdrawable
*drawable
);
1429 bool brwCreateContext(gl_api api
,
1430 const struct gl_config
*mesaVis
,
1431 __DRIcontext
*driContextPriv
,
1432 unsigned major_version
,
1433 unsigned minor_version
,
1436 void *sharedContextPrivate
);
1438 /*======================================================================
1441 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1442 uint32_t depth_level
,
1443 uint32_t depth_layer
,
1444 struct intel_mipmap_tree
*stencil_mt
,
1445 uint32_t *out_tile_mask_x
,
1446 uint32_t *out_tile_mask_y
);
1447 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1448 GLbitfield clear_mask
);
1450 /* brw_object_purgeable.c */
1451 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1453 /*======================================================================
1456 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1457 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1458 void brw_emit_query_begin(struct brw_context
*brw
);
1459 void brw_emit_query_end(struct brw_context
*brw
);
1461 /** gen6_queryobj.c */
1462 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1464 /*======================================================================
1467 void brw_debug_batch(struct brw_context
*brw
);
1468 void brw_annotate_aub(struct brw_context
*brw
);
1470 /*======================================================================
1473 void brw_validate_textures( struct brw_context
*brw
);
1476 /*======================================================================
1479 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1481 int brw_get_scratch_size(int size
);
1482 void brw_get_scratch_bo(struct brw_context
*brw
,
1483 drm_intel_bo
**scratch_bo
, int size
);
1484 void brw_init_shader_time(struct brw_context
*brw
);
1485 int brw_get_shader_time_index(struct brw_context
*brw
,
1486 struct gl_shader_program
*shader_prog
,
1487 struct gl_program
*prog
,
1488 enum shader_time_shader_type type
);
1489 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1490 void brw_destroy_shader_time(struct brw_context
*brw
);
1494 void brw_upload_urb_fence(struct brw_context
*brw
);
1498 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1500 /* brw_fs_reg_allocate.cpp
1502 void brw_fs_alloc_reg_sets(struct brw_context
*brw
);
1504 /* brw_vec4_reg_allocate.cpp */
1505 void brw_vec4_alloc_reg_set(struct brw_context
*brw
);
1508 int brw_disasm (FILE *file
, struct brw_instruction
*inst
, int gen
);
1511 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1513 /* brw_draw_upload.c */
1514 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1515 const struct gl_client_array
*glarray
);
1516 unsigned brw_get_index_type(GLenum type
);
1518 /* brw_wm_surface_state.c */
1519 void brw_init_surface_formats(struct brw_context
*brw
);
1521 brw_update_sol_surface(struct brw_context
*brw
,
1522 struct gl_buffer_object
*buffer_obj
,
1523 uint32_t *out_offset
, unsigned num_vector_components
,
1524 unsigned stride_dwords
, unsigned offset_dwords
);
1525 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1526 struct gl_shader
*shader
,
1527 struct brw_stage_state
*stage_state
,
1528 struct brw_stage_prog_data
*prog_data
);
1530 /* brw_surface_formats.c */
1531 bool brw_is_hiz_depth_format(struct brw_context
*ctx
, gl_format format
);
1532 bool brw_render_target_supported(struct brw_context
*brw
,
1533 struct gl_renderbuffer
*rb
);
1535 /* brw_performance_monitor.c */
1536 void brw_init_performance_monitors(struct brw_context
*brw
);
1538 /* intel_extensions.c */
1539 extern void intelInitExtensions(struct gl_context
*ctx
);
1542 extern int intel_translate_shadow_compare_func(GLenum func
);
1543 extern int intel_translate_compare_func(GLenum func
);
1544 extern int intel_translate_stencil_op(GLenum op
);
1545 extern int intel_translate_logic_op(GLenum opcode
);
1547 /* intel_syncobj.c */
1548 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1552 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1553 struct gl_transform_feedback_object
*obj
);
1555 brw_end_transform_feedback(struct gl_context
*ctx
,
1556 struct gl_transform_feedback_object
*obj
);
1558 /* gen7_sol_state.c */
1560 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1561 struct gl_transform_feedback_object
*obj
);
1563 gen7_end_transform_feedback(struct gl_context
*ctx
,
1564 struct gl_transform_feedback_object
*obj
);
1566 /* brw_blorp_blit.cpp */
1568 brw_blorp_framebuffer(struct brw_context
*brw
,
1569 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1570 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1571 GLbitfield mask
, GLenum filter
);
1574 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1575 struct gl_renderbuffer
*src_rb
,
1576 struct gl_texture_image
*dst_image
,
1578 int srcX0
, int srcY0
,
1579 int dstX0
, int dstY0
,
1580 int width
, int height
);
1582 /* gen6_multisample_state.c */
1584 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1585 unsigned num_samples
);
1587 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
,
1588 unsigned num_samples
, float coverage
,
1589 bool coverage_invert
, unsigned sample_mask
);
1591 gen6_get_sample_position(struct gl_context
*ctx
,
1592 struct gl_framebuffer
*fb
,
1598 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1599 unsigned gs_size
, unsigned fs_size
);
1602 gen7_emit_urb_state(struct brw_context
*brw
,
1603 unsigned nr_vs_entries
, unsigned vs_size
,
1604 unsigned vs_start
, unsigned nr_gs_entries
,
1605 unsigned gs_size
, unsigned gs_start
);
1609 /*======================================================================
1610 * Inline conversion functions. These are better-typed than the
1611 * macros used previously:
1613 static INLINE
struct brw_context
*
1614 brw_context( struct gl_context
*ctx
)
1616 return (struct brw_context
*)ctx
;
1619 static INLINE
struct brw_vertex_program
*
1620 brw_vertex_program(struct gl_vertex_program
*p
)
1622 return (struct brw_vertex_program
*) p
;
1625 static INLINE
const struct brw_vertex_program
*
1626 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1628 return (const struct brw_vertex_program
*) p
;
1631 static INLINE
struct brw_fragment_program
*
1632 brw_fragment_program(struct gl_fragment_program
*p
)
1634 return (struct brw_fragment_program
*) p
;
1637 static INLINE
const struct brw_fragment_program
*
1638 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1640 return (const struct brw_fragment_program
*) p
;
1644 * Pre-gen6, the register file of the EUs was shared between threads,
1645 * and each thread used some subset allocated on a 16-register block
1646 * granularity. The unit states wanted these block counts.
1649 brw_register_blocks(int reg_count
)
1651 return ALIGN(reg_count
, 16) / 16 - 1;
1654 static inline uint32_t
1655 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1656 uint32_t prog_offset
)
1658 if (brw
->gen
>= 5) {
1659 /* Using state base address. */
1663 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1667 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1669 return brw
->cache
.bo
->offset
+ prog_offset
;
1672 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1673 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1674 struct exec_list
*instructions
);
1676 struct opcode_desc
{
1682 extern const struct opcode_desc opcode_descs
[128];
1685 brw_emit_depthbuffer(struct brw_context
*brw
);
1688 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1689 struct intel_mipmap_tree
*depth_mt
,
1690 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1691 uint32_t depth_surface_type
,
1692 struct intel_mipmap_tree
*stencil_mt
,
1693 bool hiz
, bool separate_stencil
,
1694 uint32_t width
, uint32_t height
,
1695 uint32_t tile_x
, uint32_t tile_y
);
1698 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1699 struct intel_mipmap_tree
*depth_mt
,
1700 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1701 uint32_t depth_surface_type
,
1702 struct intel_mipmap_tree
*stencil_mt
,
1703 bool hiz
, bool separate_stencil
,
1704 uint32_t width
, uint32_t height
,
1705 uint32_t tile_x
, uint32_t tile_y
);
1707 extern const GLuint prim_to_hw_prim
[GL_TRIANGLE_STRIP_ADJACENCY
+1];
1710 brw_setup_vec4_key_clip_info(struct brw_context
*brw
,
1711 struct brw_vec4_prog_key
*key
,
1712 bool program_uses_clip_distance
);
1715 gen6_upload_vec4_push_constants(struct brw_context
*brw
,
1716 const struct gl_program
*prog
,
1717 const struct brw_vec4_prog_data
*prog_data
,
1718 struct brw_stage_state
*stage_state
,
1719 enum state_struct_type type
);
1721 /* ================================================================
1722 * From linux kernel i386 header files, copes with odd sizes better
1723 * than COPY_DWORDS would:
1724 * XXX Put this in src/mesa/main/imports.h ???
1726 #if defined(i386) || defined(__i386__)
1727 static INLINE
void * __memcpy(void * to
, const void * from
, size_t n
)
1730 __asm__
__volatile__(
1735 "1:\ttestb $1,%b4\n\t"
1739 : "=&c" (d0
), "=&D" (d1
), "=&S" (d2
)
1740 :"0" (n
/4), "q" (n
),"1" ((long) to
),"2" ((long) from
)
1745 #define __memcpy(a,b,c) memcpy(a,b,c)