2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
38 #include "main/imports.h"
39 #include "main/macros.h"
41 #include "main/mtypes.h"
42 #include "brw_structs.h"
43 #include "brw_compiler.h"
44 #include "intel_aub.h"
45 #include "program/prog_parameter.h"
49 /* Evil hack for using libdrm in a c++ compiler. */
54 #include <intel_bufmgr.h>
64 #include "intel_debug.h"
65 #include "intel_screen.h"
66 #include "intel_tex_obj.h"
67 #include "intel_resolve_map.h"
71 * URB - uniform resource buffer. A mid-sized buffer which is
72 * partitioned between the fixed function units and used for passing
73 * values (vertices, primitives, constants) between them.
75 * CURBE - constant URB entry. An urb region (entry) used to hold
76 * constant values which the fixed function units can be instructed to
77 * preload into the GRF when spawning a thread.
79 * VUE - vertex URB entry. An urb entry holding a vertex and usually
80 * a vertex header. The header contains control information and
81 * things like primitive type, Begin/end flags and clip codes.
83 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
84 * unit holding rasterization and interpolation parameters.
86 * GRF - general register file. One of several register files
87 * addressable by programmed threads. The inputs (r0, payload, curbe,
88 * urb) of the thread are preloaded to this area before the thread is
89 * spawned. The registers are individually 8 dwords wide and suitable
90 * for general usage. Registers holding thread input values are not
91 * special and may be overwritten.
93 * MRF - message register file. Threads communicate (and terminate)
94 * by sending messages. Message parameters are placed in contiguous
95 * MRF registers. All program output is via these messages. URB
96 * entries are populated by sending a message to the shared URB
97 * function containing the new data, together with a control word,
98 * often an unmodified copy of R0.
100 * R0 - GRF register 0. Typically holds control information used when
101 * sending messages to other threads.
103 * EU or GEN4 EU: The name of the programmable subsystem of the
104 * i965 hardware. Threads are executed by the EU, the registers
105 * described above are part of the EU architecture.
107 * Fixed function units:
109 * CS - Command streamer. Notional first unit, little software
110 * interaction. Holds the URB entries used for constant data, ie the
113 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
114 * this unit is responsible for pulling vertices out of vertex buffers
115 * in vram and injecting them into the processing pipe as VUEs. If
116 * enabled, it first passes them to a VS thread which is a good place
117 * for the driver to implement any active vertex shader.
119 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
120 * enabled, incoming strips etc are passed to GS threads in individual
121 * line/triangle/point units. The GS thread may perform arbitary
122 * computation and emit whatever primtives with whatever vertices it
123 * chooses. This makes GS an excellent place to implement GL's
124 * unfilled polygon modes, though of course it is capable of much
125 * more. Additionally, GS is used to translate away primitives not
126 * handled by latter units, including Quads and Lineloops.
128 * CS - Clipper. Mesa's clipping algorithms are imported to run on
129 * this unit. The fixed function part performs cliptesting against
130 * the 6 fixed clipplanes and makes descisions on whether or not the
131 * incoming primitive needs to be passed to a thread for clipping.
132 * User clip planes are handled via cooperation with the VS thread.
134 * SF - Strips Fans or Setup: Triangles are prepared for
135 * rasterization. Interpolation coefficients are calculated.
136 * Flatshading and two-side lighting usually performed here.
138 * WM - Windower. Interpolation of vertex attributes performed here.
139 * Fragment shader implemented here. SIMD aspects of EU taken full
140 * advantage of, as pixels are processed in blocks of 16.
142 * CC - Color Calculator. No EU threads associated with this unit.
143 * Handles blending and (presumably) depth and stencil testing.
148 struct brw_vs_prog_key
;
149 struct brw_vue_prog_key
;
150 struct brw_wm_prog_key
;
151 struct brw_wm_prog_data
;
152 struct brw_cs_prog_key
;
153 struct brw_cs_prog_data
;
157 BRW_COMPUTE_PIPELINE
,
164 BRW_CACHE_BLORP_BLIT_PROG
,
167 BRW_CACHE_FF_GS_PROG
,
176 /* brw_cache_ids must come first - see brw_state_cache.c */
177 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
178 BRW_STATE_FRAGMENT_PROGRAM
,
179 BRW_STATE_GEOMETRY_PROGRAM
,
180 BRW_STATE_VERTEX_PROGRAM
,
181 BRW_STATE_CURBE_OFFSETS
,
182 BRW_STATE_REDUCED_PRIMITIVE
,
187 BRW_STATE_BINDING_TABLE_POINTERS
,
191 BRW_STATE_INDEX_BUFFER
,
192 BRW_STATE_VS_CONSTBUF
,
193 BRW_STATE_GS_CONSTBUF
,
194 BRW_STATE_PROGRAM_CACHE
,
195 BRW_STATE_STATE_BASE_ADDRESS
,
196 BRW_STATE_VUE_MAP_GEOM_OUT
,
197 BRW_STATE_TRANSFORM_FEEDBACK
,
198 BRW_STATE_RASTERIZER_DISCARD
,
200 BRW_STATE_UNIFORM_BUFFER
,
201 BRW_STATE_ATOMIC_BUFFER
,
202 BRW_STATE_IMAGE_UNITS
,
203 BRW_STATE_META_IN_PROGRESS
,
204 BRW_STATE_INTERPOLATION_MAP
,
205 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
206 BRW_STATE_NUM_SAMPLES
,
207 BRW_STATE_TEXTURE_BUFFER
,
208 BRW_STATE_GEN4_UNIT_STATE
,
212 BRW_STATE_SAMPLER_STATE_TABLE
,
213 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
214 BRW_STATE_COMPUTE_PROGRAM
,
215 BRW_STATE_CS_WORK_GROUPS
,
220 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
222 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
223 * When the currently bound shader program differs from the previous draw
224 * call, these will be flagged. They cover brw->{stage}_program and
225 * ctx->{Stage}Program->_Current.
227 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
228 * driver perspective. Even if the same shader is bound at the API level,
229 * we may need to switch between multiple versions of that shader to handle
230 * changes in non-orthagonal state.
232 * Additionally, multiple shader programs may have identical vertex shaders
233 * (for example), or compile down to the same code in the backend. We combine
234 * those into a single program cache entry.
236 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
237 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
239 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
240 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
241 * use the normal state upload paths), but the cache is still used. To avoid
242 * polluting the brw_state_cache code with special cases, we retain the dirty
243 * bit for now. It should eventually be removed.
245 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_BLIT_PROG)
246 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
247 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
248 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
249 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
250 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
251 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
252 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
253 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
254 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
255 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
256 #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
257 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
258 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
259 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
260 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
261 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
262 #define BRW_NEW_BINDING_TABLE_POINTERS (1ull << BRW_STATE_BINDING_TABLE_POINTERS)
263 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
264 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
266 * Used for any batch entry with a relocated pointer that will be used
267 * by any 3D rendering.
269 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
270 /** \see brw.state.depth_region */
271 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
272 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
273 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
274 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
275 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
276 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
277 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
278 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
279 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
280 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
281 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
282 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
283 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
284 #define BRW_NEW_INTERPOLATION_MAP (1ull << BRW_STATE_INTERPOLATION_MAP)
285 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
286 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
287 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
288 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
289 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
290 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
291 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
292 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
293 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
294 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
295 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
297 struct brw_state_flags
{
298 /** State update flags signalled by mesa internals */
301 * State update flags signalled as the result of brw_tracked_state updates
306 /** Subclass of Mesa vertex program */
307 struct brw_vertex_program
{
308 struct gl_vertex_program program
;
313 /** Subclass of Mesa geometry program */
314 struct brw_geometry_program
{
315 struct gl_geometry_program program
;
316 unsigned id
; /**< serial no. to identify geom progs, never re-used */
320 /** Subclass of Mesa fragment program */
321 struct brw_fragment_program
{
322 struct gl_fragment_program program
;
323 GLuint id
; /**< serial no. to identify frag progs, never re-used */
327 /** Subclass of Mesa compute program */
328 struct brw_compute_program
{
329 struct gl_compute_program program
;
330 unsigned id
; /**< serial no. to identify compute progs, never re-used */
335 struct gl_shader base
;
341 * Bitmask indicating which fragment shader inputs represent varyings (and
342 * hence have to be delivered to the fragment shader by the SF/SBE stage).
344 #define BRW_FS_VARYING_INPUT_MASK \
345 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
346 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
350 * Mapping of VUE map slots to interpolation modes.
352 struct interpolation_mode_map
{
353 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
356 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
358 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
359 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
365 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
367 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
368 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
375 struct brw_sf_prog_data
{
376 GLuint urb_read_length
;
379 /* Each vertex may have upto 12 attributes, 4 components each,
380 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
383 * Actually we use 4 for each, so call it 12 rows.
385 GLuint urb_entry_size
;
390 * We always program SF to start reading at an offset of 1 (2 varying slots)
391 * from the start of the vertex URB entry. This causes it to skip:
392 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
393 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
395 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
398 struct brw_clip_prog_data
{
399 GLuint curb_read_length
; /* user planes? */
401 GLuint urb_read_length
;
405 struct brw_ff_gs_prog_data
{
406 GLuint urb_read_length
;
410 * Gen6 transform feedback: Amount by which the streaming vertex buffer
411 * indices should be incremented each time the GS is invoked.
413 unsigned svbi_postincrement_value
;
416 /** Number of texture sampler units */
417 #define BRW_MAX_TEX_UNIT 32
419 /** Max number of render targets in a shader */
420 #define BRW_MAX_DRAW_BUFFERS 8
422 /** Max number of UBOs in a shader */
423 #define BRW_MAX_UBO 12
425 /** Max number of SSBOs in a shader */
426 #define BRW_MAX_SSBO 12
428 /** Max number of atomic counter buffer objects in a shader */
429 #define BRW_MAX_ABO 16
431 /** Max number of image uniforms in a shader */
432 #define BRW_MAX_IMAGES 32
435 * Max number of binding table entries used for stream output.
437 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
438 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
440 * On Gen6, the size of transform feedback data is limited not by the number
441 * of components but by the number of binding table entries we set aside. We
442 * use one binding table entry for a float, one entry for a vector, and one
443 * entry per matrix column. Since the only way we can communicate our
444 * transform feedback capabilities to the client is via
445 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
446 * worst case, in which all the varyings are floats, so we use up one binding
447 * table entry per component. Therefore we need to set aside at least 64
448 * binding table entries for use by transform feedback.
450 * Note: since we don't currently pack varyings, it is currently impossible
451 * for the client to actually use up all of these binding table entries--if
452 * all of their varyings were floats, they would run out of varying slots and
453 * fail to link. But that's a bug, so it seems prudent to go ahead and
454 * allocate the number of binding table entries we will need once the bug is
457 #define BRW_MAX_SOL_BINDINGS 64
459 /** Maximum number of actual buffers used for stream output */
460 #define BRW_MAX_SOL_BUFFERS 4
462 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
463 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
468 2 + /* shader time, pull constants */ \
469 1 /* cs num work groups */)
471 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
474 * Stride in bytes between shader_time entries.
476 * We separate entries by a cacheline to reduce traffic between EUs writing to
479 #define SHADER_TIME_STRIDE 64
481 struct brw_cache_item
{
483 * Effectively part of the key, cache_id identifies what kind of state
484 * buffer is involved, and also which dirty flag should set.
486 enum brw_cache_id cache_id
;
487 /** 32-bit hash of the key data */
489 GLuint key_size
; /* for variable-sized keys */
496 struct brw_cache_item
*next
;
501 struct brw_context
*brw
;
503 struct brw_cache_item
**items
;
505 GLuint size
, n_items
;
507 uint32_t next_offset
;
512 /* Considered adding a member to this struct to document which flags
513 * an update might raise so that ordering of the state atoms can be
514 * checked or derived at runtime. Dropped the idea in favor of having
515 * a debug mode where the state is monitored for flags which are
516 * raised that have already been tested against.
518 struct brw_tracked_state
{
519 struct brw_state_flags dirty
;
520 void (*emit
)( struct brw_context
*brw
);
523 enum shader_time_shader_type
{
532 struct brw_vertex_buffer
{
533 /** Buffer object containing the uploaded vertex data */
536 /** Byte stride between elements in the uploaded array */
540 struct brw_vertex_element
{
541 const struct gl_client_array
*glarray
;
545 /** Offset of the first element within the buffer object */
549 struct brw_query_object
{
550 struct gl_query_object Base
;
552 /** Last query BO associated with this query. */
555 /** Last index in bo with query data for this object. */
558 /** True if we know the batch has been flushed since we ended the query. */
568 struct intel_batchbuffer
{
569 /** Current batchbuffer being queued up. */
571 /** Last BO submitted to the hardware. Used for glFinish(). */
572 drm_intel_bo
*last_bo
;
575 uint16_t emit
, total
;
577 uint16_t reserved_space
;
581 #define BATCH_SZ (8192*sizeof(uint32_t))
583 uint32_t state_batch_offset
;
584 enum brw_gpu_ring ring
;
585 bool needs_sol_reset
;
593 #define MAX_GS_INPUT_VERTICES 6
595 #define BRW_MAX_XFB_STREAMS 4
597 struct brw_transform_feedback_object
{
598 struct gl_transform_feedback_object base
;
600 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
601 drm_intel_bo
*offset_bo
;
603 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
606 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
607 GLenum primitive_mode
;
610 * Count of primitives generated during this transform feedback operation.
613 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
614 drm_intel_bo
*prim_count_bo
;
615 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
619 * Number of vertices written between last Begin/EndTransformFeedback().
621 * Used to implement DrawTransformFeedback().
623 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
624 bool vertices_written_valid
;
628 * Data shared between each programmable stage in the pipeline (vs, gs, and
631 struct brw_stage_state
633 gl_shader_stage stage
;
634 struct brw_stage_prog_data
*prog_data
;
637 * Optional scratch buffer used to store spilled register values and
638 * variably-indexed GRF arrays.
640 drm_intel_bo
*scratch_bo
;
642 /** Offset in the program cache to the program */
643 uint32_t prog_offset
;
645 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
646 uint32_t state_offset
;
648 uint32_t push_const_offset
; /* Offset in the batchbuffer */
649 int push_const_size
; /* in 256-bit register increments */
651 /* Binding table: pointers to SURFACE_STATE entries. */
652 uint32_t bind_bo_offset
;
653 uint32_t surf_offset
[BRW_MAX_SURFACES
];
655 /** SAMPLER_STATE count and table offset */
656 uint32_t sampler_count
;
657 uint32_t sampler_offset
;
660 enum brw_predicate_state
{
661 /* The first two states are used if we can determine whether to draw
662 * without having to look at the values in the query object buffer. This
663 * will happen if there is no conditional render in progress, if the query
664 * object is already completed or if something else has already added
665 * samples to the preliminary result such as via a BLT command.
667 BRW_PREDICATE_STATE_RENDER
,
668 BRW_PREDICATE_STATE_DONT_RENDER
,
669 /* In this case whether to draw or not depends on the result of an
670 * MI_PREDICATE command so the predicate enable bit needs to be checked.
672 BRW_PREDICATE_STATE_USE_BIT
678 * brw_context is derived from gl_context.
682 struct gl_context ctx
; /**< base class, must be first field */
686 void (*update_texture_surface
)(struct gl_context
*ctx
,
688 uint32_t *surf_offset
,
690 uint32_t (*update_renderbuffer_surface
)(struct brw_context
*brw
,
691 struct gl_renderbuffer
*rb
,
692 bool layered
, unsigned unit
,
693 uint32_t surf_index
);
695 void (*emit_texture_surface_state
)(struct brw_context
*brw
,
696 struct intel_mipmap_tree
*mt
,
704 uint32_t *surf_offset
,
705 bool rw
, bool for_gather
);
706 void (*emit_buffer_surface_state
)(struct brw_context
*brw
,
707 uint32_t *out_offset
,
709 unsigned buffer_offset
,
710 unsigned surface_format
,
711 unsigned buffer_size
,
714 void (*emit_null_surface_state
)(struct brw_context
*brw
,
718 uint32_t *out_offset
);
721 * Send the appropriate state packets to configure depth, stencil, and
722 * HiZ buffers (i965+ only)
724 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
725 struct intel_mipmap_tree
*depth_mt
,
726 uint32_t depth_offset
,
727 uint32_t depthbuffer_format
,
728 uint32_t depth_surface_type
,
729 struct intel_mipmap_tree
*stencil_mt
,
730 bool hiz
, bool separate_stencil
,
731 uint32_t width
, uint32_t height
,
732 uint32_t tile_x
, uint32_t tile_y
);
738 drm_intel_context
*hw_ctx
;
740 /** BO for post-sync nonzero writes for gen6 workaround. */
741 drm_intel_bo
*workaround_bo
;
742 uint8_t pipe_controls_since_last_cs_stall
;
745 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
746 * and would need flushing before being used from another cache domain that
747 * isn't coherent with it (i.e. the sampler).
749 struct set
*render_cache
;
752 * Number of resets observed in the system at context creation.
754 * This is tracked in the context so that we can determine that another
755 * reset has occurred.
757 uint32_t reset_count
;
759 struct intel_batchbuffer batch
;
764 uint32_t next_offset
;
768 * Set if rendering has occurred to the drawable's front buffer.
770 * This is used in the DRI2 case to detect that glFlush should also copy
771 * the contents of the fake front buffer to the real front buffer.
773 bool front_buffer_dirty
;
775 /** Framerate throttling: @{ */
776 drm_intel_bo
*throttle_batch
[2];
778 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
779 * frame of rendering to complete. This gives a very precise cap to the
780 * latency between input and output such that rendering never gets more
781 * than a frame behind the user. (With the caveat that we technically are
782 * not using the SwapBuffers itself as a barrier but the first batch
783 * submitted afterwards, which may be immediately prior to the next
786 bool need_swap_throttle
;
788 /** General throttling, not caught by throttling between SwapBuffers */
789 bool need_flush_throttle
;
799 bool always_flush_batch
;
800 bool always_flush_cache
;
801 bool disable_throttling
;
804 driOptionCache optionCache
;
807 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
809 GLenum reduced_primitive
;
812 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
813 * variable is set, this is the flag indicating to do expensive work that
814 * might lead to a perf_debug() call.
818 uint32_t max_gtt_map_object_size
;
830 bool has_separate_stencil
;
831 bool must_use_separate_stencil
;
834 bool has_surface_tile_offset
;
836 bool has_negative_rhw_bug
;
840 bool use_resource_streamer
;
843 * Some versions of Gen hardware don't do centroid interpolation correctly
844 * on unlit pixels, causing incorrect values for derivatives near triangle
845 * edges. Enabling this flag causes the fragment shader to use
846 * non-centroid interpolation for unlit pixels, at the expense of two extra
847 * fragment shader instructions.
849 bool needs_unlit_centroid_workaround
;
853 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
856 enum brw_pipeline last_pipeline
;
858 struct brw_cache cache
;
860 /** IDs for meta stencil blit shader programs. */
861 unsigned meta_stencil_blit_programs
[2];
863 /* Whether a meta-operation is in progress. */
864 bool meta_in_progress
;
866 /* Whether the last depth/stencil packets were both NULL. */
867 bool no_depth_or_stencil
;
869 /* The last PMA stall bits programmed. */
870 uint32_t pma_stall_bits
;
873 /** The value of gl_BaseVertex for the current _mesa_prim. */
877 * Buffer and offset used for GL_ARB_shader_draw_parameters
878 * (for now, only gl_BaseVertex).
880 drm_intel_bo
*draw_params_bo
;
881 uint32_t draw_params_offset
;
886 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
887 * an indirect call, and num_work_groups_offset is valid. Otherwise,
888 * num_work_groups is set based on glDispatchCompute.
890 drm_intel_bo
*num_work_groups_bo
;
891 GLintptr num_work_groups_offset
;
892 const GLuint
*num_work_groups
;
896 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
897 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
899 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
903 /* Summary of size and varying of active arrays, so we can check
904 * for changes to this state:
906 unsigned int min_index
, max_index
;
908 /* Offset from start of vertex buffer so we can avoid redefining
909 * the same VB packed over and over again.
911 unsigned int start_vertex_bias
;
914 * Certain vertex attribute formats aren't natively handled by the
915 * hardware and require special VS code to fix up their values.
917 * These bitfields indicate which workarounds are needed.
919 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
924 * Index buffer for this draw_prims call.
926 * Updates are signaled by BRW_NEW_INDICES.
928 const struct _mesa_index_buffer
*ib
;
930 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
934 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
935 * avoid re-uploading the IB packet over and over if we're actually
936 * referencing the same index buffer.
938 unsigned int start_vertex_offset
;
941 /* Active vertex program:
943 const struct gl_vertex_program
*vertex_program
;
944 const struct gl_geometry_program
*geometry_program
;
945 const struct gl_fragment_program
*fragment_program
;
946 const struct gl_compute_program
*compute_program
;
949 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
950 * that we don't have to reemit that state every time we change FBOs.
955 * Platform specific constants containing the maximum number of threads
956 * for each pipeline stage.
958 unsigned max_vs_threads
;
959 unsigned max_hs_threads
;
960 unsigned max_ds_threads
;
961 unsigned max_gs_threads
;
962 unsigned max_wm_threads
;
963 unsigned max_cs_threads
;
965 /* BRW_NEW_URB_ALLOCATIONS:
968 GLuint vsize
; /* vertex size plus header in urb registers */
969 GLuint gsize
; /* GS output size in urb registers */
970 GLuint csize
; /* constant buffer size in urb registers */
971 GLuint sfsize
; /* setup data size in urb registers */
975 GLuint min_vs_entries
; /* Minimum number of VS entries */
976 GLuint max_vs_entries
; /* Maximum number of VS entries */
977 GLuint max_hs_entries
; /* Maximum number of HS entries */
978 GLuint max_ds_entries
; /* Maximum number of DS entries */
979 GLuint max_gs_entries
; /* Maximum number of GS entries */
981 GLuint nr_vs_entries
;
982 GLuint nr_gs_entries
;
983 GLuint nr_clip_entries
;
984 GLuint nr_sf_entries
;
985 GLuint nr_cs_entries
;
992 GLuint size
; /* Hardware URB size, in KB. */
994 /* True if the most recently sent _3DSTATE_URB message allocated
995 * URB space for the GS.
1001 /* BRW_NEW_CURBE_OFFSETS:
1004 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1005 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1013 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1014 * for upload to the CURBE.
1016 drm_intel_bo
*curbe_bo
;
1017 /** Offset within curbe_bo of space for current curbe entry */
1018 GLuint curbe_offset
;
1022 * Layout of vertex data exiting the geometry portion of the pipleine.
1023 * This comes from the last enabled shader stage (GS, DS, or VS).
1025 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1027 struct brw_vue_map vue_map_geom_out
;
1030 struct brw_stage_state base
;
1031 struct brw_vs_prog_data
*prog_data
;
1035 struct brw_stage_state base
;
1036 struct brw_gs_prog_data
*prog_data
;
1039 * True if the 3DSTATE_GS command most recently emitted to the 3D
1040 * pipeline enabled the GS; false otherwise.
1046 struct brw_ff_gs_prog_data
*prog_data
;
1049 /** Offset in the program cache to the CLIP program pre-gen6 */
1050 uint32_t prog_offset
;
1051 uint32_t state_offset
;
1053 uint32_t bind_bo_offset
;
1055 * Surface offsets for the binding table. We only need surfaces to
1056 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1057 * need in this case.
1059 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1063 struct brw_clip_prog_data
*prog_data
;
1065 /** Offset in the program cache to the CLIP program pre-gen6 */
1066 uint32_t prog_offset
;
1068 /* Offset in the batch to the CLIP state on pre-gen6. */
1069 uint32_t state_offset
;
1071 /* As of gen6, this is the offset in the batch to the CLIP VP,
1079 struct brw_sf_prog_data
*prog_data
;
1081 /** Offset in the program cache to the CLIP program pre-gen6 */
1082 uint32_t prog_offset
;
1083 uint32_t state_offset
;
1085 bool viewport_transform_enable
;
1089 struct brw_stage_state base
;
1090 struct brw_wm_prog_data
*prog_data
;
1095 * Buffer object used in place of multisampled null render targets on
1096 * Gen6. See brw_emit_null_surface_state().
1098 drm_intel_bo
*multisampled_null_render_target_bo
;
1099 uint32_t fast_clear_op
;
1105 struct brw_stage_state base
;
1106 struct brw_cs_prog_data
*prog_data
;
1109 /* RS hardware binding table */
1112 uint32_t next_offset
;
1116 uint32_t state_offset
;
1117 uint32_t blend_state_offset
;
1118 uint32_t depth_stencil_state_offset
;
1123 struct brw_query_object
*obj
;
1128 enum brw_predicate_state state
;
1133 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1134 const int *statistics_registers
;
1136 /** The number of active monitors using OA counters. */
1140 * A buffer object storing OA counter snapshots taken at the start and
1141 * end of each batch (creating "bookends" around the batch).
1143 drm_intel_bo
*bookend_bo
;
1145 /** The number of snapshots written to bookend_bo. */
1146 int bookend_snapshots
;
1149 * An array of monitors whose results haven't yet been assembled based on
1150 * the data in buffer objects.
1152 * These may be active, or have already ended. However, the results
1153 * have not been requested.
1155 struct brw_perf_monitor_object
**unresolved
;
1156 int unresolved_elements
;
1157 int unresolved_array_size
;
1160 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1161 * the counter which MI_REPORT_PERF_COUNT stores there.
1163 const int *oa_snapshot_layout
;
1165 /** Number of 32-bit entries in a hardware counter snapshot. */
1166 int entries_per_oa_snapshot
;
1169 int num_atoms
[BRW_NUM_PIPELINES
];
1170 const struct brw_tracked_state render_atoms
[60];
1171 const struct brw_tracked_state compute_atoms
[9];
1173 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1177 enum aub_state_struct_type type
;
1179 } *state_batch_list
;
1180 int state_batch_count
;
1182 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1183 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1185 /* Interpolation modes, one byte per vue slot.
1186 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1188 struct interpolation_mode_map interpolation_mode
;
1190 /* PrimitiveRestart */
1193 bool enable_cut_index
;
1196 /** Computed depth/stencil/hiz state from the current attached
1197 * renderbuffers, valid only during the drawing state upload loop after
1198 * brw_workaround_depthstencil_alignment().
1201 struct intel_mipmap_tree
*depth_mt
;
1202 struct intel_mipmap_tree
*stencil_mt
;
1204 /* Inter-tile (page-aligned) byte offsets. */
1205 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1206 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1207 uint32_t tile_x
, tile_y
;
1210 uint32_t num_instances
;
1217 enum shader_time_shader_type
*types
;
1218 struct shader_times
*cumulative
;
1224 struct brw_fast_clear_state
*fast_clear_state
;
1226 __DRIcontext
*driContext
;
1227 struct intel_screen
*intelScreen
;
1230 /*======================================================================
1233 void brwInitVtbl( struct brw_context
*brw
);
1236 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1238 /*======================================================================
1241 extern const char *const brw_vendor_string
;
1243 extern const char *brw_get_renderer_string(unsigned deviceID
);
1246 DRI_CONF_BO_REUSE_DISABLED
,
1247 DRI_CONF_BO_REUSE_ALL
1250 void intel_update_renderbuffers(__DRIcontext
*context
,
1251 __DRIdrawable
*drawable
);
1252 void intel_prepare_render(struct brw_context
*brw
);
1254 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1255 __DRIdrawable
*drawable
);
1257 GLboolean
brwCreateContext(gl_api api
,
1258 const struct gl_config
*mesaVis
,
1259 __DRIcontext
*driContextPriv
,
1260 unsigned major_version
,
1261 unsigned minor_version
,
1265 void *sharedContextPrivate
);
1267 /*======================================================================
1270 GLuint
brw_get_rb_for_slice(struct brw_context
*brw
,
1271 struct intel_mipmap_tree
*mt
,
1272 unsigned level
, unsigned layer
, bool flat
);
1274 void brw_meta_updownsample(struct brw_context
*brw
,
1275 struct intel_mipmap_tree
*src
,
1276 struct intel_mipmap_tree
*dst
);
1278 void brw_meta_fbo_stencil_blit(struct brw_context
*brw
,
1279 struct gl_framebuffer
*read_fb
,
1280 struct gl_framebuffer
*draw_fb
,
1281 GLfloat srcX0
, GLfloat srcY0
,
1282 GLfloat srcX1
, GLfloat srcY1
,
1283 GLfloat dstX0
, GLfloat dstY0
,
1284 GLfloat dstX1
, GLfloat dstY1
);
1286 void brw_meta_stencil_updownsample(struct brw_context
*brw
,
1287 struct intel_mipmap_tree
*src
,
1288 struct intel_mipmap_tree
*dst
);
1290 bool brw_meta_fast_clear(struct brw_context
*brw
,
1291 struct gl_framebuffer
*fb
,
1293 bool partial_clear
);
1296 brw_meta_resolve_color(struct brw_context
*brw
,
1297 struct intel_mipmap_tree
*mt
);
1299 brw_meta_fast_clear_free(struct brw_context
*brw
);
1302 /*======================================================================
1305 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1306 uint32_t depth_level
,
1307 uint32_t depth_layer
,
1308 struct intel_mipmap_tree
*stencil_mt
,
1309 uint32_t *out_tile_mask_x
,
1310 uint32_t *out_tile_mask_y
);
1311 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1312 GLbitfield clear_mask
);
1314 /* brw_object_purgeable.c */
1315 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1317 /*======================================================================
1320 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1321 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1322 void brw_emit_query_begin(struct brw_context
*brw
);
1323 void brw_emit_query_end(struct brw_context
*brw
);
1325 /** gen6_queryobj.c */
1326 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1327 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1328 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1329 void brw_store_register_mem64(struct brw_context
*brw
,
1330 drm_intel_bo
*bo
, uint32_t reg
, int idx
);
1332 /** brw_conditional_render.c */
1333 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1334 bool brw_check_conditional_render(struct brw_context
*brw
);
1336 /** intel_batchbuffer.c */
1337 void brw_load_register_mem(struct brw_context
*brw
,
1340 uint32_t read_domains
, uint32_t write_domain
,
1342 void brw_load_register_mem64(struct brw_context
*brw
,
1345 uint32_t read_domains
, uint32_t write_domain
,
1348 /*======================================================================
1351 void brw_debug_batch(struct brw_context
*brw
);
1352 void brw_annotate_aub(struct brw_context
*brw
);
1354 /*======================================================================
1357 void brw_validate_textures( struct brw_context
*brw
);
1360 /*======================================================================
1363 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1365 /* Per-thread scratch space is a power-of-two multiple of 1KB. */
1367 brw_get_scratch_size(int size
)
1369 return util_next_power_of_two(size
| 1023);
1371 void brw_get_scratch_bo(struct brw_context
*brw
,
1372 drm_intel_bo
**scratch_bo
, int size
);
1373 void brw_init_shader_time(struct brw_context
*brw
);
1374 int brw_get_shader_time_index(struct brw_context
*brw
,
1375 struct gl_shader_program
*shader_prog
,
1376 struct gl_program
*prog
,
1377 enum shader_time_shader_type type
);
1378 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1379 void brw_destroy_shader_time(struct brw_context
*brw
);
1383 void brw_upload_urb_fence(struct brw_context
*brw
);
1387 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1389 /* brw_fs_reg_allocate.cpp
1391 void brw_fs_alloc_reg_sets(struct brw_compiler
*compiler
);
1393 /* brw_vec4_reg_allocate.cpp */
1394 void brw_vec4_alloc_reg_set(struct brw_compiler
*compiler
);
1397 int brw_disassemble_inst(FILE *file
, const struct brw_device_info
*devinfo
,
1398 struct brw_inst
*inst
, bool is_compacted
);
1401 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1403 /* brw_draw_upload.c */
1404 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1405 const struct gl_client_array
*glarray
);
1407 static inline unsigned
1408 brw_get_index_type(GLenum type
)
1410 assert((type
== GL_UNSIGNED_BYTE
)
1411 || (type
== GL_UNSIGNED_SHORT
)
1412 || (type
== GL_UNSIGNED_INT
));
1414 /* The possible values for type are GL_UNSIGNED_BYTE (0x1401),
1415 * GL_UNSIGNED_SHORT (0x1403), and GL_UNSIGNED_INT (0x1405) which we want
1416 * to map to scale factors of 0, 1, and 2, respectively. These scale
1417 * factors are then left-shfited by 8 to be in the correct position in the
1418 * CMD_INDEX_BUFFER packet.
1420 * Subtracting 0x1401 gives 0, 2, and 4. Shifting left by 7 afterwards
1421 * gives 0x00000000, 0x00000100, and 0x00000200. These just happen to be
1422 * the values the need to be written in the CMD_INDEX_BUFFER packet.
1424 return (type
- 0x1401) << 7;
1427 void brw_prepare_vertices(struct brw_context
*brw
);
1429 /* brw_wm_surface_state.c */
1430 void brw_init_surface_formats(struct brw_context
*brw
);
1431 void brw_create_constant_surface(struct brw_context
*brw
,
1435 uint32_t *out_offset
,
1437 void brw_create_buffer_surface(struct brw_context
*brw
,
1441 uint32_t *out_offset
,
1443 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1445 uint32_t *surf_offset
);
1447 brw_update_sol_surface(struct brw_context
*brw
,
1448 struct gl_buffer_object
*buffer_obj
,
1449 uint32_t *out_offset
, unsigned num_vector_components
,
1450 unsigned stride_dwords
, unsigned offset_dwords
);
1451 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1452 struct gl_shader
*shader
,
1453 struct brw_stage_state
*stage_state
,
1454 struct brw_stage_prog_data
*prog_data
,
1456 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1457 struct gl_shader
*shader
,
1458 struct brw_stage_state
*stage_state
,
1459 struct brw_stage_prog_data
*prog_data
);
1460 void brw_upload_image_surfaces(struct brw_context
*brw
,
1461 struct gl_shader
*shader
,
1462 struct brw_stage_state
*stage_state
,
1463 struct brw_stage_prog_data
*prog_data
);
1465 /* brw_surface_formats.c */
1466 bool brw_render_target_supported(struct brw_context
*brw
,
1467 struct gl_renderbuffer
*rb
);
1468 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1469 mesa_format
brw_lower_mesa_image_format(const struct brw_device_info
*devinfo
,
1470 mesa_format format
);
1472 /* brw_performance_monitor.c */
1473 void brw_init_performance_monitors(struct brw_context
*brw
);
1474 void brw_dump_perf_monitors(struct brw_context
*brw
);
1475 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1476 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1478 /* intel_buffer_objects.c */
1479 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1480 const char *bo_name
);
1481 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1482 const char *bo_name
);
1484 /* intel_extensions.c */
1485 extern void intelInitExtensions(struct gl_context
*ctx
);
1488 extern int intel_translate_shadow_compare_func(GLenum func
);
1489 extern int intel_translate_compare_func(GLenum func
);
1490 extern int intel_translate_stencil_op(GLenum op
);
1491 extern int intel_translate_logic_op(GLenum opcode
);
1493 /* intel_syncobj.c */
1494 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1497 struct gl_transform_feedback_object
*
1498 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1500 brw_delete_transform_feedback(struct gl_context
*ctx
,
1501 struct gl_transform_feedback_object
*obj
);
1503 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1504 struct gl_transform_feedback_object
*obj
);
1506 brw_end_transform_feedback(struct gl_context
*ctx
,
1507 struct gl_transform_feedback_object
*obj
);
1509 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1510 struct gl_transform_feedback_object
*obj
,
1513 /* gen7_sol_state.c */
1515 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1516 struct gl_transform_feedback_object
*obj
);
1518 gen7_end_transform_feedback(struct gl_context
*ctx
,
1519 struct gl_transform_feedback_object
*obj
);
1521 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1522 struct gl_transform_feedback_object
*obj
);
1524 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1525 struct gl_transform_feedback_object
*obj
);
1527 /* brw_blorp_blit.cpp */
1529 brw_blorp_framebuffer(struct brw_context
*brw
,
1530 struct gl_framebuffer
*readFb
,
1531 struct gl_framebuffer
*drawFb
,
1532 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1533 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1534 GLbitfield mask
, GLenum filter
);
1537 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1538 struct gl_renderbuffer
*src_rb
,
1539 struct gl_texture_image
*dst_image
,
1541 int srcX0
, int srcY0
,
1542 int dstX0
, int dstY0
,
1543 int width
, int height
);
1545 /* gen6_multisample_state.c */
1547 gen6_determine_sample_mask(struct brw_context
*brw
);
1550 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1551 unsigned num_samples
);
1553 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1555 gen6_get_sample_position(struct gl_context
*ctx
,
1556 struct gl_framebuffer
*fb
,
1560 gen6_set_sample_maps(struct gl_context
*ctx
);
1562 /* gen8_multisample_state.c */
1563 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1564 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1568 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1569 unsigned gs_size
, unsigned fs_size
);
1572 gen7_emit_urb_state(struct brw_context
*brw
,
1573 unsigned nr_vs_entries
, unsigned vs_size
,
1574 unsigned vs_start
, unsigned nr_gs_entries
,
1575 unsigned gs_size
, unsigned gs_start
);
1580 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1584 brw_init_compute_functions(struct dd_function_table
*functions
);
1586 /*======================================================================
1587 * Inline conversion functions. These are better-typed than the
1588 * macros used previously:
1590 static inline struct brw_context
*
1591 brw_context( struct gl_context
*ctx
)
1593 return (struct brw_context
*)ctx
;
1596 static inline struct brw_vertex_program
*
1597 brw_vertex_program(struct gl_vertex_program
*p
)
1599 return (struct brw_vertex_program
*) p
;
1602 static inline const struct brw_vertex_program
*
1603 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1605 return (const struct brw_vertex_program
*) p
;
1608 static inline struct brw_geometry_program
*
1609 brw_geometry_program(struct gl_geometry_program
*p
)
1611 return (struct brw_geometry_program
*) p
;
1614 static inline struct brw_fragment_program
*
1615 brw_fragment_program(struct gl_fragment_program
*p
)
1617 return (struct brw_fragment_program
*) p
;
1620 static inline const struct brw_fragment_program
*
1621 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1623 return (const struct brw_fragment_program
*) p
;
1626 static inline struct brw_compute_program
*
1627 brw_compute_program(struct gl_compute_program
*p
)
1629 return (struct brw_compute_program
*) p
;
1633 * Pre-gen6, the register file of the EUs was shared between threads,
1634 * and each thread used some subset allocated on a 16-register block
1635 * granularity. The unit states wanted these block counts.
1638 brw_register_blocks(int reg_count
)
1640 return ALIGN(reg_count
, 16) / 16 - 1;
1643 static inline uint32_t
1644 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1645 uint32_t prog_offset
)
1647 if (brw
->gen
>= 5) {
1648 /* Using state base address. */
1652 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1656 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1658 return brw
->cache
.bo
->offset64
+ prog_offset
;
1661 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1662 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1663 struct exec_list
*instructions
);
1664 bool brw_do_lower_unnormalized_offset(struct exec_list
*instructions
);
1666 struct opcode_desc
{
1672 extern const struct opcode_desc opcode_descs
[128];
1673 extern const char * const conditional_modifier
[16];
1674 extern const char *const pred_ctrl_align16
[16];
1677 brw_emit_depthbuffer(struct brw_context
*brw
);
1680 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1681 struct intel_mipmap_tree
*depth_mt
,
1682 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1683 uint32_t depth_surface_type
,
1684 struct intel_mipmap_tree
*stencil_mt
,
1685 bool hiz
, bool separate_stencil
,
1686 uint32_t width
, uint32_t height
,
1687 uint32_t tile_x
, uint32_t tile_y
);
1690 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1691 struct intel_mipmap_tree
*depth_mt
,
1692 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1693 uint32_t depth_surface_type
,
1694 struct intel_mipmap_tree
*stencil_mt
,
1695 bool hiz
, bool separate_stencil
,
1696 uint32_t width
, uint32_t height
,
1697 uint32_t tile_x
, uint32_t tile_y
);
1700 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1701 struct intel_mipmap_tree
*depth_mt
,
1702 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1703 uint32_t depth_surface_type
,
1704 struct intel_mipmap_tree
*stencil_mt
,
1705 bool hiz
, bool separate_stencil
,
1706 uint32_t width
, uint32_t height
,
1707 uint32_t tile_x
, uint32_t tile_y
);
1709 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1710 struct intel_mipmap_tree
*depth_mt
,
1711 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1712 uint32_t depth_surface_type
,
1713 struct intel_mipmap_tree
*stencil_mt
,
1714 bool hiz
, bool separate_stencil
,
1715 uint32_t width
, uint32_t height
,
1716 uint32_t tile_x
, uint32_t tile_y
);
1718 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1719 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);
1721 uint32_t get_hw_prim_for_gl_prim(int mode
);
1724 gen6_upload_push_constants(struct brw_context
*brw
,
1725 const struct gl_program
*prog
,
1726 const struct brw_stage_prog_data
*prog_data
,
1727 struct brw_stage_state
*stage_state
,
1728 enum aub_state_struct_type type
);
1731 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
1732 const struct intel_mipmap_tree
*mt
);
1734 /* brw_pipe_control.c */
1735 int brw_init_pipe_control(struct brw_context
*brw
,
1736 const struct brw_device_info
*info
);
1737 void brw_fini_pipe_control(struct brw_context
*brw
);
1739 void brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
);
1740 void brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
1741 drm_intel_bo
*bo
, uint32_t offset
,
1742 uint32_t imm_lower
, uint32_t imm_upper
);
1743 void brw_emit_mi_flush(struct brw_context
*brw
);
1744 void brw_emit_post_sync_nonzero_flush(struct brw_context
*brw
);
1745 void brw_emit_depth_stall_flushes(struct brw_context
*brw
);
1746 void gen7_emit_vs_workaround_flush(struct brw_context
*brw
);
1747 void gen7_emit_cs_stall_flush(struct brw_context
*brw
);