2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
37 #include "main/macros.h"
38 #include "main/mtypes.h"
39 #include "brw_structs.h"
40 #include "brw_pipe_control.h"
41 #include "compiler/brw_compiler.h"
44 #include "blorp/blorp.h"
46 #include <brw_bufmgr.h>
48 #include "common/gen_debug.h"
49 #include "intel_screen.h"
50 #include "intel_tex_obj.h"
57 * URB - uniform resource buffer. A mid-sized buffer which is
58 * partitioned between the fixed function units and used for passing
59 * values (vertices, primitives, constants) between them.
61 * CURBE - constant URB entry. An urb region (entry) used to hold
62 * constant values which the fixed function units can be instructed to
63 * preload into the GRF when spawning a thread.
65 * VUE - vertex URB entry. An urb entry holding a vertex and usually
66 * a vertex header. The header contains control information and
67 * things like primitive type, Begin/end flags and clip codes.
69 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
70 * unit holding rasterization and interpolation parameters.
72 * GRF - general register file. One of several register files
73 * addressable by programmed threads. The inputs (r0, payload, curbe,
74 * urb) of the thread are preloaded to this area before the thread is
75 * spawned. The registers are individually 8 dwords wide and suitable
76 * for general usage. Registers holding thread input values are not
77 * special and may be overwritten.
79 * MRF - message register file. Threads communicate (and terminate)
80 * by sending messages. Message parameters are placed in contiguous
81 * MRF registers. All program output is via these messages. URB
82 * entries are populated by sending a message to the shared URB
83 * function containing the new data, together with a control word,
84 * often an unmodified copy of R0.
86 * R0 - GRF register 0. Typically holds control information used when
87 * sending messages to other threads.
89 * EU or GEN4 EU: The name of the programmable subsystem of the
90 * i965 hardware. Threads are executed by the EU, the registers
91 * described above are part of the EU architecture.
93 * Fixed function units:
95 * CS - Command streamer. Notional first unit, little software
96 * interaction. Holds the URB entries used for constant data, ie the
99 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
100 * this unit is responsible for pulling vertices out of vertex buffers
101 * in vram and injecting them into the processing pipe as VUEs. If
102 * enabled, it first passes them to a VS thread which is a good place
103 * for the driver to implement any active vertex shader.
105 * HS - Hull Shader (Tessellation Control Shader)
107 * TE - Tessellation Engine (Tessellation Primitive Generation)
109 * DS - Domain Shader (Tessellation Evaluation Shader)
111 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
112 * enabled, incoming strips etc are passed to GS threads in individual
113 * line/triangle/point units. The GS thread may perform arbitary
114 * computation and emit whatever primtives with whatever vertices it
115 * chooses. This makes GS an excellent place to implement GL's
116 * unfilled polygon modes, though of course it is capable of much
117 * more. Additionally, GS is used to translate away primitives not
118 * handled by latter units, including Quads and Lineloops.
120 * CS - Clipper. Mesa's clipping algorithms are imported to run on
121 * this unit. The fixed function part performs cliptesting against
122 * the 6 fixed clipplanes and makes descisions on whether or not the
123 * incoming primitive needs to be passed to a thread for clipping.
124 * User clip planes are handled via cooperation with the VS thread.
126 * SF - Strips Fans or Setup: Triangles are prepared for
127 * rasterization. Interpolation coefficients are calculated.
128 * Flatshading and two-side lighting usually performed here.
130 * WM - Windower. Interpolation of vertex attributes performed here.
131 * Fragment shader implemented here. SIMD aspects of EU taken full
132 * advantage of, as pixels are processed in blocks of 16.
134 * CC - Color Calculator. No EU threads associated with this unit.
135 * Handles blending and (presumably) depth and stencil testing.
140 struct brw_vs_prog_key
;
141 struct brw_vue_prog_key
;
142 struct brw_wm_prog_key
;
143 struct brw_wm_prog_data
;
144 struct brw_cs_prog_key
;
145 struct brw_cs_prog_data
;
149 BRW_COMPUTE_PIPELINE
,
156 BRW_CACHE_BLORP_PROG
,
159 BRW_CACHE_FF_GS_PROG
,
170 /* brw_cache_ids must come first - see brw_program_cache.c */
171 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
172 BRW_STATE_FRAGMENT_PROGRAM
,
173 BRW_STATE_GEOMETRY_PROGRAM
,
174 BRW_STATE_TESS_PROGRAMS
,
175 BRW_STATE_VERTEX_PROGRAM
,
176 BRW_STATE_REDUCED_PRIMITIVE
,
177 BRW_STATE_PATCH_PRIMITIVE
,
182 BRW_STATE_BINDING_TABLE_POINTERS
,
185 BRW_STATE_DEFAULT_TESS_LEVELS
,
187 BRW_STATE_INDEX_BUFFER
,
188 BRW_STATE_VS_CONSTBUF
,
189 BRW_STATE_TCS_CONSTBUF
,
190 BRW_STATE_TES_CONSTBUF
,
191 BRW_STATE_GS_CONSTBUF
,
192 BRW_STATE_PROGRAM_CACHE
,
193 BRW_STATE_STATE_BASE_ADDRESS
,
194 BRW_STATE_VUE_MAP_GEOM_OUT
,
195 BRW_STATE_TRANSFORM_FEEDBACK
,
196 BRW_STATE_RASTERIZER_DISCARD
,
198 BRW_STATE_UNIFORM_BUFFER
,
199 BRW_STATE_IMAGE_UNITS
,
200 BRW_STATE_META_IN_PROGRESS
,
201 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
202 BRW_STATE_NUM_SAMPLES
,
203 BRW_STATE_TEXTURE_BUFFER
,
204 BRW_STATE_GEN4_UNIT_STATE
,
208 BRW_STATE_SAMPLER_STATE_TABLE
,
209 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
210 BRW_STATE_COMPUTE_PROGRAM
,
211 BRW_STATE_CS_WORK_GROUPS
,
215 BRW_STATE_VIEWPORT_COUNT
,
216 BRW_STATE_CONSERVATIVE_RASTERIZATION
,
223 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
225 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
226 * When the currently bound shader program differs from the previous draw
227 * call, these will be flagged. They cover brw->{stage}_program and
228 * ctx->{Stage}Program->_Current.
230 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
231 * driver perspective. Even if the same shader is bound at the API level,
232 * we may need to switch between multiple versions of that shader to handle
233 * changes in non-orthagonal state.
235 * Additionally, multiple shader programs may have identical vertex shaders
236 * (for example), or compile down to the same code in the backend. We combine
237 * those into a single program cache entry.
239 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
240 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
242 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
243 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
244 * use the normal state upload paths), but the cache is still used. To avoid
245 * polluting the brw_program_cache code with special cases, we retain the
246 * dirty bit for now. It should eventually be removed.
248 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_PROG)
249 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
250 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
251 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
252 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
253 #define BRW_NEW_TCS_PROG_DATA (1ull << BRW_CACHE_TCS_PROG)
254 #define BRW_NEW_TES_PROG_DATA (1ull << BRW_CACHE_TES_PROG)
255 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
256 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
257 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
258 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
259 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
260 #define BRW_NEW_TESS_PROGRAMS (1ull << BRW_STATE_TESS_PROGRAMS)
261 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
262 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
263 #define BRW_NEW_PATCH_PRIMITIVE (1ull << BRW_STATE_PATCH_PRIMITIVE)
264 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
265 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
266 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
267 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
268 #define BRW_NEW_BINDING_TABLE_POINTERS (1ull << BRW_STATE_BINDING_TABLE_POINTERS)
269 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
270 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
271 #define BRW_NEW_DEFAULT_TESS_LEVELS (1ull << BRW_STATE_DEFAULT_TESS_LEVELS)
273 * Used for any batch entry with a relocated pointer that will be used
274 * by any 3D rendering.
276 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
277 /** \see brw.state.depth_region */
278 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
279 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
280 #define BRW_NEW_TCS_CONSTBUF (1ull << BRW_STATE_TCS_CONSTBUF)
281 #define BRW_NEW_TES_CONSTBUF (1ull << BRW_STATE_TES_CONSTBUF)
282 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
283 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
284 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
285 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
286 #define BRW_NEW_VIEWPORT_COUNT (1ull << BRW_STATE_VIEWPORT_COUNT)
287 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
288 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
289 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
290 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
291 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
292 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
293 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
294 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
295 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
296 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
297 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
298 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
299 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
300 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
301 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
302 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
303 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
304 #define BRW_NEW_URB_SIZE (1ull << BRW_STATE_URB_SIZE)
305 #define BRW_NEW_CC_STATE (1ull << BRW_STATE_CC_STATE)
306 #define BRW_NEW_BLORP (1ull << BRW_STATE_BLORP)
307 #define BRW_NEW_CONSERVATIVE_RASTERIZATION (1ull << BRW_STATE_CONSERVATIVE_RASTERIZATION)
308 #define BRW_NEW_DRAW_CALL (1ull << BRW_STATE_DRAW_CALL)
309 #define BRW_NEW_AUX_STATE (1ull << BRW_STATE_AUX)
311 struct brw_state_flags
{
312 /** State update flags signalled by mesa internals */
315 * State update flags signalled as the result of brw_tracked_state updates
321 /** Subclass of Mesa program */
323 struct gl_program program
;
330 struct brw_ff_gs_prog_data
{
331 GLuint urb_read_length
;
335 * Gen6 transform feedback: Amount by which the streaming vertex buffer
336 * indices should be incremented each time the GS is invoked.
338 unsigned svbi_postincrement_value
;
341 /** Number of texture sampler units */
342 #define BRW_MAX_TEX_UNIT 32
344 /** Max number of UBOs in a shader */
345 #define BRW_MAX_UBO 14
347 /** Max number of SSBOs in a shader */
348 #define BRW_MAX_SSBO 12
350 /** Max number of atomic counter buffer objects in a shader */
351 #define BRW_MAX_ABO 16
353 /** Max number of image uniforms in a shader */
354 #define BRW_MAX_IMAGES 32
356 /** Maximum number of actual buffers used for stream output */
357 #define BRW_MAX_SOL_BUFFERS 4
359 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
360 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
365 2 + /* shader time, pull constants */ \
366 1 /* cs num work groups */)
369 struct brw_context
*brw
;
371 struct brw_cache_item
**items
;
374 GLuint size
, n_items
;
376 uint32_t next_offset
;
379 #define perf_debug(...) do { \
380 static GLuint msg_id = 0; \
381 if (unlikely(INTEL_DEBUG & DEBUG_PERF)) \
382 dbg_printf(__VA_ARGS__); \
383 if (brw->perf_debug) \
384 _mesa_gl_debug(&brw->ctx, &msg_id, \
385 MESA_DEBUG_SOURCE_API, \
386 MESA_DEBUG_TYPE_PERFORMANCE, \
387 MESA_DEBUG_SEVERITY_MEDIUM, \
391 #define WARN_ONCE(cond, fmt...) do { \
392 if (unlikely(cond)) { \
393 static bool _warned = false; \
394 static GLuint msg_id = 0; \
396 fprintf(stderr, "WARNING: "); \
397 fprintf(stderr, fmt); \
400 _mesa_gl_debug(ctx, &msg_id, \
401 MESA_DEBUG_SOURCE_API, \
402 MESA_DEBUG_TYPE_OTHER, \
403 MESA_DEBUG_SEVERITY_HIGH, fmt); \
408 /* Considered adding a member to this struct to document which flags
409 * an update might raise so that ordering of the state atoms can be
410 * checked or derived at runtime. Dropped the idea in favor of having
411 * a debug mode where the state is monitored for flags which are
412 * raised that have already been tested against.
414 struct brw_tracked_state
{
415 struct brw_state_flags dirty
;
416 void (*emit
)( struct brw_context
*brw
);
419 enum shader_time_shader_type
{
430 struct brw_vertex_buffer
{
431 /** Buffer object containing the uploaded vertex data */
435 /** Byte stride between elements in the uploaded array */
439 struct brw_vertex_element
{
440 const struct gl_vertex_array
*glarray
;
444 /** Offset of the first element within the buffer object */
448 struct brw_query_object
{
449 struct gl_query_object Base
;
451 /** Last query BO associated with this query. */
454 /** Last index in bo with query data for this object. */
457 /** True if we know the batch has been flushed since we ended the query. */
467 struct brw_reloc_list
{
468 struct drm_i915_gem_relocation_entry
*relocs
;
470 int reloc_array_size
;
473 struct brw_growing_bo
{
476 struct brw_bo
*partial_bo
;
477 uint32_t *partial_bo_map
;
478 unsigned partial_bytes
;
481 struct intel_batchbuffer
{
482 /** Current batchbuffer being queued up. */
483 struct brw_growing_bo batch
;
484 /** Current statebuffer being queued up. */
485 struct brw_growing_bo state
;
487 /** Last batchbuffer submitted to the hardware. Used for glFinish(). */
488 struct brw_bo
*last_bo
;
491 uint16_t emit
, total
;
496 enum brw_gpu_ring ring
;
497 bool use_shadow_copy
;
498 bool use_batch_first
;
499 bool needs_sol_reset
;
500 bool state_base_address_emitted
;
503 struct brw_reloc_list batch_relocs
;
504 struct brw_reloc_list state_relocs
;
505 unsigned int valid_reloc_flags
;
507 /** The validation list */
508 struct drm_i915_gem_exec_object2
*validation_list
;
509 struct brw_bo
**exec_bos
;
513 /** The amount of aperture space (in bytes) used by all exec_bos */
518 int batch_reloc_count
;
519 int state_reloc_count
;
523 /** Map from batch offset to brw_state_batch data (with DEBUG_BATCH) */
524 struct hash_table
*state_batch_sizes
;
527 #define BRW_MAX_XFB_STREAMS 4
529 struct brw_transform_feedback_counter
{
531 * Index of the first entry of this counter within the primitive count BO.
532 * An entry is considered to be an N-tuple of 64bit values, where N is the
533 * number of vertex streams supported by the platform.
538 * Index one past the last entry of this counter within the primitive
544 * Primitive count values accumulated while this counter was active,
545 * excluding any entries buffered between \c bo_start and \c bo_end, which
546 * haven't been accounted for yet.
548 uint64_t accum
[BRW_MAX_XFB_STREAMS
];
552 brw_reset_transform_feedback_counter(
553 struct brw_transform_feedback_counter
*counter
)
555 counter
->bo_start
= counter
->bo_end
;
556 memset(&counter
->accum
, 0, sizeof(counter
->accum
));
559 struct brw_transform_feedback_object
{
560 struct gl_transform_feedback_object base
;
562 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
563 struct brw_bo
*offset_bo
;
565 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
568 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
569 GLenum primitive_mode
;
572 * The maximum number of vertices that we can write without overflowing
573 * any of the buffers currently being used for transform feedback.
577 struct brw_bo
*prim_count_bo
;
580 * Count of primitives generated during this transform feedback operation.
582 struct brw_transform_feedback_counter counter
;
585 * Count of primitives generated during the previous transform feedback
586 * operation. Used to implement DrawTransformFeedback().
588 struct brw_transform_feedback_counter previous_counter
;
591 * Number of vertices written between last Begin/EndTransformFeedback().
593 * Used to implement DrawTransformFeedback().
595 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
596 bool vertices_written_valid
;
600 * Data shared between each programmable stage in the pipeline (vs, gs, and
603 struct brw_stage_state
605 gl_shader_stage stage
;
606 struct brw_stage_prog_data
*prog_data
;
609 * Optional scratch buffer used to store spilled register values and
610 * variably-indexed GRF arrays.
612 * The contents of this buffer are short-lived so the same memory can be
613 * re-used at will for multiple shader programs (executed by the same fixed
614 * function). However reusing a scratch BO for which shader invocations
615 * are still in flight with a per-thread scratch slot size other than the
616 * original can cause threads with different scratch slot size and FFTID
617 * (which may be executed in parallel depending on the shader stage and
618 * hardware generation) to map to an overlapping region of the scratch
619 * space, which can potentially lead to mutual scratch space corruption.
620 * For that reason if you borrow this scratch buffer you should only be
621 * using the slot size given by the \c per_thread_scratch member below,
622 * unless you're taking additional measures to synchronize thread execution
623 * across slot size changes.
625 struct brw_bo
*scratch_bo
;
628 * Scratch slot size allocated for each thread in the buffer object given
631 uint32_t per_thread_scratch
;
633 /** Offset in the program cache to the program */
634 uint32_t prog_offset
;
636 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
637 uint32_t state_offset
;
639 struct brw_bo
*push_const_bo
; /* NULL if using the batchbuffer */
640 uint32_t push_const_offset
; /* Offset in the push constant BO or batch */
641 int push_const_size
; /* in 256-bit register increments */
643 /* Binding table: pointers to SURFACE_STATE entries. */
644 uint32_t bind_bo_offset
;
645 uint32_t surf_offset
[BRW_MAX_SURFACES
];
647 /** SAMPLER_STATE count and table offset */
648 uint32_t sampler_count
;
649 uint32_t sampler_offset
;
651 struct brw_image_param image_param
[BRW_MAX_IMAGES
];
653 /** Need to re-emit 3DSTATE_CONSTANT_XS? */
654 bool push_constants_dirty
;
657 enum brw_predicate_state
{
658 /* The first two states are used if we can determine whether to draw
659 * without having to look at the values in the query object buffer. This
660 * will happen if there is no conditional render in progress, if the query
661 * object is already completed or if something else has already added
662 * samples to the preliminary result such as via a BLT command.
664 BRW_PREDICATE_STATE_RENDER
,
665 BRW_PREDICATE_STATE_DONT_RENDER
,
666 /* In this case whether to draw or not depends on the result of an
667 * MI_PREDICATE command so the predicate enable bit needs to be checked.
669 BRW_PREDICATE_STATE_USE_BIT
,
670 /* In this case, either MI_PREDICATE doesn't exist or we lack the
671 * necessary kernel features to use it. Stall for the query result.
673 BRW_PREDICATE_STATE_STALL_FOR_QUERY
,
678 struct gen_l3_config
;
680 enum brw_query_kind
{
685 struct brw_perf_query_register_prog
{
690 struct brw_perf_query_info
692 enum brw_query_kind kind
;
695 struct brw_perf_query_counter
*counters
;
700 uint64_t oa_metrics_set_id
;
703 /* For indexing into the accumulator[] ... */
705 int gpu_clock_offset
;
710 /* Register programming for a given query */
711 struct brw_perf_query_register_prog
*flex_regs
;
712 uint32_t n_flex_regs
;
714 struct brw_perf_query_register_prog
*mux_regs
;
717 struct brw_perf_query_register_prog
*b_counter_regs
;
718 uint32_t n_b_counter_regs
;
722 * brw_context is derived from gl_context.
726 struct gl_context ctx
; /**< base class, must be first field */
731 * Send the appropriate state packets to configure depth, stencil, and
732 * HiZ buffers (i965+ only)
734 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
735 struct intel_mipmap_tree
*depth_mt
,
736 uint32_t depth_offset
,
737 uint32_t depthbuffer_format
,
738 uint32_t depth_surface_type
,
739 struct intel_mipmap_tree
*stencil_mt
,
740 bool hiz
, bool separate_stencil
,
741 uint32_t width
, uint32_t height
,
742 uint32_t tile_x
, uint32_t tile_y
);
745 * Emit an MI_REPORT_PERF_COUNT command packet.
747 * This asks the GPU to write a report of the current OA counter values
748 * into @bo at the given offset and containing the given @report_id
749 * which we can cross-reference when parsing the report (gen7+ only).
751 void (*emit_mi_report_perf_count
)(struct brw_context
*brw
,
753 uint32_t offset_in_bytes
,
757 struct brw_bufmgr
*bufmgr
;
761 /** BO for post-sync nonzero writes for gen6 workaround. */
762 struct brw_bo
*workaround_bo
;
763 uint8_t pipe_controls_since_last_cs_stall
;
766 * Set of struct brw_bo * that have been rendered to within this batchbuffer
767 * and would need flushing before being used from another cache domain that
768 * isn't coherent with it (i.e. the sampler).
770 struct hash_table
*render_cache
;
773 * Set of struct brw_bo * that have been used as a depth buffer within this
774 * batchbuffer and would need flushing before being used from another cache
775 * domain that isn't coherent with it (i.e. the sampler).
777 struct set
*depth_cache
;
780 * Number of resets observed in the system at context creation.
782 * This is tracked in the context so that we can determine that another
783 * reset has occurred.
785 uint32_t reset_count
;
787 struct intel_batchbuffer batch
;
792 uint32_t next_offset
;
796 * Set if rendering has occurred to the drawable's front buffer.
798 * This is used in the DRI2 case to detect that glFlush should also copy
799 * the contents of the fake front buffer to the real front buffer.
801 bool front_buffer_dirty
;
803 /** Framerate throttling: @{ */
804 struct brw_bo
*throttle_batch
[2];
806 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
807 * frame of rendering to complete. This gives a very precise cap to the
808 * latency between input and output such that rendering never gets more
809 * than a frame behind the user. (With the caveat that we technically are
810 * not using the SwapBuffers itself as a barrier but the first batch
811 * submitted afterwards, which may be immediately prior to the next
814 bool need_swap_throttle
;
816 /** General throttling, not caught by throttling between SwapBuffers */
817 bool need_flush_throttle
;
827 bool always_flush_batch
;
828 bool always_flush_cache
;
829 bool disable_throttling
;
831 bool dual_color_blend_by_location
;
833 driOptionCache optionCache
;
836 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
838 GLenum reduced_primitive
;
841 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
842 * variable is set, this is the flag indicating to do expensive work that
843 * might lead to a perf_debug() call.
847 uint64_t max_gtt_map_object_size
;
850 bool has_separate_stencil
;
853 /** Derived stencil states. */
854 bool stencil_enabled
;
855 bool stencil_two_sided
;
856 bool stencil_write_enabled
;
857 /** Derived polygon state. */
858 bool polygon_front_bit
; /**< 0=GL_CCW, 1=GL_CW */
860 struct isl_device isl_dev
;
862 struct blorp_context blorp
;
866 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
869 enum brw_pipeline last_pipeline
;
871 struct brw_cache cache
;
873 /* Whether a meta-operation is in progress. */
874 bool meta_in_progress
;
876 /* Whether the last depth/stencil packets were both NULL. */
877 bool no_depth_or_stencil
;
879 /* The last PMA stall bits programmed. */
880 uint32_t pma_stall_bits
;
884 /** The value of gl_BaseVertex for the current _mesa_prim. */
887 /** The value of gl_BaseInstance for the current _mesa_prim. */
892 * Buffer and offset used for GL_ARB_shader_draw_parameters
893 * (for now, only gl_BaseVertex).
895 struct brw_bo
*draw_params_bo
;
896 uint32_t draw_params_offset
;
899 * The value of gl_DrawID for the current _mesa_prim. This always comes
900 * in from it's own vertex buffer since it's not part of the indirect
904 struct brw_bo
*draw_id_bo
;
905 uint32_t draw_id_offset
;
908 * Pointer to the the buffer storing the indirect draw parameters. It
909 * currently only stores the number of requested draw calls but more
910 * parameters could potentially be added.
912 struct brw_bo
*draw_params_count_bo
;
913 uint32_t draw_params_count_offset
;
918 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
919 * an indirect call, and num_work_groups_offset is valid. Otherwise,
920 * num_work_groups is set based on glDispatchCompute.
922 struct brw_bo
*num_work_groups_bo
;
923 GLintptr num_work_groups_offset
;
924 const GLuint
*num_work_groups
;
928 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
929 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
931 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
935 /* Summary of size and varying of active arrays, so we can check
936 * for changes to this state:
938 bool index_bounds_valid
;
939 unsigned int min_index
, max_index
;
941 /* Offset from start of vertex buffer so we can avoid redefining
942 * the same VB packed over and over again.
944 unsigned int start_vertex_bias
;
947 * Certain vertex attribute formats aren't natively handled by the
948 * hardware and require special VS code to fix up their values.
950 * These bitfields indicate which workarounds are needed.
952 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
957 * Index buffer for this draw_prims call.
959 * Updates are signaled by BRW_NEW_INDICES.
961 const struct _mesa_index_buffer
*ib
;
963 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
968 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
969 * avoid re-uploading the IB packet over and over if we're actually
970 * referencing the same index buffer.
972 unsigned int start_vertex_offset
;
975 /* Active vertex program:
977 struct gl_program
*programs
[MESA_SHADER_STAGES
];
980 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
981 * that we don't have to reemit that state every time we change FBOs.
983 unsigned int num_samples
;
985 /* BRW_NEW_URB_ALLOCATIONS:
988 GLuint vsize
; /* vertex size plus header in urb registers */
989 GLuint gsize
; /* GS output size in urb registers */
990 GLuint hsize
; /* Tessellation control output size in urb registers */
991 GLuint dsize
; /* Tessellation evaluation output size in urb registers */
992 GLuint csize
; /* constant buffer size in urb registers */
993 GLuint sfsize
; /* setup data size in urb registers */
997 GLuint nr_vs_entries
;
998 GLuint nr_hs_entries
;
999 GLuint nr_ds_entries
;
1000 GLuint nr_gs_entries
;
1001 GLuint nr_clip_entries
;
1002 GLuint nr_sf_entries
;
1003 GLuint nr_cs_entries
;
1013 * URB size in the current configuration. The units this is expressed
1014 * in are somewhat inconsistent, see gen_device_info::urb::size.
1016 * FINISHME: Represent the URB size consistently in KB on all platforms.
1020 /* True if the most recently sent _3DSTATE_URB message allocated
1021 * URB space for the GS.
1025 /* True if the most recently sent _3DSTATE_URB message allocated
1026 * URB space for the HS and DS.
1032 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1034 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1035 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1043 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1044 * for upload to the CURBE.
1046 struct brw_bo
*curbe_bo
;
1047 /** Offset within curbe_bo of space for current curbe entry */
1048 GLuint curbe_offset
;
1052 * Layout of vertex data exiting the geometry portion of the pipleine.
1053 * This comes from the last enabled shader stage (GS, DS, or VS).
1055 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1057 struct brw_vue_map vue_map_geom_out
;
1060 struct brw_stage_state base
;
1064 struct brw_stage_state base
;
1068 struct brw_stage_state base
;
1072 struct brw_stage_state base
;
1075 * True if the 3DSTATE_GS command most recently emitted to the 3D
1076 * pipeline enabled the GS; false otherwise.
1082 struct brw_ff_gs_prog_data
*prog_data
;
1085 /** Offset in the program cache to the CLIP program pre-gen6 */
1086 uint32_t prog_offset
;
1087 uint32_t state_offset
;
1089 uint32_t bind_bo_offset
;
1091 * Surface offsets for the binding table. We only need surfaces to
1092 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1093 * need in this case.
1095 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1099 struct brw_clip_prog_data
*prog_data
;
1101 /** Offset in the program cache to the CLIP program pre-gen6 */
1102 uint32_t prog_offset
;
1104 /* Offset in the batch to the CLIP state on pre-gen6. */
1105 uint32_t state_offset
;
1107 /* As of gen6, this is the offset in the batch to the CLIP VP,
1113 * The number of viewports to use. If gl_ViewportIndex is written,
1114 * we can have up to ctx->Const.MaxViewports viewports. If not,
1115 * the viewport index is always 0, so we can only emit one.
1117 uint8_t viewport_count
;
1122 struct brw_sf_prog_data
*prog_data
;
1124 /** Offset in the program cache to the CLIP program pre-gen6 */
1125 uint32_t prog_offset
;
1126 uint32_t state_offset
;
1131 struct brw_stage_state base
;
1134 * Buffer object used in place of multisampled null render targets on
1135 * Gen6. See brw_emit_null_surface_state().
1137 struct brw_bo
*multisampled_null_render_target_bo
;
1143 struct brw_stage_state base
;
1147 uint32_t state_offset
;
1148 uint32_t blend_state_offset
;
1149 uint32_t depth_stencil_state_offset
;
1154 struct brw_query_object
*obj
;
1159 enum brw_predicate_state state
;
1164 /* Variables referenced in the XML meta data for OA performance
1165 * counters, e.g in the normalization equations.
1167 * All uint64_t for consistent operand types in generated code
1170 uint64_t timestamp_frequency
; /** $GpuTimestampFrequency */
1171 uint64_t n_eus
; /** $EuCoresTotalCount */
1172 uint64_t n_eu_slices
; /** $EuSlicesTotalCount */
1173 uint64_t n_eu_sub_slices
; /** $EuSubslicesTotalCount */
1174 uint64_t eu_threads_count
; /** $EuThreadsCount */
1175 uint64_t slice_mask
; /** $SliceMask */
1176 uint64_t subslice_mask
; /** $SubsliceMask */
1177 uint64_t gt_min_freq
; /** $GpuMinFrequency */
1178 uint64_t gt_max_freq
; /** $GpuMaxFrequency */
1179 uint64_t revision
; /** $SkuRevisionId */
1182 /* OA metric sets, indexed by GUID, as know by Mesa at build time,
1183 * to cross-reference with the GUIDs of configs advertised by the
1186 struct hash_table
*oa_metrics_table
;
1188 struct brw_perf_query_info
*queries
;
1191 /* The i915 perf stream we open to setup + enable the OA counters */
1194 /* An i915 perf stream fd gives exclusive access to the OA unit that will
1195 * report counter snapshots for a specific counter set/profile in a
1196 * specific layout/format so we can only start OA queries that are
1197 * compatible with the currently open fd...
1199 int current_oa_metrics_set_id
;
1200 int current_oa_format
;
1202 /* List of buffers containing OA reports */
1203 struct exec_list sample_buffers
;
1205 /* Cached list of empty sample buffers */
1206 struct exec_list free_sample_buffers
;
1208 int n_active_oa_queries
;
1209 int n_active_pipeline_stats_queries
;
1211 /* The number of queries depending on running OA counters which
1212 * extends beyond brw_end_perf_query() since we need to wait until
1213 * the last MI_RPC command has parsed by the GPU.
1215 * Accurate accounting is important here as emitting an
1216 * MI_REPORT_PERF_COUNT command while the OA unit is disabled will
1217 * effectively hang the gpu.
1221 /* To help catch an spurious problem with the hardware or perf
1222 * forwarding samples, we emit each MI_REPORT_PERF_COUNT command
1223 * with a unique ID that we can explicitly check for...
1225 int next_query_start_report_id
;
1228 * An array of queries whose results haven't yet been assembled
1229 * based on the data in buffer objects.
1231 * These may be active, or have already ended. However, the
1232 * results have not been requested.
1234 struct brw_perf_query_object
**unaccumulated
;
1235 int unaccumulated_elements
;
1236 int unaccumulated_array_size
;
1238 /* The total number of query objects so we can relinquish
1239 * our exclusive access to perf if the application deletes
1240 * all of its objects. (NB: We only disable perf while
1241 * there are no active queries)
1243 int n_query_instances
;
1246 int num_atoms
[BRW_NUM_PIPELINES
];
1247 const struct brw_tracked_state render_atoms
[76];
1248 const struct brw_tracked_state compute_atoms
[11];
1250 const enum isl_format
*mesa_to_isl_render_format
;
1251 const bool *mesa_format_supports_render
;
1253 /* PrimitiveRestart */
1256 bool enable_cut_index
;
1259 /** Computed depth/stencil/hiz state from the current attached
1260 * renderbuffers, valid only during the drawing state upload loop after
1261 * brw_workaround_depthstencil_alignment().
1264 /* Inter-tile (page-aligned) byte offsets. */
1265 uint32_t depth_offset
;
1266 /* Intra-tile x,y offsets for drawing to combined depth-stencil. Only
1269 uint32_t tile_x
, tile_y
;
1272 uint32_t num_instances
;
1277 const struct gen_l3_config
*config
;
1284 enum shader_time_shader_type
*types
;
1285 struct shader_times
*cumulative
;
1291 struct brw_fast_clear_state
*fast_clear_state
;
1293 /* Array of flags telling if auxiliary buffer is disabled for corresponding
1294 * renderbuffer. If draw_aux_buffer_disabled[i] is set then use of
1295 * auxiliary buffer for gl_framebuffer::_ColorDrawBuffers[i] is
1297 * This is needed in case the same underlying buffer is also configured
1298 * to be sampled but with a format that the sampling engine can't treat
1299 * compressed or fast cleared.
1301 bool draw_aux_buffer_disabled
[MAX_DRAW_BUFFERS
];
1303 __DRIcontext
*driContext
;
1304 struct intel_screen
*screen
;
1308 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1310 /*======================================================================
1313 extern const char *const brw_vendor_string
;
1316 brw_get_renderer_string(const struct intel_screen
*screen
);
1319 DRI_CONF_BO_REUSE_DISABLED
,
1320 DRI_CONF_BO_REUSE_ALL
1323 void intel_update_renderbuffers(__DRIcontext
*context
,
1324 __DRIdrawable
*drawable
);
1325 void intel_prepare_render(struct brw_context
*brw
);
1327 void brw_predraw_resolve_inputs(struct brw_context
*brw
, bool rendering
);
1329 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1330 __DRIdrawable
*drawable
);
1332 GLboolean
brwCreateContext(gl_api api
,
1333 const struct gl_config
*mesaVis
,
1334 __DRIcontext
*driContextPriv
,
1335 const struct __DriverContextConfig
*ctx_config
,
1337 void *sharedContextPrivate
);
1339 /*======================================================================
1343 brw_meta_resolve_color(struct brw_context
*brw
,
1344 struct intel_mipmap_tree
*mt
);
1346 /*======================================================================
1349 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1350 GLbitfield clear_mask
);
1352 /* brw_object_purgeable.c */
1353 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1355 /*======================================================================
1358 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1359 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1360 void brw_emit_query_begin(struct brw_context
*brw
);
1361 void brw_emit_query_end(struct brw_context
*brw
);
1362 void brw_query_counter(struct gl_context
*ctx
, struct gl_query_object
*q
);
1363 bool brw_is_query_pipelined(struct brw_query_object
*query
);
1364 uint64_t brw_timebase_scale(struct brw_context
*brw
, uint64_t gpu_timestamp
);
1365 uint64_t brw_raw_timestamp_delta(struct brw_context
*brw
,
1366 uint64_t time0
, uint64_t time1
);
1368 /** gen6_queryobj.c */
1369 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1370 void brw_write_timestamp(struct brw_context
*brw
, struct brw_bo
*bo
, int idx
);
1371 void brw_write_depth_count(struct brw_context
*brw
, struct brw_bo
*bo
, int idx
);
1373 /** hsw_queryobj.c */
1374 void hsw_overflow_result_to_gpr0(struct brw_context
*brw
,
1375 struct brw_query_object
*query
,
1377 void hsw_init_queryobj_functions(struct dd_function_table
*functions
);
1379 /** brw_conditional_render.c */
1380 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1381 bool brw_check_conditional_render(struct brw_context
*brw
);
1383 /** intel_batchbuffer.c */
1384 void brw_load_register_mem(struct brw_context
*brw
,
1388 void brw_load_register_mem64(struct brw_context
*brw
,
1392 void brw_store_register_mem32(struct brw_context
*brw
,
1393 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
);
1394 void brw_store_register_mem64(struct brw_context
*brw
,
1395 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
);
1396 void brw_load_register_imm32(struct brw_context
*brw
,
1397 uint32_t reg
, uint32_t imm
);
1398 void brw_load_register_imm64(struct brw_context
*brw
,
1399 uint32_t reg
, uint64_t imm
);
1400 void brw_load_register_reg(struct brw_context
*brw
, uint32_t src
,
1402 void brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
,
1404 void brw_store_data_imm32(struct brw_context
*brw
, struct brw_bo
*bo
,
1405 uint32_t offset
, uint32_t imm
);
1406 void brw_store_data_imm64(struct brw_context
*brw
, struct brw_bo
*bo
,
1407 uint32_t offset
, uint64_t imm
);
1409 /*======================================================================
1410 * intel_tex_validate.c
1412 void brw_validate_textures( struct brw_context
*brw
);
1415 /*======================================================================
1419 key_debug(struct brw_context
*brw
, const char *name
, int a
, int b
)
1422 perf_debug(" %s %d->%d\n", name
, a
, b
);
1428 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1430 void brw_get_scratch_bo(struct brw_context
*brw
,
1431 struct brw_bo
**scratch_bo
, int size
);
1432 void brw_alloc_stage_scratch(struct brw_context
*brw
,
1433 struct brw_stage_state
*stage_state
,
1434 unsigned per_thread_size
);
1435 void brw_init_shader_time(struct brw_context
*brw
);
1436 int brw_get_shader_time_index(struct brw_context
*brw
,
1437 struct gl_program
*prog
,
1438 enum shader_time_shader_type type
,
1440 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1441 void brw_destroy_shader_time(struct brw_context
*brw
);
1445 void brw_calculate_urb_fence(struct brw_context
*brw
, unsigned csize
,
1446 unsigned vsize
, unsigned sfsize
);
1447 void brw_upload_urb_fence(struct brw_context
*brw
);
1451 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1454 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1456 /* brw_draw_upload.c */
1457 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1458 const struct gl_vertex_array
*glarray
);
1460 static inline unsigned
1461 brw_get_index_type(unsigned index_size
)
1463 /* The hw needs 0x00, 0x01, and 0x02 for ubyte, ushort, and uint,
1466 return index_size
>> 1;
1469 void brw_prepare_vertices(struct brw_context
*brw
);
1471 /* brw_wm_surface_state.c */
1472 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1474 uint32_t *surf_offset
);
1476 brw_update_sol_surface(struct brw_context
*brw
,
1477 struct gl_buffer_object
*buffer_obj
,
1478 uint32_t *out_offset
, unsigned num_vector_components
,
1479 unsigned stride_dwords
, unsigned offset_dwords
);
1480 void brw_upload_ubo_surfaces(struct brw_context
*brw
, struct gl_program
*prog
,
1481 struct brw_stage_state
*stage_state
,
1482 struct brw_stage_prog_data
*prog_data
);
1483 void brw_upload_image_surfaces(struct brw_context
*brw
,
1484 const struct gl_program
*prog
,
1485 struct brw_stage_state
*stage_state
,
1486 struct brw_stage_prog_data
*prog_data
);
1488 /* brw_surface_formats.c */
1489 void intel_screen_init_surface_formats(struct intel_screen
*screen
);
1490 void brw_init_surface_formats(struct brw_context
*brw
);
1491 bool brw_render_target_supported(struct brw_context
*brw
,
1492 struct gl_renderbuffer
*rb
);
1493 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1495 /* brw_performance_query.c */
1496 void brw_init_performance_queries(struct brw_context
*brw
);
1498 /* intel_extensions.c */
1499 extern void intelInitExtensions(struct gl_context
*ctx
);
1502 extern int intel_translate_shadow_compare_func(GLenum func
);
1503 extern int intel_translate_compare_func(GLenum func
);
1504 extern int intel_translate_stencil_op(GLenum op
);
1505 extern int intel_translate_logic_op(GLenum opcode
);
1508 void brw_init_syncobj_functions(struct dd_function_table
*functions
);
1511 struct gl_transform_feedback_object
*
1512 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1514 brw_delete_transform_feedback(struct gl_context
*ctx
,
1515 struct gl_transform_feedback_object
*obj
);
1517 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1518 struct gl_transform_feedback_object
*obj
);
1520 brw_end_transform_feedback(struct gl_context
*ctx
,
1521 struct gl_transform_feedback_object
*obj
);
1523 brw_pause_transform_feedback(struct gl_context
*ctx
,
1524 struct gl_transform_feedback_object
*obj
);
1526 brw_resume_transform_feedback(struct gl_context
*ctx
,
1527 struct gl_transform_feedback_object
*obj
);
1529 brw_save_primitives_written_counters(struct brw_context
*brw
,
1530 struct brw_transform_feedback_object
*obj
);
1532 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1533 struct gl_transform_feedback_object
*obj
,
1536 /* gen7_sol_state.c */
1538 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1539 struct gl_transform_feedback_object
*obj
);
1541 gen7_end_transform_feedback(struct gl_context
*ctx
,
1542 struct gl_transform_feedback_object
*obj
);
1544 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1545 struct gl_transform_feedback_object
*obj
);
1547 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1548 struct gl_transform_feedback_object
*obj
);
1552 hsw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1553 struct gl_transform_feedback_object
*obj
);
1555 hsw_end_transform_feedback(struct gl_context
*ctx
,
1556 struct gl_transform_feedback_object
*obj
);
1558 hsw_pause_transform_feedback(struct gl_context
*ctx
,
1559 struct gl_transform_feedback_object
*obj
);
1561 hsw_resume_transform_feedback(struct gl_context
*ctx
,
1562 struct gl_transform_feedback_object
*obj
);
1564 /* brw_blorp_blit.cpp */
1566 brw_blorp_framebuffer(struct brw_context
*brw
,
1567 struct gl_framebuffer
*readFb
,
1568 struct gl_framebuffer
*drawFb
,
1569 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1570 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1571 GLbitfield mask
, GLenum filter
);
1574 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1575 struct gl_renderbuffer
*src_rb
,
1576 struct gl_texture_image
*dst_image
,
1578 int srcX0
, int srcY0
,
1579 int dstX0
, int dstY0
,
1580 int width
, int height
);
1583 gen6_get_sample_position(struct gl_context
*ctx
,
1584 struct gl_framebuffer
*fb
,
1588 gen6_set_sample_maps(struct gl_context
*ctx
);
1590 /* gen8_multisample_state.c */
1591 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1595 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1596 unsigned hs_size
, unsigned ds_size
,
1597 unsigned gs_size
, unsigned fs_size
);
1600 gen6_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1601 bool gs_present
, unsigned gs_size
);
1603 gen7_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1604 bool gs_present
, bool tess_present
);
1608 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1610 brw_check_for_reset(struct brw_context
*brw
);
1614 brw_init_compute_functions(struct dd_function_table
*functions
);
1616 /* brw_program_binary.c */
1618 brw_program_binary_init(unsigned device_id
);
1620 brw_get_program_binary_driver_sha1(struct gl_context
*ctx
, uint8_t *sha1
);
1622 brw_deserialize_program_binary(struct gl_context
*ctx
,
1623 struct gl_shader_program
*shProg
,
1624 struct gl_program
*prog
);
1626 brw_program_serialize_nir(struct gl_context
*ctx
, struct gl_program
*prog
);
1628 brw_program_deserialize_nir(struct gl_context
*ctx
, struct gl_program
*prog
,
1629 gl_shader_stage stage
);
1631 /*======================================================================
1632 * Inline conversion functions. These are better-typed than the
1633 * macros used previously:
1635 static inline struct brw_context
*
1636 brw_context( struct gl_context
*ctx
)
1638 return (struct brw_context
*)ctx
;
1641 static inline struct brw_program
*
1642 brw_program(struct gl_program
*p
)
1644 return (struct brw_program
*) p
;
1647 static inline const struct brw_program
*
1648 brw_program_const(const struct gl_program
*p
)
1650 return (const struct brw_program
*) p
;
1654 brw_depth_writes_enabled(const struct brw_context
*brw
)
1656 const struct gl_context
*ctx
= &brw
->ctx
;
1658 /* We consider depth writes disabled if the depth function is GL_EQUAL,
1659 * because it would just overwrite the existing depth value with itself.
1661 * These bonus depth writes not only use bandwidth, but they also can
1662 * prevent early depth processing. For example, if the pixel shader
1663 * discards, the hardware must invoke the to determine whether or not
1664 * to do the depth write. If writes are disabled, we may still be able
1665 * to do the depth test before the shader, and skip the shader execution.
1667 * The Broadwell 3DSTATE_WM_DEPTH_STENCIL documentation also contains
1668 * a programming note saying to disable depth writes for EQUAL.
1670 return ctx
->Depth
.Test
&& ctx
->Depth
.Mask
&& ctx
->Depth
.Func
!= GL_EQUAL
;
1674 brw_emit_depthbuffer(struct brw_context
*brw
);
1677 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1678 struct intel_mipmap_tree
*depth_mt
,
1679 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1680 uint32_t depth_surface_type
,
1681 struct intel_mipmap_tree
*stencil_mt
,
1682 bool hiz
, bool separate_stencil
,
1683 uint32_t width
, uint32_t height
,
1684 uint32_t tile_x
, uint32_t tile_y
);
1687 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1688 struct intel_mipmap_tree
*depth_mt
,
1689 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1690 uint32_t depth_surface_type
,
1691 struct intel_mipmap_tree
*stencil_mt
,
1692 bool hiz
, bool separate_stencil
,
1693 uint32_t width
, uint32_t height
,
1694 uint32_t tile_x
, uint32_t tile_y
);
1697 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1698 struct intel_mipmap_tree
*depth_mt
,
1699 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1700 uint32_t depth_surface_type
,
1701 struct intel_mipmap_tree
*stencil_mt
,
1702 bool hiz
, bool separate_stencil
,
1703 uint32_t width
, uint32_t height
,
1704 uint32_t tile_x
, uint32_t tile_y
);
1706 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1707 struct intel_mipmap_tree
*depth_mt
,
1708 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1709 uint32_t depth_surface_type
,
1710 struct intel_mipmap_tree
*stencil_mt
,
1711 bool hiz
, bool separate_stencil
,
1712 uint32_t width
, uint32_t height
,
1713 uint32_t tile_x
, uint32_t tile_y
);
1715 uint32_t get_hw_prim_for_gl_prim(int mode
);
1718 gen6_upload_push_constants(struct brw_context
*brw
,
1719 const struct gl_program
*prog
,
1720 const struct brw_stage_prog_data
*prog_data
,
1721 struct brw_stage_state
*stage_state
);
1724 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
1725 const struct intel_mipmap_tree
*mt
);
1727 /* brw_queryformat.c */
1728 void brw_query_internal_format(struct gl_context
*ctx
, GLenum target
,
1729 GLenum internalFormat
, GLenum pname
,