2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
37 #include "main/macros.h"
38 #include "main/mtypes.h"
39 #include "brw_structs.h"
40 #include "brw_compiler.h"
41 #include "intel_aub.h"
44 #include "blorp/blorp.h"
48 /* Evil hack for using libdrm in a c++ compiler. */
52 #include <intel_bufmgr.h>
61 #include "intel_debug.h"
62 #include "intel_screen.h"
63 #include "intel_tex_obj.h"
64 #include "intel_resolve_map.h"
68 * URB - uniform resource buffer. A mid-sized buffer which is
69 * partitioned between the fixed function units and used for passing
70 * values (vertices, primitives, constants) between them.
72 * CURBE - constant URB entry. An urb region (entry) used to hold
73 * constant values which the fixed function units can be instructed to
74 * preload into the GRF when spawning a thread.
76 * VUE - vertex URB entry. An urb entry holding a vertex and usually
77 * a vertex header. The header contains control information and
78 * things like primitive type, Begin/end flags and clip codes.
80 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
81 * unit holding rasterization and interpolation parameters.
83 * GRF - general register file. One of several register files
84 * addressable by programmed threads. The inputs (r0, payload, curbe,
85 * urb) of the thread are preloaded to this area before the thread is
86 * spawned. The registers are individually 8 dwords wide and suitable
87 * for general usage. Registers holding thread input values are not
88 * special and may be overwritten.
90 * MRF - message register file. Threads communicate (and terminate)
91 * by sending messages. Message parameters are placed in contiguous
92 * MRF registers. All program output is via these messages. URB
93 * entries are populated by sending a message to the shared URB
94 * function containing the new data, together with a control word,
95 * often an unmodified copy of R0.
97 * R0 - GRF register 0. Typically holds control information used when
98 * sending messages to other threads.
100 * EU or GEN4 EU: The name of the programmable subsystem of the
101 * i965 hardware. Threads are executed by the EU, the registers
102 * described above are part of the EU architecture.
104 * Fixed function units:
106 * CS - Command streamer. Notional first unit, little software
107 * interaction. Holds the URB entries used for constant data, ie the
110 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
111 * this unit is responsible for pulling vertices out of vertex buffers
112 * in vram and injecting them into the processing pipe as VUEs. If
113 * enabled, it first passes them to a VS thread which is a good place
114 * for the driver to implement any active vertex shader.
116 * HS - Hull Shader (Tessellation Control Shader)
118 * TE - Tessellation Engine (Tessellation Primitive Generation)
120 * DS - Domain Shader (Tessellation Evaluation Shader)
122 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
123 * enabled, incoming strips etc are passed to GS threads in individual
124 * line/triangle/point units. The GS thread may perform arbitary
125 * computation and emit whatever primtives with whatever vertices it
126 * chooses. This makes GS an excellent place to implement GL's
127 * unfilled polygon modes, though of course it is capable of much
128 * more. Additionally, GS is used to translate away primitives not
129 * handled by latter units, including Quads and Lineloops.
131 * CS - Clipper. Mesa's clipping algorithms are imported to run on
132 * this unit. The fixed function part performs cliptesting against
133 * the 6 fixed clipplanes and makes descisions on whether or not the
134 * incoming primitive needs to be passed to a thread for clipping.
135 * User clip planes are handled via cooperation with the VS thread.
137 * SF - Strips Fans or Setup: Triangles are prepared for
138 * rasterization. Interpolation coefficients are calculated.
139 * Flatshading and two-side lighting usually performed here.
141 * WM - Windower. Interpolation of vertex attributes performed here.
142 * Fragment shader implemented here. SIMD aspects of EU taken full
143 * advantage of, as pixels are processed in blocks of 16.
145 * CC - Color Calculator. No EU threads associated with this unit.
146 * Handles blending and (presumably) depth and stencil testing.
151 struct brw_vs_prog_key
;
152 struct brw_vue_prog_key
;
153 struct brw_wm_prog_key
;
154 struct brw_wm_prog_data
;
155 struct brw_cs_prog_key
;
156 struct brw_cs_prog_data
;
160 BRW_COMPUTE_PIPELINE
,
167 BRW_CACHE_BLORP_PROG
,
170 BRW_CACHE_FF_GS_PROG
,
181 /* brw_cache_ids must come first - see brw_state_cache.c */
182 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
183 BRW_STATE_FRAGMENT_PROGRAM
,
184 BRW_STATE_GEOMETRY_PROGRAM
,
185 BRW_STATE_TESS_PROGRAMS
,
186 BRW_STATE_VERTEX_PROGRAM
,
187 BRW_STATE_CURBE_OFFSETS
,
188 BRW_STATE_REDUCED_PRIMITIVE
,
189 BRW_STATE_PATCH_PRIMITIVE
,
194 BRW_STATE_BINDING_TABLE_POINTERS
,
197 BRW_STATE_DEFAULT_TESS_LEVELS
,
199 BRW_STATE_INDEX_BUFFER
,
200 BRW_STATE_VS_CONSTBUF
,
201 BRW_STATE_TCS_CONSTBUF
,
202 BRW_STATE_TES_CONSTBUF
,
203 BRW_STATE_GS_CONSTBUF
,
204 BRW_STATE_PROGRAM_CACHE
,
205 BRW_STATE_STATE_BASE_ADDRESS
,
206 BRW_STATE_VUE_MAP_GEOM_OUT
,
207 BRW_STATE_TRANSFORM_FEEDBACK
,
208 BRW_STATE_RASTERIZER_DISCARD
,
210 BRW_STATE_UNIFORM_BUFFER
,
211 BRW_STATE_ATOMIC_BUFFER
,
212 BRW_STATE_IMAGE_UNITS
,
213 BRW_STATE_META_IN_PROGRESS
,
214 BRW_STATE_INTERPOLATION_MAP
,
215 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
216 BRW_STATE_NUM_SAMPLES
,
217 BRW_STATE_TEXTURE_BUFFER
,
218 BRW_STATE_GEN4_UNIT_STATE
,
222 BRW_STATE_SAMPLER_STATE_TABLE
,
223 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
224 BRW_STATE_COMPUTE_PROGRAM
,
225 BRW_STATE_CS_WORK_GROUPS
,
229 BRW_STATE_VIEWPORT_COUNT
,
234 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
236 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
237 * When the currently bound shader program differs from the previous draw
238 * call, these will be flagged. They cover brw->{stage}_program and
239 * ctx->{Stage}Program->_Current.
241 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
242 * driver perspective. Even if the same shader is bound at the API level,
243 * we may need to switch between multiple versions of that shader to handle
244 * changes in non-orthagonal state.
246 * Additionally, multiple shader programs may have identical vertex shaders
247 * (for example), or compile down to the same code in the backend. We combine
248 * those into a single program cache entry.
250 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
251 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
253 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
254 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
255 * use the normal state upload paths), but the cache is still used. To avoid
256 * polluting the brw_state_cache code with special cases, we retain the dirty
257 * bit for now. It should eventually be removed.
259 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_PROG)
260 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
261 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
262 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
263 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
264 #define BRW_NEW_TCS_PROG_DATA (1ull << BRW_CACHE_TCS_PROG)
265 #define BRW_NEW_TES_PROG_DATA (1ull << BRW_CACHE_TES_PROG)
266 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
267 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
268 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
269 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
270 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
271 #define BRW_NEW_TESS_PROGRAMS (1ull << BRW_STATE_TESS_PROGRAMS)
272 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
273 #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
274 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
275 #define BRW_NEW_PATCH_PRIMITIVE (1ull << BRW_STATE_PATCH_PRIMITIVE)
276 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
277 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
278 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
279 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
280 #define BRW_NEW_BINDING_TABLE_POINTERS (1ull << BRW_STATE_BINDING_TABLE_POINTERS)
281 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
282 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
283 #define BRW_NEW_DEFAULT_TESS_LEVELS (1ull << BRW_STATE_DEFAULT_TESS_LEVELS)
285 * Used for any batch entry with a relocated pointer that will be used
286 * by any 3D rendering.
288 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
289 /** \see brw.state.depth_region */
290 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
291 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
292 #define BRW_NEW_TCS_CONSTBUF (1ull << BRW_STATE_TCS_CONSTBUF)
293 #define BRW_NEW_TES_CONSTBUF (1ull << BRW_STATE_TES_CONSTBUF)
294 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
295 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
296 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
297 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
298 #define BRW_NEW_VIEWPORT_COUNT (1ull << BRW_STATE_VIEWPORT_COUNT)
299 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
300 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
301 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
302 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
303 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
304 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
305 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
306 #define BRW_NEW_INTERPOLATION_MAP (1ull << BRW_STATE_INTERPOLATION_MAP)
307 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
308 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
309 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
310 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
311 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
312 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
313 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
314 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
315 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
316 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
317 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
318 #define BRW_NEW_URB_SIZE (1ull << BRW_STATE_URB_SIZE)
319 #define BRW_NEW_CC_STATE (1ull << BRW_STATE_CC_STATE)
320 #define BRW_NEW_BLORP (1ull << BRW_STATE_BLORP)
322 struct brw_state_flags
{
323 /** State update flags signalled by mesa internals */
326 * State update flags signalled as the result of brw_tracked_state updates
331 /** Subclass of Mesa vertex program */
332 struct brw_vertex_program
{
333 struct gl_vertex_program program
;
338 /** Subclass of Mesa tessellation control program */
339 struct brw_tess_ctrl_program
{
340 struct gl_program program
;
341 unsigned id
; /**< serial no. to identify tess ctrl progs, never re-used */
345 /** Subclass of Mesa tessellation evaluation program */
346 struct brw_tess_eval_program
{
347 struct gl_program program
;
348 unsigned id
; /**< serial no. to identify tess eval progs, never re-used */
352 /** Subclass of Mesa geometry program */
353 struct brw_geometry_program
{
354 struct gl_program program
;
355 unsigned id
; /**< serial no. to identify geom progs, never re-used */
359 /** Subclass of Mesa fragment program */
360 struct brw_fragment_program
{
361 struct gl_fragment_program program
;
362 GLuint id
; /**< serial no. to identify frag progs, never re-used */
366 /** Subclass of Mesa compute program */
367 struct brw_compute_program
{
368 struct gl_compute_program program
;
369 unsigned id
; /**< serial no. to identify compute progs, never re-used */
374 struct gl_linked_shader base
;
380 * Bitmask indicating which fragment shader inputs represent varyings (and
381 * hence have to be delivered to the fragment shader by the SF/SBE stage).
383 #define BRW_FS_VARYING_INPUT_MASK \
384 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
385 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
389 * Mapping of VUE map slots to interpolation modes.
391 struct interpolation_mode_map
{
392 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
395 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
397 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
398 if (map
->mode
[i
] == INTERP_MODE_FLAT
)
404 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
406 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
407 if (map
->mode
[i
] == INTERP_MODE_NOPERSPECTIVE
)
414 struct brw_sf_prog_data
{
415 GLuint urb_read_length
;
418 /* Each vertex may have upto 12 attributes, 4 components each,
419 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
422 * Actually we use 4 for each, so call it 12 rows.
424 GLuint urb_entry_size
;
429 * We always program SF to start reading at an offset of 1 (2 varying slots)
430 * from the start of the vertex URB entry. This causes it to skip:
431 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
432 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
434 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
437 struct brw_clip_prog_data
{
438 GLuint curb_read_length
; /* user planes? */
440 GLuint urb_read_length
;
444 struct brw_ff_gs_prog_data
{
445 GLuint urb_read_length
;
449 * Gen6 transform feedback: Amount by which the streaming vertex buffer
450 * indices should be incremented each time the GS is invoked.
452 unsigned svbi_postincrement_value
;
455 /** Number of texture sampler units */
456 #define BRW_MAX_TEX_UNIT 32
458 /** Max number of render targets in a shader */
459 #define BRW_MAX_DRAW_BUFFERS 8
461 /** Max number of UBOs in a shader */
462 #define BRW_MAX_UBO 14
464 /** Max number of SSBOs in a shader */
465 #define BRW_MAX_SSBO 12
467 /** Max number of atomic counter buffer objects in a shader */
468 #define BRW_MAX_ABO 16
470 /** Max number of image uniforms in a shader */
471 #define BRW_MAX_IMAGES 32
474 * Max number of binding table entries used for stream output.
476 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
477 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
479 * On Gen6, the size of transform feedback data is limited not by the number
480 * of components but by the number of binding table entries we set aside. We
481 * use one binding table entry for a float, one entry for a vector, and one
482 * entry per matrix column. Since the only way we can communicate our
483 * transform feedback capabilities to the client is via
484 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
485 * worst case, in which all the varyings are floats, so we use up one binding
486 * table entry per component. Therefore we need to set aside at least 64
487 * binding table entries for use by transform feedback.
489 * Note: since we don't currently pack varyings, it is currently impossible
490 * for the client to actually use up all of these binding table entries--if
491 * all of their varyings were floats, they would run out of varying slots and
492 * fail to link. But that's a bug, so it seems prudent to go ahead and
493 * allocate the number of binding table entries we will need once the bug is
496 #define BRW_MAX_SOL_BINDINGS 64
498 /** Maximum number of actual buffers used for stream output */
499 #define BRW_MAX_SOL_BUFFERS 4
501 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
502 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
507 2 + /* shader time, pull constants */ \
508 1 /* cs num work groups */)
510 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
513 * Stride in bytes between shader_time entries.
515 * We separate entries by a cacheline to reduce traffic between EUs writing to
518 #define SHADER_TIME_STRIDE 64
520 struct brw_cache_item
{
522 * Effectively part of the key, cache_id identifies what kind of state
523 * buffer is involved, and also which dirty flag should set.
525 enum brw_cache_id cache_id
;
526 /** 32-bit hash of the key data */
528 GLuint key_size
; /* for variable-sized keys */
535 struct brw_cache_item
*next
;
540 struct brw_context
*brw
;
542 struct brw_cache_item
**items
;
544 GLuint size
, n_items
;
546 uint32_t next_offset
;
551 /* Considered adding a member to this struct to document which flags
552 * an update might raise so that ordering of the state atoms can be
553 * checked or derived at runtime. Dropped the idea in favor of having
554 * a debug mode where the state is monitored for flags which are
555 * raised that have already been tested against.
557 struct brw_tracked_state
{
558 struct brw_state_flags dirty
;
559 void (*emit
)( struct brw_context
*brw
);
562 enum shader_time_shader_type
{
573 struct brw_vertex_buffer
{
574 /** Buffer object containing the uploaded vertex data */
578 /** Byte stride between elements in the uploaded array */
582 struct brw_vertex_element
{
583 const struct gl_client_array
*glarray
;
587 /** Offset of the first element within the buffer object */
591 struct brw_query_object
{
592 struct gl_query_object Base
;
594 /** Last query BO associated with this query. */
597 /** Last index in bo with query data for this object. */
600 /** True if we know the batch has been flushed since we ended the query. */
610 struct intel_batchbuffer
{
611 /** Current batchbuffer being queued up. */
613 /** Last BO submitted to the hardware. Used for glFinish(). */
614 drm_intel_bo
*last_bo
;
617 uint16_t emit
, total
;
619 uint16_t reserved_space
;
623 #define BATCH_SZ (8192*sizeof(uint32_t))
625 uint32_t state_batch_offset
;
626 enum brw_gpu_ring ring
;
627 bool needs_sol_reset
;
628 bool state_base_address_emitted
;
636 #define MAX_GS_INPUT_VERTICES 6
638 #define BRW_MAX_XFB_STREAMS 4
640 struct brw_transform_feedback_object
{
641 struct gl_transform_feedback_object base
;
643 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
644 drm_intel_bo
*offset_bo
;
646 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
649 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
650 GLenum primitive_mode
;
653 * Count of primitives generated during this transform feedback operation.
656 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
657 drm_intel_bo
*prim_count_bo
;
658 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
662 * Number of vertices written between last Begin/EndTransformFeedback().
664 * Used to implement DrawTransformFeedback().
666 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
667 bool vertices_written_valid
;
671 * Data shared between each programmable stage in the pipeline (vs, gs, and
674 struct brw_stage_state
676 gl_shader_stage stage
;
677 struct brw_stage_prog_data
*prog_data
;
680 * Optional scratch buffer used to store spilled register values and
681 * variably-indexed GRF arrays.
683 * The contents of this buffer are short-lived so the same memory can be
684 * re-used at will for multiple shader programs (executed by the same fixed
685 * function). However reusing a scratch BO for which shader invocations
686 * are still in flight with a per-thread scratch slot size other than the
687 * original can cause threads with different scratch slot size and FFTID
688 * (which may be executed in parallel depending on the shader stage and
689 * hardware generation) to map to an overlapping region of the scratch
690 * space, which can potentially lead to mutual scratch space corruption.
691 * For that reason if you borrow this scratch buffer you should only be
692 * using the slot size given by the \c per_thread_scratch member below,
693 * unless you're taking additional measures to synchronize thread execution
694 * across slot size changes.
696 drm_intel_bo
*scratch_bo
;
699 * Scratch slot size allocated for each thread in the buffer object given
702 uint32_t per_thread_scratch
;
704 /** Offset in the program cache to the program */
705 uint32_t prog_offset
;
707 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
708 uint32_t state_offset
;
710 uint32_t push_const_offset
; /* Offset in the batchbuffer */
711 int push_const_size
; /* in 256-bit register increments */
713 /* Binding table: pointers to SURFACE_STATE entries. */
714 uint32_t bind_bo_offset
;
715 uint32_t surf_offset
[BRW_MAX_SURFACES
];
717 /** SAMPLER_STATE count and table offset */
718 uint32_t sampler_count
;
719 uint32_t sampler_offset
;
722 enum brw_predicate_state
{
723 /* The first two states are used if we can determine whether to draw
724 * without having to look at the values in the query object buffer. This
725 * will happen if there is no conditional render in progress, if the query
726 * object is already completed or if something else has already added
727 * samples to the preliminary result such as via a BLT command.
729 BRW_PREDICATE_STATE_RENDER
,
730 BRW_PREDICATE_STATE_DONT_RENDER
,
731 /* In this case whether to draw or not depends on the result of an
732 * MI_PREDICATE command so the predicate enable bit needs to be checked.
734 BRW_PREDICATE_STATE_USE_BIT
739 struct gen_l3_config
;
742 * brw_context is derived from gl_context.
746 struct gl_context ctx
; /**< base class, must be first field */
750 uint32_t (*update_renderbuffer_surface
)(struct brw_context
*brw
,
751 struct gl_renderbuffer
*rb
,
752 uint32_t flags
, unsigned unit
,
753 uint32_t surf_index
);
754 void (*emit_null_surface_state
)(struct brw_context
*brw
,
758 uint32_t *out_offset
);
761 * Send the appropriate state packets to configure depth, stencil, and
762 * HiZ buffers (i965+ only)
764 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
765 struct intel_mipmap_tree
*depth_mt
,
766 uint32_t depth_offset
,
767 uint32_t depthbuffer_format
,
768 uint32_t depth_surface_type
,
769 struct intel_mipmap_tree
*stencil_mt
,
770 bool hiz
, bool separate_stencil
,
771 uint32_t width
, uint32_t height
,
772 uint32_t tile_x
, uint32_t tile_y
);
778 drm_intel_context
*hw_ctx
;
780 /** BO for post-sync nonzero writes for gen6 workaround. */
781 drm_intel_bo
*workaround_bo
;
782 uint8_t pipe_controls_since_last_cs_stall
;
785 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
786 * and would need flushing before being used from another cache domain that
787 * isn't coherent with it (i.e. the sampler).
789 struct set
*render_cache
;
792 * Number of resets observed in the system at context creation.
794 * This is tracked in the context so that we can determine that another
795 * reset has occurred.
797 uint32_t reset_count
;
799 struct intel_batchbuffer batch
;
804 uint32_t next_offset
;
808 * Set if rendering has occurred to the drawable's front buffer.
810 * This is used in the DRI2 case to detect that glFlush should also copy
811 * the contents of the fake front buffer to the real front buffer.
813 bool front_buffer_dirty
;
815 /** Framerate throttling: @{ */
816 drm_intel_bo
*throttle_batch
[2];
818 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
819 * frame of rendering to complete. This gives a very precise cap to the
820 * latency between input and output such that rendering never gets more
821 * than a frame behind the user. (With the caveat that we technically are
822 * not using the SwapBuffers itself as a barrier but the first batch
823 * submitted afterwards, which may be immediately prior to the next
826 bool need_swap_throttle
;
828 /** General throttling, not caught by throttling between SwapBuffers */
829 bool need_flush_throttle
;
839 bool always_flush_batch
;
840 bool always_flush_cache
;
841 bool disable_throttling
;
843 bool dual_color_blend_by_location
;
845 driOptionCache optionCache
;
848 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
850 GLenum reduced_primitive
;
853 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
854 * variable is set, this is the flag indicating to do expensive work that
855 * might lead to a perf_debug() call.
859 uint64_t max_gtt_map_object_size
;
871 bool has_separate_stencil
;
872 bool must_use_separate_stencil
;
875 bool has_surface_tile_offset
;
877 bool has_negative_rhw_bug
;
881 bool use_resource_streamer
;
884 * Whether LRI can be used to write register values from the batch buffer.
886 bool can_do_pipelined_register_writes
;
889 * Some versions of Gen hardware don't do centroid interpolation correctly
890 * on unlit pixels, causing incorrect values for derivatives near triangle
891 * edges. Enabling this flag causes the fragment shader to use
892 * non-centroid interpolation for unlit pixels, at the expense of two extra
893 * fragment shader instructions.
895 bool needs_unlit_centroid_workaround
;
897 struct isl_device isl_dev
;
899 struct blorp_context blorp
;
903 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
906 enum brw_pipeline last_pipeline
;
908 struct brw_cache cache
;
910 /** IDs for meta stencil blit shader programs. */
911 struct gl_shader_program
*meta_stencil_blit_programs
[2];
913 /* Whether a meta-operation is in progress. */
914 bool meta_in_progress
;
916 /* Whether the last depth/stencil packets were both NULL. */
917 bool no_depth_or_stencil
;
919 /* The last PMA stall bits programmed. */
920 uint32_t pma_stall_bits
;
924 /** The value of gl_BaseVertex for the current _mesa_prim. */
927 /** The value of gl_BaseInstance for the current _mesa_prim. */
932 * Buffer and offset used for GL_ARB_shader_draw_parameters
933 * (for now, only gl_BaseVertex).
935 drm_intel_bo
*draw_params_bo
;
936 uint32_t draw_params_offset
;
939 * The value of gl_DrawID for the current _mesa_prim. This always comes
940 * in from it's own vertex buffer since it's not part of the indirect
944 drm_intel_bo
*draw_id_bo
;
945 uint32_t draw_id_offset
;
950 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
951 * an indirect call, and num_work_groups_offset is valid. Otherwise,
952 * num_work_groups is set based on glDispatchCompute.
954 drm_intel_bo
*num_work_groups_bo
;
955 GLintptr num_work_groups_offset
;
956 const GLuint
*num_work_groups
;
960 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
961 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
963 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
967 /* Summary of size and varying of active arrays, so we can check
968 * for changes to this state:
970 bool index_bounds_valid
;
971 unsigned int min_index
, max_index
;
973 /* Offset from start of vertex buffer so we can avoid redefining
974 * the same VB packed over and over again.
976 unsigned int start_vertex_bias
;
979 * Certain vertex attribute formats aren't natively handled by the
980 * hardware and require special VS code to fix up their values.
982 * These bitfields indicate which workarounds are needed.
984 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
989 * Index buffer for this draw_prims call.
991 * Updates are signaled by BRW_NEW_INDICES.
993 const struct _mesa_index_buffer
*ib
;
995 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
1000 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
1001 * avoid re-uploading the IB packet over and over if we're actually
1002 * referencing the same index buffer.
1004 unsigned int start_vertex_offset
;
1007 /* Active vertex program:
1009 const struct gl_vertex_program
*vertex_program
;
1010 const struct gl_program
*geometry_program
;
1011 const struct gl_program
*tess_ctrl_program
;
1012 const struct gl_program
*tess_eval_program
;
1013 const struct gl_fragment_program
*fragment_program
;
1014 const struct gl_compute_program
*compute_program
;
1017 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
1018 * that we don't have to reemit that state every time we change FBOs.
1022 /* BRW_NEW_URB_ALLOCATIONS:
1025 GLuint vsize
; /* vertex size plus header in urb registers */
1026 GLuint gsize
; /* GS output size in urb registers */
1027 GLuint hsize
; /* Tessellation control output size in urb registers */
1028 GLuint dsize
; /* Tessellation evaluation output size in urb registers */
1029 GLuint csize
; /* constant buffer size in urb registers */
1030 GLuint sfsize
; /* setup data size in urb registers */
1034 GLuint nr_vs_entries
;
1035 GLuint nr_hs_entries
;
1036 GLuint nr_ds_entries
;
1037 GLuint nr_gs_entries
;
1038 GLuint nr_clip_entries
;
1039 GLuint nr_sf_entries
;
1040 GLuint nr_cs_entries
;
1050 * URB size in the current configuration. The units this is expressed
1051 * in are somewhat inconsistent, see gen_device_info::urb::size.
1053 * FINISHME: Represent the URB size consistently in KB on all platforms.
1057 /* True if the most recently sent _3DSTATE_URB message allocated
1058 * URB space for the GS.
1062 /* True if the most recently sent _3DSTATE_URB message allocated
1063 * URB space for the HS and DS.
1069 /* BRW_NEW_CURBE_OFFSETS:
1072 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1073 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1081 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1082 * for upload to the CURBE.
1084 drm_intel_bo
*curbe_bo
;
1085 /** Offset within curbe_bo of space for current curbe entry */
1086 GLuint curbe_offset
;
1090 * Layout of vertex data exiting the geometry portion of the pipleine.
1091 * This comes from the last enabled shader stage (GS, DS, or VS).
1093 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1095 struct brw_vue_map vue_map_geom_out
;
1098 struct brw_stage_state base
;
1102 struct brw_stage_state base
;
1105 * True if the 3DSTATE_HS command most recently emitted to the 3D
1106 * pipeline enabled the HS; false otherwise.
1112 struct brw_stage_state base
;
1115 * True if the 3DSTATE_DS command most recently emitted to the 3D
1116 * pipeline enabled the DS; false otherwise.
1122 struct brw_stage_state base
;
1125 * True if the 3DSTATE_GS command most recently emitted to the 3D
1126 * pipeline enabled the GS; false otherwise.
1132 struct brw_ff_gs_prog_data
*prog_data
;
1135 /** Offset in the program cache to the CLIP program pre-gen6 */
1136 uint32_t prog_offset
;
1137 uint32_t state_offset
;
1139 uint32_t bind_bo_offset
;
1141 * Surface offsets for the binding table. We only need surfaces to
1142 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1143 * need in this case.
1145 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1149 struct brw_clip_prog_data
*prog_data
;
1151 /** Offset in the program cache to the CLIP program pre-gen6 */
1152 uint32_t prog_offset
;
1154 /* Offset in the batch to the CLIP state on pre-gen6. */
1155 uint32_t state_offset
;
1157 /* As of gen6, this is the offset in the batch to the CLIP VP,
1163 * The number of viewports to use. If gl_ViewportIndex is written,
1164 * we can have up to ctx->Const.MaxViewports viewports. If not,
1165 * the viewport index is always 0, so we can only emit one.
1167 uint8_t viewport_count
;
1172 struct brw_sf_prog_data
*prog_data
;
1174 /** Offset in the program cache to the CLIP program pre-gen6 */
1175 uint32_t prog_offset
;
1176 uint32_t state_offset
;
1178 bool viewport_transform_enable
;
1182 struct brw_stage_state base
;
1187 * Buffer object used in place of multisampled null render targets on
1188 * Gen6. See brw_emit_null_surface_state().
1190 drm_intel_bo
*multisampled_null_render_target_bo
;
1191 uint32_t fast_clear_op
;
1197 struct brw_stage_state base
;
1200 /* RS hardware binding table */
1203 uint32_t next_offset
;
1207 uint32_t state_offset
;
1208 uint32_t blend_state_offset
;
1209 uint32_t depth_stencil_state_offset
;
1214 struct brw_query_object
*obj
;
1219 enum brw_predicate_state state
;
1224 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1225 const int *statistics_registers
;
1227 /** The number of active monitors using OA counters. */
1231 * A buffer object storing OA counter snapshots taken at the start and
1232 * end of each batch (creating "bookends" around the batch).
1234 drm_intel_bo
*bookend_bo
;
1236 /** The number of snapshots written to bookend_bo. */
1237 int bookend_snapshots
;
1240 * An array of monitors whose results haven't yet been assembled based on
1241 * the data in buffer objects.
1243 * These may be active, or have already ended. However, the results
1244 * have not been requested.
1246 struct brw_perf_monitor_object
**unresolved
;
1247 int unresolved_elements
;
1248 int unresolved_array_size
;
1251 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1252 * the counter which MI_REPORT_PERF_COUNT stores there.
1254 const int *oa_snapshot_layout
;
1256 /** Number of 32-bit entries in a hardware counter snapshot. */
1257 int entries_per_oa_snapshot
;
1260 int num_atoms
[BRW_NUM_PIPELINES
];
1261 const struct brw_tracked_state render_atoms
[76];
1262 const struct brw_tracked_state compute_atoms
[11];
1264 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1268 enum aub_state_struct_type type
;
1270 } *state_batch_list
;
1271 int state_batch_count
;
1273 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1274 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1276 /* Interpolation modes, one byte per vue slot.
1277 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1279 struct interpolation_mode_map interpolation_mode
;
1281 /* PrimitiveRestart */
1284 bool enable_cut_index
;
1287 /** Computed depth/stencil/hiz state from the current attached
1288 * renderbuffers, valid only during the drawing state upload loop after
1289 * brw_workaround_depthstencil_alignment().
1292 struct intel_mipmap_tree
*depth_mt
;
1293 struct intel_mipmap_tree
*stencil_mt
;
1295 /* Inter-tile (page-aligned) byte offsets. */
1296 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1297 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1298 uint32_t tile_x
, tile_y
;
1301 uint32_t num_instances
;
1306 const struct gen_l3_config
*config
;
1313 enum shader_time_shader_type
*types
;
1314 struct shader_times
*cumulative
;
1320 struct brw_fast_clear_state
*fast_clear_state
;
1322 /* Array of flags telling if auxiliary buffer is disabled for corresponding
1323 * renderbuffer. If draw_aux_buffer_disabled[i] is set then use of
1324 * auxiliary buffer for gl_framebuffer::_ColorDrawBuffers[i] is
1326 * This is needed in case the same underlying buffer is also configured
1327 * to be sampled but with a format that the sampling engine can't treat
1328 * compressed or fast cleared.
1330 bool draw_aux_buffer_disabled
[MAX_DRAW_BUFFERS
];
1332 __DRIcontext
*driContext
;
1333 struct intel_screen
*screen
;
1336 /*======================================================================
1339 void brwInitVtbl( struct brw_context
*brw
);
1342 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1344 /*======================================================================
1347 extern const char *const brw_vendor_string
;
1350 brw_get_renderer_string(const struct intel_screen
*screen
);
1353 DRI_CONF_BO_REUSE_DISABLED
,
1354 DRI_CONF_BO_REUSE_ALL
1357 void intel_update_renderbuffers(__DRIcontext
*context
,
1358 __DRIdrawable
*drawable
);
1359 void intel_prepare_render(struct brw_context
*brw
);
1361 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1362 __DRIdrawable
*drawable
);
1364 GLboolean
brwCreateContext(gl_api api
,
1365 const struct gl_config
*mesaVis
,
1366 __DRIcontext
*driContextPriv
,
1367 unsigned major_version
,
1368 unsigned minor_version
,
1372 void *sharedContextPrivate
);
1374 /*======================================================================
1378 brw_meta_resolve_color(struct brw_context
*brw
,
1379 struct intel_mipmap_tree
*mt
);
1381 /*======================================================================
1384 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1385 uint32_t depth_level
,
1386 uint32_t depth_layer
,
1387 struct intel_mipmap_tree
*stencil_mt
,
1388 uint32_t *out_tile_mask_x
,
1389 uint32_t *out_tile_mask_y
);
1390 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1391 GLbitfield clear_mask
);
1393 /* brw_object_purgeable.c */
1394 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1396 /*======================================================================
1399 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1400 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1401 void brw_emit_query_begin(struct brw_context
*brw
);
1402 void brw_emit_query_end(struct brw_context
*brw
);
1403 void brw_query_counter(struct gl_context
*ctx
, struct gl_query_object
*q
);
1404 bool brw_is_query_pipelined(struct brw_query_object
*query
);
1406 /** gen6_queryobj.c */
1407 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1408 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1409 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1411 /** hsw_queryobj.c */
1412 void hsw_init_queryobj_functions(struct dd_function_table
*functions
);
1414 /** brw_conditional_render.c */
1415 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1416 bool brw_check_conditional_render(struct brw_context
*brw
);
1418 /** intel_batchbuffer.c */
1419 void brw_load_register_mem(struct brw_context
*brw
,
1422 uint32_t read_domains
, uint32_t write_domain
,
1424 void brw_load_register_mem64(struct brw_context
*brw
,
1427 uint32_t read_domains
, uint32_t write_domain
,
1429 void brw_store_register_mem32(struct brw_context
*brw
,
1430 drm_intel_bo
*bo
, uint32_t reg
, uint32_t offset
);
1431 void brw_store_register_mem64(struct brw_context
*brw
,
1432 drm_intel_bo
*bo
, uint32_t reg
, uint32_t offset
);
1433 void brw_load_register_imm32(struct brw_context
*brw
,
1434 uint32_t reg
, uint32_t imm
);
1435 void brw_load_register_imm64(struct brw_context
*brw
,
1436 uint32_t reg
, uint64_t imm
);
1437 void brw_load_register_reg(struct brw_context
*brw
, uint32_t src
,
1439 void brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
,
1441 void brw_store_data_imm32(struct brw_context
*brw
, drm_intel_bo
*bo
,
1442 uint32_t offset
, uint32_t imm
);
1443 void brw_store_data_imm64(struct brw_context
*brw
, drm_intel_bo
*bo
,
1444 uint32_t offset
, uint64_t imm
);
1446 /*======================================================================
1449 void brw_debug_batch(struct brw_context
*brw
);
1450 void brw_annotate_aub(struct brw_context
*brw
);
1452 /*======================================================================
1453 * intel_tex_validate.c
1455 void brw_validate_textures( struct brw_context
*brw
);
1458 /*======================================================================
1462 key_debug(struct brw_context
*brw
, const char *name
, int a
, int b
)
1465 perf_debug(" %s %d->%d\n", name
, a
, b
);
1471 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1473 /* Per-thread scratch space is a power-of-two multiple of 1KB. */
1475 brw_get_scratch_size(int size
)
1477 return MAX2(1024, util_next_power_of_two(size
));
1479 void brw_get_scratch_bo(struct brw_context
*brw
,
1480 drm_intel_bo
**scratch_bo
, int size
);
1481 void brw_alloc_stage_scratch(struct brw_context
*brw
,
1482 struct brw_stage_state
*stage_state
,
1483 unsigned per_thread_size
,
1484 unsigned thread_count
);
1485 void brw_init_shader_time(struct brw_context
*brw
);
1486 int brw_get_shader_time_index(struct brw_context
*brw
,
1487 struct gl_shader_program
*shader_prog
,
1488 struct gl_program
*prog
,
1489 enum shader_time_shader_type type
);
1490 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1491 void brw_destroy_shader_time(struct brw_context
*brw
);
1495 void brw_upload_urb_fence(struct brw_context
*brw
);
1499 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1501 /* brw_fs_reg_allocate.cpp
1503 void brw_fs_alloc_reg_sets(struct brw_compiler
*compiler
);
1505 /* brw_vec4_reg_allocate.cpp */
1506 void brw_vec4_alloc_reg_set(struct brw_compiler
*compiler
);
1509 int brw_disassemble_inst(FILE *file
, const struct gen_device_info
*devinfo
,
1510 struct brw_inst
*inst
, bool is_compacted
);
1513 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1515 /* brw_draw_upload.c */
1516 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1517 const struct gl_client_array
*glarray
);
1519 static inline unsigned
1520 brw_get_index_type(GLenum type
)
1522 assert((type
== GL_UNSIGNED_BYTE
)
1523 || (type
== GL_UNSIGNED_SHORT
)
1524 || (type
== GL_UNSIGNED_INT
));
1526 /* The possible values for type are GL_UNSIGNED_BYTE (0x1401),
1527 * GL_UNSIGNED_SHORT (0x1403), and GL_UNSIGNED_INT (0x1405) which we want
1528 * to map to scale factors of 0, 1, and 2, respectively. These scale
1529 * factors are then left-shfited by 8 to be in the correct position in the
1530 * CMD_INDEX_BUFFER packet.
1532 * Subtracting 0x1401 gives 0, 2, and 4. Shifting left by 7 afterwards
1533 * gives 0x00000000, 0x00000100, and 0x00000200. These just happen to be
1534 * the values the need to be written in the CMD_INDEX_BUFFER packet.
1536 return (type
- 0x1401) << 7;
1539 void brw_prepare_vertices(struct brw_context
*brw
);
1541 /* brw_wm_surface_state.c */
1542 void brw_init_surface_formats(struct brw_context
*brw
);
1543 void brw_create_constant_surface(struct brw_context
*brw
,
1547 uint32_t *out_offset
);
1548 void brw_create_buffer_surface(struct brw_context
*brw
,
1552 uint32_t *out_offset
);
1553 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1555 uint32_t *surf_offset
);
1557 brw_update_sol_surface(struct brw_context
*brw
,
1558 struct gl_buffer_object
*buffer_obj
,
1559 uint32_t *out_offset
, unsigned num_vector_components
,
1560 unsigned stride_dwords
, unsigned offset_dwords
);
1561 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1562 struct gl_linked_shader
*shader
,
1563 struct brw_stage_state
*stage_state
,
1564 struct brw_stage_prog_data
*prog_data
);
1565 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1566 struct gl_linked_shader
*shader
,
1567 struct brw_stage_state
*stage_state
,
1568 struct brw_stage_prog_data
*prog_data
);
1569 void brw_upload_image_surfaces(struct brw_context
*brw
,
1570 struct gl_linked_shader
*shader
,
1571 struct brw_stage_state
*stage_state
,
1572 struct brw_stage_prog_data
*prog_data
);
1574 /* brw_surface_formats.c */
1575 bool brw_render_target_supported(struct brw_context
*brw
,
1576 struct gl_renderbuffer
*rb
);
1577 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1579 /* brw_performance_monitor.c */
1580 void brw_init_performance_monitors(struct brw_context
*brw
);
1581 void brw_dump_perf_monitors(struct brw_context
*brw
);
1582 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1583 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1585 /* intel_buffer_objects.c */
1586 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1587 const char *bo_name
);
1588 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1589 const char *bo_name
);
1591 /* intel_extensions.c */
1592 extern void intelInitExtensions(struct gl_context
*ctx
);
1595 extern int intel_translate_shadow_compare_func(GLenum func
);
1596 extern int intel_translate_compare_func(GLenum func
);
1597 extern int intel_translate_stencil_op(GLenum op
);
1598 extern int intel_translate_logic_op(GLenum opcode
);
1601 void brw_init_syncobj_functions(struct dd_function_table
*functions
);
1604 struct gl_transform_feedback_object
*
1605 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1607 brw_delete_transform_feedback(struct gl_context
*ctx
,
1608 struct gl_transform_feedback_object
*obj
);
1610 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1611 struct gl_transform_feedback_object
*obj
);
1613 brw_end_transform_feedback(struct gl_context
*ctx
,
1614 struct gl_transform_feedback_object
*obj
);
1616 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1617 struct gl_transform_feedback_object
*obj
,
1620 /* gen7_sol_state.c */
1622 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1623 struct gl_transform_feedback_object
*obj
);
1625 gen7_end_transform_feedback(struct gl_context
*ctx
,
1626 struct gl_transform_feedback_object
*obj
);
1628 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1629 struct gl_transform_feedback_object
*obj
);
1631 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1632 struct gl_transform_feedback_object
*obj
);
1636 hsw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1637 struct gl_transform_feedback_object
*obj
);
1639 hsw_end_transform_feedback(struct gl_context
*ctx
,
1640 struct gl_transform_feedback_object
*obj
);
1642 hsw_pause_transform_feedback(struct gl_context
*ctx
,
1643 struct gl_transform_feedback_object
*obj
);
1645 hsw_resume_transform_feedback(struct gl_context
*ctx
,
1646 struct gl_transform_feedback_object
*obj
);
1648 /* brw_blorp_blit.cpp */
1650 brw_blorp_framebuffer(struct brw_context
*brw
,
1651 struct gl_framebuffer
*readFb
,
1652 struct gl_framebuffer
*drawFb
,
1653 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1654 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1655 GLbitfield mask
, GLenum filter
);
1658 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1659 struct gl_renderbuffer
*src_rb
,
1660 struct gl_texture_image
*dst_image
,
1662 int srcX0
, int srcY0
,
1663 int dstX0
, int dstY0
,
1664 int width
, int height
);
1666 /* gen6_multisample_state.c */
1668 gen6_determine_sample_mask(struct brw_context
*brw
);
1671 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1672 unsigned num_samples
);
1674 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1676 gen6_get_sample_position(struct gl_context
*ctx
,
1677 struct gl_framebuffer
*fb
,
1681 gen6_set_sample_maps(struct gl_context
*ctx
);
1683 /* gen8_multisample_state.c */
1684 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1685 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1689 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1690 unsigned hs_size
, unsigned ds_size
,
1691 unsigned gs_size
, unsigned fs_size
);
1694 gen6_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1695 bool gs_present
, unsigned gs_size
);
1697 gen7_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1698 bool gs_present
, bool tess_present
);
1702 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1704 brw_check_for_reset(struct brw_context
*brw
);
1708 brw_init_compute_functions(struct dd_function_table
*functions
);
1710 /*======================================================================
1711 * Inline conversion functions. These are better-typed than the
1712 * macros used previously:
1714 static inline struct brw_context
*
1715 brw_context( struct gl_context
*ctx
)
1717 return (struct brw_context
*)ctx
;
1720 static inline struct brw_vertex_program
*
1721 brw_vertex_program(struct gl_vertex_program
*p
)
1723 return (struct brw_vertex_program
*) p
;
1726 static inline const struct brw_vertex_program
*
1727 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1729 return (const struct brw_vertex_program
*) p
;
1732 static inline struct brw_tess_ctrl_program
*
1733 brw_tess_ctrl_program(struct gl_program
*p
)
1735 return (struct brw_tess_ctrl_program
*) p
;
1738 static inline struct brw_tess_eval_program
*
1739 brw_tess_eval_program(struct gl_program
*p
)
1741 return (struct brw_tess_eval_program
*) p
;
1744 static inline struct brw_geometry_program
*
1745 brw_geometry_program(struct gl_program
*p
)
1747 return (struct brw_geometry_program
*) p
;
1750 static inline struct brw_fragment_program
*
1751 brw_fragment_program(struct gl_fragment_program
*p
)
1753 return (struct brw_fragment_program
*) p
;
1756 static inline const struct brw_fragment_program
*
1757 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1759 return (const struct brw_fragment_program
*) p
;
1762 static inline struct brw_compute_program
*
1763 brw_compute_program(struct gl_compute_program
*p
)
1765 return (struct brw_compute_program
*) p
;
1769 * Pre-gen6, the register file of the EUs was shared between threads,
1770 * and each thread used some subset allocated on a 16-register block
1771 * granularity. The unit states wanted these block counts.
1774 brw_register_blocks(int reg_count
)
1776 return ALIGN(reg_count
, 16) / 16 - 1;
1779 static inline uint32_t
1780 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1781 uint32_t prog_offset
)
1783 if (brw
->gen
>= 5) {
1784 /* Using state base address. */
1788 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1792 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1794 return brw
->cache
.bo
->offset64
+ prog_offset
;
1797 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1798 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1799 struct exec_list
*instructions
);
1801 extern const char * const conditional_modifier
[16];
1802 extern const char *const pred_ctrl_align16
[16];
1805 brw_emit_depthbuffer(struct brw_context
*brw
);
1808 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1809 struct intel_mipmap_tree
*depth_mt
,
1810 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1811 uint32_t depth_surface_type
,
1812 struct intel_mipmap_tree
*stencil_mt
,
1813 bool hiz
, bool separate_stencil
,
1814 uint32_t width
, uint32_t height
,
1815 uint32_t tile_x
, uint32_t tile_y
);
1818 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1819 struct intel_mipmap_tree
*depth_mt
,
1820 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1821 uint32_t depth_surface_type
,
1822 struct intel_mipmap_tree
*stencil_mt
,
1823 bool hiz
, bool separate_stencil
,
1824 uint32_t width
, uint32_t height
,
1825 uint32_t tile_x
, uint32_t tile_y
);
1828 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1829 struct intel_mipmap_tree
*depth_mt
,
1830 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1831 uint32_t depth_surface_type
,
1832 struct intel_mipmap_tree
*stencil_mt
,
1833 bool hiz
, bool separate_stencil
,
1834 uint32_t width
, uint32_t height
,
1835 uint32_t tile_x
, uint32_t tile_y
);
1837 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1838 struct intel_mipmap_tree
*depth_mt
,
1839 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1840 uint32_t depth_surface_type
,
1841 struct intel_mipmap_tree
*stencil_mt
,
1842 bool hiz
, bool separate_stencil
,
1843 uint32_t width
, uint32_t height
,
1844 uint32_t tile_x
, uint32_t tile_y
);
1846 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1847 unsigned int level
, unsigned int layer
, enum blorp_hiz_op op
);
1849 uint32_t get_hw_prim_for_gl_prim(int mode
);
1852 gen6_upload_push_constants(struct brw_context
*brw
,
1853 const struct gl_program
*prog
,
1854 const struct brw_stage_prog_data
*prog_data
,
1855 struct brw_stage_state
*stage_state
,
1856 enum aub_state_struct_type type
);
1859 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
1860 const struct intel_mipmap_tree
*mt
);
1862 /* brw_pipe_control.c */
1863 int brw_init_pipe_control(struct brw_context
*brw
,
1864 const struct gen_device_info
*info
);
1865 void brw_fini_pipe_control(struct brw_context
*brw
);
1867 void brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
);
1868 void brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
1869 drm_intel_bo
*bo
, uint32_t offset
,
1870 uint32_t imm_lower
, uint32_t imm_upper
);
1871 void brw_emit_mi_flush(struct brw_context
*brw
);
1872 void brw_emit_post_sync_nonzero_flush(struct brw_context
*brw
);
1873 void brw_emit_depth_stall_flushes(struct brw_context
*brw
);
1874 void gen7_emit_vs_workaround_flush(struct brw_context
*brw
);
1875 void gen7_emit_cs_stall_flush(struct brw_context
*brw
);
1877 /* brw_queryformat.c */
1878 void brw_query_internal_format(struct gl_context
*ctx
, GLenum target
,
1879 GLenum internalFormat
, GLenum pname
,