2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
38 #include "main/imports.h"
39 #include "main/macros.h"
41 #include "main/mtypes.h"
42 #include "brw_structs.h"
43 #include "intel_aub.h"
44 #include "program/prog_parameter.h"
48 /* Evil hack for using libdrm in a c++ compiler. */
53 #include <intel_bufmgr.h>
63 #include "intel_debug.h"
64 #include "intel_screen.h"
65 #include "intel_tex_obj.h"
66 #include "intel_resolve_map.h"
70 * URB - uniform resource buffer. A mid-sized buffer which is
71 * partitioned between the fixed function units and used for passing
72 * values (vertices, primitives, constants) between them.
74 * CURBE - constant URB entry. An urb region (entry) used to hold
75 * constant values which the fixed function units can be instructed to
76 * preload into the GRF when spawning a thread.
78 * VUE - vertex URB entry. An urb entry holding a vertex and usually
79 * a vertex header. The header contains control information and
80 * things like primitive type, Begin/end flags and clip codes.
82 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
83 * unit holding rasterization and interpolation parameters.
85 * GRF - general register file. One of several register files
86 * addressable by programmed threads. The inputs (r0, payload, curbe,
87 * urb) of the thread are preloaded to this area before the thread is
88 * spawned. The registers are individually 8 dwords wide and suitable
89 * for general usage. Registers holding thread input values are not
90 * special and may be overwritten.
92 * MRF - message register file. Threads communicate (and terminate)
93 * by sending messages. Message parameters are placed in contiguous
94 * MRF registers. All program output is via these messages. URB
95 * entries are populated by sending a message to the shared URB
96 * function containing the new data, together with a control word,
97 * often an unmodified copy of R0.
99 * R0 - GRF register 0. Typically holds control information used when
100 * sending messages to other threads.
102 * EU or GEN4 EU: The name of the programmable subsystem of the
103 * i965 hardware. Threads are executed by the EU, the registers
104 * described above are part of the EU architecture.
106 * Fixed function units:
108 * CS - Command streamer. Notional first unit, little software
109 * interaction. Holds the URB entries used for constant data, ie the
112 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
113 * this unit is responsible for pulling vertices out of vertex buffers
114 * in vram and injecting them into the processing pipe as VUEs. If
115 * enabled, it first passes them to a VS thread which is a good place
116 * for the driver to implement any active vertex shader.
118 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
119 * enabled, incoming strips etc are passed to GS threads in individual
120 * line/triangle/point units. The GS thread may perform arbitary
121 * computation and emit whatever primtives with whatever vertices it
122 * chooses. This makes GS an excellent place to implement GL's
123 * unfilled polygon modes, though of course it is capable of much
124 * more. Additionally, GS is used to translate away primitives not
125 * handled by latter units, including Quads and Lineloops.
127 * CS - Clipper. Mesa's clipping algorithms are imported to run on
128 * this unit. The fixed function part performs cliptesting against
129 * the 6 fixed clipplanes and makes descisions on whether or not the
130 * incoming primitive needs to be passed to a thread for clipping.
131 * User clip planes are handled via cooperation with the VS thread.
133 * SF - Strips Fans or Setup: Triangles are prepared for
134 * rasterization. Interpolation coefficients are calculated.
135 * Flatshading and two-side lighting usually performed here.
137 * WM - Windower. Interpolation of vertex attributes performed here.
138 * Fragment shader implemented here. SIMD aspects of EU taken full
139 * advantage of, as pixels are processed in blocks of 16.
141 * CC - Color Calculator. No EU threads associated with this unit.
142 * Handles blending and (presumably) depth and stencil testing.
147 struct brw_vs_prog_key
;
148 struct brw_vec4_prog_key
;
149 struct brw_wm_prog_key
;
150 struct brw_wm_prog_data
;
154 BRW_STATE_FRAGMENT_PROGRAM
,
155 BRW_STATE_GEOMETRY_PROGRAM
,
156 BRW_STATE_VERTEX_PROGRAM
,
157 BRW_STATE_CURBE_OFFSETS
,
158 BRW_STATE_REDUCED_PRIMITIVE
,
163 BRW_STATE_VS_BINDING_TABLE
,
164 BRW_STATE_GS_BINDING_TABLE
,
165 BRW_STATE_PS_BINDING_TABLE
,
169 BRW_STATE_INDEX_BUFFER
,
170 BRW_STATE_VS_CONSTBUF
,
171 BRW_STATE_GS_CONSTBUF
,
172 BRW_STATE_PROGRAM_CACHE
,
173 BRW_STATE_STATE_BASE_ADDRESS
,
174 BRW_STATE_VUE_MAP_VS
,
175 BRW_STATE_VUE_MAP_GEOM_OUT
,
176 BRW_STATE_TRANSFORM_FEEDBACK
,
177 BRW_STATE_RASTERIZER_DISCARD
,
179 BRW_STATE_UNIFORM_BUFFER
,
180 BRW_STATE_ATOMIC_BUFFER
,
181 BRW_STATE_META_IN_PROGRESS
,
182 BRW_STATE_INTERPOLATION_MAP
,
183 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
184 BRW_STATE_NUM_SAMPLES
,
188 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
189 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
190 #define BRW_NEW_GEOMETRY_PROGRAM (1 << BRW_STATE_GEOMETRY_PROGRAM)
191 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
192 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
193 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
194 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
195 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
196 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
197 #define BRW_NEW_SURFACES (1 << BRW_STATE_SURFACES)
198 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
199 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
200 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
201 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
202 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
204 * Used for any batch entry with a relocated pointer that will be used
205 * by any 3D rendering.
207 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
208 /** \see brw.state.depth_region */
209 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
210 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
211 #define BRW_NEW_GS_CONSTBUF (1 << BRW_STATE_GS_CONSTBUF)
212 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
213 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
214 #define BRW_NEW_VUE_MAP_VS (1 << BRW_STATE_VUE_MAP_VS)
215 #define BRW_NEW_VUE_MAP_GEOM_OUT (1 << BRW_STATE_VUE_MAP_GEOM_OUT)
216 #define BRW_NEW_TRANSFORM_FEEDBACK (1 << BRW_STATE_TRANSFORM_FEEDBACK)
217 #define BRW_NEW_RASTERIZER_DISCARD (1 << BRW_STATE_RASTERIZER_DISCARD)
218 #define BRW_NEW_STATS_WM (1 << BRW_STATE_STATS_WM)
219 #define BRW_NEW_UNIFORM_BUFFER (1 << BRW_STATE_UNIFORM_BUFFER)
220 #define BRW_NEW_ATOMIC_BUFFER (1 << BRW_STATE_ATOMIC_BUFFER)
221 #define BRW_NEW_META_IN_PROGRESS (1 << BRW_STATE_META_IN_PROGRESS)
222 #define BRW_NEW_INTERPOLATION_MAP (1 << BRW_STATE_INTERPOLATION_MAP)
223 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1 << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
224 #define BRW_NEW_NUM_SAMPLES (1 << BRW_STATE_NUM_SAMPLES)
226 struct brw_state_flags
{
227 /** State update flags signalled by mesa internals */
230 * State update flags signalled as the result of brw_tracked_state updates
234 * State update flags that used to be signalled by brw_state_cache.c
237 * Now almost all of that state is just streamed out on demand, but the
238 * flags for those state blobs updating have stayed in the same bitfield.
239 * brw_state_cache.c still flags CACHE_NEW_*_PROG.
246 * Set one of the bits in a field of brw_state_flags.
248 #define SET_DIRTY_BIT(FIELD, FLAG) brw->state.dirty.FIELD |= (FLAG)
252 * Set all of the bits in a field of brw_state_flags.
254 #define SET_DIRTY_ALL(FIELD) \
256 /* ~0 == 0xffffffff, so make sure field is <= 32 bits */ \
257 STATIC_ASSERT(sizeof(brw->state.dirty.FIELD) == 4); \
258 brw->state.dirty.FIELD = ~0; \
262 /** Subclass of Mesa vertex program */
263 struct brw_vertex_program
{
264 struct gl_vertex_program program
;
269 /** Subclass of Mesa geometry program */
270 struct brw_geometry_program
{
271 struct gl_geometry_program program
;
272 unsigned id
; /**< serial no. to identify geom progs, never re-used */
276 /** Subclass of Mesa fragment program */
277 struct brw_fragment_program
{
278 struct gl_fragment_program program
;
279 GLuint id
; /**< serial no. to identify frag progs, never re-used */
283 /** Subclass of Mesa compute program */
284 struct brw_compute_program
{
285 struct gl_compute_program program
;
286 unsigned id
; /**< serial no. to identify compute progs, never re-used */
291 struct gl_shader base
;
296 /* Note: If adding fields that need anything besides a normal memcmp() for
297 * comparing them, be sure to go fix brw_stage_prog_data_compare().
299 struct brw_stage_prog_data
{
301 /** size of our binding table. */
305 * surface indices for the various groups of surfaces
307 uint32_t pull_constants_start
;
308 uint32_t texture_start
;
309 uint32_t gather_texture_start
;
312 uint32_t shader_time_start
;
316 GLuint nr_params
; /**< number of float params/constants */
317 GLuint nr_pull_params
;
320 * Register where the thread expects to find input data from the URB
321 * (typically uniforms, followed by vertex or fragment attributes).
323 unsigned dispatch_grf_start_reg
;
325 /* Pointers to tracked values (only valid once
326 * _mesa_load_state_parameters has been called at runtime).
328 * These must be the last fields of the struct (see
329 * brw_stage_prog_data_compare()).
331 const gl_constant_value
**param
;
332 const gl_constant_value
**pull_param
;
335 /* Data about a particular attempt to compile a program. Note that
336 * there can be many of these, each in a different GL state
337 * corresponding to a different brw_wm_prog_key struct, with different
340 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
343 struct brw_wm_prog_data
{
344 struct brw_stage_prog_data base
;
346 GLuint curb_read_length
;
347 GLuint num_varying_inputs
;
349 GLuint dispatch_grf_start_reg_16
;
351 GLuint reg_blocks_16
;
352 GLuint total_scratch
;
356 * surface indices the WM-specific surfaces
358 uint32_t render_target_start
;
364 bool uses_pos_offset
;
366 uint32_t prog_offset_16
;
369 * Mask of which interpolation modes are required by the fragment shader.
370 * Used in hardware setup on gen6+.
372 uint32_t barycentric_interp_modes
;
375 * Map from gl_varying_slot to the position within the FS setup data
376 * payload where the varying's attribute vertex deltas should be delivered.
377 * For varying slots that are not used by the FS, the value is -1.
379 int urb_setup
[VARYING_SLOT_MAX
];
383 * Enum representing the i965-specific vertex results that don't correspond
384 * exactly to any element of gl_varying_slot. The values of this enum are
385 * assigned such that they don't conflict with gl_varying_slot.
389 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
390 BRW_VARYING_SLOT_PAD
,
392 * Technically this is not a varying but just a placeholder that
393 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
394 * builtin variable to be compiled correctly. see compile_sf_prog() for
397 BRW_VARYING_SLOT_PNTC
,
398 BRW_VARYING_SLOT_COUNT
403 * Data structure recording the relationship between the gl_varying_slot enum
404 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
405 * single octaword within the VUE (128 bits).
407 * Note that each BRW register contains 256 bits (2 octawords), so when
408 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
409 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
410 * in a vertex shader), each register corresponds to a single VUE slot, since
411 * it contains data for two separate vertices.
415 * Bitfield representing all varying slots that are (a) stored in this VUE
416 * map, and (b) actually written by the shader. Does not include any of
417 * the additional varying slots defined in brw_varying_slot.
419 GLbitfield64 slots_valid
;
422 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
423 * not stored in a slot (because they are not written, or because
424 * additional processing is applied before storing them in the VUE), the
427 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
430 * Map from VUE slot to gl_varying_slot value. For slots that do not
431 * directly correspond to a gl_varying_slot, the value comes from
434 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
435 * simplifies code that uses the value stored in slot_to_varying to
436 * create a bit mask).
438 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
441 * Total number of VUE slots in use
447 * Convert a VUE slot number into a byte offset within the VUE.
449 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
455 * Convert a vertex output (brw_varying_slot) into a byte offset within the
458 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
461 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
464 void brw_compute_vue_map(struct brw_context
*brw
, struct brw_vue_map
*vue_map
,
465 GLbitfield64 slots_valid
);
469 * Bitmask indicating which fragment shader inputs represent varyings (and
470 * hence have to be delivered to the fragment shader by the SF/SBE stage).
472 #define BRW_FS_VARYING_INPUT_MASK \
473 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
474 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
478 * Mapping of VUE map slots to interpolation modes.
480 struct interpolation_mode_map
{
481 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
484 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
486 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
487 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
493 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
495 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
496 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
503 struct brw_sf_prog_data
{
504 GLuint urb_read_length
;
507 /* Each vertex may have upto 12 attributes, 4 components each,
508 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
511 * Actually we use 4 for each, so call it 12 rows.
513 GLuint urb_entry_size
;
518 * We always program SF to start reading at an offset of 1 (2 varying slots)
519 * from the start of the vertex URB entry. This causes it to skip:
520 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
521 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
523 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
526 struct brw_clip_prog_data
{
527 GLuint curb_read_length
; /* user planes? */
529 GLuint urb_read_length
;
533 struct brw_ff_gs_prog_data
{
534 GLuint urb_read_length
;
538 * Gen6 transform feedback: Amount by which the streaming vertex buffer
539 * indices should be incremented each time the GS is invoked.
541 unsigned svbi_postincrement_value
;
545 /* Note: brw_vec4_prog_data_compare() must be updated when adding fields to
548 struct brw_vec4_prog_data
{
549 struct brw_stage_prog_data base
;
550 struct brw_vue_map vue_map
;
552 GLuint curb_read_length
;
553 GLuint urb_read_length
;
555 GLuint total_scratch
;
557 /* Used for calculating urb partitions. In the VS, this is the size of the
558 * URB entry used for both input and output to the thread. In the GS, this
559 * is the size of the URB entry used for output.
561 GLuint urb_entry_size
;
565 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
568 struct brw_vs_prog_data
{
569 struct brw_vec4_prog_data base
;
571 GLbitfield64 inputs_read
;
577 /* Note: brw_gs_prog_data_compare() must be updated when adding fields to
580 struct brw_gs_prog_data
582 struct brw_vec4_prog_data base
;
585 * Size of an output vertex, measured in HWORDS (32 bytes).
587 unsigned output_vertex_size_hwords
;
589 unsigned output_topology
;
592 * Size of the control data (cut bits or StreamID bits), in hwords (32
593 * bytes). 0 if there is no control data.
595 unsigned control_data_header_size_hwords
;
598 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
599 * if the control data is StreamID bits, or
600 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
601 * Ignored if control_data_header_size is 0.
603 unsigned control_data_format
;
605 bool include_primitive_id
;
610 * True if the thread should be dispatched in DUAL_INSTANCE mode, false if
611 * it should be dispatched in DUAL_OBJECT mode.
613 bool dual_instanced_dispatch
;
616 /** Number of texture sampler units */
617 #define BRW_MAX_TEX_UNIT 32
619 /** Max number of render targets in a shader */
620 #define BRW_MAX_DRAW_BUFFERS 8
622 /** Max number of atomic counter buffer objects in a shader */
623 #define BRW_MAX_ABO 16
626 * Max number of binding table entries used for stream output.
628 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
629 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
631 * On Gen6, the size of transform feedback data is limited not by the number
632 * of components but by the number of binding table entries we set aside. We
633 * use one binding table entry for a float, one entry for a vector, and one
634 * entry per matrix column. Since the only way we can communicate our
635 * transform feedback capabilities to the client is via
636 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
637 * worst case, in which all the varyings are floats, so we use up one binding
638 * table entry per component. Therefore we need to set aside at least 64
639 * binding table entries for use by transform feedback.
641 * Note: since we don't currently pack varyings, it is currently impossible
642 * for the client to actually use up all of these binding table entries--if
643 * all of their varyings were floats, they would run out of varying slots and
644 * fail to link. But that's a bug, so it seems prudent to go ahead and
645 * allocate the number of binding table entries we will need once the bug is
648 #define BRW_MAX_SOL_BINDINGS 64
650 /** Maximum number of actual buffers used for stream output */
651 #define BRW_MAX_SOL_BUFFERS 4
653 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
654 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
657 2 /* shader time, pull constants */)
659 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
660 #define BRW_MAX_GEN6_GS_SURFACES SURF_INDEX_GEN6_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
663 * Stride in bytes between shader_time entries.
665 * We separate entries by a cacheline to reduce traffic between EUs writing to
668 #define SHADER_TIME_STRIDE 64
675 BRW_BLORP_CONST_COLOR_PROG
,
680 BRW_SF_UNIT
, /* scissor state on gen6 */
693 struct brw_cache_item
{
695 * Effectively part of the key, cache_id identifies what kind of state
696 * buffer is involved, and also which brw->state.dirty.cache flag should
697 * be set when this cache item is chosen.
699 enum brw_cache_id cache_id
;
700 /** 32-bit hash of the key data */
702 GLuint key_size
; /* for variable-sized keys */
709 struct brw_cache_item
*next
;
713 typedef bool (*cache_aux_compare_func
)(const void *a
, const void *b
);
714 typedef void (*cache_aux_free_func
)(const void *aux
);
717 struct brw_context
*brw
;
719 struct brw_cache_item
**items
;
721 GLuint size
, n_items
;
723 uint32_t next_offset
;
727 * Optional functions used in determining whether the prog_data for a new
728 * cache item matches an existing cache item (in case there's relevant data
729 * outside of the prog_data). If NULL, a plain memcmp is done.
731 cache_aux_compare_func aux_compare
[BRW_MAX_CACHE
];
732 /** Optional functions for freeing other pointers attached to a prog_data. */
733 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
737 /* Considered adding a member to this struct to document which flags
738 * an update might raise so that ordering of the state atoms can be
739 * checked or derived at runtime. Dropped the idea in favor of having
740 * a debug mode where the state is monitored for flags which are
741 * raised that have already been tested against.
743 struct brw_tracked_state
{
744 struct brw_state_flags dirty
;
745 void (*emit
)( struct brw_context
*brw
);
748 enum shader_time_shader_type
{
764 /* Flags for brw->state.cache.
766 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
767 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
768 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
769 #define CACHE_NEW_BLORP_BLIT_PROG (1<<BRW_BLORP_BLIT_PROG)
770 #define CACHE_NEW_BLORP_CONST_COLOR_PROG (1<<BRW_BLORP_CONST_COLOR_PROG)
771 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
772 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
773 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
774 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
775 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
776 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
777 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
778 #define CACHE_NEW_FF_GS_UNIT (1<<BRW_FF_GS_UNIT)
779 #define CACHE_NEW_FF_GS_PROG (1<<BRW_FF_GS_PROG)
780 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
781 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
782 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
783 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
785 struct brw_vertex_buffer
{
786 /** Buffer object containing the uploaded vertex data */
789 /** Byte stride between elements in the uploaded array */
793 struct brw_vertex_element
{
794 const struct gl_client_array
*glarray
;
798 /** Offset of the first element within the buffer object */
802 struct brw_query_object
{
803 struct gl_query_object Base
;
805 /** Last query BO associated with this query. */
808 /** Last index in bo with query data for this object. */
812 struct intel_sync_object
{
813 struct gl_sync_object Base
;
815 /** Batch associated with this sync object */
825 struct intel_batchbuffer
{
826 /** Current batchbuffer being queued up. */
828 /** Last BO submitted to the hardware. Used for glFinish(). */
829 drm_intel_bo
*last_bo
;
830 /** BO for post-sync nonzero writes for gen6 workaround. */
831 drm_intel_bo
*workaround_bo
;
832 bool need_workaround_flush
;
834 uint16_t emit
, total
;
835 uint16_t used
, reserved_space
;
838 #define BATCH_SZ (8192*sizeof(uint32_t))
840 uint32_t state_batch_offset
;
841 enum brw_gpu_ring ring
;
842 bool needs_sol_reset
;
850 #define BRW_MAX_XFB_STREAMS 4
852 struct brw_transform_feedback_object
{
853 struct gl_transform_feedback_object base
;
855 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
856 drm_intel_bo
*offset_bo
;
858 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
861 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
862 GLenum primitive_mode
;
865 * Count of primitives generated during this transform feedback operation.
868 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
869 drm_intel_bo
*prim_count_bo
;
870 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
874 * Number of vertices written between last Begin/EndTransformFeedback().
876 * Used to implement DrawTransformFeedback().
878 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
879 bool vertices_written_valid
;
883 * Data shared between each programmable stage in the pipeline (vs, gs, and
886 struct brw_stage_state
888 gl_shader_stage stage
;
889 struct brw_stage_prog_data
*prog_data
;
892 * Optional scratch buffer used to store spilled register values and
893 * variably-indexed GRF arrays.
895 drm_intel_bo
*scratch_bo
;
897 /** Offset in the program cache to the program */
898 uint32_t prog_offset
;
900 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
901 uint32_t state_offset
;
903 uint32_t push_const_offset
; /* Offset in the batchbuffer */
904 int push_const_size
; /* in 256-bit register increments */
906 /* Binding table: pointers to SURFACE_STATE entries. */
907 uint32_t bind_bo_offset
;
908 uint32_t surf_offset
[BRW_MAX_SURFACES
];
910 /** SAMPLER_STATE count and table offset */
911 uint32_t sampler_count
;
912 uint32_t sampler_offset
;
917 * brw_context is derived from gl_context.
921 struct gl_context ctx
; /**< base class, must be first field */
925 void (*update_texture_surface
)(struct gl_context
*ctx
,
927 uint32_t *surf_offset
,
929 void (*update_renderbuffer_surface
)(struct brw_context
*brw
,
930 struct gl_renderbuffer
*rb
,
933 void (*update_null_renderbuffer_surface
)(struct brw_context
*brw
,
936 void (*create_raw_surface
)(struct brw_context
*brw
,
940 uint32_t *out_offset
,
942 void (*emit_buffer_surface_state
)(struct brw_context
*brw
,
943 uint32_t *out_offset
,
945 unsigned buffer_offset
,
946 unsigned surface_format
,
947 unsigned buffer_size
,
953 * Send the appropriate state packets to configure depth, stencil, and
954 * HiZ buffers (i965+ only)
956 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
957 struct intel_mipmap_tree
*depth_mt
,
958 uint32_t depth_offset
,
959 uint32_t depthbuffer_format
,
960 uint32_t depth_surface_type
,
961 struct intel_mipmap_tree
*stencil_mt
,
962 bool hiz
, bool separate_stencil
,
963 uint32_t width
, uint32_t height
,
964 uint32_t tile_x
, uint32_t tile_y
);
970 drm_intel_context
*hw_ctx
;
973 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
974 * and would need flushing before being used from another cache domain that
975 * isn't coherent with it (i.e. the sampler).
977 struct set
*render_cache
;
980 * Number of resets observed in the system at context creation.
982 * This is tracked in the context so that we can determine that another
985 uint32_t reset_count
;
987 struct intel_batchbuffer batch
;
992 uint32_t next_offset
;
996 * Set if rendering has occured to the drawable's front buffer.
998 * This is used in the DRI2 case to detect that glFlush should also copy
999 * the contents of the fake front buffer to the real front buffer.
1001 bool front_buffer_dirty
;
1003 /** Framerate throttling: @{ */
1004 drm_intel_bo
*first_post_swapbuffers_batch
;
1015 bool always_flush_batch
;
1016 bool always_flush_cache
;
1017 bool disable_throttling
;
1019 bool disable_derivative_optimization
;
1021 driOptionCache optionCache
;
1024 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
1026 GLenum reduced_primitive
;
1029 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
1030 * variable is set, this is the flag indicating to do expensive work that
1031 * might lead to a perf_debug() call.
1035 uint32_t max_gtt_map_object_size
;
1046 bool has_separate_stencil
;
1047 bool must_use_separate_stencil
;
1050 bool has_surface_tile_offset
;
1052 bool has_negative_rhw_bug
;
1058 * Some versions of Gen hardware don't do centroid interpolation correctly
1059 * on unlit pixels, causing incorrect values for derivatives near triangle
1060 * edges. Enabling this flag causes the fragment shader to use
1061 * non-centroid interpolation for unlit pixels, at the expense of two extra
1062 * fragment shader instructions.
1064 bool needs_unlit_centroid_workaround
;
1068 struct brw_state_flags dirty
;
1071 struct brw_cache cache
;
1073 /** IDs for meta stencil blit shader programs. */
1074 unsigned meta_stencil_blit_programs
[2];
1076 /* Whether a meta-operation is in progress. */
1077 bool meta_in_progress
;
1079 /* Whether the last depth/stencil packets were both NULL. */
1080 bool no_depth_or_stencil
;
1083 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
1084 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
1086 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
1090 /* Summary of size and varying of active arrays, so we can check
1091 * for changes to this state:
1093 unsigned int min_index
, max_index
;
1095 /* Offset from start of vertex buffer so we can avoid redefining
1096 * the same VB packed over and over again.
1098 unsigned int start_vertex_bias
;
1103 * Index buffer for this draw_prims call.
1105 * Updates are signaled by BRW_NEW_INDICES.
1107 const struct _mesa_index_buffer
*ib
;
1109 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
1113 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
1114 * avoid re-uploading the IB packet over and over if we're actually
1115 * referencing the same index buffer.
1117 unsigned int start_vertex_offset
;
1120 /* Active vertex program:
1122 const struct gl_vertex_program
*vertex_program
;
1123 const struct gl_geometry_program
*geometry_program
;
1124 const struct gl_fragment_program
*fragment_program
;
1127 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
1128 * that we don't have to reemit that state every time we change FBOs.
1133 * Platform specific constants containing the maximum number of threads
1134 * for each pipeline stage.
1140 /* BRW_NEW_URB_ALLOCATIONS:
1143 GLuint vsize
; /* vertex size plus header in urb registers */
1144 GLuint csize
; /* constant buffer size in urb registers */
1145 GLuint sfsize
; /* setup data size in urb registers */
1149 GLuint min_vs_entries
; /* Minimum number of VS entries */
1150 GLuint max_vs_entries
; /* Maximum number of VS entries */
1151 GLuint max_gs_entries
; /* Maximum number of GS entries */
1153 GLuint nr_vs_entries
;
1154 GLuint nr_gs_entries
;
1155 GLuint nr_clip_entries
;
1156 GLuint nr_sf_entries
;
1157 GLuint nr_cs_entries
;
1164 GLuint size
; /* Hardware URB size, in KB. */
1166 /* gen6: True if the most recently sent _3DSTATE_URB message allocated
1167 * URB space for the GS.
1169 bool gen6_gs_previously_active
;
1173 /* BRW_NEW_CURBE_OFFSETS:
1176 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1177 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1185 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1186 * for upload to the CURBE.
1188 drm_intel_bo
*curbe_bo
;
1189 /** Offset within curbe_bo of space for current curbe entry */
1190 GLuint curbe_offset
;
1194 * Layout of vertex data exiting the vertex shader.
1196 * BRW_NEW_VUE_MAP_VS is flagged when this VUE map changes.
1198 struct brw_vue_map vue_map_vs
;
1201 * Layout of vertex data exiting the geometry portion of the pipleine.
1202 * This comes from the geometry shader if one exists, otherwise from the
1205 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1207 struct brw_vue_map vue_map_geom_out
;
1210 struct brw_stage_state base
;
1211 struct brw_vs_prog_data
*prog_data
;
1215 struct brw_stage_state base
;
1216 struct brw_gs_prog_data
*prog_data
;
1219 * True if the 3DSTATE_GS command most recently emitted to the 3D
1220 * pipeline enabled the GS; false otherwise.
1226 struct brw_ff_gs_prog_data
*prog_data
;
1229 /** Offset in the program cache to the CLIP program pre-gen6 */
1230 uint32_t prog_offset
;
1231 uint32_t state_offset
;
1233 uint32_t bind_bo_offset
;
1234 uint32_t surf_offset
[BRW_MAX_GEN6_GS_SURFACES
];
1238 struct brw_clip_prog_data
*prog_data
;
1240 /** Offset in the program cache to the CLIP program pre-gen6 */
1241 uint32_t prog_offset
;
1243 /* Offset in the batch to the CLIP state on pre-gen6. */
1244 uint32_t state_offset
;
1246 /* As of gen6, this is the offset in the batch to the CLIP VP,
1254 struct brw_sf_prog_data
*prog_data
;
1256 /** Offset in the program cache to the CLIP program pre-gen6 */
1257 uint32_t prog_offset
;
1258 uint32_t state_offset
;
1260 bool viewport_transform_enable
;
1264 struct brw_stage_state base
;
1265 struct brw_wm_prog_data
*prog_data
;
1270 * Buffer object used in place of multisampled null render targets on
1271 * Gen6. See brw_update_null_renderbuffer_surface().
1273 drm_intel_bo
*multisampled_null_render_target_bo
;
1274 uint32_t fast_clear_op
;
1279 uint32_t state_offset
;
1280 uint32_t blend_state_offset
;
1281 uint32_t depth_stencil_state_offset
;
1286 struct brw_query_object
*obj
;
1291 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1292 const int *statistics_registers
;
1294 /** The number of active monitors using OA counters. */
1298 * A buffer object storing OA counter snapshots taken at the start and
1299 * end of each batch (creating "bookends" around the batch).
1301 drm_intel_bo
*bookend_bo
;
1303 /** The number of snapshots written to bookend_bo. */
1304 int bookend_snapshots
;
1307 * An array of monitors whose results haven't yet been assembled based on
1308 * the data in buffer objects.
1310 * These may be active, or have already ended. However, the results
1311 * have not been requested.
1313 struct brw_perf_monitor_object
**unresolved
;
1314 int unresolved_elements
;
1315 int unresolved_array_size
;
1318 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1319 * the counter which MI_REPORT_PERF_COUNT stores there.
1321 const int *oa_snapshot_layout
;
1323 /** Number of 32-bit entries in a hardware counter snapshot. */
1324 int entries_per_oa_snapshot
;
1328 const struct brw_tracked_state
**atoms
;
1330 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1334 enum aub_state_struct_type type
;
1335 } *state_batch_list
;
1336 int state_batch_count
;
1338 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1339 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1341 /* Interpolation modes, one byte per vue slot.
1342 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1344 struct interpolation_mode_map interpolation_mode
;
1346 /* PrimitiveRestart */
1349 bool enable_cut_index
;
1352 /** Computed depth/stencil/hiz state from the current attached
1353 * renderbuffers, valid only during the drawing state upload loop after
1354 * brw_workaround_depthstencil_alignment().
1357 struct intel_mipmap_tree
*depth_mt
;
1358 struct intel_mipmap_tree
*stencil_mt
;
1360 /* Inter-tile (page-aligned) byte offsets. */
1361 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1362 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1363 uint32_t tile_x
, tile_y
;
1366 uint32_t num_instances
;
1371 struct gl_shader_program
**shader_programs
;
1372 struct gl_program
**programs
;
1373 enum shader_time_shader_type
*types
;
1374 uint64_t *cumulative
;
1380 struct brw_fast_clear_state
*fast_clear_state
;
1382 __DRIcontext
*driContext
;
1383 struct intel_screen
*intelScreen
;
1386 /*======================================================================
1389 void brwInitVtbl( struct brw_context
*brw
);
1392 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1394 /*======================================================================
1397 extern const char *const brw_vendor_string
;
1399 extern const char *brw_get_renderer_string(unsigned deviceID
);
1402 DRI_CONF_BO_REUSE_DISABLED
,
1403 DRI_CONF_BO_REUSE_ALL
1406 void intel_update_renderbuffers(__DRIcontext
*context
,
1407 __DRIdrawable
*drawable
);
1408 void intel_prepare_render(struct brw_context
*brw
);
1410 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1411 __DRIdrawable
*drawable
);
1413 GLboolean
brwCreateContext(gl_api api
,
1414 const struct gl_config
*mesaVis
,
1415 __DRIcontext
*driContextPriv
,
1416 unsigned major_version
,
1417 unsigned minor_version
,
1421 void *sharedContextPrivate
);
1423 /*======================================================================
1426 GLuint
brw_get_rb_for_slice(struct brw_context
*brw
,
1427 struct intel_mipmap_tree
*mt
,
1428 unsigned level
, unsigned layer
, bool flat
);
1430 void brw_meta_updownsample(struct brw_context
*brw
,
1431 struct intel_mipmap_tree
*src
,
1432 struct intel_mipmap_tree
*dst
);
1434 void brw_meta_fbo_stencil_blit(struct brw_context
*brw
,
1435 GLfloat srcX0
, GLfloat srcY0
,
1436 GLfloat srcX1
, GLfloat srcY1
,
1437 GLfloat dstX0
, GLfloat dstY0
,
1438 GLfloat dstX1
, GLfloat dstY1
);
1440 void brw_meta_stencil_updownsample(struct brw_context
*brw
,
1441 struct intel_mipmap_tree
*src
,
1442 struct intel_mipmap_tree
*dst
);
1444 bool brw_meta_fast_clear(struct brw_context
*brw
,
1445 struct gl_framebuffer
*fb
,
1447 bool partial_clear
);
1450 brw_meta_resolve_color(struct brw_context
*brw
,
1451 struct intel_mipmap_tree
*mt
);
1453 brw_meta_fast_clear_free(struct brw_context
*brw
);
1456 /*======================================================================
1459 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1460 uint32_t depth_level
,
1461 uint32_t depth_layer
,
1462 struct intel_mipmap_tree
*stencil_mt
,
1463 uint32_t *out_tile_mask_x
,
1464 uint32_t *out_tile_mask_y
);
1465 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1466 GLbitfield clear_mask
);
1468 /* brw_object_purgeable.c */
1469 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1471 /*======================================================================
1474 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1475 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1476 void brw_emit_query_begin(struct brw_context
*brw
);
1477 void brw_emit_query_end(struct brw_context
*brw
);
1479 /** gen6_queryobj.c */
1480 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1481 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1482 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1483 void brw_store_register_mem64(struct brw_context
*brw
,
1484 drm_intel_bo
*bo
, uint32_t reg
, int idx
);
1486 /** intel_batchbuffer.c */
1487 void brw_load_register_mem(struct brw_context
*brw
,
1490 uint32_t read_domains
, uint32_t write_domain
,
1493 /*======================================================================
1496 void brw_debug_batch(struct brw_context
*brw
);
1497 void brw_annotate_aub(struct brw_context
*brw
);
1499 /*======================================================================
1502 void brw_validate_textures( struct brw_context
*brw
);
1505 /*======================================================================
1508 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1510 int brw_get_scratch_size(int size
);
1511 void brw_get_scratch_bo(struct brw_context
*brw
,
1512 drm_intel_bo
**scratch_bo
, int size
);
1513 void brw_init_shader_time(struct brw_context
*brw
);
1514 int brw_get_shader_time_index(struct brw_context
*brw
,
1515 struct gl_shader_program
*shader_prog
,
1516 struct gl_program
*prog
,
1517 enum shader_time_shader_type type
);
1518 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1519 void brw_destroy_shader_time(struct brw_context
*brw
);
1523 void brw_upload_urb_fence(struct brw_context
*brw
);
1527 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1529 /* brw_fs_reg_allocate.cpp
1531 void brw_fs_alloc_reg_sets(struct intel_screen
*screen
);
1533 /* brw_vec4_reg_allocate.cpp */
1534 void brw_vec4_alloc_reg_set(struct intel_screen
*screen
);
1537 int brw_disassemble_inst(FILE *file
, struct brw_context
*brw
,
1538 struct brw_inst
*inst
, bool is_compacted
);
1541 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1543 /* brw_draw_upload.c */
1544 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1545 const struct gl_client_array
*glarray
);
1546 unsigned brw_get_index_type(GLenum type
);
1547 void brw_prepare_vertices(struct brw_context
*brw
);
1549 /* brw_wm_surface_state.c */
1550 void brw_init_surface_formats(struct brw_context
*brw
);
1551 void brw_create_constant_surface(struct brw_context
*brw
,
1555 uint32_t *out_offset
,
1557 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1559 uint32_t *surf_offset
);
1561 brw_update_sol_surface(struct brw_context
*brw
,
1562 struct gl_buffer_object
*buffer_obj
,
1563 uint32_t *out_offset
, unsigned num_vector_components
,
1564 unsigned stride_dwords
, unsigned offset_dwords
);
1565 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1566 struct gl_shader
*shader
,
1567 struct brw_stage_state
*stage_state
,
1568 struct brw_stage_prog_data
*prog_data
);
1569 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1570 struct gl_shader_program
*prog
,
1571 struct brw_stage_state
*stage_state
,
1572 struct brw_stage_prog_data
*prog_data
);
1574 /* brw_surface_formats.c */
1575 bool brw_is_hiz_depth_format(struct brw_context
*ctx
, mesa_format format
);
1576 bool brw_render_target_supported(struct brw_context
*brw
,
1577 struct gl_renderbuffer
*rb
);
1578 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1580 /* brw_performance_monitor.c */
1581 void brw_init_performance_monitors(struct brw_context
*brw
);
1582 void brw_dump_perf_monitors(struct brw_context
*brw
);
1583 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1584 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1586 /* intel_buffer_objects.c */
1587 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1588 const char *bo_name
);
1589 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1590 const char *bo_name
);
1592 /* intel_extensions.c */
1593 extern void intelInitExtensions(struct gl_context
*ctx
);
1596 extern int intel_translate_shadow_compare_func(GLenum func
);
1597 extern int intel_translate_compare_func(GLenum func
);
1598 extern int intel_translate_stencil_op(GLenum op
);
1599 extern int intel_translate_logic_op(GLenum opcode
);
1601 /* intel_syncobj.c */
1602 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1605 struct gl_transform_feedback_object
*
1606 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1608 brw_delete_transform_feedback(struct gl_context
*ctx
,
1609 struct gl_transform_feedback_object
*obj
);
1611 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1612 struct gl_transform_feedback_object
*obj
);
1614 brw_end_transform_feedback(struct gl_context
*ctx
,
1615 struct gl_transform_feedback_object
*obj
);
1617 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1618 struct gl_transform_feedback_object
*obj
,
1621 /* gen7_sol_state.c */
1623 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1624 struct gl_transform_feedback_object
*obj
);
1626 gen7_end_transform_feedback(struct gl_context
*ctx
,
1627 struct gl_transform_feedback_object
*obj
);
1629 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1630 struct gl_transform_feedback_object
*obj
);
1632 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1633 struct gl_transform_feedback_object
*obj
);
1635 /* brw_blorp_blit.cpp */
1637 brw_blorp_framebuffer(struct brw_context
*brw
,
1638 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1639 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1640 GLbitfield mask
, GLenum filter
);
1643 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1644 struct gl_renderbuffer
*src_rb
,
1645 struct gl_texture_image
*dst_image
,
1647 int srcX0
, int srcY0
,
1648 int dstX0
, int dstY0
,
1649 int width
, int height
);
1651 /* gen6_multisample_state.c */
1653 gen6_determine_sample_mask(struct brw_context
*brw
);
1656 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1657 unsigned num_samples
);
1659 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1661 gen6_get_sample_position(struct gl_context
*ctx
,
1662 struct gl_framebuffer
*fb
,
1666 /* gen8_multisample_state.c */
1667 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1668 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1672 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1673 unsigned gs_size
, unsigned fs_size
);
1676 gen7_emit_urb_state(struct brw_context
*brw
,
1677 unsigned nr_vs_entries
, unsigned vs_size
,
1678 unsigned vs_start
, unsigned nr_gs_entries
,
1679 unsigned gs_size
, unsigned gs_start
);
1684 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1686 /*======================================================================
1687 * Inline conversion functions. These are better-typed than the
1688 * macros used previously:
1690 static inline struct brw_context
*
1691 brw_context( struct gl_context
*ctx
)
1693 return (struct brw_context
*)ctx
;
1696 static inline struct brw_vertex_program
*
1697 brw_vertex_program(struct gl_vertex_program
*p
)
1699 return (struct brw_vertex_program
*) p
;
1702 static inline const struct brw_vertex_program
*
1703 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1705 return (const struct brw_vertex_program
*) p
;
1708 static inline struct brw_geometry_program
*
1709 brw_geometry_program(struct gl_geometry_program
*p
)
1711 return (struct brw_geometry_program
*) p
;
1714 static inline struct brw_fragment_program
*
1715 brw_fragment_program(struct gl_fragment_program
*p
)
1717 return (struct brw_fragment_program
*) p
;
1720 static inline const struct brw_fragment_program
*
1721 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1723 return (const struct brw_fragment_program
*) p
;
1727 * Pre-gen6, the register file of the EUs was shared between threads,
1728 * and each thread used some subset allocated on a 16-register block
1729 * granularity. The unit states wanted these block counts.
1732 brw_register_blocks(int reg_count
)
1734 return ALIGN(reg_count
, 16) / 16 - 1;
1737 static inline uint32_t
1738 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1739 uint32_t prog_offset
)
1741 if (brw
->gen
>= 5) {
1742 /* Using state base address. */
1746 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1750 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1752 return brw
->cache
.bo
->offset64
+ prog_offset
;
1755 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1756 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1757 struct exec_list
*instructions
);
1758 bool brw_do_lower_unnormalized_offset(struct exec_list
*instructions
);
1760 struct opcode_desc
{
1766 extern const struct opcode_desc opcode_descs
[128];
1767 extern const char * const conditional_modifier
[16];
1770 brw_emit_depthbuffer(struct brw_context
*brw
);
1773 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1774 struct intel_mipmap_tree
*depth_mt
,
1775 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1776 uint32_t depth_surface_type
,
1777 struct intel_mipmap_tree
*stencil_mt
,
1778 bool hiz
, bool separate_stencil
,
1779 uint32_t width
, uint32_t height
,
1780 uint32_t tile_x
, uint32_t tile_y
);
1783 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1784 struct intel_mipmap_tree
*depth_mt
,
1785 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1786 uint32_t depth_surface_type
,
1787 struct intel_mipmap_tree
*stencil_mt
,
1788 bool hiz
, bool separate_stencil
,
1789 uint32_t width
, uint32_t height
,
1790 uint32_t tile_x
, uint32_t tile_y
);
1793 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1794 struct intel_mipmap_tree
*depth_mt
,
1795 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1796 uint32_t depth_surface_type
,
1797 struct intel_mipmap_tree
*stencil_mt
,
1798 bool hiz
, bool separate_stencil
,
1799 uint32_t width
, uint32_t height
,
1800 uint32_t tile_x
, uint32_t tile_y
);
1802 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1803 struct intel_mipmap_tree
*depth_mt
,
1804 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1805 uint32_t depth_surface_type
,
1806 struct intel_mipmap_tree
*stencil_mt
,
1807 bool hiz
, bool separate_stencil
,
1808 uint32_t width
, uint32_t height
,
1809 uint32_t tile_x
, uint32_t tile_y
);
1811 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1812 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);
1814 uint32_t get_hw_prim_for_gl_prim(int mode
);
1817 brw_setup_vec4_key_clip_info(struct brw_context
*brw
,
1818 struct brw_vec4_prog_key
*key
,
1819 bool program_uses_clip_distance
);
1822 gen6_upload_push_constants(struct brw_context
*brw
,
1823 const struct gl_program
*prog
,
1824 const struct brw_stage_prog_data
*prog_data
,
1825 struct brw_stage_state
*stage_state
,
1826 enum aub_state_struct_type type
);
1828 /* ================================================================
1829 * From linux kernel i386 header files, copes with odd sizes better
1830 * than COPY_DWORDS would:
1831 * XXX Put this in src/mesa/main/imports.h ???
1833 #if defined(i386) || defined(__i386__)
1834 static inline void * __memcpy(void * to
, const void * from
, size_t n
)
1837 __asm__
__volatile__(
1842 "1:\ttestb $1,%b4\n\t"
1846 : "=&c" (d0
), "=&D" (d1
), "=&S" (d2
)
1847 :"0" (n
/4), "q" (n
),"1" ((long) to
),"2" ((long) from
)
1852 #define __memcpy(a,b,c) memcpy(a,b,c)