2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
38 #include "main/imports.h"
39 #include "main/macros.h"
41 #include "main/mtypes.h"
42 #include "brw_structs.h"
43 #include "intel_aub.h"
44 #include "program/prog_parameter.h"
48 /* Evil hack for using libdrm in a c++ compiler. */
53 #include <intel_bufmgr.h>
63 #include "intel_debug.h"
64 #include "intel_screen.h"
65 #include "intel_tex_obj.h"
66 #include "intel_resolve_map.h"
70 * URB - uniform resource buffer. A mid-sized buffer which is
71 * partitioned between the fixed function units and used for passing
72 * values (vertices, primitives, constants) between them.
74 * CURBE - constant URB entry. An urb region (entry) used to hold
75 * constant values which the fixed function units can be instructed to
76 * preload into the GRF when spawning a thread.
78 * VUE - vertex URB entry. An urb entry holding a vertex and usually
79 * a vertex header. The header contains control information and
80 * things like primitive type, Begin/end flags and clip codes.
82 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
83 * unit holding rasterization and interpolation parameters.
85 * GRF - general register file. One of several register files
86 * addressable by programmed threads. The inputs (r0, payload, curbe,
87 * urb) of the thread are preloaded to this area before the thread is
88 * spawned. The registers are individually 8 dwords wide and suitable
89 * for general usage. Registers holding thread input values are not
90 * special and may be overwritten.
92 * MRF - message register file. Threads communicate (and terminate)
93 * by sending messages. Message parameters are placed in contiguous
94 * MRF registers. All program output is via these messages. URB
95 * entries are populated by sending a message to the shared URB
96 * function containing the new data, together with a control word,
97 * often an unmodified copy of R0.
99 * R0 - GRF register 0. Typically holds control information used when
100 * sending messages to other threads.
102 * EU or GEN4 EU: The name of the programmable subsystem of the
103 * i965 hardware. Threads are executed by the EU, the registers
104 * described above are part of the EU architecture.
106 * Fixed function units:
108 * CS - Command streamer. Notional first unit, little software
109 * interaction. Holds the URB entries used for constant data, ie the
112 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
113 * this unit is responsible for pulling vertices out of vertex buffers
114 * in vram and injecting them into the processing pipe as VUEs. If
115 * enabled, it first passes them to a VS thread which is a good place
116 * for the driver to implement any active vertex shader.
118 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
119 * enabled, incoming strips etc are passed to GS threads in individual
120 * line/triangle/point units. The GS thread may perform arbitary
121 * computation and emit whatever primtives with whatever vertices it
122 * chooses. This makes GS an excellent place to implement GL's
123 * unfilled polygon modes, though of course it is capable of much
124 * more. Additionally, GS is used to translate away primitives not
125 * handled by latter units, including Quads and Lineloops.
127 * CS - Clipper. Mesa's clipping algorithms are imported to run on
128 * this unit. The fixed function part performs cliptesting against
129 * the 6 fixed clipplanes and makes descisions on whether or not the
130 * incoming primitive needs to be passed to a thread for clipping.
131 * User clip planes are handled via cooperation with the VS thread.
133 * SF - Strips Fans or Setup: Triangles are prepared for
134 * rasterization. Interpolation coefficients are calculated.
135 * Flatshading and two-side lighting usually performed here.
137 * WM - Windower. Interpolation of vertex attributes performed here.
138 * Fragment shader implemented here. SIMD aspects of EU taken full
139 * advantage of, as pixels are processed in blocks of 16.
141 * CC - Color Calculator. No EU threads associated with this unit.
142 * Handles blending and (presumably) depth and stencil testing.
147 struct brw_vs_prog_key
;
148 struct brw_vec4_prog_key
;
149 struct brw_wm_prog_key
;
150 struct brw_wm_prog_data
;
154 BRW_STATE_FRAGMENT_PROGRAM
,
155 BRW_STATE_GEOMETRY_PROGRAM
,
156 BRW_STATE_VERTEX_PROGRAM
,
157 BRW_STATE_CURBE_OFFSETS
,
158 BRW_STATE_REDUCED_PRIMITIVE
,
163 BRW_STATE_VS_BINDING_TABLE
,
164 BRW_STATE_GS_BINDING_TABLE
,
165 BRW_STATE_PS_BINDING_TABLE
,
169 BRW_STATE_INDEX_BUFFER
,
170 BRW_STATE_VS_CONSTBUF
,
171 BRW_STATE_GS_CONSTBUF
,
172 BRW_STATE_PROGRAM_CACHE
,
173 BRW_STATE_STATE_BASE_ADDRESS
,
174 BRW_STATE_VUE_MAP_VS
,
175 BRW_STATE_VUE_MAP_GEOM_OUT
,
176 BRW_STATE_TRANSFORM_FEEDBACK
,
177 BRW_STATE_RASTERIZER_DISCARD
,
179 BRW_STATE_UNIFORM_BUFFER
,
180 BRW_STATE_ATOMIC_BUFFER
,
181 BRW_STATE_META_IN_PROGRESS
,
182 BRW_STATE_INTERPOLATION_MAP
,
183 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
184 BRW_STATE_NUM_SAMPLES
,
188 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
189 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
190 #define BRW_NEW_GEOMETRY_PROGRAM (1 << BRW_STATE_GEOMETRY_PROGRAM)
191 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
192 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
193 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
194 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
195 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
196 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
197 #define BRW_NEW_SURFACES (1 << BRW_STATE_SURFACES)
198 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
199 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
200 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
201 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
202 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
204 * Used for any batch entry with a relocated pointer that will be used
205 * by any 3D rendering.
207 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
208 /** \see brw.state.depth_region */
209 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
210 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
211 #define BRW_NEW_GS_CONSTBUF (1 << BRW_STATE_GS_CONSTBUF)
212 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
213 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
214 #define BRW_NEW_VUE_MAP_VS (1 << BRW_STATE_VUE_MAP_VS)
215 #define BRW_NEW_VUE_MAP_GEOM_OUT (1 << BRW_STATE_VUE_MAP_GEOM_OUT)
216 #define BRW_NEW_TRANSFORM_FEEDBACK (1 << BRW_STATE_TRANSFORM_FEEDBACK)
217 #define BRW_NEW_RASTERIZER_DISCARD (1 << BRW_STATE_RASTERIZER_DISCARD)
218 #define BRW_NEW_STATS_WM (1 << BRW_STATE_STATS_WM)
219 #define BRW_NEW_UNIFORM_BUFFER (1 << BRW_STATE_UNIFORM_BUFFER)
220 #define BRW_NEW_ATOMIC_BUFFER (1 << BRW_STATE_ATOMIC_BUFFER)
221 #define BRW_NEW_META_IN_PROGRESS (1 << BRW_STATE_META_IN_PROGRESS)
222 #define BRW_NEW_INTERPOLATION_MAP (1 << BRW_STATE_INTERPOLATION_MAP)
223 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1 << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
224 #define BRW_NEW_NUM_SAMPLES (1 << BRW_STATE_NUM_SAMPLES)
226 struct brw_state_flags
{
227 /** State update flags signalled by mesa internals */
230 * State update flags signalled as the result of brw_tracked_state updates
234 * State update flags that used to be signalled by brw_state_cache.c
237 * Now almost all of that state is just streamed out on demand, but the
238 * flags for those state blobs updating have stayed in the same bitfield.
239 * brw_state_cache.c still flags CACHE_NEW_*_PROG.
244 /** Subclass of Mesa vertex program */
245 struct brw_vertex_program
{
246 struct gl_vertex_program program
;
251 /** Subclass of Mesa geometry program */
252 struct brw_geometry_program
{
253 struct gl_geometry_program program
;
254 unsigned id
; /**< serial no. to identify geom progs, never re-used */
258 /** Subclass of Mesa fragment program */
259 struct brw_fragment_program
{
260 struct gl_fragment_program program
;
261 GLuint id
; /**< serial no. to identify frag progs, never re-used */
265 /** Subclass of Mesa compute program */
266 struct brw_compute_program
{
267 struct gl_compute_program program
;
268 unsigned id
; /**< serial no. to identify compute progs, never re-used */
273 struct gl_shader base
;
278 /* Note: If adding fields that need anything besides a normal memcmp() for
279 * comparing them, be sure to go fix brw_stage_prog_data_compare().
281 struct brw_stage_prog_data
{
283 /** size of our binding table. */
287 * surface indices for the various groups of surfaces
289 uint32_t pull_constants_start
;
290 uint32_t texture_start
;
291 uint32_t gather_texture_start
;
294 uint32_t shader_time_start
;
298 GLuint nr_params
; /**< number of float params/constants */
299 GLuint nr_pull_params
;
302 * Register where the thread expects to find input data from the URB
303 * (typically uniforms, followed by vertex or fragment attributes).
305 unsigned dispatch_grf_start_reg
;
307 /* Pointers to tracked values (only valid once
308 * _mesa_load_state_parameters has been called at runtime).
310 * These must be the last fields of the struct (see
311 * brw_stage_prog_data_compare()).
313 const gl_constant_value
**param
;
314 const gl_constant_value
**pull_param
;
317 /* Data about a particular attempt to compile a program. Note that
318 * there can be many of these, each in a different GL state
319 * corresponding to a different brw_wm_prog_key struct, with different
322 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
325 struct brw_wm_prog_data
{
326 struct brw_stage_prog_data base
;
328 GLuint curb_read_length
;
329 GLuint num_varying_inputs
;
331 GLuint dispatch_grf_start_reg_16
;
333 GLuint reg_blocks_16
;
334 GLuint total_scratch
;
338 * surface indices the WM-specific surfaces
340 uint32_t render_target_start
;
346 bool uses_pos_offset
;
348 uint32_t prog_offset_16
;
351 * Mask of which interpolation modes are required by the fragment shader.
352 * Used in hardware setup on gen6+.
354 uint32_t barycentric_interp_modes
;
357 * Map from gl_varying_slot to the position within the FS setup data
358 * payload where the varying's attribute vertex deltas should be delivered.
359 * For varying slots that are not used by the FS, the value is -1.
361 int urb_setup
[VARYING_SLOT_MAX
];
365 * Enum representing the i965-specific vertex results that don't correspond
366 * exactly to any element of gl_varying_slot. The values of this enum are
367 * assigned such that they don't conflict with gl_varying_slot.
371 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
372 BRW_VARYING_SLOT_PAD
,
374 * Technically this is not a varying but just a placeholder that
375 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
376 * builtin variable to be compiled correctly. see compile_sf_prog() for
379 BRW_VARYING_SLOT_PNTC
,
380 BRW_VARYING_SLOT_COUNT
385 * Data structure recording the relationship between the gl_varying_slot enum
386 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
387 * single octaword within the VUE (128 bits).
389 * Note that each BRW register contains 256 bits (2 octawords), so when
390 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
391 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
392 * in a vertex shader), each register corresponds to a single VUE slot, since
393 * it contains data for two separate vertices.
397 * Bitfield representing all varying slots that are (a) stored in this VUE
398 * map, and (b) actually written by the shader. Does not include any of
399 * the additional varying slots defined in brw_varying_slot.
401 GLbitfield64 slots_valid
;
404 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
405 * not stored in a slot (because they are not written, or because
406 * additional processing is applied before storing them in the VUE), the
409 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
412 * Map from VUE slot to gl_varying_slot value. For slots that do not
413 * directly correspond to a gl_varying_slot, the value comes from
416 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
417 * simplifies code that uses the value stored in slot_to_varying to
418 * create a bit mask).
420 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
423 * Total number of VUE slots in use
429 * Convert a VUE slot number into a byte offset within the VUE.
431 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
437 * Convert a vertex output (brw_varying_slot) into a byte offset within the
440 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
443 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
446 void brw_compute_vue_map(struct brw_context
*brw
, struct brw_vue_map
*vue_map
,
447 GLbitfield64 slots_valid
);
451 * Bitmask indicating which fragment shader inputs represent varyings (and
452 * hence have to be delivered to the fragment shader by the SF/SBE stage).
454 #define BRW_FS_VARYING_INPUT_MASK \
455 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
456 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
460 * Mapping of VUE map slots to interpolation modes.
462 struct interpolation_mode_map
{
463 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
466 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
468 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
469 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
475 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
477 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
478 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
485 struct brw_sf_prog_data
{
486 GLuint urb_read_length
;
489 /* Each vertex may have upto 12 attributes, 4 components each,
490 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
493 * Actually we use 4 for each, so call it 12 rows.
495 GLuint urb_entry_size
;
500 * We always program SF to start reading at an offset of 1 (2 varying slots)
501 * from the start of the vertex URB entry. This causes it to skip:
502 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
503 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
505 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
508 struct brw_clip_prog_data
{
509 GLuint curb_read_length
; /* user planes? */
511 GLuint urb_read_length
;
515 struct brw_ff_gs_prog_data
{
516 GLuint urb_read_length
;
520 * Gen6 transform feedback: Amount by which the streaming vertex buffer
521 * indices should be incremented each time the GS is invoked.
523 unsigned svbi_postincrement_value
;
527 /* Note: brw_vec4_prog_data_compare() must be updated when adding fields to
530 struct brw_vec4_prog_data
{
531 struct brw_stage_prog_data base
;
532 struct brw_vue_map vue_map
;
534 GLuint curb_read_length
;
535 GLuint urb_read_length
;
537 GLuint total_scratch
;
539 /* Used for calculating urb partitions. In the VS, this is the size of the
540 * URB entry used for both input and output to the thread. In the GS, this
541 * is the size of the URB entry used for output.
543 GLuint urb_entry_size
;
547 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
550 struct brw_vs_prog_data
{
551 struct brw_vec4_prog_data base
;
553 GLbitfield64 inputs_read
;
559 /* Note: brw_gs_prog_data_compare() must be updated when adding fields to
562 struct brw_gs_prog_data
564 struct brw_vec4_prog_data base
;
567 * Size of an output vertex, measured in HWORDS (32 bytes).
569 unsigned output_vertex_size_hwords
;
571 unsigned output_topology
;
574 * Size of the control data (cut bits or StreamID bits), in hwords (32
575 * bytes). 0 if there is no control data.
577 unsigned control_data_header_size_hwords
;
580 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
581 * if the control data is StreamID bits, or
582 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
583 * Ignored if control_data_header_size is 0.
585 unsigned control_data_format
;
587 bool include_primitive_id
;
592 * True if the thread should be dispatched in DUAL_INSTANCE mode, false if
593 * it should be dispatched in DUAL_OBJECT mode.
595 bool dual_instanced_dispatch
;
598 /** Number of texture sampler units */
599 #define BRW_MAX_TEX_UNIT 32
601 /** Max number of render targets in a shader */
602 #define BRW_MAX_DRAW_BUFFERS 8
604 /** Max number of atomic counter buffer objects in a shader */
605 #define BRW_MAX_ABO 16
608 * Max number of binding table entries used for stream output.
610 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
611 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
613 * On Gen6, the size of transform feedback data is limited not by the number
614 * of components but by the number of binding table entries we set aside. We
615 * use one binding table entry for a float, one entry for a vector, and one
616 * entry per matrix column. Since the only way we can communicate our
617 * transform feedback capabilities to the client is via
618 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
619 * worst case, in which all the varyings are floats, so we use up one binding
620 * table entry per component. Therefore we need to set aside at least 64
621 * binding table entries for use by transform feedback.
623 * Note: since we don't currently pack varyings, it is currently impossible
624 * for the client to actually use up all of these binding table entries--if
625 * all of their varyings were floats, they would run out of varying slots and
626 * fail to link. But that's a bug, so it seems prudent to go ahead and
627 * allocate the number of binding table entries we will need once the bug is
630 #define BRW_MAX_SOL_BINDINGS 64
632 /** Maximum number of actual buffers used for stream output */
633 #define BRW_MAX_SOL_BUFFERS 4
635 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
636 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
639 2 /* shader time, pull constants */)
641 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
642 #define BRW_MAX_GEN6_GS_SURFACES SURF_INDEX_GEN6_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
645 * Stride in bytes between shader_time entries.
647 * We separate entries by a cacheline to reduce traffic between EUs writing to
650 #define SHADER_TIME_STRIDE 64
657 BRW_BLORP_CONST_COLOR_PROG
,
662 BRW_SF_UNIT
, /* scissor state on gen6 */
675 struct brw_cache_item
{
677 * Effectively part of the key, cache_id identifies what kind of state
678 * buffer is involved, and also which brw->state.dirty.cache flag should
679 * be set when this cache item is chosen.
681 enum brw_cache_id cache_id
;
682 /** 32-bit hash of the key data */
684 GLuint key_size
; /* for variable-sized keys */
691 struct brw_cache_item
*next
;
695 typedef bool (*cache_aux_compare_func
)(const void *a
, const void *b
);
696 typedef void (*cache_aux_free_func
)(const void *aux
);
699 struct brw_context
*brw
;
701 struct brw_cache_item
**items
;
703 GLuint size
, n_items
;
705 uint32_t next_offset
;
709 * Optional functions used in determining whether the prog_data for a new
710 * cache item matches an existing cache item (in case there's relevant data
711 * outside of the prog_data). If NULL, a plain memcmp is done.
713 cache_aux_compare_func aux_compare
[BRW_MAX_CACHE
];
714 /** Optional functions for freeing other pointers attached to a prog_data. */
715 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
719 /* Considered adding a member to this struct to document which flags
720 * an update might raise so that ordering of the state atoms can be
721 * checked or derived at runtime. Dropped the idea in favor of having
722 * a debug mode where the state is monitored for flags which are
723 * raised that have already been tested against.
725 struct brw_tracked_state
{
726 struct brw_state_flags dirty
;
727 void (*emit
)( struct brw_context
*brw
);
730 enum shader_time_shader_type
{
746 /* Flags for brw->state.cache.
748 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
749 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
750 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
751 #define CACHE_NEW_BLORP_BLIT_PROG (1<<BRW_BLORP_BLIT_PROG)
752 #define CACHE_NEW_BLORP_CONST_COLOR_PROG (1<<BRW_BLORP_CONST_COLOR_PROG)
753 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
754 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
755 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
756 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
757 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
758 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
759 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
760 #define CACHE_NEW_FF_GS_UNIT (1<<BRW_FF_GS_UNIT)
761 #define CACHE_NEW_FF_GS_PROG (1<<BRW_FF_GS_PROG)
762 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
763 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
764 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
765 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
767 struct brw_vertex_buffer
{
768 /** Buffer object containing the uploaded vertex data */
771 /** Byte stride between elements in the uploaded array */
775 struct brw_vertex_element
{
776 const struct gl_client_array
*glarray
;
780 /** Offset of the first element within the buffer object */
784 struct brw_query_object
{
785 struct gl_query_object Base
;
787 /** Last query BO associated with this query. */
790 /** Last index in bo with query data for this object. */
794 struct intel_sync_object
{
795 struct gl_sync_object Base
;
797 /** Batch associated with this sync object */
807 struct intel_batchbuffer
{
808 /** Current batchbuffer being queued up. */
810 /** Last BO submitted to the hardware. Used for glFinish(). */
811 drm_intel_bo
*last_bo
;
812 /** BO for post-sync nonzero writes for gen6 workaround. */
813 drm_intel_bo
*workaround_bo
;
814 bool need_workaround_flush
;
816 uint16_t emit
, total
;
817 uint16_t used
, reserved_space
;
820 #define BATCH_SZ (8192*sizeof(uint32_t))
822 uint32_t state_batch_offset
;
823 enum brw_gpu_ring ring
;
824 bool needs_sol_reset
;
832 #define BRW_MAX_XFB_STREAMS 4
834 struct brw_transform_feedback_object
{
835 struct gl_transform_feedback_object base
;
837 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
838 drm_intel_bo
*offset_bo
;
840 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
843 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
844 GLenum primitive_mode
;
847 * Count of primitives generated during this transform feedback operation.
850 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
851 drm_intel_bo
*prim_count_bo
;
852 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
856 * Number of vertices written between last Begin/EndTransformFeedback().
858 * Used to implement DrawTransformFeedback().
860 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
861 bool vertices_written_valid
;
865 * Data shared between each programmable stage in the pipeline (vs, gs, and
868 struct brw_stage_state
870 gl_shader_stage stage
;
871 struct brw_stage_prog_data
*prog_data
;
874 * Optional scratch buffer used to store spilled register values and
875 * variably-indexed GRF arrays.
877 drm_intel_bo
*scratch_bo
;
879 /** Offset in the program cache to the program */
880 uint32_t prog_offset
;
882 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
883 uint32_t state_offset
;
885 uint32_t push_const_offset
; /* Offset in the batchbuffer */
886 int push_const_size
; /* in 256-bit register increments */
888 /* Binding table: pointers to SURFACE_STATE entries. */
889 uint32_t bind_bo_offset
;
890 uint32_t surf_offset
[BRW_MAX_SURFACES
];
892 /** SAMPLER_STATE count and table offset */
893 uint32_t sampler_count
;
894 uint32_t sampler_offset
;
899 * brw_context is derived from gl_context.
903 struct gl_context ctx
; /**< base class, must be first field */
907 void (*update_texture_surface
)(struct gl_context
*ctx
,
909 uint32_t *surf_offset
,
911 void (*update_renderbuffer_surface
)(struct brw_context
*brw
,
912 struct gl_renderbuffer
*rb
,
915 void (*update_null_renderbuffer_surface
)(struct brw_context
*brw
,
918 void (*create_raw_surface
)(struct brw_context
*brw
,
922 uint32_t *out_offset
,
924 void (*emit_buffer_surface_state
)(struct brw_context
*brw
,
925 uint32_t *out_offset
,
927 unsigned buffer_offset
,
928 unsigned surface_format
,
929 unsigned buffer_size
,
935 * Send the appropriate state packets to configure depth, stencil, and
936 * HiZ buffers (i965+ only)
938 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
939 struct intel_mipmap_tree
*depth_mt
,
940 uint32_t depth_offset
,
941 uint32_t depthbuffer_format
,
942 uint32_t depth_surface_type
,
943 struct intel_mipmap_tree
*stencil_mt
,
944 bool hiz
, bool separate_stencil
,
945 uint32_t width
, uint32_t height
,
946 uint32_t tile_x
, uint32_t tile_y
);
952 drm_intel_context
*hw_ctx
;
955 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
956 * and would need flushing before being used from another cache domain that
957 * isn't coherent with it (i.e. the sampler).
959 struct set
*render_cache
;
962 * Number of resets observed in the system at context creation.
964 * This is tracked in the context so that we can determine that another
967 uint32_t reset_count
;
969 struct intel_batchbuffer batch
;
974 uint32_t next_offset
;
978 * Set if rendering has occured to the drawable's front buffer.
980 * This is used in the DRI2 case to detect that glFlush should also copy
981 * the contents of the fake front buffer to the real front buffer.
983 bool front_buffer_dirty
;
985 /** Framerate throttling: @{ */
986 drm_intel_bo
*first_post_swapbuffers_batch
;
997 bool always_flush_batch
;
998 bool always_flush_cache
;
999 bool disable_throttling
;
1001 bool disable_derivative_optimization
;
1003 driOptionCache optionCache
;
1006 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
1008 GLenum reduced_primitive
;
1011 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
1012 * variable is set, this is the flag indicating to do expensive work that
1013 * might lead to a perf_debug() call.
1017 uint32_t max_gtt_map_object_size
;
1028 bool has_separate_stencil
;
1029 bool must_use_separate_stencil
;
1032 bool has_surface_tile_offset
;
1034 bool has_negative_rhw_bug
;
1040 * Some versions of Gen hardware don't do centroid interpolation correctly
1041 * on unlit pixels, causing incorrect values for derivatives near triangle
1042 * edges. Enabling this flag causes the fragment shader to use
1043 * non-centroid interpolation for unlit pixels, at the expense of two extra
1044 * fragment shader instructions.
1046 bool needs_unlit_centroid_workaround
;
1050 struct brw_state_flags dirty
;
1053 struct brw_cache cache
;
1055 /** IDs for meta stencil blit shader programs. */
1056 unsigned meta_stencil_blit_programs
[2];
1058 /* Whether a meta-operation is in progress. */
1059 bool meta_in_progress
;
1061 /* Whether the last depth/stencil packets were both NULL. */
1062 bool no_depth_or_stencil
;
1065 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
1066 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
1068 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
1072 /* Summary of size and varying of active arrays, so we can check
1073 * for changes to this state:
1075 unsigned int min_index
, max_index
;
1077 /* Offset from start of vertex buffer so we can avoid redefining
1078 * the same VB packed over and over again.
1080 unsigned int start_vertex_bias
;
1085 * Index buffer for this draw_prims call.
1087 * Updates are signaled by BRW_NEW_INDICES.
1089 const struct _mesa_index_buffer
*ib
;
1091 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
1095 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
1096 * avoid re-uploading the IB packet over and over if we're actually
1097 * referencing the same index buffer.
1099 unsigned int start_vertex_offset
;
1102 /* Active vertex program:
1104 const struct gl_vertex_program
*vertex_program
;
1105 const struct gl_geometry_program
*geometry_program
;
1106 const struct gl_fragment_program
*fragment_program
;
1109 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
1110 * that we don't have to reemit that state every time we change FBOs.
1115 * Platform specific constants containing the maximum number of threads
1116 * for each pipeline stage.
1122 /* BRW_NEW_URB_ALLOCATIONS:
1125 GLuint vsize
; /* vertex size plus header in urb registers */
1126 GLuint csize
; /* constant buffer size in urb registers */
1127 GLuint sfsize
; /* setup data size in urb registers */
1131 GLuint min_vs_entries
; /* Minimum number of VS entries */
1132 GLuint max_vs_entries
; /* Maximum number of VS entries */
1133 GLuint max_gs_entries
; /* Maximum number of GS entries */
1135 GLuint nr_vs_entries
;
1136 GLuint nr_gs_entries
;
1137 GLuint nr_clip_entries
;
1138 GLuint nr_sf_entries
;
1139 GLuint nr_cs_entries
;
1146 GLuint size
; /* Hardware URB size, in KB. */
1148 /* gen6: True if the most recently sent _3DSTATE_URB message allocated
1149 * URB space for the GS.
1151 bool gen6_gs_previously_active
;
1155 /* BRW_NEW_CURBE_OFFSETS:
1158 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1159 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1167 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1168 * for upload to the CURBE.
1170 drm_intel_bo
*curbe_bo
;
1171 /** Offset within curbe_bo of space for current curbe entry */
1172 GLuint curbe_offset
;
1176 * Layout of vertex data exiting the vertex shader.
1178 * BRW_NEW_VUE_MAP_VS is flagged when this VUE map changes.
1180 struct brw_vue_map vue_map_vs
;
1183 * Layout of vertex data exiting the geometry portion of the pipleine.
1184 * This comes from the geometry shader if one exists, otherwise from the
1187 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1189 struct brw_vue_map vue_map_geom_out
;
1192 struct brw_stage_state base
;
1193 struct brw_vs_prog_data
*prog_data
;
1197 struct brw_stage_state base
;
1198 struct brw_gs_prog_data
*prog_data
;
1201 * True if the 3DSTATE_GS command most recently emitted to the 3D
1202 * pipeline enabled the GS; false otherwise.
1208 struct brw_ff_gs_prog_data
*prog_data
;
1211 /** Offset in the program cache to the CLIP program pre-gen6 */
1212 uint32_t prog_offset
;
1213 uint32_t state_offset
;
1215 uint32_t bind_bo_offset
;
1216 uint32_t surf_offset
[BRW_MAX_GEN6_GS_SURFACES
];
1220 struct brw_clip_prog_data
*prog_data
;
1222 /** Offset in the program cache to the CLIP program pre-gen6 */
1223 uint32_t prog_offset
;
1225 /* Offset in the batch to the CLIP state on pre-gen6. */
1226 uint32_t state_offset
;
1228 /* As of gen6, this is the offset in the batch to the CLIP VP,
1236 struct brw_sf_prog_data
*prog_data
;
1238 /** Offset in the program cache to the CLIP program pre-gen6 */
1239 uint32_t prog_offset
;
1240 uint32_t state_offset
;
1242 bool viewport_transform_enable
;
1246 struct brw_stage_state base
;
1247 struct brw_wm_prog_data
*prog_data
;
1252 * Buffer object used in place of multisampled null render targets on
1253 * Gen6. See brw_update_null_renderbuffer_surface().
1255 drm_intel_bo
*multisampled_null_render_target_bo
;
1256 uint32_t fast_clear_op
;
1261 uint32_t state_offset
;
1262 uint32_t blend_state_offset
;
1263 uint32_t depth_stencil_state_offset
;
1268 struct brw_query_object
*obj
;
1273 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1274 const int *statistics_registers
;
1276 /** The number of active monitors using OA counters. */
1280 * A buffer object storing OA counter snapshots taken at the start and
1281 * end of each batch (creating "bookends" around the batch).
1283 drm_intel_bo
*bookend_bo
;
1285 /** The number of snapshots written to bookend_bo. */
1286 int bookend_snapshots
;
1289 * An array of monitors whose results haven't yet been assembled based on
1290 * the data in buffer objects.
1292 * These may be active, or have already ended. However, the results
1293 * have not been requested.
1295 struct brw_perf_monitor_object
**unresolved
;
1296 int unresolved_elements
;
1297 int unresolved_array_size
;
1300 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1301 * the counter which MI_REPORT_PERF_COUNT stores there.
1303 const int *oa_snapshot_layout
;
1305 /** Number of 32-bit entries in a hardware counter snapshot. */
1306 int entries_per_oa_snapshot
;
1310 const struct brw_tracked_state
**atoms
;
1312 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1316 enum aub_state_struct_type type
;
1317 } *state_batch_list
;
1318 int state_batch_count
;
1320 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1321 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1323 /* Interpolation modes, one byte per vue slot.
1324 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1326 struct interpolation_mode_map interpolation_mode
;
1328 /* PrimitiveRestart */
1331 bool enable_cut_index
;
1334 /** Computed depth/stencil/hiz state from the current attached
1335 * renderbuffers, valid only during the drawing state upload loop after
1336 * brw_workaround_depthstencil_alignment().
1339 struct intel_mipmap_tree
*depth_mt
;
1340 struct intel_mipmap_tree
*stencil_mt
;
1342 /* Inter-tile (page-aligned) byte offsets. */
1343 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1344 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1345 uint32_t tile_x
, tile_y
;
1348 uint32_t num_instances
;
1353 struct gl_shader_program
**shader_programs
;
1354 struct gl_program
**programs
;
1355 enum shader_time_shader_type
*types
;
1356 uint64_t *cumulative
;
1362 struct brw_fast_clear_state
*fast_clear_state
;
1364 __DRIcontext
*driContext
;
1365 struct intel_screen
*intelScreen
;
1368 /*======================================================================
1371 void brwInitVtbl( struct brw_context
*brw
);
1374 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1376 /*======================================================================
1379 extern const char *const brw_vendor_string
;
1381 extern const char *brw_get_renderer_string(unsigned deviceID
);
1384 DRI_CONF_BO_REUSE_DISABLED
,
1385 DRI_CONF_BO_REUSE_ALL
1388 void intel_update_renderbuffers(__DRIcontext
*context
,
1389 __DRIdrawable
*drawable
);
1390 void intel_prepare_render(struct brw_context
*brw
);
1392 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1393 __DRIdrawable
*drawable
);
1395 GLboolean
brwCreateContext(gl_api api
,
1396 const struct gl_config
*mesaVis
,
1397 __DRIcontext
*driContextPriv
,
1398 unsigned major_version
,
1399 unsigned minor_version
,
1403 void *sharedContextPrivate
);
1405 /*======================================================================
1408 GLuint
brw_get_rb_for_slice(struct brw_context
*brw
,
1409 struct intel_mipmap_tree
*mt
,
1410 unsigned level
, unsigned layer
, bool flat
);
1412 void brw_meta_updownsample(struct brw_context
*brw
,
1413 struct intel_mipmap_tree
*src
,
1414 struct intel_mipmap_tree
*dst
);
1416 void brw_meta_fbo_stencil_blit(struct brw_context
*brw
,
1417 GLfloat srcX0
, GLfloat srcY0
,
1418 GLfloat srcX1
, GLfloat srcY1
,
1419 GLfloat dstX0
, GLfloat dstY0
,
1420 GLfloat dstX1
, GLfloat dstY1
);
1422 void brw_meta_stencil_updownsample(struct brw_context
*brw
,
1423 struct intel_mipmap_tree
*src
,
1424 struct intel_mipmap_tree
*dst
);
1426 bool brw_meta_fast_clear(struct brw_context
*brw
,
1427 struct gl_framebuffer
*fb
,
1429 bool partial_clear
);
1432 brw_meta_resolve_color(struct brw_context
*brw
,
1433 struct intel_mipmap_tree
*mt
);
1435 brw_meta_fast_clear_free(struct brw_context
*brw
);
1438 /*======================================================================
1441 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1442 uint32_t depth_level
,
1443 uint32_t depth_layer
,
1444 struct intel_mipmap_tree
*stencil_mt
,
1445 uint32_t *out_tile_mask_x
,
1446 uint32_t *out_tile_mask_y
);
1447 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1448 GLbitfield clear_mask
);
1450 /* brw_object_purgeable.c */
1451 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1453 /*======================================================================
1456 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1457 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1458 void brw_emit_query_begin(struct brw_context
*brw
);
1459 void brw_emit_query_end(struct brw_context
*brw
);
1461 /** gen6_queryobj.c */
1462 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1463 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1464 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1465 void brw_store_register_mem64(struct brw_context
*brw
,
1466 drm_intel_bo
*bo
, uint32_t reg
, int idx
);
1468 /** intel_batchbuffer.c */
1469 void brw_load_register_mem(struct brw_context
*brw
,
1472 uint32_t read_domains
, uint32_t write_domain
,
1475 /*======================================================================
1478 void brw_debug_batch(struct brw_context
*brw
);
1479 void brw_annotate_aub(struct brw_context
*brw
);
1481 /*======================================================================
1484 void brw_validate_textures( struct brw_context
*brw
);
1487 /*======================================================================
1490 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1492 int brw_get_scratch_size(int size
);
1493 void brw_get_scratch_bo(struct brw_context
*brw
,
1494 drm_intel_bo
**scratch_bo
, int size
);
1495 void brw_init_shader_time(struct brw_context
*brw
);
1496 int brw_get_shader_time_index(struct brw_context
*brw
,
1497 struct gl_shader_program
*shader_prog
,
1498 struct gl_program
*prog
,
1499 enum shader_time_shader_type type
);
1500 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1501 void brw_destroy_shader_time(struct brw_context
*brw
);
1505 void brw_upload_urb_fence(struct brw_context
*brw
);
1509 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1511 /* brw_fs_reg_allocate.cpp
1513 void brw_fs_alloc_reg_sets(struct intel_screen
*screen
);
1515 /* brw_vec4_reg_allocate.cpp */
1516 void brw_vec4_alloc_reg_set(struct intel_screen
*screen
);
1519 int brw_disassemble_inst(FILE *file
, struct brw_context
*brw
,
1520 struct brw_inst
*inst
, bool is_compacted
);
1523 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1525 /* brw_draw_upload.c */
1526 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1527 const struct gl_client_array
*glarray
);
1528 unsigned brw_get_index_type(GLenum type
);
1529 void brw_prepare_vertices(struct brw_context
*brw
);
1531 /* brw_wm_surface_state.c */
1532 void brw_init_surface_formats(struct brw_context
*brw
);
1533 void brw_create_constant_surface(struct brw_context
*brw
,
1537 uint32_t *out_offset
,
1539 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1541 uint32_t *surf_offset
);
1543 brw_update_sol_surface(struct brw_context
*brw
,
1544 struct gl_buffer_object
*buffer_obj
,
1545 uint32_t *out_offset
, unsigned num_vector_components
,
1546 unsigned stride_dwords
, unsigned offset_dwords
);
1547 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1548 struct gl_shader
*shader
,
1549 struct brw_stage_state
*stage_state
,
1550 struct brw_stage_prog_data
*prog_data
);
1551 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1552 struct gl_shader_program
*prog
,
1553 struct brw_stage_state
*stage_state
,
1554 struct brw_stage_prog_data
*prog_data
);
1556 /* brw_surface_formats.c */
1557 bool brw_is_hiz_depth_format(struct brw_context
*ctx
, mesa_format format
);
1558 bool brw_render_target_supported(struct brw_context
*brw
,
1559 struct gl_renderbuffer
*rb
);
1560 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1562 /* brw_performance_monitor.c */
1563 void brw_init_performance_monitors(struct brw_context
*brw
);
1564 void brw_dump_perf_monitors(struct brw_context
*brw
);
1565 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1566 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1568 /* intel_buffer_objects.c */
1569 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1570 const char *bo_name
);
1571 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1572 const char *bo_name
);
1574 /* intel_extensions.c */
1575 extern void intelInitExtensions(struct gl_context
*ctx
);
1578 extern int intel_translate_shadow_compare_func(GLenum func
);
1579 extern int intel_translate_compare_func(GLenum func
);
1580 extern int intel_translate_stencil_op(GLenum op
);
1581 extern int intel_translate_logic_op(GLenum opcode
);
1583 /* intel_syncobj.c */
1584 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1587 struct gl_transform_feedback_object
*
1588 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1590 brw_delete_transform_feedback(struct gl_context
*ctx
,
1591 struct gl_transform_feedback_object
*obj
);
1593 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1594 struct gl_transform_feedback_object
*obj
);
1596 brw_end_transform_feedback(struct gl_context
*ctx
,
1597 struct gl_transform_feedback_object
*obj
);
1599 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1600 struct gl_transform_feedback_object
*obj
,
1603 /* gen7_sol_state.c */
1605 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1606 struct gl_transform_feedback_object
*obj
);
1608 gen7_end_transform_feedback(struct gl_context
*ctx
,
1609 struct gl_transform_feedback_object
*obj
);
1611 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1612 struct gl_transform_feedback_object
*obj
);
1614 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1615 struct gl_transform_feedback_object
*obj
);
1617 /* brw_blorp_blit.cpp */
1619 brw_blorp_framebuffer(struct brw_context
*brw
,
1620 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1621 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1622 GLbitfield mask
, GLenum filter
);
1625 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1626 struct gl_renderbuffer
*src_rb
,
1627 struct gl_texture_image
*dst_image
,
1629 int srcX0
, int srcY0
,
1630 int dstX0
, int dstY0
,
1631 int width
, int height
);
1633 /* gen6_multisample_state.c */
1635 gen6_determine_sample_mask(struct brw_context
*brw
);
1638 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1639 unsigned num_samples
);
1641 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1643 gen6_get_sample_position(struct gl_context
*ctx
,
1644 struct gl_framebuffer
*fb
,
1648 /* gen8_multisample_state.c */
1649 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1650 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1654 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1655 unsigned gs_size
, unsigned fs_size
);
1658 gen7_emit_urb_state(struct brw_context
*brw
,
1659 unsigned nr_vs_entries
, unsigned vs_size
,
1660 unsigned vs_start
, unsigned nr_gs_entries
,
1661 unsigned gs_size
, unsigned gs_start
);
1666 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1668 /*======================================================================
1669 * Inline conversion functions. These are better-typed than the
1670 * macros used previously:
1672 static inline struct brw_context
*
1673 brw_context( struct gl_context
*ctx
)
1675 return (struct brw_context
*)ctx
;
1678 static inline struct brw_vertex_program
*
1679 brw_vertex_program(struct gl_vertex_program
*p
)
1681 return (struct brw_vertex_program
*) p
;
1684 static inline const struct brw_vertex_program
*
1685 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1687 return (const struct brw_vertex_program
*) p
;
1690 static inline struct brw_geometry_program
*
1691 brw_geometry_program(struct gl_geometry_program
*p
)
1693 return (struct brw_geometry_program
*) p
;
1696 static inline struct brw_fragment_program
*
1697 brw_fragment_program(struct gl_fragment_program
*p
)
1699 return (struct brw_fragment_program
*) p
;
1702 static inline const struct brw_fragment_program
*
1703 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1705 return (const struct brw_fragment_program
*) p
;
1709 * Pre-gen6, the register file of the EUs was shared between threads,
1710 * and each thread used some subset allocated on a 16-register block
1711 * granularity. The unit states wanted these block counts.
1714 brw_register_blocks(int reg_count
)
1716 return ALIGN(reg_count
, 16) / 16 - 1;
1719 static inline uint32_t
1720 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1721 uint32_t prog_offset
)
1723 if (brw
->gen
>= 5) {
1724 /* Using state base address. */
1728 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1732 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1734 return brw
->cache
.bo
->offset64
+ prog_offset
;
1737 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1738 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1739 struct exec_list
*instructions
);
1740 bool brw_do_lower_unnormalized_offset(struct exec_list
*instructions
);
1742 struct opcode_desc
{
1748 extern const struct opcode_desc opcode_descs
[128];
1749 extern const char * const conditional_modifier
[16];
1752 brw_emit_depthbuffer(struct brw_context
*brw
);
1755 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1756 struct intel_mipmap_tree
*depth_mt
,
1757 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1758 uint32_t depth_surface_type
,
1759 struct intel_mipmap_tree
*stencil_mt
,
1760 bool hiz
, bool separate_stencil
,
1761 uint32_t width
, uint32_t height
,
1762 uint32_t tile_x
, uint32_t tile_y
);
1765 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1766 struct intel_mipmap_tree
*depth_mt
,
1767 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1768 uint32_t depth_surface_type
,
1769 struct intel_mipmap_tree
*stencil_mt
,
1770 bool hiz
, bool separate_stencil
,
1771 uint32_t width
, uint32_t height
,
1772 uint32_t tile_x
, uint32_t tile_y
);
1775 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1776 struct intel_mipmap_tree
*depth_mt
,
1777 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1778 uint32_t depth_surface_type
,
1779 struct intel_mipmap_tree
*stencil_mt
,
1780 bool hiz
, bool separate_stencil
,
1781 uint32_t width
, uint32_t height
,
1782 uint32_t tile_x
, uint32_t tile_y
);
1784 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1785 struct intel_mipmap_tree
*depth_mt
,
1786 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1787 uint32_t depth_surface_type
,
1788 struct intel_mipmap_tree
*stencil_mt
,
1789 bool hiz
, bool separate_stencil
,
1790 uint32_t width
, uint32_t height
,
1791 uint32_t tile_x
, uint32_t tile_y
);
1793 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1794 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);
1796 uint32_t get_hw_prim_for_gl_prim(int mode
);
1799 brw_setup_vec4_key_clip_info(struct brw_context
*brw
,
1800 struct brw_vec4_prog_key
*key
,
1801 bool program_uses_clip_distance
);
1804 gen6_upload_push_constants(struct brw_context
*brw
,
1805 const struct gl_program
*prog
,
1806 const struct brw_stage_prog_data
*prog_data
,
1807 struct brw_stage_state
*stage_state
,
1808 enum aub_state_struct_type type
);
1810 /* ================================================================
1811 * From linux kernel i386 header files, copes with odd sizes better
1812 * than COPY_DWORDS would:
1813 * XXX Put this in src/mesa/main/imports.h ???
1815 #if defined(i386) || defined(__i386__)
1816 static inline void * __memcpy(void * to
, const void * from
, size_t n
)
1819 __asm__
__volatile__(
1824 "1:\ttestb $1,%b4\n\t"
1828 : "=&c" (d0
), "=&D" (d1
), "=&S" (d2
)
1829 :"0" (n
/4), "q" (n
),"1" ((long) to
),"2" ((long) from
)
1834 #define __memcpy(a,b,c) memcpy(a,b,c)