2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
37 #include "main/macros.h"
38 #include "main/mtypes.h"
39 #include "brw_structs.h"
40 #include "brw_compiler.h"
41 #include "intel_aub.h"
45 /* Evil hack for using libdrm in a c++ compiler. */
49 #include <intel_bufmgr.h>
58 #include "intel_debug.h"
59 #include "intel_screen.h"
60 #include "intel_tex_obj.h"
61 #include "intel_resolve_map.h"
65 * URB - uniform resource buffer. A mid-sized buffer which is
66 * partitioned between the fixed function units and used for passing
67 * values (vertices, primitives, constants) between them.
69 * CURBE - constant URB entry. An urb region (entry) used to hold
70 * constant values which the fixed function units can be instructed to
71 * preload into the GRF when spawning a thread.
73 * VUE - vertex URB entry. An urb entry holding a vertex and usually
74 * a vertex header. The header contains control information and
75 * things like primitive type, Begin/end flags and clip codes.
77 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
78 * unit holding rasterization and interpolation parameters.
80 * GRF - general register file. One of several register files
81 * addressable by programmed threads. The inputs (r0, payload, curbe,
82 * urb) of the thread are preloaded to this area before the thread is
83 * spawned. The registers are individually 8 dwords wide and suitable
84 * for general usage. Registers holding thread input values are not
85 * special and may be overwritten.
87 * MRF - message register file. Threads communicate (and terminate)
88 * by sending messages. Message parameters are placed in contiguous
89 * MRF registers. All program output is via these messages. URB
90 * entries are populated by sending a message to the shared URB
91 * function containing the new data, together with a control word,
92 * often an unmodified copy of R0.
94 * R0 - GRF register 0. Typically holds control information used when
95 * sending messages to other threads.
97 * EU or GEN4 EU: The name of the programmable subsystem of the
98 * i965 hardware. Threads are executed by the EU, the registers
99 * described above are part of the EU architecture.
101 * Fixed function units:
103 * CS - Command streamer. Notional first unit, little software
104 * interaction. Holds the URB entries used for constant data, ie the
107 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
108 * this unit is responsible for pulling vertices out of vertex buffers
109 * in vram and injecting them into the processing pipe as VUEs. If
110 * enabled, it first passes them to a VS thread which is a good place
111 * for the driver to implement any active vertex shader.
113 * HS - Hull Shader (Tessellation Control Shader)
115 * TE - Tessellation Engine (Tessellation Primitive Generation)
117 * DS - Domain Shader (Tessellation Evaluation Shader)
119 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
120 * enabled, incoming strips etc are passed to GS threads in individual
121 * line/triangle/point units. The GS thread may perform arbitary
122 * computation and emit whatever primtives with whatever vertices it
123 * chooses. This makes GS an excellent place to implement GL's
124 * unfilled polygon modes, though of course it is capable of much
125 * more. Additionally, GS is used to translate away primitives not
126 * handled by latter units, including Quads and Lineloops.
128 * CS - Clipper. Mesa's clipping algorithms are imported to run on
129 * this unit. The fixed function part performs cliptesting against
130 * the 6 fixed clipplanes and makes descisions on whether or not the
131 * incoming primitive needs to be passed to a thread for clipping.
132 * User clip planes are handled via cooperation with the VS thread.
134 * SF - Strips Fans or Setup: Triangles are prepared for
135 * rasterization. Interpolation coefficients are calculated.
136 * Flatshading and two-side lighting usually performed here.
138 * WM - Windower. Interpolation of vertex attributes performed here.
139 * Fragment shader implemented here. SIMD aspects of EU taken full
140 * advantage of, as pixels are processed in blocks of 16.
142 * CC - Color Calculator. No EU threads associated with this unit.
143 * Handles blending and (presumably) depth and stencil testing.
148 struct brw_vs_prog_key
;
149 struct brw_vue_prog_key
;
150 struct brw_wm_prog_key
;
151 struct brw_wm_prog_data
;
152 struct brw_cs_prog_key
;
153 struct brw_cs_prog_data
;
157 BRW_COMPUTE_PIPELINE
,
164 BRW_CACHE_BLORP_PROG
,
167 BRW_CACHE_FF_GS_PROG
,
178 /* brw_cache_ids must come first - see brw_state_cache.c */
179 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
180 BRW_STATE_FRAGMENT_PROGRAM
,
181 BRW_STATE_GEOMETRY_PROGRAM
,
182 BRW_STATE_TESS_PROGRAMS
,
183 BRW_STATE_VERTEX_PROGRAM
,
184 BRW_STATE_CURBE_OFFSETS
,
185 BRW_STATE_REDUCED_PRIMITIVE
,
186 BRW_STATE_PATCH_PRIMITIVE
,
191 BRW_STATE_BINDING_TABLE_POINTERS
,
194 BRW_STATE_DEFAULT_TESS_LEVELS
,
196 BRW_STATE_INDEX_BUFFER
,
197 BRW_STATE_VS_CONSTBUF
,
198 BRW_STATE_TCS_CONSTBUF
,
199 BRW_STATE_TES_CONSTBUF
,
200 BRW_STATE_GS_CONSTBUF
,
201 BRW_STATE_PROGRAM_CACHE
,
202 BRW_STATE_STATE_BASE_ADDRESS
,
203 BRW_STATE_VUE_MAP_GEOM_OUT
,
204 BRW_STATE_TRANSFORM_FEEDBACK
,
205 BRW_STATE_RASTERIZER_DISCARD
,
207 BRW_STATE_UNIFORM_BUFFER
,
208 BRW_STATE_ATOMIC_BUFFER
,
209 BRW_STATE_IMAGE_UNITS
,
210 BRW_STATE_META_IN_PROGRESS
,
211 BRW_STATE_INTERPOLATION_MAP
,
212 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
213 BRW_STATE_NUM_SAMPLES
,
214 BRW_STATE_TEXTURE_BUFFER
,
215 BRW_STATE_GEN4_UNIT_STATE
,
219 BRW_STATE_SAMPLER_STATE_TABLE
,
220 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
221 BRW_STATE_COMPUTE_PROGRAM
,
222 BRW_STATE_CS_WORK_GROUPS
,
230 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
232 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
233 * When the currently bound shader program differs from the previous draw
234 * call, these will be flagged. They cover brw->{stage}_program and
235 * ctx->{Stage}Program->_Current.
237 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
238 * driver perspective. Even if the same shader is bound at the API level,
239 * we may need to switch between multiple versions of that shader to handle
240 * changes in non-orthagonal state.
242 * Additionally, multiple shader programs may have identical vertex shaders
243 * (for example), or compile down to the same code in the backend. We combine
244 * those into a single program cache entry.
246 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
247 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
249 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
250 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
251 * use the normal state upload paths), but the cache is still used. To avoid
252 * polluting the brw_state_cache code with special cases, we retain the dirty
253 * bit for now. It should eventually be removed.
255 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_PROG)
256 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
257 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
258 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
259 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
260 #define BRW_NEW_TCS_PROG_DATA (1ull << BRW_CACHE_TCS_PROG)
261 #define BRW_NEW_TES_PROG_DATA (1ull << BRW_CACHE_TES_PROG)
262 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
263 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
264 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
265 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
266 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
267 #define BRW_NEW_TESS_PROGRAMS (1ull << BRW_STATE_TESS_PROGRAMS)
268 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
269 #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
270 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
271 #define BRW_NEW_PATCH_PRIMITIVE (1ull << BRW_STATE_PATCH_PRIMITIVE)
272 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
273 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
274 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
275 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
276 #define BRW_NEW_BINDING_TABLE_POINTERS (1ull << BRW_STATE_BINDING_TABLE_POINTERS)
277 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
278 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
279 #define BRW_NEW_DEFAULT_TESS_LEVELS (1ull << BRW_STATE_DEFAULT_TESS_LEVELS)
281 * Used for any batch entry with a relocated pointer that will be used
282 * by any 3D rendering.
284 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
285 /** \see brw.state.depth_region */
286 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
287 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
288 #define BRW_NEW_TCS_CONSTBUF (1ull << BRW_STATE_TCS_CONSTBUF)
289 #define BRW_NEW_TES_CONSTBUF (1ull << BRW_STATE_TES_CONSTBUF)
290 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
291 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
292 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
293 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
294 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
295 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
296 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
297 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
298 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
299 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
300 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
301 #define BRW_NEW_INTERPOLATION_MAP (1ull << BRW_STATE_INTERPOLATION_MAP)
302 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
303 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
304 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
305 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
306 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
307 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
308 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
309 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
310 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
311 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
312 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
313 #define BRW_NEW_URB_SIZE (1ull << BRW_STATE_URB_SIZE)
314 #define BRW_NEW_CC_STATE (1ull << BRW_STATE_CC_STATE)
315 #define BRW_NEW_BLORP (1ull << BRW_STATE_BLORP)
317 struct brw_state_flags
{
318 /** State update flags signalled by mesa internals */
321 * State update flags signalled as the result of brw_tracked_state updates
326 /** Subclass of Mesa vertex program */
327 struct brw_vertex_program
{
328 struct gl_vertex_program program
;
333 /** Subclass of Mesa tessellation control program */
334 struct brw_tess_ctrl_program
{
335 struct gl_tess_ctrl_program program
;
336 unsigned id
; /**< serial no. to identify tess ctrl progs, never re-used */
340 /** Subclass of Mesa tessellation evaluation program */
341 struct brw_tess_eval_program
{
342 struct gl_tess_eval_program program
;
343 unsigned id
; /**< serial no. to identify tess eval progs, never re-used */
347 /** Subclass of Mesa geometry program */
348 struct brw_geometry_program
{
349 struct gl_geometry_program program
;
350 unsigned id
; /**< serial no. to identify geom progs, never re-used */
354 /** Subclass of Mesa fragment program */
355 struct brw_fragment_program
{
356 struct gl_fragment_program program
;
357 GLuint id
; /**< serial no. to identify frag progs, never re-used */
361 /** Subclass of Mesa compute program */
362 struct brw_compute_program
{
363 struct gl_compute_program program
;
364 unsigned id
; /**< serial no. to identify compute progs, never re-used */
369 struct gl_shader base
;
375 * Bitmask indicating which fragment shader inputs represent varyings (and
376 * hence have to be delivered to the fragment shader by the SF/SBE stage).
378 #define BRW_FS_VARYING_INPUT_MASK \
379 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
380 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
384 * Mapping of VUE map slots to interpolation modes.
386 struct interpolation_mode_map
{
387 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
390 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
392 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
393 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
399 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
401 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
402 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
409 struct brw_sf_prog_data
{
410 GLuint urb_read_length
;
413 /* Each vertex may have upto 12 attributes, 4 components each,
414 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
417 * Actually we use 4 for each, so call it 12 rows.
419 GLuint urb_entry_size
;
424 * We always program SF to start reading at an offset of 1 (2 varying slots)
425 * from the start of the vertex URB entry. This causes it to skip:
426 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
427 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
429 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
432 struct brw_clip_prog_data
{
433 GLuint curb_read_length
; /* user planes? */
435 GLuint urb_read_length
;
439 struct brw_ff_gs_prog_data
{
440 GLuint urb_read_length
;
444 * Gen6 transform feedback: Amount by which the streaming vertex buffer
445 * indices should be incremented each time the GS is invoked.
447 unsigned svbi_postincrement_value
;
450 /** Number of texture sampler units */
451 #define BRW_MAX_TEX_UNIT 32
453 /** Max number of render targets in a shader */
454 #define BRW_MAX_DRAW_BUFFERS 8
456 /** Max number of UBOs in a shader */
457 #define BRW_MAX_UBO 14
459 /** Max number of SSBOs in a shader */
460 #define BRW_MAX_SSBO 12
462 /** Max number of atomic counter buffer objects in a shader */
463 #define BRW_MAX_ABO 16
465 /** Max number of image uniforms in a shader */
466 #define BRW_MAX_IMAGES 32
469 * Max number of binding table entries used for stream output.
471 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
472 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
474 * On Gen6, the size of transform feedback data is limited not by the number
475 * of components but by the number of binding table entries we set aside. We
476 * use one binding table entry for a float, one entry for a vector, and one
477 * entry per matrix column. Since the only way we can communicate our
478 * transform feedback capabilities to the client is via
479 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
480 * worst case, in which all the varyings are floats, so we use up one binding
481 * table entry per component. Therefore we need to set aside at least 64
482 * binding table entries for use by transform feedback.
484 * Note: since we don't currently pack varyings, it is currently impossible
485 * for the client to actually use up all of these binding table entries--if
486 * all of their varyings were floats, they would run out of varying slots and
487 * fail to link. But that's a bug, so it seems prudent to go ahead and
488 * allocate the number of binding table entries we will need once the bug is
491 #define BRW_MAX_SOL_BINDINGS 64
493 /** Maximum number of actual buffers used for stream output */
494 #define BRW_MAX_SOL_BUFFERS 4
496 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
497 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
502 2 + /* shader time, pull constants */ \
503 1 /* cs num work groups */)
505 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
508 * Stride in bytes between shader_time entries.
510 * We separate entries by a cacheline to reduce traffic between EUs writing to
513 #define SHADER_TIME_STRIDE 64
515 struct brw_cache_item
{
517 * Effectively part of the key, cache_id identifies what kind of state
518 * buffer is involved, and also which dirty flag should set.
520 enum brw_cache_id cache_id
;
521 /** 32-bit hash of the key data */
523 GLuint key_size
; /* for variable-sized keys */
530 struct brw_cache_item
*next
;
535 struct brw_context
*brw
;
537 struct brw_cache_item
**items
;
539 GLuint size
, n_items
;
541 uint32_t next_offset
;
546 /* Considered adding a member to this struct to document which flags
547 * an update might raise so that ordering of the state atoms can be
548 * checked or derived at runtime. Dropped the idea in favor of having
549 * a debug mode where the state is monitored for flags which are
550 * raised that have already been tested against.
552 struct brw_tracked_state
{
553 struct brw_state_flags dirty
;
554 void (*emit
)( struct brw_context
*brw
);
557 enum shader_time_shader_type
{
568 struct brw_vertex_buffer
{
569 /** Buffer object containing the uploaded vertex data */
573 /** Byte stride between elements in the uploaded array */
577 struct brw_vertex_element
{
578 const struct gl_client_array
*glarray
;
582 /** Offset of the first element within the buffer object */
586 struct brw_query_object
{
587 struct gl_query_object Base
;
589 /** Last query BO associated with this query. */
592 /** Last index in bo with query data for this object. */
595 /** True if we know the batch has been flushed since we ended the query. */
605 struct intel_batchbuffer
{
606 /** Current batchbuffer being queued up. */
608 /** Last BO submitted to the hardware. Used for glFinish(). */
609 drm_intel_bo
*last_bo
;
612 uint16_t emit
, total
;
614 uint16_t reserved_space
;
618 #define BATCH_SZ (8192*sizeof(uint32_t))
620 uint32_t state_batch_offset
;
621 enum brw_gpu_ring ring
;
622 bool needs_sol_reset
;
623 bool state_base_address_emitted
;
631 #define MAX_GS_INPUT_VERTICES 6
633 #define BRW_MAX_XFB_STREAMS 4
635 struct brw_transform_feedback_object
{
636 struct gl_transform_feedback_object base
;
638 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
639 drm_intel_bo
*offset_bo
;
641 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
644 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
645 GLenum primitive_mode
;
648 * Count of primitives generated during this transform feedback operation.
651 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
652 drm_intel_bo
*prim_count_bo
;
653 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
657 * Number of vertices written between last Begin/EndTransformFeedback().
659 * Used to implement DrawTransformFeedback().
661 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
662 bool vertices_written_valid
;
666 * Data shared between each programmable stage in the pipeline (vs, gs, and
669 struct brw_stage_state
671 gl_shader_stage stage
;
672 struct brw_stage_prog_data
*prog_data
;
675 * Optional scratch buffer used to store spilled register values and
676 * variably-indexed GRF arrays.
678 * The contents of this buffer are short-lived so the same memory can be
679 * re-used at will for multiple shader programs (executed by the same fixed
680 * function). However reusing a scratch BO for which shader invocations
681 * are still in flight with a per-thread scratch slot size other than the
682 * original can cause threads with different scratch slot size and FFTID
683 * (which may be executed in parallel depending on the shader stage and
684 * hardware generation) to map to an overlapping region of the scratch
685 * space, which can potentially lead to mutual scratch space corruption.
686 * For that reason if you borrow this scratch buffer you should only be
687 * using the slot size given by the \c per_thread_scratch member below,
688 * unless you're taking additional measures to synchronize thread execution
689 * across slot size changes.
691 drm_intel_bo
*scratch_bo
;
694 * Scratch slot size allocated for each thread in the buffer object given
697 uint32_t per_thread_scratch
;
699 /** Offset in the program cache to the program */
700 uint32_t prog_offset
;
702 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
703 uint32_t state_offset
;
705 uint32_t push_const_offset
; /* Offset in the batchbuffer */
706 int push_const_size
; /* in 256-bit register increments */
708 /* Binding table: pointers to SURFACE_STATE entries. */
709 uint32_t bind_bo_offset
;
710 uint32_t surf_offset
[BRW_MAX_SURFACES
];
712 /** SAMPLER_STATE count and table offset */
713 uint32_t sampler_count
;
714 uint32_t sampler_offset
;
717 enum brw_predicate_state
{
718 /* The first two states are used if we can determine whether to draw
719 * without having to look at the values in the query object buffer. This
720 * will happen if there is no conditional render in progress, if the query
721 * object is already completed or if something else has already added
722 * samples to the preliminary result such as via a BLT command.
724 BRW_PREDICATE_STATE_RENDER
,
725 BRW_PREDICATE_STATE_DONT_RENDER
,
726 /* In this case whether to draw or not depends on the result of an
727 * MI_PREDICATE command so the predicate enable bit needs to be checked.
729 BRW_PREDICATE_STATE_USE_BIT
734 struct brw_l3_config
;
737 * brw_context is derived from gl_context.
741 struct gl_context ctx
; /**< base class, must be first field */
745 void (*update_texture_surface
)(struct gl_context
*ctx
,
747 uint32_t *surf_offset
,
748 bool for_gather
, uint32_t plane
);
749 uint32_t (*update_renderbuffer_surface
)(struct brw_context
*brw
,
750 struct gl_renderbuffer
*rb
,
751 bool layered
, unsigned unit
,
752 uint32_t surf_index
);
754 void (*emit_texture_surface_state
)(struct brw_context
*brw
,
755 struct intel_mipmap_tree
*mt
,
763 uint32_t *surf_offset
,
765 bool rw
, bool for_gather
);
766 void (*emit_buffer_surface_state
)(struct brw_context
*brw
,
767 uint32_t *out_offset
,
769 unsigned buffer_offset
,
770 unsigned surface_format
,
771 unsigned buffer_size
,
774 void (*emit_null_surface_state
)(struct brw_context
*brw
,
778 uint32_t *out_offset
);
781 * Send the appropriate state packets to configure depth, stencil, and
782 * HiZ buffers (i965+ only)
784 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
785 struct intel_mipmap_tree
*depth_mt
,
786 uint32_t depth_offset
,
787 uint32_t depthbuffer_format
,
788 uint32_t depth_surface_type
,
789 struct intel_mipmap_tree
*stencil_mt
,
790 bool hiz
, bool separate_stencil
,
791 uint32_t width
, uint32_t height
,
792 uint32_t tile_x
, uint32_t tile_y
);
798 drm_intel_context
*hw_ctx
;
800 /** BO for post-sync nonzero writes for gen6 workaround. */
801 drm_intel_bo
*workaround_bo
;
802 uint8_t pipe_controls_since_last_cs_stall
;
805 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
806 * and would need flushing before being used from another cache domain that
807 * isn't coherent with it (i.e. the sampler).
809 struct set
*render_cache
;
812 * Number of resets observed in the system at context creation.
814 * This is tracked in the context so that we can determine that another
815 * reset has occurred.
817 uint32_t reset_count
;
819 struct intel_batchbuffer batch
;
824 uint32_t next_offset
;
828 * Set if rendering has occurred to the drawable's front buffer.
830 * This is used in the DRI2 case to detect that glFlush should also copy
831 * the contents of the fake front buffer to the real front buffer.
833 bool front_buffer_dirty
;
835 /** Framerate throttling: @{ */
836 drm_intel_bo
*throttle_batch
[2];
838 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
839 * frame of rendering to complete. This gives a very precise cap to the
840 * latency between input and output such that rendering never gets more
841 * than a frame behind the user. (With the caveat that we technically are
842 * not using the SwapBuffers itself as a barrier but the first batch
843 * submitted afterwards, which may be immediately prior to the next
846 bool need_swap_throttle
;
848 /** General throttling, not caught by throttling between SwapBuffers */
849 bool need_flush_throttle
;
859 bool always_flush_batch
;
860 bool always_flush_cache
;
861 bool disable_throttling
;
863 bool dual_color_blend_by_location
;
865 driOptionCache optionCache
;
868 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
870 GLenum reduced_primitive
;
873 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
874 * variable is set, this is the flag indicating to do expensive work that
875 * might lead to a perf_debug() call.
879 uint32_t max_gtt_map_object_size
;
891 bool has_separate_stencil
;
892 bool must_use_separate_stencil
;
895 bool has_surface_tile_offset
;
897 bool has_negative_rhw_bug
;
901 bool use_resource_streamer
;
904 * Whether LRI can be used to write register values from the batch buffer.
906 bool can_do_pipelined_register_writes
;
909 * Some versions of Gen hardware don't do centroid interpolation correctly
910 * on unlit pixels, causing incorrect values for derivatives near triangle
911 * edges. Enabling this flag causes the fragment shader to use
912 * non-centroid interpolation for unlit pixels, at the expense of two extra
913 * fragment shader instructions.
915 bool needs_unlit_centroid_workaround
;
919 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
922 enum brw_pipeline last_pipeline
;
924 struct brw_cache cache
;
926 /** IDs for meta stencil blit shader programs. */
927 struct gl_shader_program
*meta_stencil_blit_programs
[2];
929 /* Whether a meta-operation is in progress. */
930 bool meta_in_progress
;
932 /* Whether the last depth/stencil packets were both NULL. */
933 bool no_depth_or_stencil
;
935 /* The last PMA stall bits programmed. */
936 uint32_t pma_stall_bits
;
940 /** The value of gl_BaseVertex for the current _mesa_prim. */
943 /** The value of gl_BaseInstance for the current _mesa_prim. */
948 * Buffer and offset used for GL_ARB_shader_draw_parameters
949 * (for now, only gl_BaseVertex).
951 drm_intel_bo
*draw_params_bo
;
952 uint32_t draw_params_offset
;
955 * The value of gl_DrawID for the current _mesa_prim. This always comes
956 * in from it's own vertex buffer since it's not part of the indirect
960 drm_intel_bo
*draw_id_bo
;
961 uint32_t draw_id_offset
;
966 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
967 * an indirect call, and num_work_groups_offset is valid. Otherwise,
968 * num_work_groups is set based on glDispatchCompute.
970 drm_intel_bo
*num_work_groups_bo
;
971 GLintptr num_work_groups_offset
;
972 const GLuint
*num_work_groups
;
976 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
977 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
979 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
983 /* Summary of size and varying of active arrays, so we can check
984 * for changes to this state:
986 bool index_bounds_valid
;
987 unsigned int min_index
, max_index
;
989 /* Offset from start of vertex buffer so we can avoid redefining
990 * the same VB packed over and over again.
992 unsigned int start_vertex_bias
;
995 * Certain vertex attribute formats aren't natively handled by the
996 * hardware and require special VS code to fix up their values.
998 * These bitfields indicate which workarounds are needed.
1000 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
1005 * Index buffer for this draw_prims call.
1007 * Updates are signaled by BRW_NEW_INDICES.
1009 const struct _mesa_index_buffer
*ib
;
1011 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
1016 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
1017 * avoid re-uploading the IB packet over and over if we're actually
1018 * referencing the same index buffer.
1020 unsigned int start_vertex_offset
;
1023 /* Active vertex program:
1025 const struct gl_vertex_program
*vertex_program
;
1026 const struct gl_geometry_program
*geometry_program
;
1027 const struct gl_tess_ctrl_program
*tess_ctrl_program
;
1028 const struct gl_tess_eval_program
*tess_eval_program
;
1029 const struct gl_fragment_program
*fragment_program
;
1030 const struct gl_compute_program
*compute_program
;
1033 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
1034 * that we don't have to reemit that state every time we change FBOs.
1039 * Platform specific constants containing the maximum number of threads
1040 * for each pipeline stage.
1042 unsigned max_vs_threads
;
1043 unsigned max_hs_threads
;
1044 unsigned max_ds_threads
;
1045 unsigned max_gs_threads
;
1046 unsigned max_wm_threads
;
1047 unsigned max_cs_threads
;
1049 /* BRW_NEW_URB_ALLOCATIONS:
1052 GLuint vsize
; /* vertex size plus header in urb registers */
1053 GLuint gsize
; /* GS output size in urb registers */
1054 GLuint hsize
; /* Tessellation control output size in urb registers */
1055 GLuint dsize
; /* Tessellation evaluation output size in urb registers */
1056 GLuint csize
; /* constant buffer size in urb registers */
1057 GLuint sfsize
; /* setup data size in urb registers */
1061 GLuint min_vs_entries
; /* Minimum number of VS entries */
1062 GLuint max_vs_entries
; /* Maximum number of VS entries */
1063 GLuint max_hs_entries
; /* Maximum number of HS entries */
1064 GLuint max_ds_entries
; /* Maximum number of DS entries */
1065 GLuint max_gs_entries
; /* Maximum number of GS entries */
1067 GLuint nr_vs_entries
;
1068 GLuint nr_hs_entries
;
1069 GLuint nr_ds_entries
;
1070 GLuint nr_gs_entries
;
1071 GLuint nr_clip_entries
;
1072 GLuint nr_sf_entries
;
1073 GLuint nr_cs_entries
;
1083 * URB size in the current configuration. The units this is expressed
1084 * in are somewhat inconsistent, see brw_device_info::urb::size.
1086 * FINISHME: Represent the URB size consistently in KB on all platforms.
1090 /* True if the most recently sent _3DSTATE_URB message allocated
1091 * URB space for the GS.
1095 /* True if the most recently sent _3DSTATE_URB message allocated
1096 * URB space for the HS and DS.
1102 /* BRW_NEW_CURBE_OFFSETS:
1105 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1106 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1114 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1115 * for upload to the CURBE.
1117 drm_intel_bo
*curbe_bo
;
1118 /** Offset within curbe_bo of space for current curbe entry */
1119 GLuint curbe_offset
;
1123 * Layout of vertex data exiting the geometry portion of the pipleine.
1124 * This comes from the last enabled shader stage (GS, DS, or VS).
1126 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1128 struct brw_vue_map vue_map_geom_out
;
1131 struct brw_stage_state base
;
1132 struct brw_vs_prog_data
*prog_data
;
1136 struct brw_stage_state base
;
1137 struct brw_tcs_prog_data
*prog_data
;
1140 * True if the 3DSTATE_HS command most recently emitted to the 3D
1141 * pipeline enabled the HS; false otherwise.
1147 struct brw_stage_state base
;
1148 struct brw_tes_prog_data
*prog_data
;
1151 * True if the 3DSTATE_DS command most recently emitted to the 3D
1152 * pipeline enabled the DS; false otherwise.
1158 struct brw_stage_state base
;
1159 struct brw_gs_prog_data
*prog_data
;
1162 * True if the 3DSTATE_GS command most recently emitted to the 3D
1163 * pipeline enabled the GS; false otherwise.
1169 struct brw_ff_gs_prog_data
*prog_data
;
1172 /** Offset in the program cache to the CLIP program pre-gen6 */
1173 uint32_t prog_offset
;
1174 uint32_t state_offset
;
1176 uint32_t bind_bo_offset
;
1178 * Surface offsets for the binding table. We only need surfaces to
1179 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1180 * need in this case.
1182 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1186 struct brw_clip_prog_data
*prog_data
;
1188 /** Offset in the program cache to the CLIP program pre-gen6 */
1189 uint32_t prog_offset
;
1191 /* Offset in the batch to the CLIP state on pre-gen6. */
1192 uint32_t state_offset
;
1194 /* As of gen6, this is the offset in the batch to the CLIP VP,
1202 struct brw_sf_prog_data
*prog_data
;
1204 /** Offset in the program cache to the CLIP program pre-gen6 */
1205 uint32_t prog_offset
;
1206 uint32_t state_offset
;
1208 bool viewport_transform_enable
;
1212 struct brw_stage_state base
;
1213 struct brw_wm_prog_data
*prog_data
;
1218 * Buffer object used in place of multisampled null render targets on
1219 * Gen6. See brw_emit_null_surface_state().
1221 drm_intel_bo
*multisampled_null_render_target_bo
;
1222 uint32_t fast_clear_op
;
1228 struct brw_stage_state base
;
1229 struct brw_cs_prog_data
*prog_data
;
1232 /* RS hardware binding table */
1235 uint32_t next_offset
;
1239 uint32_t state_offset
;
1240 uint32_t blend_state_offset
;
1241 uint32_t depth_stencil_state_offset
;
1246 struct brw_query_object
*obj
;
1251 enum brw_predicate_state state
;
1256 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1257 const int *statistics_registers
;
1259 /** The number of active monitors using OA counters. */
1263 * A buffer object storing OA counter snapshots taken at the start and
1264 * end of each batch (creating "bookends" around the batch).
1266 drm_intel_bo
*bookend_bo
;
1268 /** The number of snapshots written to bookend_bo. */
1269 int bookend_snapshots
;
1272 * An array of monitors whose results haven't yet been assembled based on
1273 * the data in buffer objects.
1275 * These may be active, or have already ended. However, the results
1276 * have not been requested.
1278 struct brw_perf_monitor_object
**unresolved
;
1279 int unresolved_elements
;
1280 int unresolved_array_size
;
1283 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1284 * the counter which MI_REPORT_PERF_COUNT stores there.
1286 const int *oa_snapshot_layout
;
1288 /** Number of 32-bit entries in a hardware counter snapshot. */
1289 int entries_per_oa_snapshot
;
1292 int num_atoms
[BRW_NUM_PIPELINES
];
1293 const struct brw_tracked_state render_atoms
[76];
1294 const struct brw_tracked_state compute_atoms
[11];
1296 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1300 enum aub_state_struct_type type
;
1302 } *state_batch_list
;
1303 int state_batch_count
;
1305 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1306 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1308 /* Interpolation modes, one byte per vue slot.
1309 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1311 struct interpolation_mode_map interpolation_mode
;
1313 /* PrimitiveRestart */
1316 bool enable_cut_index
;
1319 /** Computed depth/stencil/hiz state from the current attached
1320 * renderbuffers, valid only during the drawing state upload loop after
1321 * brw_workaround_depthstencil_alignment().
1324 struct intel_mipmap_tree
*depth_mt
;
1325 struct intel_mipmap_tree
*stencil_mt
;
1327 /* Inter-tile (page-aligned) byte offsets. */
1328 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1329 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1330 uint32_t tile_x
, tile_y
;
1333 uint32_t num_instances
;
1338 const struct brw_l3_config
*config
;
1345 enum shader_time_shader_type
*types
;
1346 struct shader_times
*cumulative
;
1352 struct brw_fast_clear_state
*fast_clear_state
;
1354 __DRIcontext
*driContext
;
1355 struct intel_screen
*intelScreen
;
1358 /*======================================================================
1361 void brwInitVtbl( struct brw_context
*brw
);
1364 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1366 /*======================================================================
1369 extern const char *const brw_vendor_string
;
1372 brw_get_renderer_string(const struct intel_screen
*intelScreen
);
1375 DRI_CONF_BO_REUSE_DISABLED
,
1376 DRI_CONF_BO_REUSE_ALL
1379 void intel_update_renderbuffers(__DRIcontext
*context
,
1380 __DRIdrawable
*drawable
);
1381 void intel_prepare_render(struct brw_context
*brw
);
1383 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1384 __DRIdrawable
*drawable
);
1386 GLboolean
brwCreateContext(gl_api api
,
1387 const struct gl_config
*mesaVis
,
1388 __DRIcontext
*driContextPriv
,
1389 unsigned major_version
,
1390 unsigned minor_version
,
1394 void *sharedContextPrivate
);
1396 /*======================================================================
1400 brw_meta_resolve_color(struct brw_context
*brw
,
1401 struct intel_mipmap_tree
*mt
);
1403 /*======================================================================
1406 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1407 uint32_t depth_level
,
1408 uint32_t depth_layer
,
1409 struct intel_mipmap_tree
*stencil_mt
,
1410 uint32_t *out_tile_mask_x
,
1411 uint32_t *out_tile_mask_y
);
1412 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1413 GLbitfield clear_mask
);
1415 /* brw_object_purgeable.c */
1416 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1418 /*======================================================================
1421 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1422 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1423 void brw_emit_query_begin(struct brw_context
*brw
);
1424 void brw_emit_query_end(struct brw_context
*brw
);
1425 void brw_query_counter(struct gl_context
*ctx
, struct gl_query_object
*q
);
1426 bool brw_is_query_pipelined(struct brw_query_object
*query
);
1428 /** gen6_queryobj.c */
1429 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1430 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1431 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1433 /** hsw_queryobj.c */
1434 void hsw_init_queryobj_functions(struct dd_function_table
*functions
);
1436 /** brw_conditional_render.c */
1437 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1438 bool brw_check_conditional_render(struct brw_context
*brw
);
1440 /** intel_batchbuffer.c */
1441 void brw_load_register_mem(struct brw_context
*brw
,
1444 uint32_t read_domains
, uint32_t write_domain
,
1446 void brw_load_register_mem64(struct brw_context
*brw
,
1449 uint32_t read_domains
, uint32_t write_domain
,
1451 void brw_store_register_mem32(struct brw_context
*brw
,
1452 drm_intel_bo
*bo
, uint32_t reg
, uint32_t offset
);
1453 void brw_store_register_mem64(struct brw_context
*brw
,
1454 drm_intel_bo
*bo
, uint32_t reg
, uint32_t offset
);
1455 void brw_load_register_imm32(struct brw_context
*brw
,
1456 uint32_t reg
, uint32_t imm
);
1457 void brw_load_register_imm64(struct brw_context
*brw
,
1458 uint32_t reg
, uint64_t imm
);
1459 void brw_load_register_reg(struct brw_context
*brw
, uint32_t src
,
1461 void brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
,
1463 void brw_store_data_imm32(struct brw_context
*brw
, drm_intel_bo
*bo
,
1464 uint32_t offset
, uint32_t imm
);
1465 void brw_store_data_imm64(struct brw_context
*brw
, drm_intel_bo
*bo
,
1466 uint32_t offset
, uint64_t imm
);
1468 /*======================================================================
1471 void brw_debug_batch(struct brw_context
*brw
);
1472 void brw_annotate_aub(struct brw_context
*brw
);
1474 /*======================================================================
1477 void brw_validate_textures( struct brw_context
*brw
);
1480 /*======================================================================
1484 key_debug(struct brw_context
*brw
, const char *name
, int a
, int b
)
1487 perf_debug(" %s %d->%d\n", name
, a
, b
);
1493 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1495 /* Per-thread scratch space is a power-of-two multiple of 1KB. */
1497 brw_get_scratch_size(int size
)
1499 return MAX2(1024, util_next_power_of_two(size
));
1501 void brw_get_scratch_bo(struct brw_context
*brw
,
1502 drm_intel_bo
**scratch_bo
, int size
);
1503 void brw_alloc_stage_scratch(struct brw_context
*brw
,
1504 struct brw_stage_state
*stage_state
,
1505 unsigned per_thread_size
,
1506 unsigned thread_count
);
1507 void brw_init_shader_time(struct brw_context
*brw
);
1508 int brw_get_shader_time_index(struct brw_context
*brw
,
1509 struct gl_shader_program
*shader_prog
,
1510 struct gl_program
*prog
,
1511 enum shader_time_shader_type type
);
1512 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1513 void brw_destroy_shader_time(struct brw_context
*brw
);
1517 void brw_upload_urb_fence(struct brw_context
*brw
);
1521 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1523 /* brw_fs_reg_allocate.cpp
1525 void brw_fs_alloc_reg_sets(struct brw_compiler
*compiler
);
1527 /* brw_vec4_reg_allocate.cpp */
1528 void brw_vec4_alloc_reg_set(struct brw_compiler
*compiler
);
1531 int brw_disassemble_inst(FILE *file
, const struct brw_device_info
*devinfo
,
1532 struct brw_inst
*inst
, bool is_compacted
);
1535 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1537 /* brw_draw_upload.c */
1538 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1539 const struct gl_client_array
*glarray
);
1541 static inline unsigned
1542 brw_get_index_type(GLenum type
)
1544 assert((type
== GL_UNSIGNED_BYTE
)
1545 || (type
== GL_UNSIGNED_SHORT
)
1546 || (type
== GL_UNSIGNED_INT
));
1548 /* The possible values for type are GL_UNSIGNED_BYTE (0x1401),
1549 * GL_UNSIGNED_SHORT (0x1403), and GL_UNSIGNED_INT (0x1405) which we want
1550 * to map to scale factors of 0, 1, and 2, respectively. These scale
1551 * factors are then left-shfited by 8 to be in the correct position in the
1552 * CMD_INDEX_BUFFER packet.
1554 * Subtracting 0x1401 gives 0, 2, and 4. Shifting left by 7 afterwards
1555 * gives 0x00000000, 0x00000100, and 0x00000200. These just happen to be
1556 * the values the need to be written in the CMD_INDEX_BUFFER packet.
1558 return (type
- 0x1401) << 7;
1561 void brw_prepare_vertices(struct brw_context
*brw
);
1563 /* brw_wm_surface_state.c */
1564 void brw_init_surface_formats(struct brw_context
*brw
);
1565 void brw_create_constant_surface(struct brw_context
*brw
,
1569 uint32_t *out_offset
);
1570 void brw_create_buffer_surface(struct brw_context
*brw
,
1574 uint32_t *out_offset
);
1575 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1577 uint32_t *surf_offset
);
1579 brw_update_sol_surface(struct brw_context
*brw
,
1580 struct gl_buffer_object
*buffer_obj
,
1581 uint32_t *out_offset
, unsigned num_vector_components
,
1582 unsigned stride_dwords
, unsigned offset_dwords
);
1583 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1584 struct gl_shader
*shader
,
1585 struct brw_stage_state
*stage_state
,
1586 struct brw_stage_prog_data
*prog_data
);
1587 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1588 struct gl_shader
*shader
,
1589 struct brw_stage_state
*stage_state
,
1590 struct brw_stage_prog_data
*prog_data
);
1591 void brw_upload_image_surfaces(struct brw_context
*brw
,
1592 struct gl_shader
*shader
,
1593 struct brw_stage_state
*stage_state
,
1594 struct brw_stage_prog_data
*prog_data
);
1596 /* brw_surface_formats.c */
1597 bool brw_render_target_supported(struct brw_context
*brw
,
1598 struct gl_renderbuffer
*rb
);
1599 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1601 /* brw_performance_monitor.c */
1602 void brw_init_performance_monitors(struct brw_context
*brw
);
1603 void brw_dump_perf_monitors(struct brw_context
*brw
);
1604 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1605 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1607 /* intel_buffer_objects.c */
1608 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1609 const char *bo_name
);
1610 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1611 const char *bo_name
);
1613 /* intel_extensions.c */
1614 extern void intelInitExtensions(struct gl_context
*ctx
);
1617 extern int intel_translate_shadow_compare_func(GLenum func
);
1618 extern int intel_translate_compare_func(GLenum func
);
1619 extern int intel_translate_stencil_op(GLenum op
);
1620 extern int intel_translate_logic_op(GLenum opcode
);
1622 /* intel_syncobj.c */
1623 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1626 struct gl_transform_feedback_object
*
1627 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1629 brw_delete_transform_feedback(struct gl_context
*ctx
,
1630 struct gl_transform_feedback_object
*obj
);
1632 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1633 struct gl_transform_feedback_object
*obj
);
1635 brw_end_transform_feedback(struct gl_context
*ctx
,
1636 struct gl_transform_feedback_object
*obj
);
1638 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1639 struct gl_transform_feedback_object
*obj
,
1642 /* gen7_sol_state.c */
1644 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1645 struct gl_transform_feedback_object
*obj
);
1647 gen7_end_transform_feedback(struct gl_context
*ctx
,
1648 struct gl_transform_feedback_object
*obj
);
1650 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1651 struct gl_transform_feedback_object
*obj
);
1653 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1654 struct gl_transform_feedback_object
*obj
);
1658 hsw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1659 struct gl_transform_feedback_object
*obj
);
1661 hsw_end_transform_feedback(struct gl_context
*ctx
,
1662 struct gl_transform_feedback_object
*obj
);
1664 hsw_pause_transform_feedback(struct gl_context
*ctx
,
1665 struct gl_transform_feedback_object
*obj
);
1667 hsw_resume_transform_feedback(struct gl_context
*ctx
,
1668 struct gl_transform_feedback_object
*obj
);
1670 /* brw_blorp_blit.cpp */
1672 brw_blorp_framebuffer(struct brw_context
*brw
,
1673 struct gl_framebuffer
*readFb
,
1674 struct gl_framebuffer
*drawFb
,
1675 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1676 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1677 GLbitfield mask
, GLenum filter
);
1680 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1681 struct gl_renderbuffer
*src_rb
,
1682 struct gl_texture_image
*dst_image
,
1684 int srcX0
, int srcY0
,
1685 int dstX0
, int dstY0
,
1686 int width
, int height
);
1688 /* gen6_multisample_state.c */
1690 gen6_determine_sample_mask(struct brw_context
*brw
);
1693 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1694 unsigned num_samples
);
1696 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1698 gen6_get_sample_position(struct gl_context
*ctx
,
1699 struct gl_framebuffer
*fb
,
1703 gen6_set_sample_maps(struct gl_context
*ctx
);
1705 /* gen8_multisample_state.c */
1706 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1707 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1711 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1712 unsigned hs_size
, unsigned ds_size
,
1713 unsigned gs_size
, unsigned fs_size
);
1716 gen7_emit_urb_state(struct brw_context
*brw
,
1717 unsigned nr_vs_entries
,
1718 unsigned vs_size
, unsigned vs_start
,
1719 unsigned nr_hs_entries
,
1720 unsigned hs_size
, unsigned hs_start
,
1721 unsigned nr_ds_entries
,
1722 unsigned ds_size
, unsigned ds_start
,
1723 unsigned nr_gs_entries
,
1724 unsigned gs_size
, unsigned gs_start
);
1729 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1731 brw_check_for_reset(struct brw_context
*brw
);
1735 brw_init_compute_functions(struct dd_function_table
*functions
);
1737 /*======================================================================
1738 * Inline conversion functions. These are better-typed than the
1739 * macros used previously:
1741 static inline struct brw_context
*
1742 brw_context( struct gl_context
*ctx
)
1744 return (struct brw_context
*)ctx
;
1747 static inline struct brw_vertex_program
*
1748 brw_vertex_program(struct gl_vertex_program
*p
)
1750 return (struct brw_vertex_program
*) p
;
1753 static inline const struct brw_vertex_program
*
1754 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1756 return (const struct brw_vertex_program
*) p
;
1759 static inline struct brw_tess_ctrl_program
*
1760 brw_tess_ctrl_program(struct gl_tess_ctrl_program
*p
)
1762 return (struct brw_tess_ctrl_program
*) p
;
1765 static inline struct brw_tess_eval_program
*
1766 brw_tess_eval_program(struct gl_tess_eval_program
*p
)
1768 return (struct brw_tess_eval_program
*) p
;
1771 static inline struct brw_geometry_program
*
1772 brw_geometry_program(struct gl_geometry_program
*p
)
1774 return (struct brw_geometry_program
*) p
;
1777 static inline struct brw_fragment_program
*
1778 brw_fragment_program(struct gl_fragment_program
*p
)
1780 return (struct brw_fragment_program
*) p
;
1783 static inline const struct brw_fragment_program
*
1784 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1786 return (const struct brw_fragment_program
*) p
;
1789 static inline struct brw_compute_program
*
1790 brw_compute_program(struct gl_compute_program
*p
)
1792 return (struct brw_compute_program
*) p
;
1796 * Pre-gen6, the register file of the EUs was shared between threads,
1797 * and each thread used some subset allocated on a 16-register block
1798 * granularity. The unit states wanted these block counts.
1801 brw_register_blocks(int reg_count
)
1803 return ALIGN(reg_count
, 16) / 16 - 1;
1806 static inline uint32_t
1807 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1808 uint32_t prog_offset
)
1810 if (brw
->gen
>= 5) {
1811 /* Using state base address. */
1815 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1819 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1821 return brw
->cache
.bo
->offset64
+ prog_offset
;
1824 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1825 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1826 struct exec_list
*instructions
);
1827 bool brw_do_lower_unnormalized_offset(struct exec_list
*instructions
);
1829 extern const char * const conditional_modifier
[16];
1830 extern const char *const pred_ctrl_align16
[16];
1833 brw_emit_depthbuffer(struct brw_context
*brw
);
1836 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1837 struct intel_mipmap_tree
*depth_mt
,
1838 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1839 uint32_t depth_surface_type
,
1840 struct intel_mipmap_tree
*stencil_mt
,
1841 bool hiz
, bool separate_stencil
,
1842 uint32_t width
, uint32_t height
,
1843 uint32_t tile_x
, uint32_t tile_y
);
1846 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1847 struct intel_mipmap_tree
*depth_mt
,
1848 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1849 uint32_t depth_surface_type
,
1850 struct intel_mipmap_tree
*stencil_mt
,
1851 bool hiz
, bool separate_stencil
,
1852 uint32_t width
, uint32_t height
,
1853 uint32_t tile_x
, uint32_t tile_y
);
1856 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1857 struct intel_mipmap_tree
*depth_mt
,
1858 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1859 uint32_t depth_surface_type
,
1860 struct intel_mipmap_tree
*stencil_mt
,
1861 bool hiz
, bool separate_stencil
,
1862 uint32_t width
, uint32_t height
,
1863 uint32_t tile_x
, uint32_t tile_y
);
1865 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1866 struct intel_mipmap_tree
*depth_mt
,
1867 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1868 uint32_t depth_surface_type
,
1869 struct intel_mipmap_tree
*stencil_mt
,
1870 bool hiz
, bool separate_stencil
,
1871 uint32_t width
, uint32_t height
,
1872 uint32_t tile_x
, uint32_t tile_y
);
1874 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1875 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);
1877 uint32_t get_hw_prim_for_gl_prim(int mode
);
1880 gen6_upload_push_constants(struct brw_context
*brw
,
1881 const struct gl_program
*prog
,
1882 const struct brw_stage_prog_data
*prog_data
,
1883 struct brw_stage_state
*stage_state
,
1884 enum aub_state_struct_type type
);
1887 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
1888 const struct intel_mipmap_tree
*mt
);
1890 /* brw_pipe_control.c */
1891 int brw_init_pipe_control(struct brw_context
*brw
,
1892 const struct brw_device_info
*info
);
1893 void brw_fini_pipe_control(struct brw_context
*brw
);
1895 void brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
);
1896 void brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
1897 drm_intel_bo
*bo
, uint32_t offset
,
1898 uint32_t imm_lower
, uint32_t imm_upper
);
1899 void brw_emit_mi_flush(struct brw_context
*brw
);
1900 void brw_emit_post_sync_nonzero_flush(struct brw_context
*brw
);
1901 void brw_emit_depth_stall_flushes(struct brw_context
*brw
);
1902 void gen7_emit_vs_workaround_flush(struct brw_context
*brw
);
1903 void gen7_emit_cs_stall_flush(struct brw_context
*brw
);
1905 /* brw_queryformat.c */
1906 void brw_query_internal_format(struct gl_context
*ctx
, GLenum target
,
1907 GLenum internalFormat
, GLenum pname
,