2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
36 #include "intel_context.h"
37 #include "brw_structs.h"
38 #include "main/imports.h"
43 * URB - uniform resource buffer. A mid-sized buffer which is
44 * partitioned between the fixed function units and used for passing
45 * values (vertices, primitives, constants) between them.
47 * CURBE - constant URB entry. An urb region (entry) used to hold
48 * constant values which the fixed function units can be instructed to
49 * preload into the GRF when spawning a thread.
51 * VUE - vertex URB entry. An urb entry holding a vertex and usually
52 * a vertex header. The header contains control information and
53 * things like primitive type, Begin/end flags and clip codes.
55 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
56 * unit holding rasterization and interpolation parameters.
58 * GRF - general register file. One of several register files
59 * addressable by programmed threads. The inputs (r0, payload, curbe,
60 * urb) of the thread are preloaded to this area before the thread is
61 * spawned. The registers are individually 8 dwords wide and suitable
62 * for general usage. Registers holding thread input values are not
63 * special and may be overwritten.
65 * MRF - message register file. Threads communicate (and terminate)
66 * by sending messages. Message parameters are placed in contiguous
67 * MRF registers. All program output is via these messages. URB
68 * entries are populated by sending a message to the shared URB
69 * function containing the new data, together with a control word,
70 * often an unmodified copy of R0.
72 * R0 - GRF register 0. Typically holds control information used when
73 * sending messages to other threads.
75 * EU or GEN4 EU: The name of the programmable subsystem of the
76 * i965 hardware. Threads are executed by the EU, the registers
77 * described above are part of the EU architecture.
79 * Fixed function units:
81 * CS - Command streamer. Notional first unit, little software
82 * interaction. Holds the URB entries used for constant data, ie the
85 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
86 * this unit is responsible for pulling vertices out of vertex buffers
87 * in vram and injecting them into the processing pipe as VUEs. If
88 * enabled, it first passes them to a VS thread which is a good place
89 * for the driver to implement any active vertex shader.
91 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
92 * enabled, incoming strips etc are passed to GS threads in individual
93 * line/triangle/point units. The GS thread may perform arbitary
94 * computation and emit whatever primtives with whatever vertices it
95 * chooses. This makes GS an excellent place to implement GL's
96 * unfilled polygon modes, though of course it is capable of much
97 * more. Additionally, GS is used to translate away primitives not
98 * handled by latter units, including Quads and Lineloops.
100 * CS - Clipper. Mesa's clipping algorithms are imported to run on
101 * this unit. The fixed function part performs cliptesting against
102 * the 6 fixed clipplanes and makes descisions on whether or not the
103 * incoming primitive needs to be passed to a thread for clipping.
104 * User clip planes are handled via cooperation with the VS thread.
106 * SF - Strips Fans or Setup: Triangles are prepared for
107 * rasterization. Interpolation coefficients are calculated.
108 * Flatshading and two-side lighting usually performed here.
110 * WM - Windower. Interpolation of vertex attributes performed here.
111 * Fragment shader implemented here. SIMD aspects of EU taken full
112 * advantage of, as pixels are processed in blocks of 16.
114 * CC - Color Calculator. No EU threads associated with this unit.
115 * Handles blending and (presumably) depth and stencil testing.
119 #define BRW_MAX_CURBE (32*16)
125 BRW_STATE_FRAGMENT_PROGRAM
,
126 BRW_STATE_VERTEX_PROGRAM
,
127 BRW_STATE_INPUT_DIMENSIONS
,
128 BRW_STATE_CURBE_OFFSETS
,
129 BRW_STATE_REDUCED_PRIMITIVE
,
132 BRW_STATE_WM_INPUT_DIMENSIONS
,
134 BRW_STATE_WM_SURFACES
,
135 BRW_STATE_VS_BINDING_TABLE
,
136 BRW_STATE_GS_BINDING_TABLE
,
137 BRW_STATE_PS_BINDING_TABLE
,
141 BRW_STATE_NR_WM_SURFACES
,
142 BRW_STATE_NR_VS_SURFACES
,
143 BRW_STATE_INDEX_BUFFER
,
144 BRW_STATE_VS_CONSTBUF
,
145 BRW_STATE_PROGRAM_CACHE
,
146 BRW_STATE_STATE_BASE_ADDRESS
,
150 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
151 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
152 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
153 #define BRW_NEW_INPUT_DIMENSIONS (1 << BRW_STATE_INPUT_DIMENSIONS)
154 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
155 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
156 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
157 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
158 #define BRW_NEW_WM_INPUT_DIMENSIONS (1 << BRW_STATE_WM_INPUT_DIMENSIONS)
159 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
160 #define BRW_NEW_WM_SURFACES (1 << BRW_STATE_WM_SURFACES)
161 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
162 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
163 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
164 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
165 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
167 * Used for any batch entry with a relocated pointer that will be used
168 * by any 3D rendering.
170 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
171 /** \see brw.state.depth_region */
172 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
173 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
174 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
175 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
176 #define BRW_NEW_HIZ (1 << BRW_STATE_HIZ)
178 struct brw_state_flags
{
179 /** State update flags signalled by mesa internals */
182 * State update flags signalled as the result of brw_tracked_state updates
185 /** State update flags signalled by brw_state_cache.c searches */
189 enum state_struct_type
{
190 AUB_TRACE_VS_STATE
= 1,
191 AUB_TRACE_GS_STATE
= 2,
192 AUB_TRACE_CLIP_STATE
= 3,
193 AUB_TRACE_SF_STATE
= 4,
194 AUB_TRACE_WM_STATE
= 5,
195 AUB_TRACE_CC_STATE
= 6,
196 AUB_TRACE_CLIP_VP_STATE
= 7,
197 AUB_TRACE_SF_VP_STATE
= 8,
198 AUB_TRACE_CC_VP_STATE
= 0x9,
199 AUB_TRACE_SAMPLER_STATE
= 0xa,
200 AUB_TRACE_KERNEL_INSTRUCTIONS
= 0xb,
201 AUB_TRACE_SCRATCH_SPACE
= 0xc,
202 AUB_TRACE_SAMPLER_DEFAULT_COLOR
= 0xd,
204 AUB_TRACE_SCISSOR_STATE
= 0x15,
205 AUB_TRACE_BLEND_STATE
= 0x16,
206 AUB_TRACE_DEPTH_STENCIL_STATE
= 0x17,
208 /* Not written to .aub files the same way the structures above are. */
209 AUB_TRACE_NO_TYPE
= 0x100,
210 AUB_TRACE_BINDING_TABLE
= 0x101,
211 AUB_TRACE_SURFACE_STATE
= 0x102,
212 AUB_TRACE_VS_CONSTANTS
= 0x103,
213 AUB_TRACE_WM_CONSTANTS
= 0x104,
216 /** Subclass of Mesa vertex program */
217 struct brw_vertex_program
{
218 struct gl_vertex_program program
;
220 bool use_const_buffer
;
224 /** Subclass of Mesa fragment program */
225 struct brw_fragment_program
{
226 struct gl_fragment_program program
;
227 GLuint id
; /**< serial no. to identify frag progs, never re-used */
231 struct gl_shader base
;
233 /** Shader IR transformed for native compile, at link time. */
234 struct exec_list
*ir
;
237 struct brw_shader_program
{
238 struct gl_shader_program base
;
241 enum param_conversion
{
249 /* Data about a particular attempt to compile a program. Note that
250 * there can be many of these, each in a different GL state
251 * corresponding to a different brw_wm_prog_key struct, with different
254 struct brw_wm_prog_data
{
255 GLuint curb_read_length
;
256 GLuint urb_read_length
;
258 GLuint first_curbe_grf
;
259 GLuint first_curbe_grf_16
;
261 GLuint reg_blocks_16
;
262 GLuint total_scratch
;
264 GLuint nr_params
; /**< number of float params/constants */
265 GLuint nr_pull_params
;
268 uint32_t prog_offset_16
;
270 /* Pointer to tracked values (only valid once
271 * _mesa_load_state_parameters has been called at runtime).
273 const float *param
[MAX_UNIFORMS
* 4]; /* should be: BRW_MAX_CURBE */
274 enum param_conversion param_convert
[MAX_UNIFORMS
* 4];
275 const float *pull_param
[MAX_UNIFORMS
* 4];
276 enum param_conversion pull_param_convert
[MAX_UNIFORMS
* 4];
280 * Enum representing the i965-specific vertex results that don't correspond
281 * exactly to any element of gl_vert_result. The values of this enum are
282 * assigned such that they don't conflict with gl_vert_result.
286 BRW_VERT_RESULT_NDC
= VERT_RESULT_MAX
,
287 BRW_VERT_RESULT_HPOS_DUPLICATE
,
294 * Data structure recording the relationship between the gl_vert_result enum
295 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
296 * single octaword within the VUE (128 bits).
298 * Note that each BRW register contains 256 bits (2 octawords), so when
299 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
300 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
301 * in a vertex shader), each register corresponds to a single VUE slot, since
302 * it contains data for two separate vertices.
306 * Map from gl_vert_result value to VUE slot. For gl_vert_results that are
307 * not stored in a slot (because they are not written, or because
308 * additional processing is applied before storing them in the VUE), the
311 int vert_result_to_slot
[BRW_VERT_RESULT_MAX
];
314 * Map from VUE slot to gl_vert_result value. For slots that do not
315 * directly correspond to a gl_vert_result, the value comes from
318 * For slots that are not in use, the value is BRW_VERT_RESULT_MAX (this
319 * simplifies code that uses the value stored in slot_to_vert_result to
320 * create a bit mask).
322 int slot_to_vert_result
[BRW_VERT_RESULT_MAX
];
325 * Total number of VUE slots in use
331 * Convert a VUE slot number into a byte offset within the VUE.
333 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
339 * Convert a vert_result into a byte offset within the VUE.
341 static inline GLuint
brw_vert_result_to_offset(struct brw_vue_map
*vue_map
,
344 return brw_vue_slot_to_offset(vue_map
->vert_result_to_slot
[vert_result
]);
348 struct brw_sf_prog_data
{
349 GLuint urb_read_length
;
352 /* Each vertex may have upto 12 attributes, 4 components each,
353 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
356 * Actually we use 4 for each, so call it 12 rows.
358 GLuint urb_entry_size
;
361 struct brw_clip_prog_data
{
362 GLuint curb_read_length
; /* user planes? */
364 GLuint urb_read_length
;
368 struct brw_gs_prog_data
{
369 GLuint urb_read_length
;
373 struct brw_vs_prog_data
{
374 GLuint curb_read_length
;
375 GLuint urb_read_length
;
377 GLbitfield64 outputs_written
;
378 GLuint nr_params
; /**< number of float params/constants */
379 GLuint nr_pull_params
; /**< number of dwords referenced by pull_param[] */
380 GLuint total_scratch
;
382 GLbitfield64 inputs_read
;
384 /* Used for calculating urb partitions:
386 GLuint urb_entry_size
;
388 const float *param
[MAX_UNIFORMS
* 4]; /* should be: BRW_MAX_CURBE */
389 const float *pull_param
[MAX_UNIFORMS
* 4];
391 bool uses_new_param_layout
;
396 /* Size == 0 if output either not written, or always [0,0,0,1]
398 struct brw_vs_ouput_sizes
{
399 GLubyte output_size
[VERT_RESULT_MAX
];
403 /** Number of texture sampler units */
404 #define BRW_MAX_TEX_UNIT 16
406 /** Max number of render targets in a shader */
407 #define BRW_MAX_DRAW_BUFFERS 8
410 * Helpers to create Surface Binding Table indexes for draw buffers,
411 * textures, and constant buffers.
413 * Shader threads access surfaces via numeric handles, rather than directly
414 * using pointers. The binding table maps these numeric handles to the
415 * address of the actual buffer.
417 * For example, a shader might ask to sample from "surface 7." In this case,
418 * bind[7] would contain a pointer to a texture.
420 * Although the hardware supports separate binding tables per pipeline stage
421 * (VS, HS, DS, GS, PS), we currently share a single binding table for all of
422 * them. This is purely for convenience.
424 * Currently our binding tables are (arbitrarily) programmed as follows:
426 * +-------------------------------+
427 * | 0 | Draw buffer 0 | .
429 * | : | : | > Only relevant to the WM.
430 * | 7 | Draw buffer 7 | /
431 * |-----|-------------------------| `
432 * | 8 | VS Pull Constant Buffer |
433 * | 9 | WM Pull Constant Buffer |
434 * |-----|-------------------------|
438 * | 25 | Texture 15 |
439 * +-------------------------------+
441 * Note that nothing actually uses the SURF_INDEX_DRAW macro, so it has to be
442 * the identity function or things will break. We do want to keep draw buffers
443 * first so we can use headerless render target writes for RT 0.
445 #define SURF_INDEX_DRAW(d) (d)
446 #define SURF_INDEX_VERT_CONST_BUFFER (BRW_MAX_DRAW_BUFFERS + 0)
447 #define SURF_INDEX_FRAG_CONST_BUFFER (BRW_MAX_DRAW_BUFFERS + 1)
448 #define SURF_INDEX_TEXTURE(t) (BRW_MAX_DRAW_BUFFERS + 2 + (t))
450 /** Maximum size of the binding table. */
451 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + BRW_MAX_TEX_UNIT + 2)
455 BRW_DEPTH_STENCIL_STATE
,
456 BRW_COLOR_CALC_STATE
,
464 BRW_SF_UNIT
, /* scissor state on gen6 */
476 struct brw_cache_item
{
478 * Effectively part of the key, cache_id identifies what kind of state
479 * buffer is involved, and also which brw->state.dirty.cache flag should
480 * be set when this cache item is chosen.
482 enum brw_cache_id cache_id
;
483 /** 32-bit hash of the key data */
485 GLuint key_size
; /* for variable-sized keys */
492 struct brw_cache_item
*next
;
498 struct brw_context
*brw
;
500 struct brw_cache_item
**items
;
502 GLuint size
, n_items
;
504 uint32_t next_offset
;
509 /* Considered adding a member to this struct to document which flags
510 * an update might raise so that ordering of the state atoms can be
511 * checked or derived at runtime. Dropped the idea in favor of having
512 * a debug mode where the state is monitored for flags which are
513 * raised that have already been tested against.
515 struct brw_tracked_state
{
516 struct brw_state_flags dirty
;
517 void (*emit
)( struct brw_context
*brw
);
520 /* Flags for brw->state.cache.
522 #define CACHE_NEW_BLEND_STATE (1<<BRW_BLEND_STATE)
523 #define CACHE_NEW_DEPTH_STENCIL_STATE (1<<BRW_DEPTH_STENCIL_STATE)
524 #define CACHE_NEW_COLOR_CALC_STATE (1<<BRW_COLOR_CALC_STATE)
525 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
526 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
527 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
528 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
529 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
530 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
531 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
532 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
533 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
534 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
535 #define CACHE_NEW_GS_UNIT (1<<BRW_GS_UNIT)
536 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
537 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
538 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
539 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
541 struct brw_cached_batch_item
{
542 struct header
*header
;
544 struct brw_cached_batch_item
*next
;
549 /* Protect against a future where VERT_ATTRIB_MAX > 32. Wouldn't life
550 * be easier if C allowed arrays of packed elements?
552 #define ATTRIB_BIT_DWORDS ((VERT_ATTRIB_MAX+31)/32)
554 struct brw_vertex_buffer
{
555 /** Buffer object containing the uploaded vertex data */
558 /** Byte stride between elements in the uploaded array */
561 struct brw_vertex_element
{
562 const struct gl_client_array
*glarray
;
566 /** The corresponding Mesa vertex attribute */
567 gl_vert_attrib attrib
;
568 /** Size of a complete element */
570 /** Offset of the first element within the buffer object */
576 struct brw_vertex_info
{
577 GLuint sizes
[ATTRIB_BIT_DWORDS
* 2]; /* sizes:2[VERT_ATTRIB_MAX] */
580 struct brw_query_object
{
581 struct gl_query_object Base
;
583 /** Last query BO associated with this query. */
585 /** First index in bo with query data for this object. */
587 /** Last index in bo with query data for this object. */
593 * brw_context is derived from intel_context.
597 struct intel_context intel
; /**< base class, must be first field */
598 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
600 bool emit_state_always
;
601 bool has_surface_tile_offset
;
603 bool has_negative_rhw_bug
;
604 bool has_aa_line_parameters
;
610 struct brw_state_flags dirty
;
613 struct brw_cache cache
;
614 struct brw_cached_batch_item
*cached_batch_items
;
617 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
618 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
623 } current_buffers
[VERT_ATTRIB_MAX
];
625 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
627 GLuint nr_buffers
, nr_current_buffers
;
629 /* Summary of size and varying of active arrays, so we can check
630 * for changes to this state:
632 struct brw_vertex_info info
;
633 unsigned int min_index
, max_index
;
635 /* Offset from start of vertex buffer so we can avoid redefining
636 * the same VB packed over and over again.
638 unsigned int start_vertex_bias
;
643 * Index buffer for this draw_prims call.
645 * Updates are signaled by BRW_NEW_INDICES.
647 const struct _mesa_index_buffer
*ib
;
649 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
653 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
654 * avoid re-uploading the IB packet over and over if we're actually
655 * referencing the same index buffer.
657 unsigned int start_vertex_offset
;
660 /* Active vertex program:
662 const struct gl_vertex_program
*vertex_program
;
663 const struct gl_fragment_program
*fragment_program
;
665 /* hw-dependent 3DSTATE_VF_STATISTICS opcode */
666 uint32_t CMD_VF_STATISTICS
;
667 /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
668 uint32_t CMD_PIPELINE_SELECT
;
671 * Platform specific constants containing the maximum number of threads
672 * for each pipeline stage.
678 /* BRW_NEW_URB_ALLOCATIONS:
681 GLuint vsize
; /* vertex size plus header in urb registers */
682 GLuint csize
; /* constant buffer size in urb registers */
683 GLuint sfsize
; /* setup data size in urb registers */
687 GLuint max_vs_entries
; /* Maximum number of VS entries */
688 GLuint max_gs_entries
; /* Maximum number of GS entries */
690 GLuint nr_vs_entries
;
691 GLuint nr_gs_entries
;
692 GLuint nr_clip_entries
;
693 GLuint nr_sf_entries
;
694 GLuint nr_cs_entries
;
697 * The length of each URB entry owned by the VS (or GS), as
698 * a number of 1024-bit (128-byte) rows. Should be >= 1.
700 * gen7: Same meaning, but in 512-bit (64-byte) rows.
710 GLuint size
; /* Hardware URB size, in KB. */
712 /* gen6: True if the most recently sent _3DSTATE_URB message allocated
713 * URB space for the GS.
715 bool gen6_gs_previously_active
;
719 /* BRW_NEW_CURBE_OFFSETS:
722 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
723 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
730 drm_intel_bo
*curbe_bo
;
731 /** Offset within curbe_bo of space for current curbe entry */
733 /** Offset within curbe_bo of space for next curbe entry */
734 GLuint curbe_next_offset
;
737 * Copy of the last set of CURBEs uploaded. Frequently we'll end up
738 * in brw_curbe.c with the same set of constant data to be uploaded,
739 * so we'd rather not upload new constants in that case (it can cause
740 * a pipeline bubble since only up to 4 can be pipelined at a time).
744 * Allocation for where to calculate the next set of CURBEs.
745 * It's a hot enough path that malloc/free of that data matters.
752 /** Binding table of pointers to surf_bo entries */
754 uint32_t surf_offset
[BRW_MAX_SURFACES
];
757 /** SAMPLER_STATE count and offset */
764 struct brw_vs_prog_data
*prog_data
;
765 int8_t *constant_map
; /* variable array following prog_data */
767 drm_intel_bo
*scratch_bo
;
768 drm_intel_bo
*const_bo
;
769 /** Offset in the program cache to the VS program */
770 uint32_t prog_offset
;
771 uint32_t state_offset
;
773 uint32_t push_const_offset
; /* Offset in the batchbuffer */
774 int push_const_size
; /* in 256-bit register increments */
776 /** @{ register allocator */
778 struct ra_regs
*regs
;
781 * Array of the ra classes for the unaligned contiguous register
787 * Mapping for register-allocated objects in *regs to the first
788 * GRF for that object.
790 uint8_t *ra_reg_to_grf
;
795 struct brw_gs_prog_data
*prog_data
;
798 /** Offset in the program cache to the CLIP program pre-gen6 */
799 uint32_t prog_offset
;
800 uint32_t state_offset
;
804 struct brw_clip_prog_data
*prog_data
;
806 /** Offset in the program cache to the CLIP program pre-gen6 */
807 uint32_t prog_offset
;
809 /* Offset in the batch to the CLIP state on pre-gen6. */
810 uint32_t state_offset
;
812 /* As of gen6, this is the offset in the batch to the CLIP VP,
820 struct brw_sf_prog_data
*prog_data
;
822 /** Offset in the program cache to the CLIP program pre-gen6 */
823 uint32_t prog_offset
;
824 uint32_t state_offset
;
829 struct brw_wm_prog_data
*prog_data
;
830 struct brw_wm_compile
*compile_data
;
832 /** Input sizes, calculated from active vertex program.
833 * One bit per fragment program input attribute.
835 GLbitfield input_size_masks
[4];
837 /** offsets in the batch to sampler default colors (texture border color)
839 uint32_t sdc_offset
[BRW_MAX_TEX_UNIT
];
843 drm_intel_bo
*scratch_bo
;
845 /** Offset in the program cache to the WM program */
846 uint32_t prog_offset
;
848 uint32_t state_offset
; /* offset in batchbuffer to pre-gen6 WM state */
850 drm_intel_bo
*const_bo
; /* pull constant buffer. */
852 * This is offset in the batch to the push constants on gen6.
854 * Pre-gen6, push constants live in the CURBE.
856 uint32_t push_const_offset
;
858 /** @{ register allocator */
860 struct ra_regs
*regs
;
862 /** Array of the ra classes for the unaligned contiguous
863 * register block sizes used.
868 * Mapping for register-allocated objects in *regs to the first
869 * GRF for that object.
871 uint8_t *ra_reg_to_grf
;
874 * ra class for the aligned pairs we use for PLN, which doesn't
875 * appear in *classes.
877 int aligned_pairs_class
;
884 uint32_t state_offset
;
885 uint32_t blend_state_offset
;
886 uint32_t depth_stencil_state_offset
;
891 struct brw_query_object
*obj
;
896 /* Used to give every program string a unique id
901 const struct brw_tracked_state
**atoms
;
903 /* If (INTEL_DEBUG & DEBUG_BATCH) */
907 enum state_struct_type type
;
909 int state_batch_count
;
912 * \brief State needed to execute HiZ meta-ops
914 * All fields except \c op are initialized by gen6_hiz_init().
916 struct brw_hiz_state
{
918 * \brief Indicates which HiZ operation is in progress.
920 * See the following sections of the Sandy Bridge PRM, Volume 1, Part2:
921 * - 7.5.3.1 Depth Buffer Clear
922 * - 7.5.3.2 Depth Buffer Resolve
923 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
927 BRW_HIZ_OP_DEPTH_CLEAR
,
928 BRW_HIZ_OP_DEPTH_RESOLVE
,
929 BRW_HIZ_OP_HIZ_RESOLVE
,
932 /** \brief Shader state */
936 GLint position_location
;
939 /** \brief VAO for the rectangle primitive's vertices. */
943 struct gl_renderbuffer
*depth_rb
;
946 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
947 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
952 #define BRW_PACKCOLOR8888(r,g,b,a) ((r<<24) | (g<<16) | (b<<8) | a)
954 struct brw_instruction_info
{
960 extern const struct brw_instruction_info brw_opcodes
[128];
962 /*======================================================================
965 void brwInitVtbl( struct brw_context
*brw
);
967 /*======================================================================
970 bool brwCreateContext(int api
,
971 const struct gl_config
*mesaVis
,
972 __DRIcontext
*driContextPriv
,
973 void *sharedContextPrivate
);
975 /*======================================================================
978 void brw_init_queryobj_functions(struct dd_function_table
*functions
);
979 void brw_prepare_query_begin(struct brw_context
*brw
);
980 void brw_emit_query_begin(struct brw_context
*brw
);
981 void brw_emit_query_end(struct brw_context
*brw
);
983 /*======================================================================
986 void brw_debug_batch(struct intel_context
*intel
);
988 /*======================================================================
991 void brw_validate_textures( struct brw_context
*brw
);
994 /*======================================================================
997 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
999 int brw_get_scratch_size(int size
);
1000 void brw_get_scratch_bo(struct intel_context
*intel
,
1001 drm_intel_bo
**scratch_bo
, int size
);
1006 void brw_upload_urb_fence(struct brw_context
*brw
);
1010 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1013 int brw_disasm (FILE *file
, struct brw_instruction
*inst
, int gen
);
1016 void brw_compute_vue_map(struct brw_vue_map
*vue_map
,
1017 const struct intel_context
*intel
,
1018 bool userclip_active
,
1019 GLbitfield64 outputs_written
);
1020 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1024 brw_compute_barycentric_interp_modes(bool shade_model_flat
,
1025 const struct gl_fragment_program
*fprog
);
1027 /* brw_wm_surface_state.c */
1028 void brw_init_surface_formats(struct brw_context
*brw
);
1030 /* gen6_clip_state.c */
1032 brw_fprog_uses_noperspective(const struct gl_fragment_program
*fprog
);
1036 /*======================================================================
1037 * Inline conversion functions. These are better-typed than the
1038 * macros used previously:
1040 static INLINE
struct brw_context
*
1041 brw_context( struct gl_context
*ctx
)
1043 return (struct brw_context
*)ctx
;
1046 static INLINE
struct brw_vertex_program
*
1047 brw_vertex_program(struct gl_vertex_program
*p
)
1049 return (struct brw_vertex_program
*) p
;
1052 static INLINE
const struct brw_vertex_program
*
1053 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1055 return (const struct brw_vertex_program
*) p
;
1058 static INLINE
struct brw_fragment_program
*
1059 brw_fragment_program(struct gl_fragment_program
*p
)
1061 return (struct brw_fragment_program
*) p
;
1064 static INLINE
const struct brw_fragment_program
*
1065 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1067 return (const struct brw_fragment_program
*) p
;
1071 float convert_param(enum param_conversion conversion
, const float *param
)
1079 switch (conversion
) {
1080 case PARAM_NO_CONVERT
:
1082 case PARAM_CONVERT_F2I
:
1085 case PARAM_CONVERT_F2U
:
1088 case PARAM_CONVERT_F2B
:
1094 case PARAM_CONVERT_ZERO
:
1102 * Pre-gen6, the register file of the EUs was shared between threads,
1103 * and each thread used some subset allocated on a 16-register block
1104 * granularity. The unit states wanted these block counts.
1107 brw_register_blocks(int reg_count
)
1109 return ALIGN(reg_count
, 16) / 16 - 1;
1112 static inline uint32_t
1113 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1114 uint32_t prog_offset
)
1116 struct intel_context
*intel
= &brw
->intel
;
1118 if (intel
->gen
>= 5) {
1119 /* Using state base address. */
1123 drm_intel_bo_emit_reloc(intel
->batch
.bo
,
1127 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1129 return brw
->cache
.bo
->offset
+ prog_offset
;
1132 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);