2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
38 #include "main/imports.h"
39 #include "main/macros.h"
41 #include "main/mtypes.h"
42 #include "brw_structs.h"
43 #include "intel_aub.h"
44 #include "program/prog_parameter.h"
48 /* Evil hack for using libdrm in a c++ compiler. */
53 #include <intel_bufmgr.h>
63 #include "intel_debug.h"
64 #include "intel_screen.h"
65 #include "intel_tex_obj.h"
66 #include "intel_resolve_map.h"
70 * URB - uniform resource buffer. A mid-sized buffer which is
71 * partitioned between the fixed function units and used for passing
72 * values (vertices, primitives, constants) between them.
74 * CURBE - constant URB entry. An urb region (entry) used to hold
75 * constant values which the fixed function units can be instructed to
76 * preload into the GRF when spawning a thread.
78 * VUE - vertex URB entry. An urb entry holding a vertex and usually
79 * a vertex header. The header contains control information and
80 * things like primitive type, Begin/end flags and clip codes.
82 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
83 * unit holding rasterization and interpolation parameters.
85 * GRF - general register file. One of several register files
86 * addressable by programmed threads. The inputs (r0, payload, curbe,
87 * urb) of the thread are preloaded to this area before the thread is
88 * spawned. The registers are individually 8 dwords wide and suitable
89 * for general usage. Registers holding thread input values are not
90 * special and may be overwritten.
92 * MRF - message register file. Threads communicate (and terminate)
93 * by sending messages. Message parameters are placed in contiguous
94 * MRF registers. All program output is via these messages. URB
95 * entries are populated by sending a message to the shared URB
96 * function containing the new data, together with a control word,
97 * often an unmodified copy of R0.
99 * R0 - GRF register 0. Typically holds control information used when
100 * sending messages to other threads.
102 * EU or GEN4 EU: The name of the programmable subsystem of the
103 * i965 hardware. Threads are executed by the EU, the registers
104 * described above are part of the EU architecture.
106 * Fixed function units:
108 * CS - Command streamer. Notional first unit, little software
109 * interaction. Holds the URB entries used for constant data, ie the
112 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
113 * this unit is responsible for pulling vertices out of vertex buffers
114 * in vram and injecting them into the processing pipe as VUEs. If
115 * enabled, it first passes them to a VS thread which is a good place
116 * for the driver to implement any active vertex shader.
118 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
119 * enabled, incoming strips etc are passed to GS threads in individual
120 * line/triangle/point units. The GS thread may perform arbitary
121 * computation and emit whatever primtives with whatever vertices it
122 * chooses. This makes GS an excellent place to implement GL's
123 * unfilled polygon modes, though of course it is capable of much
124 * more. Additionally, GS is used to translate away primitives not
125 * handled by latter units, including Quads and Lineloops.
127 * CS - Clipper. Mesa's clipping algorithms are imported to run on
128 * this unit. The fixed function part performs cliptesting against
129 * the 6 fixed clipplanes and makes descisions on whether or not the
130 * incoming primitive needs to be passed to a thread for clipping.
131 * User clip planes are handled via cooperation with the VS thread.
133 * SF - Strips Fans or Setup: Triangles are prepared for
134 * rasterization. Interpolation coefficients are calculated.
135 * Flatshading and two-side lighting usually performed here.
137 * WM - Windower. Interpolation of vertex attributes performed here.
138 * Fragment shader implemented here. SIMD aspects of EU taken full
139 * advantage of, as pixels are processed in blocks of 16.
141 * CC - Color Calculator. No EU threads associated with this unit.
142 * Handles blending and (presumably) depth and stencil testing.
147 struct brw_vs_prog_key
;
148 struct brw_vec4_prog_key
;
149 struct brw_wm_prog_key
;
150 struct brw_wm_prog_data
;
154 BRW_CACHE_BLORP_BLIT_PROG
,
157 BRW_CACHE_FF_GS_PROG
,
165 /* brw_cache_ids must come first - see brw_state_cache.c */
166 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
167 BRW_STATE_FRAGMENT_PROGRAM
,
168 BRW_STATE_GEOMETRY_PROGRAM
,
169 BRW_STATE_VERTEX_PROGRAM
,
170 BRW_STATE_CURBE_OFFSETS
,
171 BRW_STATE_REDUCED_PRIMITIVE
,
176 BRW_STATE_VS_BINDING_TABLE
,
177 BRW_STATE_GS_BINDING_TABLE
,
178 BRW_STATE_PS_BINDING_TABLE
,
182 BRW_STATE_INDEX_BUFFER
,
183 BRW_STATE_VS_CONSTBUF
,
184 BRW_STATE_GS_CONSTBUF
,
185 BRW_STATE_PROGRAM_CACHE
,
186 BRW_STATE_STATE_BASE_ADDRESS
,
187 BRW_STATE_VUE_MAP_VS
,
188 BRW_STATE_VUE_MAP_GEOM_OUT
,
189 BRW_STATE_TRANSFORM_FEEDBACK
,
190 BRW_STATE_RASTERIZER_DISCARD
,
192 BRW_STATE_UNIFORM_BUFFER
,
193 BRW_STATE_ATOMIC_BUFFER
,
194 BRW_STATE_META_IN_PROGRESS
,
195 BRW_STATE_INTERPOLATION_MAP
,
196 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
197 BRW_STATE_NUM_SAMPLES
,
198 BRW_STATE_TEXTURE_BUFFER
,
199 BRW_STATE_GEN4_UNIT_STATE
,
203 BRW_STATE_SAMPLER_STATE_TABLE
,
204 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
209 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
211 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
212 * When the currently bound shader program differs from the previous draw
213 * call, these will be flagged. They cover brw->{stage}_program and
214 * ctx->{Stage}Program->_Current.
216 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
217 * driver perspective. Even if the same shader is bound at the API level,
218 * we may need to switch between multiple versions of that shader to handle
219 * changes in non-orthagonal state.
221 * Additionally, multiple shader programs may have identical vertex shaders
222 * (for example), or compile down to the same code in the backend. We combine
223 * those into a single program cache entry.
225 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
226 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
228 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
229 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
230 * use the normal state upload paths), but the cache is still used. To avoid
231 * polluting the brw_state_cache code with special cases, we retain the dirty
232 * bit for now. It should eventually be removed.
234 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_BLIT_PROG)
235 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
236 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
237 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
238 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
239 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
240 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
241 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
242 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
243 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
244 #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
245 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
246 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
247 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
248 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
249 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
250 #define BRW_NEW_VS_BINDING_TABLE (1ull << BRW_STATE_VS_BINDING_TABLE)
251 #define BRW_NEW_GS_BINDING_TABLE (1ull << BRW_STATE_GS_BINDING_TABLE)
252 #define BRW_NEW_PS_BINDING_TABLE (1ull << BRW_STATE_PS_BINDING_TABLE)
253 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
254 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
256 * Used for any batch entry with a relocated pointer that will be used
257 * by any 3D rendering.
259 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
260 /** \see brw.state.depth_region */
261 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
262 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
263 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
264 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
265 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
266 #define BRW_NEW_VUE_MAP_VS (1ull << BRW_STATE_VUE_MAP_VS)
267 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
268 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
269 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
270 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
271 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
272 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
273 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
274 #define BRW_NEW_INTERPOLATION_MAP (1ull << BRW_STATE_INTERPOLATION_MAP)
275 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
276 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
277 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
278 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
279 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
280 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
281 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
282 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
283 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
285 struct brw_state_flags
{
286 /** State update flags signalled by mesa internals */
289 * State update flags signalled as the result of brw_tracked_state updates
294 /** Subclass of Mesa vertex program */
295 struct brw_vertex_program
{
296 struct gl_vertex_program program
;
301 /** Subclass of Mesa geometry program */
302 struct brw_geometry_program
{
303 struct gl_geometry_program program
;
304 unsigned id
; /**< serial no. to identify geom progs, never re-used */
308 /** Subclass of Mesa fragment program */
309 struct brw_fragment_program
{
310 struct gl_fragment_program program
;
311 GLuint id
; /**< serial no. to identify frag progs, never re-used */
315 /** Subclass of Mesa compute program */
316 struct brw_compute_program
{
317 struct gl_compute_program program
;
318 unsigned id
; /**< serial no. to identify compute progs, never re-used */
323 struct gl_shader base
;
328 /* Note: If adding fields that need anything besides a normal memcmp() for
329 * comparing them, be sure to go fix brw_stage_prog_data_compare().
331 struct brw_stage_prog_data
{
333 /** size of our binding table. */
337 * surface indices for the various groups of surfaces
339 uint32_t pull_constants_start
;
340 uint32_t texture_start
;
341 uint32_t gather_texture_start
;
344 uint32_t shader_time_start
;
348 GLuint nr_params
; /**< number of float params/constants */
349 GLuint nr_pull_params
;
351 unsigned curb_read_length
;
352 unsigned total_scratch
;
355 * Register where the thread expects to find input data from the URB
356 * (typically uniforms, followed by vertex or fragment attributes).
358 unsigned dispatch_grf_start_reg
;
360 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
362 /* Pointers to tracked values (only valid once
363 * _mesa_load_state_parameters has been called at runtime).
365 * These must be the last fields of the struct (see
366 * brw_stage_prog_data_compare()).
368 const gl_constant_value
**param
;
369 const gl_constant_value
**pull_param
;
372 /* Data about a particular attempt to compile a program. Note that
373 * there can be many of these, each in a different GL state
374 * corresponding to a different brw_wm_prog_key struct, with different
377 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
380 struct brw_wm_prog_data
{
381 struct brw_stage_prog_data base
;
383 GLuint num_varying_inputs
;
385 GLuint dispatch_grf_start_reg_16
;
387 GLuint reg_blocks_16
;
391 * surface indices the WM-specific surfaces
393 uint32_t render_target_start
;
397 uint8_t computed_depth_mode
;
401 bool uses_pos_offset
;
404 uint32_t prog_offset_16
;
407 * Mask of which interpolation modes are required by the fragment shader.
408 * Used in hardware setup on gen6+.
410 uint32_t barycentric_interp_modes
;
413 * Map from gl_varying_slot to the position within the FS setup data
414 * payload where the varying's attribute vertex deltas should be delivered.
415 * For varying slots that are not used by the FS, the value is -1.
417 int urb_setup
[VARYING_SLOT_MAX
];
421 * Enum representing the i965-specific vertex results that don't correspond
422 * exactly to any element of gl_varying_slot. The values of this enum are
423 * assigned such that they don't conflict with gl_varying_slot.
427 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
428 BRW_VARYING_SLOT_PAD
,
430 * Technically this is not a varying but just a placeholder that
431 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
432 * builtin variable to be compiled correctly. see compile_sf_prog() for
435 BRW_VARYING_SLOT_PNTC
,
436 BRW_VARYING_SLOT_COUNT
441 * Data structure recording the relationship between the gl_varying_slot enum
442 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
443 * single octaword within the VUE (128 bits).
445 * Note that each BRW register contains 256 bits (2 octawords), so when
446 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
447 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
448 * in a vertex shader), each register corresponds to a single VUE slot, since
449 * it contains data for two separate vertices.
453 * Bitfield representing all varying slots that are (a) stored in this VUE
454 * map, and (b) actually written by the shader. Does not include any of
455 * the additional varying slots defined in brw_varying_slot.
457 GLbitfield64 slots_valid
;
460 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
461 * not stored in a slot (because they are not written, or because
462 * additional processing is applied before storing them in the VUE), the
465 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
468 * Map from VUE slot to gl_varying_slot value. For slots that do not
469 * directly correspond to a gl_varying_slot, the value comes from
472 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
473 * simplifies code that uses the value stored in slot_to_varying to
474 * create a bit mask).
476 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
479 * Total number of VUE slots in use
485 * Convert a VUE slot number into a byte offset within the VUE.
487 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
493 * Convert a vertex output (brw_varying_slot) into a byte offset within the
496 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
499 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
502 void brw_compute_vue_map(struct brw_context
*brw
, struct brw_vue_map
*vue_map
,
503 GLbitfield64 slots_valid
);
507 * Bitmask indicating which fragment shader inputs represent varyings (and
508 * hence have to be delivered to the fragment shader by the SF/SBE stage).
510 #define BRW_FS_VARYING_INPUT_MASK \
511 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
512 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
516 * Mapping of VUE map slots to interpolation modes.
518 struct interpolation_mode_map
{
519 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
522 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
524 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
525 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
531 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
533 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
534 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
541 struct brw_sf_prog_data
{
542 GLuint urb_read_length
;
545 /* Each vertex may have upto 12 attributes, 4 components each,
546 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
549 * Actually we use 4 for each, so call it 12 rows.
551 GLuint urb_entry_size
;
556 * We always program SF to start reading at an offset of 1 (2 varying slots)
557 * from the start of the vertex URB entry. This causes it to skip:
558 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
559 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
561 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
564 struct brw_clip_prog_data
{
565 GLuint curb_read_length
; /* user planes? */
567 GLuint urb_read_length
;
571 struct brw_ff_gs_prog_data
{
572 GLuint urb_read_length
;
576 * Gen6 transform feedback: Amount by which the streaming vertex buffer
577 * indices should be incremented each time the GS is invoked.
579 unsigned svbi_postincrement_value
;
583 /* Note: brw_vec4_prog_data_compare() must be updated when adding fields to
586 struct brw_vec4_prog_data
{
587 struct brw_stage_prog_data base
;
588 struct brw_vue_map vue_map
;
590 GLuint urb_read_length
;
593 /* Used for calculating urb partitions. In the VS, this is the size of the
594 * URB entry used for both input and output to the thread. In the GS, this
595 * is the size of the URB entry used for output.
597 GLuint urb_entry_size
;
603 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
606 struct brw_vs_prog_data
{
607 struct brw_vec4_prog_data base
;
609 GLbitfield64 inputs_read
;
612 bool uses_instanceid
;
615 /** Number of texture sampler units */
616 #define BRW_MAX_TEX_UNIT 32
618 /** Max number of render targets in a shader */
619 #define BRW_MAX_DRAW_BUFFERS 8
621 /** Max number of atomic counter buffer objects in a shader */
622 #define BRW_MAX_ABO 16
625 * Max number of binding table entries used for stream output.
627 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
628 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
630 * On Gen6, the size of transform feedback data is limited not by the number
631 * of components but by the number of binding table entries we set aside. We
632 * use one binding table entry for a float, one entry for a vector, and one
633 * entry per matrix column. Since the only way we can communicate our
634 * transform feedback capabilities to the client is via
635 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
636 * worst case, in which all the varyings are floats, so we use up one binding
637 * table entry per component. Therefore we need to set aside at least 64
638 * binding table entries for use by transform feedback.
640 * Note: since we don't currently pack varyings, it is currently impossible
641 * for the client to actually use up all of these binding table entries--if
642 * all of their varyings were floats, they would run out of varying slots and
643 * fail to link. But that's a bug, so it seems prudent to go ahead and
644 * allocate the number of binding table entries we will need once the bug is
647 #define BRW_MAX_SOL_BINDINGS 64
649 /** Maximum number of actual buffers used for stream output */
650 #define BRW_MAX_SOL_BUFFERS 4
652 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
653 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
656 2 /* shader time, pull constants */)
658 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
660 /* Note: brw_gs_prog_data_compare() must be updated when adding fields to
663 struct brw_gs_prog_data
665 struct brw_vec4_prog_data base
;
668 * Size of an output vertex, measured in HWORDS (32 bytes).
670 unsigned output_vertex_size_hwords
;
672 unsigned output_topology
;
675 * Size of the control data (cut bits or StreamID bits), in hwords (32
676 * bytes). 0 if there is no control data.
678 unsigned control_data_header_size_hwords
;
681 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
682 * if the control data is StreamID bits, or
683 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
684 * Ignored if control_data_header_size is 0.
686 unsigned control_data_format
;
688 bool include_primitive_id
;
693 * Dispatch mode, can be any of:
694 * GEN7_GS_DISPATCH_MODE_DUAL_OBJECT
695 * GEN7_GS_DISPATCH_MODE_DUAL_INSTANCE
696 * GEN7_GS_DISPATCH_MODE_SINGLE
701 * Gen6 transform feedback enabled flag.
703 bool gen6_xfb_enabled
;
706 * Gen6: Provoking vertex convention for odd-numbered triangles
712 * Gen6: Number of varyings that are output to transform feedback.
714 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
717 * Gen6: Map from the index of a transform feedback binding table entry to the
718 * gl_varying_slot that should be streamed out through that binding table
721 unsigned char transform_feedback_bindings
[BRW_MAX_SOL_BINDINGS
];
724 * Gen6: Map from the index of a transform feedback binding table entry to the
725 * swizzles that should be used when streaming out data through that
726 * binding table entry.
728 unsigned char transform_feedback_swizzles
[BRW_MAX_SOL_BINDINGS
];
732 * Stride in bytes between shader_time entries.
734 * We separate entries by a cacheline to reduce traffic between EUs writing to
737 #define SHADER_TIME_STRIDE 64
739 struct brw_cache_item
{
741 * Effectively part of the key, cache_id identifies what kind of state
742 * buffer is involved, and also which dirty flag should set.
744 enum brw_cache_id cache_id
;
745 /** 32-bit hash of the key data */
747 GLuint key_size
; /* for variable-sized keys */
754 struct brw_cache_item
*next
;
758 typedef bool (*cache_aux_compare_func
)(const void *a
, const void *b
);
759 typedef void (*cache_aux_free_func
)(const void *aux
);
762 struct brw_context
*brw
;
764 struct brw_cache_item
**items
;
766 GLuint size
, n_items
;
768 uint32_t next_offset
;
772 * Optional functions used in determining whether the prog_data for a new
773 * cache item matches an existing cache item (in case there's relevant data
774 * outside of the prog_data). If NULL, a plain memcmp is done.
776 cache_aux_compare_func aux_compare
[BRW_MAX_CACHE
];
777 /** Optional functions for freeing other pointers attached to a prog_data. */
778 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
782 /* Considered adding a member to this struct to document which flags
783 * an update might raise so that ordering of the state atoms can be
784 * checked or derived at runtime. Dropped the idea in favor of having
785 * a debug mode where the state is monitored for flags which are
786 * raised that have already been tested against.
788 struct brw_tracked_state
{
789 struct brw_state_flags dirty
;
790 void (*emit
)( struct brw_context
*brw
);
793 enum shader_time_shader_type
{
809 struct brw_vertex_buffer
{
810 /** Buffer object containing the uploaded vertex data */
813 /** Byte stride between elements in the uploaded array */
817 struct brw_vertex_element
{
818 const struct gl_client_array
*glarray
;
822 /** Offset of the first element within the buffer object */
826 struct brw_query_object
{
827 struct gl_query_object Base
;
829 /** Last query BO associated with this query. */
832 /** Last index in bo with query data for this object. */
836 struct intel_sync_object
{
837 struct gl_sync_object Base
;
839 /** Batch associated with this sync object */
849 struct intel_batchbuffer
{
850 /** Current batchbuffer being queued up. */
852 /** Last BO submitted to the hardware. Used for glFinish(). */
853 drm_intel_bo
*last_bo
;
854 /** BO for post-sync nonzero writes for gen6 workaround. */
855 drm_intel_bo
*workaround_bo
;
856 bool need_workaround_flush
;
858 uint16_t emit
, total
;
859 uint16_t used
, reserved_space
;
862 #define BATCH_SZ (8192*sizeof(uint32_t))
864 uint32_t state_batch_offset
;
865 enum brw_gpu_ring ring
;
866 bool needs_sol_reset
;
874 #define BRW_MAX_XFB_STREAMS 4
876 struct brw_transform_feedback_object
{
877 struct gl_transform_feedback_object base
;
879 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
880 drm_intel_bo
*offset_bo
;
882 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
885 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
886 GLenum primitive_mode
;
889 * Count of primitives generated during this transform feedback operation.
892 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
893 drm_intel_bo
*prim_count_bo
;
894 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
898 * Number of vertices written between last Begin/EndTransformFeedback().
900 * Used to implement DrawTransformFeedback().
902 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
903 bool vertices_written_valid
;
907 * Data shared between each programmable stage in the pipeline (vs, gs, and
910 struct brw_stage_state
912 gl_shader_stage stage
;
913 struct brw_stage_prog_data
*prog_data
;
916 * Optional scratch buffer used to store spilled register values and
917 * variably-indexed GRF arrays.
919 drm_intel_bo
*scratch_bo
;
921 /** Offset in the program cache to the program */
922 uint32_t prog_offset
;
924 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
925 uint32_t state_offset
;
927 uint32_t push_const_offset
; /* Offset in the batchbuffer */
928 int push_const_size
; /* in 256-bit register increments */
930 /* Binding table: pointers to SURFACE_STATE entries. */
931 uint32_t bind_bo_offset
;
932 uint32_t surf_offset
[BRW_MAX_SURFACES
];
934 /** SAMPLER_STATE count and table offset */
935 uint32_t sampler_count
;
936 uint32_t sampler_offset
;
941 * brw_context is derived from gl_context.
945 struct gl_context ctx
; /**< base class, must be first field */
949 void (*update_texture_surface
)(struct gl_context
*ctx
,
951 uint32_t *surf_offset
,
953 void (*update_renderbuffer_surface
)(struct brw_context
*brw
,
954 struct gl_renderbuffer
*rb
,
957 void (*update_null_renderbuffer_surface
)(struct brw_context
*brw
,
960 void (*create_raw_surface
)(struct brw_context
*brw
,
964 uint32_t *out_offset
,
966 void (*emit_buffer_surface_state
)(struct brw_context
*brw
,
967 uint32_t *out_offset
,
969 unsigned buffer_offset
,
970 unsigned surface_format
,
971 unsigned buffer_size
,
977 * Send the appropriate state packets to configure depth, stencil, and
978 * HiZ buffers (i965+ only)
980 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
981 struct intel_mipmap_tree
*depth_mt
,
982 uint32_t depth_offset
,
983 uint32_t depthbuffer_format
,
984 uint32_t depth_surface_type
,
985 struct intel_mipmap_tree
*stencil_mt
,
986 bool hiz
, bool separate_stencil
,
987 uint32_t width
, uint32_t height
,
988 uint32_t tile_x
, uint32_t tile_y
);
994 drm_intel_context
*hw_ctx
;
997 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
998 * and would need flushing before being used from another cache domain that
999 * isn't coherent with it (i.e. the sampler).
1001 struct set
*render_cache
;
1004 * Number of resets observed in the system at context creation.
1006 * This is tracked in the context so that we can determine that another
1007 * reset has occured.
1009 uint32_t reset_count
;
1011 struct intel_batchbuffer batch
;
1016 uint32_t next_offset
;
1020 * Set if rendering has occured to the drawable's front buffer.
1022 * This is used in the DRI2 case to detect that glFlush should also copy
1023 * the contents of the fake front buffer to the real front buffer.
1025 bool front_buffer_dirty
;
1027 /** Framerate throttling: @{ */
1028 drm_intel_bo
*first_post_swapbuffers_batch
;
1039 bool always_flush_batch
;
1040 bool always_flush_cache
;
1041 bool disable_throttling
;
1044 driOptionCache optionCache
;
1047 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
1049 GLenum reduced_primitive
;
1052 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
1053 * variable is set, this is the flag indicating to do expensive work that
1054 * might lead to a perf_debug() call.
1058 uint32_t max_gtt_map_object_size
;
1069 bool has_separate_stencil
;
1070 bool must_use_separate_stencil
;
1073 bool has_surface_tile_offset
;
1075 bool has_negative_rhw_bug
;
1081 * Some versions of Gen hardware don't do centroid interpolation correctly
1082 * on unlit pixels, causing incorrect values for derivatives near triangle
1083 * edges. Enabling this flag causes the fragment shader to use
1084 * non-centroid interpolation for unlit pixels, at the expense of two extra
1085 * fragment shader instructions.
1087 bool needs_unlit_centroid_workaround
;
1091 struct brw_state_flags dirty
;
1094 struct brw_cache cache
;
1096 /** IDs for meta stencil blit shader programs. */
1097 unsigned meta_stencil_blit_programs
[2];
1099 /* Whether a meta-operation is in progress. */
1100 bool meta_in_progress
;
1102 /* Whether the last depth/stencil packets were both NULL. */
1103 bool no_depth_or_stencil
;
1105 /* The last PMA stall bits programmed. */
1106 uint32_t pma_stall_bits
;
1109 /** Does the current draw use the index buffer? */
1112 int start_vertex_location
;
1113 int base_vertex_location
;
1116 * Buffer and offset used for GL_ARB_shader_draw_parameters
1117 * (for now, only gl_BaseVertex).
1119 drm_intel_bo
*draw_params_bo
;
1120 uint32_t draw_params_offset
;
1124 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
1125 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
1127 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
1131 /* Summary of size and varying of active arrays, so we can check
1132 * for changes to this state:
1134 unsigned int min_index
, max_index
;
1136 /* Offset from start of vertex buffer so we can avoid redefining
1137 * the same VB packed over and over again.
1139 unsigned int start_vertex_bias
;
1142 * Certain vertex attribute formats aren't natively handled by the
1143 * hardware and require special VS code to fix up their values.
1145 * These bitfields indicate which workarounds are needed.
1147 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
1152 * Index buffer for this draw_prims call.
1154 * Updates are signaled by BRW_NEW_INDICES.
1156 const struct _mesa_index_buffer
*ib
;
1158 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
1162 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
1163 * avoid re-uploading the IB packet over and over if we're actually
1164 * referencing the same index buffer.
1166 unsigned int start_vertex_offset
;
1169 /* Active vertex program:
1171 const struct gl_vertex_program
*vertex_program
;
1172 const struct gl_geometry_program
*geometry_program
;
1173 const struct gl_fragment_program
*fragment_program
;
1176 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
1177 * that we don't have to reemit that state every time we change FBOs.
1182 * Platform specific constants containing the maximum number of threads
1183 * for each pipeline stage.
1189 /* BRW_NEW_URB_ALLOCATIONS:
1192 GLuint vsize
; /* vertex size plus header in urb registers */
1193 GLuint gsize
; /* GS output size in urb registers */
1194 GLuint csize
; /* constant buffer size in urb registers */
1195 GLuint sfsize
; /* setup data size in urb registers */
1199 GLuint min_vs_entries
; /* Minimum number of VS entries */
1200 GLuint max_vs_entries
; /* Maximum number of VS entries */
1201 GLuint max_gs_entries
; /* Maximum number of GS entries */
1203 GLuint nr_vs_entries
;
1204 GLuint nr_gs_entries
;
1205 GLuint nr_clip_entries
;
1206 GLuint nr_sf_entries
;
1207 GLuint nr_cs_entries
;
1214 GLuint size
; /* Hardware URB size, in KB. */
1216 /* True if the most recently sent _3DSTATE_URB message allocated
1217 * URB space for the GS.
1223 /* BRW_NEW_CURBE_OFFSETS:
1226 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1227 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1235 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1236 * for upload to the CURBE.
1238 drm_intel_bo
*curbe_bo
;
1239 /** Offset within curbe_bo of space for current curbe entry */
1240 GLuint curbe_offset
;
1244 * Layout of vertex data exiting the vertex shader.
1246 * BRW_NEW_VUE_MAP_VS is flagged when this VUE map changes.
1248 struct brw_vue_map vue_map_vs
;
1251 * Layout of vertex data exiting the geometry portion of the pipleine.
1252 * This comes from the geometry shader if one exists, otherwise from the
1255 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1257 struct brw_vue_map vue_map_geom_out
;
1260 struct brw_stage_state base
;
1261 struct brw_vs_prog_data
*prog_data
;
1265 struct brw_stage_state base
;
1266 struct brw_gs_prog_data
*prog_data
;
1269 * True if the 3DSTATE_GS command most recently emitted to the 3D
1270 * pipeline enabled the GS; false otherwise.
1276 struct brw_ff_gs_prog_data
*prog_data
;
1279 /** Offset in the program cache to the CLIP program pre-gen6 */
1280 uint32_t prog_offset
;
1281 uint32_t state_offset
;
1283 uint32_t bind_bo_offset
;
1285 * Surface offsets for the binding table. We only need surfaces to
1286 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1287 * need in this case.
1289 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1293 struct brw_clip_prog_data
*prog_data
;
1295 /** Offset in the program cache to the CLIP program pre-gen6 */
1296 uint32_t prog_offset
;
1298 /* Offset in the batch to the CLIP state on pre-gen6. */
1299 uint32_t state_offset
;
1301 /* As of gen6, this is the offset in the batch to the CLIP VP,
1309 struct brw_sf_prog_data
*prog_data
;
1311 /** Offset in the program cache to the CLIP program pre-gen6 */
1312 uint32_t prog_offset
;
1313 uint32_t state_offset
;
1315 bool viewport_transform_enable
;
1319 struct brw_stage_state base
;
1320 struct brw_wm_prog_data
*prog_data
;
1325 * Buffer object used in place of multisampled null render targets on
1326 * Gen6. See brw_update_null_renderbuffer_surface().
1328 drm_intel_bo
*multisampled_null_render_target_bo
;
1329 uint32_t fast_clear_op
;
1334 uint32_t state_offset
;
1335 uint32_t blend_state_offset
;
1336 uint32_t depth_stencil_state_offset
;
1341 struct brw_query_object
*obj
;
1346 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1347 const int *statistics_registers
;
1349 /** The number of active monitors using OA counters. */
1353 * A buffer object storing OA counter snapshots taken at the start and
1354 * end of each batch (creating "bookends" around the batch).
1356 drm_intel_bo
*bookend_bo
;
1358 /** The number of snapshots written to bookend_bo. */
1359 int bookend_snapshots
;
1362 * An array of monitors whose results haven't yet been assembled based on
1363 * the data in buffer objects.
1365 * These may be active, or have already ended. However, the results
1366 * have not been requested.
1368 struct brw_perf_monitor_object
**unresolved
;
1369 int unresolved_elements
;
1370 int unresolved_array_size
;
1373 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1374 * the counter which MI_REPORT_PERF_COUNT stores there.
1376 const int *oa_snapshot_layout
;
1378 /** Number of 32-bit entries in a hardware counter snapshot. */
1379 int entries_per_oa_snapshot
;
1383 const struct brw_tracked_state
**atoms
;
1385 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1389 enum aub_state_struct_type type
;
1390 } *state_batch_list
;
1391 int state_batch_count
;
1393 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1394 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1396 /* Interpolation modes, one byte per vue slot.
1397 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1399 struct interpolation_mode_map interpolation_mode
;
1401 /* PrimitiveRestart */
1404 bool enable_cut_index
;
1407 /** Computed depth/stencil/hiz state from the current attached
1408 * renderbuffers, valid only during the drawing state upload loop after
1409 * brw_workaround_depthstencil_alignment().
1412 struct intel_mipmap_tree
*depth_mt
;
1413 struct intel_mipmap_tree
*stencil_mt
;
1415 /* Inter-tile (page-aligned) byte offsets. */
1416 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1417 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1418 uint32_t tile_x
, tile_y
;
1421 uint32_t num_instances
;
1426 struct gl_shader_program
**shader_programs
;
1427 struct gl_program
**programs
;
1428 enum shader_time_shader_type
*types
;
1429 uint64_t *cumulative
;
1435 struct brw_fast_clear_state
*fast_clear_state
;
1437 __DRIcontext
*driContext
;
1438 struct intel_screen
*intelScreen
;
1441 /*======================================================================
1444 void brwInitVtbl( struct brw_context
*brw
);
1447 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1449 /*======================================================================
1452 extern const char *const brw_vendor_string
;
1454 extern const char *brw_get_renderer_string(unsigned deviceID
);
1457 DRI_CONF_BO_REUSE_DISABLED
,
1458 DRI_CONF_BO_REUSE_ALL
1461 void intel_update_renderbuffers(__DRIcontext
*context
,
1462 __DRIdrawable
*drawable
);
1463 void intel_prepare_render(struct brw_context
*brw
);
1465 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1466 __DRIdrawable
*drawable
);
1468 GLboolean
brwCreateContext(gl_api api
,
1469 const struct gl_config
*mesaVis
,
1470 __DRIcontext
*driContextPriv
,
1471 unsigned major_version
,
1472 unsigned minor_version
,
1476 void *sharedContextPrivate
);
1478 /*======================================================================
1481 GLuint
brw_get_rb_for_slice(struct brw_context
*brw
,
1482 struct intel_mipmap_tree
*mt
,
1483 unsigned level
, unsigned layer
, bool flat
);
1485 void brw_meta_updownsample(struct brw_context
*brw
,
1486 struct intel_mipmap_tree
*src
,
1487 struct intel_mipmap_tree
*dst
);
1489 void brw_meta_fbo_stencil_blit(struct brw_context
*brw
,
1490 GLfloat srcX0
, GLfloat srcY0
,
1491 GLfloat srcX1
, GLfloat srcY1
,
1492 GLfloat dstX0
, GLfloat dstY0
,
1493 GLfloat dstX1
, GLfloat dstY1
);
1495 void brw_meta_stencil_updownsample(struct brw_context
*brw
,
1496 struct intel_mipmap_tree
*src
,
1497 struct intel_mipmap_tree
*dst
);
1499 bool brw_meta_fast_clear(struct brw_context
*brw
,
1500 struct gl_framebuffer
*fb
,
1502 bool partial_clear
);
1505 brw_meta_resolve_color(struct brw_context
*brw
,
1506 struct intel_mipmap_tree
*mt
);
1508 brw_meta_fast_clear_free(struct brw_context
*brw
);
1511 /*======================================================================
1514 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1515 uint32_t depth_level
,
1516 uint32_t depth_layer
,
1517 struct intel_mipmap_tree
*stencil_mt
,
1518 uint32_t *out_tile_mask_x
,
1519 uint32_t *out_tile_mask_y
);
1520 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1521 GLbitfield clear_mask
);
1523 /* brw_object_purgeable.c */
1524 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1526 /*======================================================================
1529 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1530 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1531 void brw_emit_query_begin(struct brw_context
*brw
);
1532 void brw_emit_query_end(struct brw_context
*brw
);
1534 /** gen6_queryobj.c */
1535 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1536 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1537 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1538 void brw_store_register_mem64(struct brw_context
*brw
,
1539 drm_intel_bo
*bo
, uint32_t reg
, int idx
);
1541 /** intel_batchbuffer.c */
1542 void brw_load_register_mem(struct brw_context
*brw
,
1545 uint32_t read_domains
, uint32_t write_domain
,
1548 /*======================================================================
1551 void brw_debug_batch(struct brw_context
*brw
);
1552 void brw_annotate_aub(struct brw_context
*brw
);
1554 /*======================================================================
1557 void brw_validate_textures( struct brw_context
*brw
);
1560 /*======================================================================
1563 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1565 int brw_get_scratch_size(int size
);
1566 void brw_get_scratch_bo(struct brw_context
*brw
,
1567 drm_intel_bo
**scratch_bo
, int size
);
1568 void brw_init_shader_time(struct brw_context
*brw
);
1569 int brw_get_shader_time_index(struct brw_context
*brw
,
1570 struct gl_shader_program
*shader_prog
,
1571 struct gl_program
*prog
,
1572 enum shader_time_shader_type type
);
1573 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1574 void brw_destroy_shader_time(struct brw_context
*brw
);
1578 void brw_upload_urb_fence(struct brw_context
*brw
);
1582 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1584 /* brw_fs_reg_allocate.cpp
1586 void brw_fs_alloc_reg_sets(struct intel_screen
*screen
);
1588 /* brw_vec4_reg_allocate.cpp */
1589 void brw_vec4_alloc_reg_set(struct intel_screen
*screen
);
1592 int brw_disassemble_inst(FILE *file
, struct brw_context
*brw
,
1593 struct brw_inst
*inst
, bool is_compacted
);
1596 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1598 /* brw_draw_upload.c */
1599 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1600 const struct gl_client_array
*glarray
);
1601 unsigned brw_get_index_type(GLenum type
);
1602 void brw_prepare_vertices(struct brw_context
*brw
);
1604 /* brw_wm_surface_state.c */
1605 void brw_init_surface_formats(struct brw_context
*brw
);
1606 void brw_create_constant_surface(struct brw_context
*brw
,
1610 uint32_t *out_offset
,
1612 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1614 uint32_t *surf_offset
);
1616 brw_update_sol_surface(struct brw_context
*brw
,
1617 struct gl_buffer_object
*buffer_obj
,
1618 uint32_t *out_offset
, unsigned num_vector_components
,
1619 unsigned stride_dwords
, unsigned offset_dwords
);
1620 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1621 struct gl_shader
*shader
,
1622 struct brw_stage_state
*stage_state
,
1623 struct brw_stage_prog_data
*prog_data
,
1625 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1626 struct gl_shader_program
*prog
,
1627 struct brw_stage_state
*stage_state
,
1628 struct brw_stage_prog_data
*prog_data
);
1630 /* brw_surface_formats.c */
1631 bool brw_is_hiz_depth_format(struct brw_context
*ctx
, mesa_format format
);
1632 bool brw_render_target_supported(struct brw_context
*brw
,
1633 struct gl_renderbuffer
*rb
);
1634 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1636 /* brw_performance_monitor.c */
1637 void brw_init_performance_monitors(struct brw_context
*brw
);
1638 void brw_dump_perf_monitors(struct brw_context
*brw
);
1639 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1640 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1642 /* intel_buffer_objects.c */
1643 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1644 const char *bo_name
);
1645 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1646 const char *bo_name
);
1648 /* intel_extensions.c */
1649 extern void intelInitExtensions(struct gl_context
*ctx
);
1652 extern int intel_translate_shadow_compare_func(GLenum func
);
1653 extern int intel_translate_compare_func(GLenum func
);
1654 extern int intel_translate_stencil_op(GLenum op
);
1655 extern int intel_translate_logic_op(GLenum opcode
);
1657 /* intel_syncobj.c */
1658 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1661 struct gl_transform_feedback_object
*
1662 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1664 brw_delete_transform_feedback(struct gl_context
*ctx
,
1665 struct gl_transform_feedback_object
*obj
);
1667 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1668 struct gl_transform_feedback_object
*obj
);
1670 brw_end_transform_feedback(struct gl_context
*ctx
,
1671 struct gl_transform_feedback_object
*obj
);
1673 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1674 struct gl_transform_feedback_object
*obj
,
1677 /* gen7_sol_state.c */
1679 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1680 struct gl_transform_feedback_object
*obj
);
1682 gen7_end_transform_feedback(struct gl_context
*ctx
,
1683 struct gl_transform_feedback_object
*obj
);
1685 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1686 struct gl_transform_feedback_object
*obj
);
1688 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1689 struct gl_transform_feedback_object
*obj
);
1691 /* brw_blorp_blit.cpp */
1693 brw_blorp_framebuffer(struct brw_context
*brw
,
1694 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1695 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1696 GLbitfield mask
, GLenum filter
);
1699 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1700 struct gl_renderbuffer
*src_rb
,
1701 struct gl_texture_image
*dst_image
,
1703 int srcX0
, int srcY0
,
1704 int dstX0
, int dstY0
,
1705 int width
, int height
);
1707 /* gen6_multisample_state.c */
1709 gen6_determine_sample_mask(struct brw_context
*brw
);
1712 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1713 unsigned num_samples
);
1715 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1717 gen6_get_sample_position(struct gl_context
*ctx
,
1718 struct gl_framebuffer
*fb
,
1722 gen6_set_sample_maps(struct gl_context
*ctx
);
1724 /* gen8_multisample_state.c */
1725 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1726 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1730 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1731 unsigned gs_size
, unsigned fs_size
);
1734 gen7_emit_urb_state(struct brw_context
*brw
,
1735 unsigned nr_vs_entries
, unsigned vs_size
,
1736 unsigned vs_start
, unsigned nr_gs_entries
,
1737 unsigned gs_size
, unsigned gs_start
);
1742 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1744 /*======================================================================
1745 * Inline conversion functions. These are better-typed than the
1746 * macros used previously:
1748 static inline struct brw_context
*
1749 brw_context( struct gl_context
*ctx
)
1751 return (struct brw_context
*)ctx
;
1754 static inline struct brw_vertex_program
*
1755 brw_vertex_program(struct gl_vertex_program
*p
)
1757 return (struct brw_vertex_program
*) p
;
1760 static inline const struct brw_vertex_program
*
1761 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1763 return (const struct brw_vertex_program
*) p
;
1766 static inline struct brw_geometry_program
*
1767 brw_geometry_program(struct gl_geometry_program
*p
)
1769 return (struct brw_geometry_program
*) p
;
1772 static inline struct brw_fragment_program
*
1773 brw_fragment_program(struct gl_fragment_program
*p
)
1775 return (struct brw_fragment_program
*) p
;
1778 static inline const struct brw_fragment_program
*
1779 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1781 return (const struct brw_fragment_program
*) p
;
1785 * Pre-gen6, the register file of the EUs was shared between threads,
1786 * and each thread used some subset allocated on a 16-register block
1787 * granularity. The unit states wanted these block counts.
1790 brw_register_blocks(int reg_count
)
1792 return ALIGN(reg_count
, 16) / 16 - 1;
1795 static inline uint32_t
1796 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1797 uint32_t prog_offset
)
1799 if (brw
->gen
>= 5) {
1800 /* Using state base address. */
1804 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1808 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1810 return brw
->cache
.bo
->offset64
+ prog_offset
;
1813 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1814 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1815 struct exec_list
*instructions
);
1816 bool brw_do_lower_unnormalized_offset(struct exec_list
*instructions
);
1818 struct opcode_desc
{
1824 extern const struct opcode_desc opcode_descs
[128];
1825 extern const char * const conditional_modifier
[16];
1828 brw_emit_depthbuffer(struct brw_context
*brw
);
1831 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1832 struct intel_mipmap_tree
*depth_mt
,
1833 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1834 uint32_t depth_surface_type
,
1835 struct intel_mipmap_tree
*stencil_mt
,
1836 bool hiz
, bool separate_stencil
,
1837 uint32_t width
, uint32_t height
,
1838 uint32_t tile_x
, uint32_t tile_y
);
1841 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1842 struct intel_mipmap_tree
*depth_mt
,
1843 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1844 uint32_t depth_surface_type
,
1845 struct intel_mipmap_tree
*stencil_mt
,
1846 bool hiz
, bool separate_stencil
,
1847 uint32_t width
, uint32_t height
,
1848 uint32_t tile_x
, uint32_t tile_y
);
1851 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1852 struct intel_mipmap_tree
*depth_mt
,
1853 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1854 uint32_t depth_surface_type
,
1855 struct intel_mipmap_tree
*stencil_mt
,
1856 bool hiz
, bool separate_stencil
,
1857 uint32_t width
, uint32_t height
,
1858 uint32_t tile_x
, uint32_t tile_y
);
1860 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1861 struct intel_mipmap_tree
*depth_mt
,
1862 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1863 uint32_t depth_surface_type
,
1864 struct intel_mipmap_tree
*stencil_mt
,
1865 bool hiz
, bool separate_stencil
,
1866 uint32_t width
, uint32_t height
,
1867 uint32_t tile_x
, uint32_t tile_y
);
1869 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1870 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);
1872 uint32_t get_hw_prim_for_gl_prim(int mode
);
1875 brw_setup_vec4_key_clip_info(struct brw_context
*brw
,
1876 struct brw_vec4_prog_key
*key
,
1877 bool program_uses_clip_distance
);
1880 gen6_upload_push_constants(struct brw_context
*brw
,
1881 const struct gl_program
*prog
,
1882 const struct brw_stage_prog_data
*prog_data
,
1883 struct brw_stage_state
*stage_state
,
1884 enum aub_state_struct_type type
);
1886 /* ================================================================
1887 * From linux kernel i386 header files, copes with odd sizes better
1888 * than COPY_DWORDS would:
1889 * XXX Put this in src/mesa/main/imports.h ???
1891 #if defined(i386) || defined(__i386__)
1892 static inline void * __memcpy(void * to
, const void * from
, size_t n
)
1895 __asm__
__volatile__(
1900 "1:\ttestb $1,%b4\n\t"
1904 : "=&c" (d0
), "=&D" (d1
), "=&S" (d2
)
1905 :"0" (n
/4), "q" (n
),"1" ((long) to
),"2" ((long) from
)
1910 #define __memcpy(a,b,c) memcpy(a,b,c)