2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
38 #include "main/imports.h"
39 #include "main/macros.h"
41 #include "main/mtypes.h"
42 #include "brw_structs.h"
46 /* Evil hack for using libdrm in a c++ compiler. */
51 #include <intel_bufmgr.h>
61 #include "intel_debug.h"
62 #include "intel_screen.h"
63 #include "intel_tex_obj.h"
67 * URB - uniform resource buffer. A mid-sized buffer which is
68 * partitioned between the fixed function units and used for passing
69 * values (vertices, primitives, constants) between them.
71 * CURBE - constant URB entry. An urb region (entry) used to hold
72 * constant values which the fixed function units can be instructed to
73 * preload into the GRF when spawning a thread.
75 * VUE - vertex URB entry. An urb entry holding a vertex and usually
76 * a vertex header. The header contains control information and
77 * things like primitive type, Begin/end flags and clip codes.
79 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
80 * unit holding rasterization and interpolation parameters.
82 * GRF - general register file. One of several register files
83 * addressable by programmed threads. The inputs (r0, payload, curbe,
84 * urb) of the thread are preloaded to this area before the thread is
85 * spawned. The registers are individually 8 dwords wide and suitable
86 * for general usage. Registers holding thread input values are not
87 * special and may be overwritten.
89 * MRF - message register file. Threads communicate (and terminate)
90 * by sending messages. Message parameters are placed in contiguous
91 * MRF registers. All program output is via these messages. URB
92 * entries are populated by sending a message to the shared URB
93 * function containing the new data, together with a control word,
94 * often an unmodified copy of R0.
96 * R0 - GRF register 0. Typically holds control information used when
97 * sending messages to other threads.
99 * EU or GEN4 EU: The name of the programmable subsystem of the
100 * i965 hardware. Threads are executed by the EU, the registers
101 * described above are part of the EU architecture.
103 * Fixed function units:
105 * CS - Command streamer. Notional first unit, little software
106 * interaction. Holds the URB entries used for constant data, ie the
109 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
110 * this unit is responsible for pulling vertices out of vertex buffers
111 * in vram and injecting them into the processing pipe as VUEs. If
112 * enabled, it first passes them to a VS thread which is a good place
113 * for the driver to implement any active vertex shader.
115 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
116 * enabled, incoming strips etc are passed to GS threads in individual
117 * line/triangle/point units. The GS thread may perform arbitary
118 * computation and emit whatever primtives with whatever vertices it
119 * chooses. This makes GS an excellent place to implement GL's
120 * unfilled polygon modes, though of course it is capable of much
121 * more. Additionally, GS is used to translate away primitives not
122 * handled by latter units, including Quads and Lineloops.
124 * CS - Clipper. Mesa's clipping algorithms are imported to run on
125 * this unit. The fixed function part performs cliptesting against
126 * the 6 fixed clipplanes and makes descisions on whether or not the
127 * incoming primitive needs to be passed to a thread for clipping.
128 * User clip planes are handled via cooperation with the VS thread.
130 * SF - Strips Fans or Setup: Triangles are prepared for
131 * rasterization. Interpolation coefficients are calculated.
132 * Flatshading and two-side lighting usually performed here.
134 * WM - Windower. Interpolation of vertex attributes performed here.
135 * Fragment shader implemented here. SIMD aspects of EU taken full
136 * advantage of, as pixels are processed in blocks of 16.
138 * CC - Color Calculator. No EU threads associated with this unit.
139 * Handles blending and (presumably) depth and stencil testing.
142 #define INTEL_WRITE_PART 0x1
143 #define INTEL_WRITE_FULL 0x2
144 #define INTEL_READ 0x4
146 #define BRW_MAX_CURBE (32*16)
149 struct brw_instruction
;
150 struct brw_vs_prog_key
;
151 struct brw_vec4_prog_key
;
152 struct brw_wm_prog_key
;
153 struct brw_wm_prog_data
;
154 struct brw_perf_bo_layout
;
158 BRW_STATE_FRAGMENT_PROGRAM
,
159 BRW_STATE_GEOMETRY_PROGRAM
,
160 BRW_STATE_VERTEX_PROGRAM
,
161 BRW_STATE_CURBE_OFFSETS
,
162 BRW_STATE_REDUCED_PRIMITIVE
,
167 BRW_STATE_VS_BINDING_TABLE
,
168 BRW_STATE_GS_BINDING_TABLE
,
169 BRW_STATE_PS_BINDING_TABLE
,
173 BRW_STATE_INDEX_BUFFER
,
174 BRW_STATE_VS_CONSTBUF
,
175 BRW_STATE_GS_CONSTBUF
,
176 BRW_STATE_PROGRAM_CACHE
,
177 BRW_STATE_STATE_BASE_ADDRESS
,
178 BRW_STATE_VUE_MAP_VS
,
179 BRW_STATE_VUE_MAP_GEOM_OUT
,
180 BRW_STATE_TRANSFORM_FEEDBACK
,
181 BRW_STATE_RASTERIZER_DISCARD
,
183 BRW_STATE_UNIFORM_BUFFER
,
184 BRW_STATE_ATOMIC_BUFFER
,
185 BRW_STATE_META_IN_PROGRESS
,
186 BRW_STATE_INTERPOLATION_MAP
,
187 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
191 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
192 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
193 #define BRW_NEW_GEOMETRY_PROGRAM (1 << BRW_STATE_GEOMETRY_PROGRAM)
194 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
195 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
196 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
197 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
198 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
199 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
200 #define BRW_NEW_SURFACES (1 << BRW_STATE_SURFACES)
201 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
202 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
203 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
204 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
205 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
207 * Used for any batch entry with a relocated pointer that will be used
208 * by any 3D rendering.
210 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
211 /** \see brw.state.depth_region */
212 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
213 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
214 #define BRW_NEW_GS_CONSTBUF (1 << BRW_STATE_GS_CONSTBUF)
215 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
216 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
217 #define BRW_NEW_VUE_MAP_VS (1 << BRW_STATE_VUE_MAP_VS)
218 #define BRW_NEW_VUE_MAP_GEOM_OUT (1 << BRW_STATE_VUE_MAP_GEOM_OUT)
219 #define BRW_NEW_TRANSFORM_FEEDBACK (1 << BRW_STATE_TRANSFORM_FEEDBACK)
220 #define BRW_NEW_RASTERIZER_DISCARD (1 << BRW_STATE_RASTERIZER_DISCARD)
221 #define BRW_NEW_STATS_WM (1 << BRW_STATE_STATS_WM)
222 #define BRW_NEW_UNIFORM_BUFFER (1 << BRW_STATE_UNIFORM_BUFFER)
223 #define BRW_NEW_ATOMIC_BUFFER (1 << BRW_STATE_ATOMIC_BUFFER)
224 #define BRW_NEW_META_IN_PROGRESS (1 << BRW_STATE_META_IN_PROGRESS)
225 #define BRW_NEW_INTERPOLATION_MAP (1 << BRW_STATE_INTERPOLATION_MAP)
226 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1 << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
228 struct brw_state_flags
{
229 /** State update flags signalled by mesa internals */
232 * State update flags signalled as the result of brw_tracked_state updates
235 /** State update flags signalled by brw_state_cache.c searches */
239 #define AUB_TRACE_TYPE_MASK 0x0000ff00
240 #define AUB_TRACE_TYPE_NOTYPE (0 << 8)
241 #define AUB_TRACE_TYPE_BATCH (1 << 8)
242 #define AUB_TRACE_TYPE_VERTEX_BUFFER (5 << 8)
243 #define AUB_TRACE_TYPE_2D_MAP (6 << 8)
244 #define AUB_TRACE_TYPE_CUBE_MAP (7 << 8)
245 #define AUB_TRACE_TYPE_VOLUME_MAP (9 << 8)
246 #define AUB_TRACE_TYPE_1D_MAP (10 << 8)
247 #define AUB_TRACE_TYPE_CONSTANT_BUFFER (11 << 8)
248 #define AUB_TRACE_TYPE_CONSTANT_URB (12 << 8)
249 #define AUB_TRACE_TYPE_INDEX_BUFFER (13 << 8)
250 #define AUB_TRACE_TYPE_GENERAL (14 << 8)
251 #define AUB_TRACE_TYPE_SURFACE (15 << 8)
254 * state_struct_type enum values are encoded with the top 16 bits representing
255 * the type to be delivered to the .aub file, and the bottom 16 bits
256 * representing the subtype. This macro performs the encoding.
258 #define ENCODE_SS_TYPE(type, subtype) (((type) << 16) | (subtype))
260 enum state_struct_type
{
261 AUB_TRACE_VS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 1),
262 AUB_TRACE_GS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 2),
263 AUB_TRACE_CLIP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 3),
264 AUB_TRACE_SF_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 4),
265 AUB_TRACE_WM_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 5),
266 AUB_TRACE_CC_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 6),
267 AUB_TRACE_CLIP_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 7),
268 AUB_TRACE_SF_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 8),
269 AUB_TRACE_CC_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x9),
270 AUB_TRACE_SAMPLER_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xa),
271 AUB_TRACE_KERNEL_INSTRUCTIONS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xb),
272 AUB_TRACE_SCRATCH_SPACE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xc),
273 AUB_TRACE_SAMPLER_DEFAULT_COLOR
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xd),
275 AUB_TRACE_SCISSOR_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x15),
276 AUB_TRACE_BLEND_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x16),
277 AUB_TRACE_DEPTH_STENCIL_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x17),
279 AUB_TRACE_VERTEX_BUFFER
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_VERTEX_BUFFER
, 0),
280 AUB_TRACE_BINDING_TABLE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x100),
281 AUB_TRACE_SURFACE_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x200),
282 AUB_TRACE_VS_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 0),
283 AUB_TRACE_WM_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 1),
287 * Decode a state_struct_type value to determine the type that should be
288 * stored in the .aub file.
290 static inline uint32_t AUB_TRACE_TYPE(enum state_struct_type ss_type
)
292 return (ss_type
& 0xFFFF0000) >> 16;
296 * Decode a state_struct_type value to determine the subtype that should be
297 * stored in the .aub file.
299 static inline uint32_t AUB_TRACE_SUBTYPE(enum state_struct_type ss_type
)
301 return ss_type
& 0xFFFF;
304 /** Subclass of Mesa vertex program */
305 struct brw_vertex_program
{
306 struct gl_vertex_program program
;
311 /** Subclass of Mesa geometry program */
312 struct brw_geometry_program
{
313 struct gl_geometry_program program
;
314 unsigned id
; /**< serial no. to identify geom progs, never re-used */
318 /** Subclass of Mesa fragment program */
319 struct brw_fragment_program
{
320 struct gl_fragment_program program
;
321 GLuint id
; /**< serial no. to identify frag progs, never re-used */
325 struct gl_shader base
;
329 /** Shader IR transformed for native compile, at link time. */
330 struct exec_list
*ir
;
333 /* Note: If adding fields that need anything besides a normal memcmp() for
334 * comparing them, be sure to go fix the the stage-specific
335 * prog_data_compare().
337 struct brw_stage_prog_data
{
339 /** size of our binding table. */
343 * surface indices for the various groups of surfaces
345 uint32_t pull_constants_start
;
346 uint32_t texture_start
;
347 uint32_t gather_texture_start
;
350 uint32_t shader_time_start
;
355 /* Data about a particular attempt to compile a program. Note that
356 * there can be many of these, each in a different GL state
357 * corresponding to a different brw_wm_prog_key struct, with different
360 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
363 struct brw_wm_prog_data
{
364 struct brw_stage_prog_data base
;
366 GLuint curb_read_length
;
367 GLuint num_varying_inputs
;
369 GLuint first_curbe_grf
;
370 GLuint first_curbe_grf_16
;
372 GLuint reg_blocks_16
;
373 GLuint total_scratch
;
377 * surface indices the WM-specific surfaces
379 uint32_t render_target_start
;
383 GLuint nr_params
; /**< number of float params/constants */
384 GLuint nr_pull_params
;
386 uint32_t prog_offset_16
;
389 * Mask of which interpolation modes are required by the fragment shader.
390 * Used in hardware setup on gen6+.
392 uint32_t barycentric_interp_modes
;
395 * Map from gl_varying_slot to the position within the FS setup data
396 * payload where the varying's attribute vertex deltas should be delivered.
397 * For varying slots that are not used by the FS, the value is -1.
399 int urb_setup
[VARYING_SLOT_MAX
];
401 /* Pointers to tracked values (only valid once
402 * _mesa_load_state_parameters has been called at runtime).
404 * These must be the last fields of the struct (see
405 * brw_wm_prog_data_compare()).
408 const float **pull_param
;
412 * Enum representing the i965-specific vertex results that don't correspond
413 * exactly to any element of gl_varying_slot. The values of this enum are
414 * assigned such that they don't conflict with gl_varying_slot.
418 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
419 BRW_VARYING_SLOT_PAD
,
421 * Technically this is not a varying but just a placeholder that
422 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
423 * builtin variable to be compiled correctly. see compile_sf_prog() for
426 BRW_VARYING_SLOT_PNTC
,
427 BRW_VARYING_SLOT_COUNT
432 * Data structure recording the relationship between the gl_varying_slot enum
433 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
434 * single octaword within the VUE (128 bits).
436 * Note that each BRW register contains 256 bits (2 octawords), so when
437 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
438 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
439 * in a vertex shader), each register corresponds to a single VUE slot, since
440 * it contains data for two separate vertices.
444 * Bitfield representing all varying slots that are (a) stored in this VUE
445 * map, and (b) actually written by the shader. Does not include any of
446 * the additional varying slots defined in brw_varying_slot.
448 GLbitfield64 slots_valid
;
451 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
452 * not stored in a slot (because they are not written, or because
453 * additional processing is applied before storing them in the VUE), the
456 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
459 * Map from VUE slot to gl_varying_slot value. For slots that do not
460 * directly correspond to a gl_varying_slot, the value comes from
463 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
464 * simplifies code that uses the value stored in slot_to_varying to
465 * create a bit mask).
467 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
470 * Total number of VUE slots in use
476 * Convert a VUE slot number into a byte offset within the VUE.
478 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
484 * Convert a vertex output (brw_varying_slot) into a byte offset within the
487 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
490 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
493 void brw_compute_vue_map(struct brw_context
*brw
, struct brw_vue_map
*vue_map
,
494 GLbitfield64 slots_valid
);
498 * Bitmask indicating which fragment shader inputs represent varyings (and
499 * hence have to be delivered to the fragment shader by the SF/SBE stage).
501 #define BRW_FS_VARYING_INPUT_MASK \
502 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
503 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
507 * Mapping of VUE map slots to interpolation modes.
509 struct interpolation_mode_map
{
510 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
513 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
515 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
516 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
522 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
524 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
525 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
532 struct brw_sf_prog_data
{
533 GLuint urb_read_length
;
536 /* Each vertex may have upto 12 attributes, 4 components each,
537 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
540 * Actually we use 4 for each, so call it 12 rows.
542 GLuint urb_entry_size
;
547 * We always program SF to start reading at an offset of 1 (2 varying slots)
548 * from the start of the vertex URB entry. This causes it to skip:
549 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
550 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
552 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
555 struct brw_clip_prog_data
{
556 GLuint curb_read_length
; /* user planes? */
558 GLuint urb_read_length
;
562 struct brw_ff_gs_prog_data
{
563 GLuint urb_read_length
;
567 * Gen6 transform feedback: Amount by which the streaming vertex buffer
568 * indices should be incremented each time the GS is invoked.
570 unsigned svbi_postincrement_value
;
574 /* Note: brw_vec4_prog_data_compare() must be updated when adding fields to
577 struct brw_vec4_prog_data
{
578 struct brw_stage_prog_data base
;
579 struct brw_vue_map vue_map
;
582 * Register where the thread expects to find input data from the URB
583 * (typically uniforms, followed by per-vertex inputs).
585 unsigned dispatch_grf_start_reg
;
587 GLuint curb_read_length
;
588 GLuint urb_read_length
;
590 GLuint nr_params
; /**< number of float params/constants */
591 GLuint nr_pull_params
; /**< number of dwords referenced by pull_param[] */
592 GLuint total_scratch
;
594 /* Used for calculating urb partitions. In the VS, this is the size of the
595 * URB entry used for both input and output to the thread. In the GS, this
596 * is the size of the URB entry used for output.
598 GLuint urb_entry_size
;
600 /* These pointers must appear last. See brw_vec4_prog_data_compare(). */
602 const float **pull_param
;
606 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
609 struct brw_vs_prog_data
{
610 struct brw_vec4_prog_data base
;
612 GLbitfield64 inputs_read
;
618 /* Note: brw_gs_prog_data_compare() must be updated when adding fields to
621 struct brw_gs_prog_data
623 struct brw_vec4_prog_data base
;
626 * Size of an output vertex, measured in HWORDS (32 bytes).
628 unsigned output_vertex_size_hwords
;
630 unsigned output_topology
;
633 * Size of the control data (cut bits or StreamID bits), in hwords (32
634 * bytes). 0 if there is no control data.
636 unsigned control_data_header_size_hwords
;
639 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
640 * if the control data is StreamID bits, or
641 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
642 * Ignored if control_data_header_size is 0.
644 unsigned control_data_format
;
646 bool include_primitive_id
;
649 * True if the thread should be dispatched in DUAL_INSTANCE mode, false if
650 * it should be dispatched in DUAL_OBJECT mode.
652 bool dual_instanced_dispatch
;
655 /** Number of texture sampler units */
656 #define BRW_MAX_TEX_UNIT 16
658 /** Max number of render targets in a shader */
659 #define BRW_MAX_DRAW_BUFFERS 8
661 /** Max number of atomic counter buffer objects in a shader */
662 #define BRW_MAX_ABO 4
665 * Max number of binding table entries used for stream output.
667 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
668 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
670 * On Gen6, the size of transform feedback data is limited not by the number
671 * of components but by the number of binding table entries we set aside. We
672 * use one binding table entry for a float, one entry for a vector, and one
673 * entry per matrix column. Since the only way we can communicate our
674 * transform feedback capabilities to the client is via
675 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
676 * worst case, in which all the varyings are floats, so we use up one binding
677 * table entry per component. Therefore we need to set aside at least 64
678 * binding table entries for use by transform feedback.
680 * Note: since we don't currently pack varyings, it is currently impossible
681 * for the client to actually use up all of these binding table entries--if
682 * all of their varyings were floats, they would run out of varying slots and
683 * fail to link. But that's a bug, so it seems prudent to go ahead and
684 * allocate the number of binding table entries we will need once the bug is
687 #define BRW_MAX_SOL_BINDINGS 64
689 /** Maximum number of actual buffers used for stream output */
690 #define BRW_MAX_SOL_BUFFERS 4
692 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
693 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
696 2 /* shader time, pull constants */)
698 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
699 #define BRW_MAX_GEN6_GS_SURFACES SURF_INDEX_GEN6_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
702 * Stride in bytes between shader_time entries.
704 * We separate entries by a cacheline to reduce traffic between EUs writing to
707 #define SHADER_TIME_STRIDE 64
714 BRW_BLORP_CONST_COLOR_PROG
,
719 BRW_SF_UNIT
, /* scissor state on gen6 */
732 struct brw_cache_item
{
734 * Effectively part of the key, cache_id identifies what kind of state
735 * buffer is involved, and also which brw->state.dirty.cache flag should
736 * be set when this cache item is chosen.
738 enum brw_cache_id cache_id
;
739 /** 32-bit hash of the key data */
741 GLuint key_size
; /* for variable-sized keys */
748 struct brw_cache_item
*next
;
752 typedef bool (*cache_aux_compare_func
)(const void *a
, const void *b
);
753 typedef void (*cache_aux_free_func
)(const void *aux
);
756 struct brw_context
*brw
;
758 struct brw_cache_item
**items
;
760 GLuint size
, n_items
;
762 uint32_t next_offset
;
766 * Optional functions used in determining whether the prog_data for a new
767 * cache item matches an existing cache item (in case there's relevant data
768 * outside of the prog_data). If NULL, a plain memcmp is done.
770 cache_aux_compare_func aux_compare
[BRW_MAX_CACHE
];
771 /** Optional functions for freeing other pointers attached to a prog_data. */
772 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
776 /* Considered adding a member to this struct to document which flags
777 * an update might raise so that ordering of the state atoms can be
778 * checked or derived at runtime. Dropped the idea in favor of having
779 * a debug mode where the state is monitored for flags which are
780 * raised that have already been tested against.
782 struct brw_tracked_state
{
783 struct brw_state_flags dirty
;
784 void (*emit
)( struct brw_context
*brw
);
787 enum shader_time_shader_type
{
800 /* Flags for brw->state.cache.
802 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
803 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
804 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
805 #define CACHE_NEW_BLORP_BLIT_PROG (1<<BRW_BLORP_BLIT_PROG)
806 #define CACHE_NEW_BLORP_CONST_COLOR_PROG (1<<BRW_BLORP_CONST_COLOR_PROG)
807 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
808 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
809 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
810 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
811 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
812 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
813 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
814 #define CACHE_NEW_FF_GS_UNIT (1<<BRW_FF_GS_UNIT)
815 #define CACHE_NEW_FF_GS_PROG (1<<BRW_FF_GS_PROG)
816 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
817 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
818 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
819 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
821 struct brw_cached_batch_item
{
822 struct header
*header
;
824 struct brw_cached_batch_item
*next
;
827 struct brw_vertex_buffer
{
828 /** Buffer object containing the uploaded vertex data */
831 /** Byte stride between elements in the uploaded array */
835 struct brw_vertex_element
{
836 const struct gl_client_array
*glarray
;
840 /** The corresponding Mesa vertex attribute */
841 gl_vert_attrib attrib
;
842 /** Offset of the first element within the buffer object */
846 struct brw_query_object
{
847 struct gl_query_object Base
;
849 /** Last query BO associated with this query. */
852 /** Last index in bo with query data for this object. */
856 struct intel_sync_object
{
857 struct gl_sync_object Base
;
859 /** Batch associated with this sync object */
863 struct intel_batchbuffer
{
864 /** Current batchbuffer being queued up. */
866 /** Last BO submitted to the hardware. Used for glFinish(). */
867 drm_intel_bo
*last_bo
;
868 /** BO for post-sync nonzero writes for gen6 workaround. */
869 drm_intel_bo
*workaround_bo
;
870 bool need_workaround_flush
;
872 struct cached_batch_item
*cached_items
;
874 uint16_t emit
, total
;
875 uint16_t used
, reserved_space
;
878 #define BATCH_SZ (8192*sizeof(uint32_t))
880 uint32_t state_batch_offset
;
882 bool needs_sol_reset
;
891 * Data shared between each programmable stage in the pipeline (vs, gs, and
894 struct brw_stage_state
896 struct brw_stage_prog_data
*prog_data
;
899 * Optional scratch buffer used to store spilled register values and
900 * variably-indexed GRF arrays.
902 drm_intel_bo
*scratch_bo
;
904 /** Pull constant buffer */
905 drm_intel_bo
*const_bo
;
907 /** Offset in the program cache to the program */
908 uint32_t prog_offset
;
910 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
911 uint32_t state_offset
;
913 uint32_t push_const_offset
; /* Offset in the batchbuffer */
914 int push_const_size
; /* in 256-bit register increments */
916 /* Binding table: pointers to SURFACE_STATE entries. */
917 uint32_t bind_bo_offset
;
918 uint32_t surf_offset
[BRW_MAX_SURFACES
];
920 /** SAMPLER_STATE count and table offset */
921 uint32_t sampler_count
;
922 uint32_t sampler_offset
;
924 /** Offsets in the batch to sampler default colors (texture border color) */
925 uint32_t sdc_offset
[BRW_MAX_TEX_UNIT
];
930 * brw_context is derived from gl_context.
934 struct gl_context ctx
; /**< base class, must be first field */
938 void (*update_texture_surface
)(struct gl_context
*ctx
,
940 uint32_t *surf_offset
,
942 void (*update_renderbuffer_surface
)(struct brw_context
*brw
,
943 struct gl_renderbuffer
*rb
,
946 void (*update_null_renderbuffer_surface
)(struct brw_context
*brw
,
948 void (*create_constant_surface
)(struct brw_context
*brw
,
952 uint32_t *out_offset
,
955 void (*create_raw_surface
)(struct brw_context
*brw
,
959 uint32_t *out_offset
,
962 /** Upload a SAMPLER_STATE table. */
963 void (*upload_sampler_state_table
)(struct brw_context
*brw
,
964 struct gl_program
*prog
,
965 uint32_t sampler_count
,
966 uint32_t *sst_offset
,
967 uint32_t *sdc_offset
);
970 * Send the appropriate state packets to configure depth, stencil, and
971 * HiZ buffers (i965+ only)
973 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
974 struct intel_mipmap_tree
*depth_mt
,
975 uint32_t depth_offset
,
976 uint32_t depthbuffer_format
,
977 uint32_t depth_surface_type
,
978 struct intel_mipmap_tree
*stencil_mt
,
979 bool hiz
, bool separate_stencil
,
980 uint32_t width
, uint32_t height
,
981 uint32_t tile_x
, uint32_t tile_y
);
987 drm_intel_context
*hw_ctx
;
989 struct intel_batchbuffer batch
;
996 uint32_t buffer_offset
;
1001 * Set if rendering has occured to the drawable's front buffer.
1003 * This is used in the DRI2 case to detect that glFlush should also copy
1004 * the contents of the fake front buffer to the real front buffer.
1006 bool front_buffer_dirty
;
1009 * Track whether front-buffer rendering is currently enabled
1011 * A separate flag is used to track this in order to support MRT more
1014 bool is_front_buffer_rendering
;
1017 * Track whether front-buffer is the current read target.
1019 * This is closely associated with is_front_buffer_rendering, but may
1020 * be set separately. The DRI2 fake front buffer must be referenced
1023 bool is_front_buffer_reading
;
1025 /** Framerate throttling: @{ */
1026 drm_intel_bo
*first_post_swapbuffers_batch
;
1037 bool always_flush_batch
;
1038 bool always_flush_cache
;
1039 bool disable_throttling
;
1041 bool disable_derivative_optimization
;
1043 driOptionCache optionCache
;
1046 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
1048 GLenum reduced_primitive
;
1051 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
1052 * variable is set, this is the flag indicating to do expensive work that
1053 * might lead to a perf_debug() call.
1057 uint32_t max_gtt_map_object_size
;
1067 bool has_separate_stencil
;
1068 bool must_use_separate_stencil
;
1071 bool has_surface_tile_offset
;
1073 bool has_negative_rhw_bug
;
1077 * Some versions of Gen hardware don't do centroid interpolation correctly
1078 * on unlit pixels, causing incorrect values for derivatives near triangle
1079 * edges. Enabling this flag causes the fragment shader to use
1080 * non-centroid interpolation for unlit pixels, at the expense of two extra
1081 * fragment shader instructions.
1083 bool needs_unlit_centroid_workaround
;
1087 struct brw_state_flags dirty
;
1090 struct brw_cache cache
;
1091 struct brw_cached_batch_item
*cached_batch_items
;
1093 /* Whether a meta-operation is in progress. */
1094 bool meta_in_progress
;
1097 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
1098 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
1100 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
1104 /* Summary of size and varying of active arrays, so we can check
1105 * for changes to this state:
1107 unsigned int min_index
, max_index
;
1109 /* Offset from start of vertex buffer so we can avoid redefining
1110 * the same VB packed over and over again.
1112 unsigned int start_vertex_bias
;
1117 * Index buffer for this draw_prims call.
1119 * Updates are signaled by BRW_NEW_INDICES.
1121 const struct _mesa_index_buffer
*ib
;
1123 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
1127 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
1128 * avoid re-uploading the IB packet over and over if we're actually
1129 * referencing the same index buffer.
1131 unsigned int start_vertex_offset
;
1134 /* Active vertex program:
1136 const struct gl_vertex_program
*vertex_program
;
1137 const struct gl_geometry_program
*geometry_program
;
1138 const struct gl_fragment_program
*fragment_program
;
1140 /* hw-dependent 3DSTATE_VF_STATISTICS opcode */
1141 uint32_t CMD_VF_STATISTICS
;
1142 /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
1143 uint32_t CMD_PIPELINE_SELECT
;
1146 * Platform specific constants containing the maximum number of threads
1147 * for each pipeline stage.
1153 /* BRW_NEW_URB_ALLOCATIONS:
1156 GLuint vsize
; /* vertex size plus header in urb registers */
1157 GLuint csize
; /* constant buffer size in urb registers */
1158 GLuint sfsize
; /* setup data size in urb registers */
1162 GLuint min_vs_entries
; /* Minimum number of VS entries */
1163 GLuint max_vs_entries
; /* Maximum number of VS entries */
1164 GLuint max_gs_entries
; /* Maximum number of GS entries */
1166 GLuint nr_vs_entries
;
1167 GLuint nr_gs_entries
;
1168 GLuint nr_clip_entries
;
1169 GLuint nr_sf_entries
;
1170 GLuint nr_cs_entries
;
1177 GLuint size
; /* Hardware URB size, in KB. */
1179 /* gen6: True if the most recently sent _3DSTATE_URB message allocated
1180 * URB space for the GS.
1182 bool gen6_gs_previously_active
;
1186 /* BRW_NEW_CURBE_OFFSETS:
1189 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1190 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1197 drm_intel_bo
*curbe_bo
;
1198 /** Offset within curbe_bo of space for current curbe entry */
1199 GLuint curbe_offset
;
1200 /** Offset within curbe_bo of space for next curbe entry */
1201 GLuint curbe_next_offset
;
1204 * Copy of the last set of CURBEs uploaded. Frequently we'll end up
1205 * in brw_curbe.c with the same set of constant data to be uploaded,
1206 * so we'd rather not upload new constants in that case (it can cause
1207 * a pipeline bubble since only up to 4 can be pipelined at a time).
1211 * Allocation for where to calculate the next set of CURBEs.
1212 * It's a hot enough path that malloc/free of that data matters.
1219 * Layout of vertex data exiting the vertex shader.
1221 * BRW_NEW_VUE_MAP_VS is flagged when this VUE map changes.
1223 struct brw_vue_map vue_map_vs
;
1226 * Layout of vertex data exiting the geometry portion of the pipleine.
1227 * This comes from the geometry shader if one exists, otherwise from the
1230 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1232 struct brw_vue_map vue_map_geom_out
;
1235 * Data structures used by all vec4 program compiles (not specific to any
1236 * particular program).
1239 struct ra_regs
*regs
;
1242 * Array of the ra classes for the unaligned contiguous register
1248 * Mapping for register-allocated objects in *regs to the first
1249 * GRF for that object.
1251 uint8_t *ra_reg_to_grf
;
1255 struct brw_stage_state base
;
1256 struct brw_vs_prog_data
*prog_data
;
1260 struct brw_stage_state base
;
1261 struct brw_gs_prog_data
*prog_data
;
1265 struct brw_ff_gs_prog_data
*prog_data
;
1268 /** Offset in the program cache to the CLIP program pre-gen6 */
1269 uint32_t prog_offset
;
1270 uint32_t state_offset
;
1272 uint32_t bind_bo_offset
;
1273 uint32_t surf_offset
[BRW_MAX_GEN6_GS_SURFACES
];
1277 struct brw_clip_prog_data
*prog_data
;
1279 /** Offset in the program cache to the CLIP program pre-gen6 */
1280 uint32_t prog_offset
;
1282 /* Offset in the batch to the CLIP state on pre-gen6. */
1283 uint32_t state_offset
;
1285 /* As of gen6, this is the offset in the batch to the CLIP VP,
1293 struct brw_sf_prog_data
*prog_data
;
1295 /** Offset in the program cache to the CLIP program pre-gen6 */
1296 uint32_t prog_offset
;
1297 uint32_t state_offset
;
1302 struct brw_stage_state base
;
1303 struct brw_wm_prog_data
*prog_data
;
1308 * Buffer object used in place of multisampled null render targets on
1309 * Gen6. See brw_update_null_renderbuffer_surface().
1311 drm_intel_bo
*multisampled_null_render_target_bo
;
1314 struct ra_regs
*regs
;
1317 * Array of the ra classes for the unaligned contiguous register
1318 * block sizes used, indexed by register size.
1323 * Mapping for register-allocated objects in *regs to the first
1324 * GRF for that object.
1326 uint8_t *ra_reg_to_grf
;
1329 * ra class for the aligned pairs we use for PLN, which doesn't
1330 * appear in *classes.
1332 int aligned_pairs_class
;
1338 uint32_t state_offset
;
1339 uint32_t blend_state_offset
;
1340 uint32_t depth_stencil_state_offset
;
1345 struct brw_query_object
*obj
;
1350 /* A map describing which counters are stored at a particular 32-bit
1351 * offset in the buffer object.
1353 const struct brw_perf_bo_layout
*bo_layout
;
1355 /* Number of 32-bit entries in the buffer object. */
1360 const struct brw_tracked_state
**atoms
;
1362 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1366 enum state_struct_type type
;
1367 } *state_batch_list
;
1368 int state_batch_count
;
1370 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1371 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1373 /* Interpolation modes, one byte per vue slot.
1374 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1376 struct interpolation_mode_map interpolation_mode
;
1378 /* PrimitiveRestart */
1381 bool enable_cut_index
;
1384 /** Computed depth/stencil/hiz state from the current attached
1385 * renderbuffers, valid only during the drawing state upload loop after
1386 * brw_workaround_depthstencil_alignment().
1389 struct intel_mipmap_tree
*depth_mt
;
1390 struct intel_mipmap_tree
*stencil_mt
;
1392 /* Inter-tile (page-aligned) byte offsets. */
1393 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1394 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1395 uint32_t tile_x
, tile_y
;
1398 uint32_t num_instances
;
1403 struct gl_shader_program
**shader_programs
;
1404 struct gl_program
**programs
;
1405 enum shader_time_shader_type
*types
;
1406 uint64_t *cumulative
;
1412 __DRIcontext
*driContext
;
1413 struct intel_screen
*intelScreen
;
1414 void (*saved_viewport
)(struct gl_context
*ctx
,
1415 GLint x
, GLint y
, GLsizei width
, GLsizei height
);
1419 is_power_of_two(uint32_t value
)
1421 return (value
& (value
- 1)) == 0;
1424 /*======================================================================
1427 void brwInitVtbl( struct brw_context
*brw
);
1430 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1432 /*======================================================================
1435 extern void intelFinish(struct gl_context
* ctx
);
1438 DRI_CONF_BO_REUSE_DISABLED
,
1439 DRI_CONF_BO_REUSE_ALL
1442 void intel_update_renderbuffers(__DRIcontext
*context
,
1443 __DRIdrawable
*drawable
);
1444 void intel_prepare_render(struct brw_context
*brw
);
1446 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1447 __DRIdrawable
*drawable
);
1449 bool brwCreateContext(gl_api api
,
1450 const struct gl_config
*mesaVis
,
1451 __DRIcontext
*driContextPriv
,
1452 unsigned major_version
,
1453 unsigned minor_version
,
1456 void *sharedContextPrivate
);
1458 /*======================================================================
1461 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1462 uint32_t depth_level
,
1463 uint32_t depth_layer
,
1464 struct intel_mipmap_tree
*stencil_mt
,
1465 uint32_t *out_tile_mask_x
,
1466 uint32_t *out_tile_mask_y
);
1467 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1468 GLbitfield clear_mask
);
1470 /* brw_object_purgeable.c */
1471 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1473 /*======================================================================
1476 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1477 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1478 void brw_emit_query_begin(struct brw_context
*brw
);
1479 void brw_emit_query_end(struct brw_context
*brw
);
1481 /** gen6_queryobj.c */
1482 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1483 void brw_store_register_mem64(struct brw_context
*brw
,
1484 drm_intel_bo
*bo
, uint32_t reg
, int idx
);
1486 /*======================================================================
1489 void brw_debug_batch(struct brw_context
*brw
);
1490 void brw_annotate_aub(struct brw_context
*brw
);
1492 /*======================================================================
1495 void brw_validate_textures( struct brw_context
*brw
);
1498 /*======================================================================
1501 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1503 int brw_get_scratch_size(int size
);
1504 void brw_get_scratch_bo(struct brw_context
*brw
,
1505 drm_intel_bo
**scratch_bo
, int size
);
1506 void brw_init_shader_time(struct brw_context
*brw
);
1507 int brw_get_shader_time_index(struct brw_context
*brw
,
1508 struct gl_shader_program
*shader_prog
,
1509 struct gl_program
*prog
,
1510 enum shader_time_shader_type type
);
1511 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1512 void brw_destroy_shader_time(struct brw_context
*brw
);
1516 void brw_upload_urb_fence(struct brw_context
*brw
);
1520 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1522 /* brw_fs_reg_allocate.cpp
1524 void brw_fs_alloc_reg_sets(struct brw_context
*brw
);
1526 /* brw_vec4_reg_allocate.cpp */
1527 void brw_vec4_alloc_reg_set(struct brw_context
*brw
);
1530 int brw_disasm (FILE *file
, struct brw_instruction
*inst
, int gen
);
1533 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1535 /* brw_draw_upload.c */
1536 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1537 const struct gl_client_array
*glarray
);
1538 unsigned brw_get_index_type(GLenum type
);
1540 /* brw_wm_surface_state.c */
1541 void brw_init_surface_formats(struct brw_context
*brw
);
1543 brw_update_sol_surface(struct brw_context
*brw
,
1544 struct gl_buffer_object
*buffer_obj
,
1545 uint32_t *out_offset
, unsigned num_vector_components
,
1546 unsigned stride_dwords
, unsigned offset_dwords
);
1547 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1548 struct gl_shader
*shader
,
1549 struct brw_stage_state
*stage_state
,
1550 struct brw_stage_prog_data
*prog_data
);
1551 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1552 struct gl_shader_program
*prog
,
1553 struct brw_stage_state
*stage_state
,
1554 struct brw_stage_prog_data
*prog_data
);
1556 /* brw_surface_formats.c */
1557 bool brw_is_hiz_depth_format(struct brw_context
*ctx
, gl_format format
);
1558 bool brw_render_target_supported(struct brw_context
*brw
,
1559 struct gl_renderbuffer
*rb
);
1561 /* brw_performance_monitor.c */
1562 void brw_init_performance_monitors(struct brw_context
*brw
);
1564 /* intel_extensions.c */
1565 extern void intelInitExtensions(struct gl_context
*ctx
);
1568 extern int intel_translate_shadow_compare_func(GLenum func
);
1569 extern int intel_translate_compare_func(GLenum func
);
1570 extern int intel_translate_stencil_op(GLenum op
);
1571 extern int intel_translate_logic_op(GLenum opcode
);
1573 /* intel_syncobj.c */
1574 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1578 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1579 struct gl_transform_feedback_object
*obj
);
1581 brw_end_transform_feedback(struct gl_context
*ctx
,
1582 struct gl_transform_feedback_object
*obj
);
1584 /* gen7_sol_state.c */
1586 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1587 struct gl_transform_feedback_object
*obj
);
1589 gen7_end_transform_feedback(struct gl_context
*ctx
,
1590 struct gl_transform_feedback_object
*obj
);
1592 /* brw_blorp_blit.cpp */
1594 brw_blorp_framebuffer(struct brw_context
*brw
,
1595 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1596 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1597 GLbitfield mask
, GLenum filter
);
1600 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1601 struct gl_renderbuffer
*src_rb
,
1602 struct gl_texture_image
*dst_image
,
1604 int srcX0
, int srcY0
,
1605 int dstX0
, int dstY0
,
1606 int width
, int height
);
1608 /* gen6_multisample_state.c */
1610 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1611 unsigned num_samples
);
1613 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
,
1614 unsigned num_samples
, float coverage
,
1615 bool coverage_invert
, unsigned sample_mask
);
1617 gen6_get_sample_position(struct gl_context
*ctx
,
1618 struct gl_framebuffer
*fb
,
1624 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1625 unsigned gs_size
, unsigned fs_size
);
1628 gen7_emit_urb_state(struct brw_context
*brw
,
1629 unsigned nr_vs_entries
, unsigned vs_size
,
1630 unsigned vs_start
, unsigned nr_gs_entries
,
1631 unsigned gs_size
, unsigned gs_start
);
1635 /*======================================================================
1636 * Inline conversion functions. These are better-typed than the
1637 * macros used previously:
1639 static INLINE
struct brw_context
*
1640 brw_context( struct gl_context
*ctx
)
1642 return (struct brw_context
*)ctx
;
1645 static INLINE
struct brw_vertex_program
*
1646 brw_vertex_program(struct gl_vertex_program
*p
)
1648 return (struct brw_vertex_program
*) p
;
1651 static INLINE
const struct brw_vertex_program
*
1652 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1654 return (const struct brw_vertex_program
*) p
;
1657 static INLINE
struct brw_geometry_program
*
1658 brw_geometry_program(struct gl_geometry_program
*p
)
1660 return (struct brw_geometry_program
*) p
;
1663 static INLINE
struct brw_fragment_program
*
1664 brw_fragment_program(struct gl_fragment_program
*p
)
1666 return (struct brw_fragment_program
*) p
;
1669 static INLINE
const struct brw_fragment_program
*
1670 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1672 return (const struct brw_fragment_program
*) p
;
1676 * Pre-gen6, the register file of the EUs was shared between threads,
1677 * and each thread used some subset allocated on a 16-register block
1678 * granularity. The unit states wanted these block counts.
1681 brw_register_blocks(int reg_count
)
1683 return ALIGN(reg_count
, 16) / 16 - 1;
1686 static inline uint32_t
1687 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1688 uint32_t prog_offset
)
1690 if (brw
->gen
>= 5) {
1691 /* Using state base address. */
1695 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1699 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1701 return brw
->cache
.bo
->offset
+ prog_offset
;
1704 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1705 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1706 struct exec_list
*instructions
);
1707 bool brw_do_lower_offset_arrays(struct exec_list
*instructions
);
1708 bool brw_do_lower_unnormalized_offset(struct exec_list
*instructions
);
1710 struct opcode_desc
{
1716 extern const struct opcode_desc opcode_descs
[128];
1719 brw_emit_depthbuffer(struct brw_context
*brw
);
1722 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1723 struct intel_mipmap_tree
*depth_mt
,
1724 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1725 uint32_t depth_surface_type
,
1726 struct intel_mipmap_tree
*stencil_mt
,
1727 bool hiz
, bool separate_stencil
,
1728 uint32_t width
, uint32_t height
,
1729 uint32_t tile_x
, uint32_t tile_y
);
1732 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1733 struct intel_mipmap_tree
*depth_mt
,
1734 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1735 uint32_t depth_surface_type
,
1736 struct intel_mipmap_tree
*stencil_mt
,
1737 bool hiz
, bool separate_stencil
,
1738 uint32_t width
, uint32_t height
,
1739 uint32_t tile_x
, uint32_t tile_y
);
1741 extern const GLuint prim_to_hw_prim
[GL_TRIANGLE_STRIP_ADJACENCY
+1];
1744 brw_setup_vec4_key_clip_info(struct brw_context
*brw
,
1745 struct brw_vec4_prog_key
*key
,
1746 bool program_uses_clip_distance
);
1749 gen6_upload_vec4_push_constants(struct brw_context
*brw
,
1750 const struct gl_program
*prog
,
1751 const struct brw_vec4_prog_data
*prog_data
,
1752 struct brw_stage_state
*stage_state
,
1753 enum state_struct_type type
);
1755 /* ================================================================
1756 * From linux kernel i386 header files, copes with odd sizes better
1757 * than COPY_DWORDS would:
1758 * XXX Put this in src/mesa/main/imports.h ???
1760 #if defined(i386) || defined(__i386__)
1761 static INLINE
void * __memcpy(void * to
, const void * from
, size_t n
)
1764 __asm__
__volatile__(
1769 "1:\ttestb $1,%b4\n\t"
1773 : "=&c" (d0
), "=&D" (d1
), "=&S" (d2
)
1774 :"0" (n
/4), "q" (n
),"1" ((long) to
),"2" ((long) from
)
1779 #define __memcpy(a,b,c) memcpy(a,b,c)