2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
36 #include "intel_context.h"
37 #include "brw_structs.h"
38 #include "main/imports.h"
43 * URB - uniform resource buffer. A mid-sized buffer which is
44 * partitioned between the fixed function units and used for passing
45 * values (vertices, primitives, constants) between them.
47 * CURBE - constant URB entry. An urb region (entry) used to hold
48 * constant values which the fixed function units can be instructed to
49 * preload into the GRF when spawning a thread.
51 * VUE - vertex URB entry. An urb entry holding a vertex and usually
52 * a vertex header. The header contains control information and
53 * things like primitive type, Begin/end flags and clip codes.
55 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
56 * unit holding rasterization and interpolation parameters.
58 * GRF - general register file. One of several register files
59 * addressable by programmed threads. The inputs (r0, payload, curbe,
60 * urb) of the thread are preloaded to this area before the thread is
61 * spawned. The registers are individually 8 dwords wide and suitable
62 * for general usage. Registers holding thread input values are not
63 * special and may be overwritten.
65 * MRF - message register file. Threads communicate (and terminate)
66 * by sending messages. Message parameters are placed in contiguous
67 * MRF registers. All program output is via these messages. URB
68 * entries are populated by sending a message to the shared URB
69 * function containing the new data, together with a control word,
70 * often an unmodified copy of R0.
72 * R0 - GRF register 0. Typically holds control information used when
73 * sending messages to other threads.
75 * EU or GEN4 EU: The name of the programmable subsystem of the
76 * i965 hardware. Threads are executed by the EU, the registers
77 * described above are part of the EU architecture.
79 * Fixed function units:
81 * CS - Command streamer. Notional first unit, little software
82 * interaction. Holds the URB entries used for constant data, ie the
85 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
86 * this unit is responsible for pulling vertices out of vertex buffers
87 * in vram and injecting them into the processing pipe as VUEs. If
88 * enabled, it first passes them to a VS thread which is a good place
89 * for the driver to implement any active vertex shader.
91 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
92 * enabled, incoming strips etc are passed to GS threads in individual
93 * line/triangle/point units. The GS thread may perform arbitary
94 * computation and emit whatever primtives with whatever vertices it
95 * chooses. This makes GS an excellent place to implement GL's
96 * unfilled polygon modes, though of course it is capable of much
97 * more. Additionally, GS is used to translate away primitives not
98 * handled by latter units, including Quads and Lineloops.
100 * CS - Clipper. Mesa's clipping algorithms are imported to run on
101 * this unit. The fixed function part performs cliptesting against
102 * the 6 fixed clipplanes and makes descisions on whether or not the
103 * incoming primitive needs to be passed to a thread for clipping.
104 * User clip planes are handled via cooperation with the VS thread.
106 * SF - Strips Fans or Setup: Triangles are prepared for
107 * rasterization. Interpolation coefficients are calculated.
108 * Flatshading and two-side lighting usually performed here.
110 * WM - Windower. Interpolation of vertex attributes performed here.
111 * Fragment shader implemented here. SIMD aspects of EU taken full
112 * advantage of, as pixels are processed in blocks of 16.
114 * CC - Color Calculator. No EU threads associated with this unit.
115 * Handles blending and (presumably) depth and stencil testing.
119 #define BRW_MAX_CURBE (32*16)
125 BRW_STATE_FRAGMENT_PROGRAM
,
126 BRW_STATE_VERTEX_PROGRAM
,
127 BRW_STATE_INPUT_DIMENSIONS
,
128 BRW_STATE_CURBE_OFFSETS
,
129 BRW_STATE_REDUCED_PRIMITIVE
,
132 BRW_STATE_WM_INPUT_DIMENSIONS
,
134 BRW_STATE_WM_SURFACES
,
135 BRW_STATE_VS_BINDING_TABLE
,
136 BRW_STATE_GS_BINDING_TABLE
,
137 BRW_STATE_PS_BINDING_TABLE
,
141 BRW_STATE_NR_WM_SURFACES
,
142 BRW_STATE_NR_VS_SURFACES
,
143 BRW_STATE_INDEX_BUFFER
,
144 BRW_STATE_VS_CONSTBUF
,
145 BRW_STATE_WM_CONSTBUF
,
146 BRW_STATE_PROGRAM_CACHE
,
147 BRW_STATE_STATE_BASE_ADDRESS
,
150 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
151 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
152 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
153 #define BRW_NEW_INPUT_DIMENSIONS (1 << BRW_STATE_INPUT_DIMENSIONS)
154 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
155 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
156 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
157 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
158 #define BRW_NEW_WM_INPUT_DIMENSIONS (1 << BRW_STATE_WM_INPUT_DIMENSIONS)
159 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
160 #define BRW_NEW_WM_SURFACES (1 << BRW_STATE_WM_SURFACES)
161 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
162 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
163 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
164 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
165 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
167 * Used for any batch entry with a relocated pointer that will be used
168 * by any 3D rendering.
170 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
171 /** \see brw.state.depth_region */
172 #define BRW_NEW_NR_WM_SURFACES (1 << BRW_STATE_NR_WM_SURFACES)
173 #define BRW_NEW_NR_VS_SURFACES (1 << BRW_STATE_NR_VS_SURFACES)
174 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
175 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
176 #define BRW_NEW_WM_CONSTBUF (1 << BRW_STATE_WM_CONSTBUF)
177 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
178 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
180 struct brw_state_flags
{
181 /** State update flags signalled by mesa internals */
184 * State update flags signalled as the result of brw_tracked_state updates
187 /** State update flags signalled by brw_state_cache.c searches */
191 enum state_struct_type
{
192 AUB_TRACE_VS_STATE
= 1,
193 AUB_TRACE_GS_STATE
= 2,
194 AUB_TRACE_CLIP_STATE
= 3,
195 AUB_TRACE_SF_STATE
= 4,
196 AUB_TRACE_WM_STATE
= 5,
197 AUB_TRACE_CC_STATE
= 6,
198 AUB_TRACE_CLIP_VP_STATE
= 7,
199 AUB_TRACE_SF_VP_STATE
= 8,
200 AUB_TRACE_CC_VP_STATE
= 0x9,
201 AUB_TRACE_SAMPLER_STATE
= 0xa,
202 AUB_TRACE_KERNEL_INSTRUCTIONS
= 0xb,
203 AUB_TRACE_SCRATCH_SPACE
= 0xc,
204 AUB_TRACE_SAMPLER_DEFAULT_COLOR
= 0xd,
206 AUB_TRACE_SCISSOR_STATE
= 0x15,
207 AUB_TRACE_BLEND_STATE
= 0x16,
208 AUB_TRACE_DEPTH_STENCIL_STATE
= 0x17,
210 /* Not written to .aub files the same way the structures above are. */
211 AUB_TRACE_NO_TYPE
= 0x100,
212 AUB_TRACE_BINDING_TABLE
= 0x101,
213 AUB_TRACE_SURFACE_STATE
= 0x102,
214 AUB_TRACE_VS_CONSTANTS
= 0x103,
215 AUB_TRACE_WM_CONSTANTS
= 0x104,
218 /** Subclass of Mesa vertex program */
219 struct brw_vertex_program
{
220 struct gl_vertex_program program
;
222 GLboolean use_const_buffer
;
226 /** Subclass of Mesa fragment program */
227 struct brw_fragment_program
{
228 struct gl_fragment_program program
;
229 GLuint id
; /**< serial no. to identify frag progs, never re-used */
231 /** for debugging, which texture units are referenced */
232 GLbitfield tex_units_used
;
236 struct gl_shader base
;
238 /** Shader IR transformed for native compile, at link time. */
239 struct exec_list
*ir
;
242 struct brw_shader_program
{
243 struct gl_shader_program base
;
246 enum param_conversion
{
253 /* Data about a particular attempt to compile a program. Note that
254 * there can be many of these, each in a different GL state
255 * corresponding to a different brw_wm_prog_key struct, with different
258 struct brw_wm_prog_data
{
259 GLuint curb_read_length
;
260 GLuint urb_read_length
;
262 GLuint first_curbe_grf
;
263 GLuint first_curbe_grf_16
;
265 GLuint reg_blocks_16
;
266 GLuint total_scratch
;
268 GLuint nr_params
; /**< number of float params/constants */
269 GLuint nr_pull_params
;
272 uint32_t prog_offset_16
;
274 /* Pointer to tracked values (only valid once
275 * _mesa_load_state_parameters has been called at runtime).
277 const float *param
[MAX_UNIFORMS
* 4]; /* should be: BRW_MAX_CURBE */
278 enum param_conversion param_convert
[MAX_UNIFORMS
* 4];
279 const float *pull_param
[MAX_UNIFORMS
* 4];
280 enum param_conversion pull_param_convert
[MAX_UNIFORMS
* 4];
283 struct brw_sf_prog_data
{
284 GLuint urb_read_length
;
287 /* Each vertex may have upto 12 attributes, 4 components each,
288 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
291 * Actually we use 4 for each, so call it 12 rows.
293 GLuint urb_entry_size
;
296 struct brw_clip_prog_data
{
297 GLuint curb_read_length
; /* user planes? */
299 GLuint urb_read_length
;
303 struct brw_gs_prog_data
{
304 GLuint urb_read_length
;
308 struct brw_vs_prog_data
{
309 GLuint curb_read_length
;
310 GLuint urb_read_length
;
312 GLbitfield64 outputs_written
;
313 GLuint nr_params
; /**< number of float params/constants */
317 /* Used for calculating urb partitions:
319 GLuint urb_entry_size
;
323 /* Size == 0 if output either not written, or always [0,0,0,1]
325 struct brw_vs_ouput_sizes
{
326 GLubyte output_size
[VERT_RESULT_MAX
];
330 /** Number of texture sampler units */
331 #define BRW_MAX_TEX_UNIT 16
333 /** Max number of render targets in a shader */
334 #define BRW_MAX_DRAW_BUFFERS 8
337 * Size of our surface binding table for the WM.
338 * This contains pointers to the drawing surfaces and current texture
339 * objects and shader constant buffers (+2).
341 #define BRW_WM_MAX_SURF (BRW_MAX_DRAW_BUFFERS + BRW_MAX_TEX_UNIT + 1)
344 * Helpers to convert drawing buffers, textures and constant buffers
345 * to surface binding table indexes, for WM.
347 #define SURF_INDEX_DRAW(d) (d)
348 #define SURF_INDEX_FRAG_CONST_BUFFER (BRW_MAX_DRAW_BUFFERS)
349 #define SURF_INDEX_TEXTURE(t) (BRW_MAX_DRAW_BUFFERS + 1 + (t))
352 * Size of surface binding table for the VS.
353 * Only one constant buffer for now.
355 #define BRW_VS_MAX_SURF 1
358 * Only a VS constant buffer
360 #define SURF_INDEX_VERT_CONST_BUFFER 0
365 BRW_DEPTH_STENCIL_STATE
,
366 BRW_COLOR_CALC_STATE
,
374 BRW_SF_UNIT
, /* scissor state on gen6 */
386 struct brw_cache_item
{
388 * Effectively part of the key, cache_id identifies what kind of state
389 * buffer is involved, and also which brw->state.dirty.cache flag should
390 * be set when this cache item is chosen.
392 enum brw_cache_id cache_id
;
393 /** 32-bit hash of the key data */
395 GLuint key_size
; /* for variable-sized keys */
402 struct brw_cache_item
*next
;
408 struct brw_context
*brw
;
410 struct brw_cache_item
**items
;
412 GLuint size
, n_items
;
414 uint32_t next_offset
;
419 /* Considered adding a member to this struct to document which flags
420 * an update might raise so that ordering of the state atoms can be
421 * checked or derived at runtime. Dropped the idea in favor of having
422 * a debug mode where the state is monitored for flags which are
423 * raised that have already been tested against.
425 struct brw_tracked_state
{
426 struct brw_state_flags dirty
;
427 void (*prepare
)( struct brw_context
*brw
);
428 void (*emit
)( struct brw_context
*brw
);
431 /* Flags for brw->state.cache.
433 #define CACHE_NEW_BLEND_STATE (1<<BRW_BLEND_STATE)
434 #define CACHE_NEW_DEPTH_STENCIL_STATE (1<<BRW_DEPTH_STENCIL_STATE)
435 #define CACHE_NEW_COLOR_CALC_STATE (1<<BRW_COLOR_CALC_STATE)
436 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
437 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
438 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
439 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
440 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
441 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
442 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
443 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
444 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
445 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
446 #define CACHE_NEW_GS_UNIT (1<<BRW_GS_UNIT)
447 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
448 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
449 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
450 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
452 struct brw_cached_batch_item
{
453 struct header
*header
;
455 struct brw_cached_batch_item
*next
;
460 /* Protect against a future where VERT_ATTRIB_MAX > 32. Wouldn't life
461 * be easier if C allowed arrays of packed elements?
463 #define ATTRIB_BIT_DWORDS ((VERT_ATTRIB_MAX+31)/32)
465 struct brw_vertex_buffer
{
466 /** Buffer object containing the uploaded vertex data */
469 /** Byte stride between elements in the uploaded array */
472 struct brw_vertex_element
{
473 const struct gl_client_array
*glarray
;
477 /** The corresponding Mesa vertex attribute */
478 gl_vert_attrib attrib
;
479 /** Size of a complete element */
481 /** Offset of the first element within the buffer object */
487 struct brw_vertex_info
{
488 GLuint sizes
[ATTRIB_BIT_DWORDS
* 2]; /* sizes:2[VERT_ATTRIB_MAX] */
491 struct brw_query_object
{
492 struct gl_query_object Base
;
494 /** Last query BO associated with this query. */
496 /** First index in bo with query data for this object. */
498 /** Last index in bo with query data for this object. */
504 * brw_context is derived from intel_context.
508 struct intel_context intel
; /**< base class, must be first field */
511 GLboolean emit_state_always
;
512 GLboolean has_surface_tile_offset
;
513 GLboolean has_compr4
;
514 GLboolean has_negative_rhw_bug
;
515 GLboolean has_aa_line_parameters
;
519 struct brw_state_flags dirty
;
521 * List of buffers accumulated in brw_validate_state to receive
522 * drm_intel_bo_check_aperture treatment before exec, so we can
523 * know if we should flush the batch and try again before
524 * emitting primitives.
526 * This can be a fixed number as we only have a limited number of
527 * objects referenced from the batchbuffer in a primitive emit,
528 * consisting of the vertex buffers, pipelined state pointers,
529 * the CURBE, the depth buffer, and a query BO.
531 drm_intel_bo
*validated_bos
[VERT_ATTRIB_MAX
+ BRW_WM_MAX_SURF
+ 16];
532 unsigned int validated_bo_count
;
535 struct brw_cache cache
;
536 struct brw_cached_batch_item
*cached_batch_items
;
539 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
540 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
545 } current_buffers
[VERT_ATTRIB_MAX
];
547 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
549 GLuint nr_buffers
, nr_current_buffers
;
551 /* Summary of size and varying of active arrays, so we can check
552 * for changes to this state:
554 struct brw_vertex_info info
;
555 unsigned int min_index
, max_index
;
557 /* Offset from start of vertex buffer so we can avoid redefining
558 * the same VB packed over and over again.
560 unsigned int start_vertex_bias
;
565 * Index buffer for this draw_prims call.
567 * Updates are signaled by BRW_NEW_INDICES.
569 const struct _mesa_index_buffer
*ib
;
571 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
575 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
576 * avoid re-uploading the IB packet over and over if we're actually
577 * referencing the same index buffer.
579 unsigned int start_vertex_offset
;
582 /* Active vertex program:
584 const struct gl_vertex_program
*vertex_program
;
585 const struct gl_fragment_program
*fragment_program
;
587 /* hw-dependent 3DSTATE_VF_STATISTICS opcode */
588 uint32_t CMD_VF_STATISTICS
;
589 /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
590 uint32_t CMD_PIPELINE_SELECT
;
594 /* BRW_NEW_URB_ALLOCATIONS:
597 GLuint vsize
; /* vertex size plus header in urb registers */
598 GLuint csize
; /* constant buffer size in urb registers */
599 GLuint sfsize
; /* setup data size in urb registers */
601 GLboolean constrained
;
603 GLuint max_vs_entries
; /* Maximum number of VS entries */
604 GLuint max_gs_entries
; /* Maximum number of GS entries */
606 GLuint nr_vs_entries
;
607 GLuint nr_gs_entries
;
608 GLuint nr_clip_entries
;
609 GLuint nr_sf_entries
;
610 GLuint nr_cs_entries
;
613 * The length of each URB entry owned by the VS (or GS), as
614 * a number of 1024-bit (128-byte) rows. Should be >= 1.
616 * gen7: Same meaning, but in 512-bit (64-byte) rows.
626 GLuint size
; /* Hardware URB size, in KB. */
630 /* BRW_NEW_CURBE_OFFSETS:
633 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
634 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
641 drm_intel_bo
*curbe_bo
;
642 /** Offset within curbe_bo of space for current curbe entry */
644 /** Offset within curbe_bo of space for next curbe entry */
645 GLuint curbe_next_offset
;
648 * Copy of the last set of CURBEs uploaded. Frequently we'll end up
649 * in brw_curbe.c with the same set of constant data to be uploaded,
650 * so we'd rather not upload new constants in that case (it can cause
651 * a pipeline bubble since only up to 4 can be pipelined at a time).
655 * Allocation for where to calculate the next set of CURBEs.
656 * It's a hot enough path that malloc/free of that data matters.
663 struct brw_vs_prog_data
*prog_data
;
664 int8_t *constant_map
; /* variable array following prog_data */
666 drm_intel_bo
*const_bo
;
667 /** Offset in the program cache to the VS program */
668 uint32_t prog_offset
;
669 uint32_t state_offset
;
671 /** Binding table of pointers to surf_bo entries */
672 uint32_t bind_bo_offset
;
673 uint32_t surf_offset
[BRW_VS_MAX_SURF
];
676 uint32_t push_const_offset
; /* Offset in the batchbuffer */
677 int push_const_size
; /* in 256-bit register increments */
681 struct brw_gs_prog_data
*prog_data
;
683 GLboolean prog_active
;
684 /** Offset in the program cache to the CLIP program pre-gen6 */
685 uint32_t prog_offset
;
686 uint32_t state_offset
;
690 struct brw_clip_prog_data
*prog_data
;
692 /** Offset in the program cache to the CLIP program pre-gen6 */
693 uint32_t prog_offset
;
695 /* Offset in the batch to the CLIP state on pre-gen6. */
696 uint32_t state_offset
;
698 /* As of gen6, this is the offset in the batch to the CLIP VP,
706 struct brw_sf_prog_data
*prog_data
;
708 /** Offset in the program cache to the CLIP program pre-gen6 */
709 uint32_t prog_offset
;
710 uint32_t state_offset
;
715 struct brw_wm_prog_data
*prog_data
;
716 struct brw_wm_compile
*compile_data
;
718 /** Input sizes, calculated from active vertex program.
719 * One bit per fragment program input attribute.
721 GLbitfield input_size_masks
[4];
723 /** offsets in the batch to sampler default colors (texture border color)
725 uint32_t sdc_offset
[BRW_MAX_TEX_UNIT
];
731 drm_intel_bo
*scratch_bo
;
733 GLuint sampler_count
;
734 uint32_t sampler_offset
;
736 /** Offset in the program cache to the WM program */
737 uint32_t prog_offset
;
739 /** Binding table of pointers to surf_bo entries */
740 uint32_t bind_bo_offset
;
741 uint32_t surf_offset
[BRW_WM_MAX_SURF
];
742 uint32_t state_offset
; /* offset in batchbuffer to pre-gen6 WM state */
744 drm_intel_bo
*const_bo
; /* pull constant buffer. */
746 * This is offset in the batch to the push constants on gen6.
748 * Pre-gen6, push constants live in the CURBE.
750 uint32_t push_const_offset
;
752 /** @{ register allocator */
754 struct ra_regs
*regs
;
756 /** Array of the ra classes for the unaligned contiguous
757 * register block sizes used.
762 * Mapping for register-allocated objects in *regs to the first
763 * GRF for that object.
765 uint8_t *ra_reg_to_grf
;
768 * ra class for the aligned pairs we use for PLN, which doesn't
769 * appear in *classes.
771 int aligned_pairs_class
;
778 uint32_t state_offset
;
779 uint32_t blend_state_offset
;
780 uint32_t depth_stencil_state_offset
;
785 struct brw_query_object
*obj
;
790 /* Used to give every program string a unique id
794 int num_prepare_atoms
, num_emit_atoms
;
795 struct brw_tracked_state prepare_atoms
[64], emit_atoms
[64];
797 /* If (INTEL_DEBUG & DEBUG_BATCH) */
801 enum state_struct_type type
;
803 int state_batch_count
;
807 #define BRW_PACKCOLOR8888(r,g,b,a) ((r<<24) | (g<<16) | (b<<8) | a)
809 struct brw_instruction_info
{
815 extern const struct brw_instruction_info brw_opcodes
[128];
817 /*======================================================================
820 void brwInitVtbl( struct brw_context
*brw
);
822 /*======================================================================
825 GLboolean
brwCreateContext( int api
,
826 const struct gl_config
*mesaVis
,
827 __DRIcontext
*driContextPriv
,
828 void *sharedContextPrivate
);
830 /*======================================================================
833 void brw_init_queryobj_functions(struct dd_function_table
*functions
);
834 void brw_prepare_query_begin(struct brw_context
*brw
);
835 void brw_emit_query_begin(struct brw_context
*brw
);
836 void brw_emit_query_end(struct brw_context
*brw
);
838 /*======================================================================
841 void brw_debug_batch(struct intel_context
*intel
);
843 /*======================================================================
846 void brw_validate_textures( struct brw_context
*brw
);
849 /*======================================================================
852 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
857 void brw_upload_urb_fence(struct brw_context
*brw
);
861 void brw_upload_cs_urb_state(struct brw_context
*brw
);
864 int brw_disasm (FILE *file
, struct brw_instruction
*inst
, int gen
);
866 /*======================================================================
867 * Inline conversion functions. These are better-typed than the
868 * macros used previously:
870 static INLINE
struct brw_context
*
871 brw_context( struct gl_context
*ctx
)
873 return (struct brw_context
*)ctx
;
876 static INLINE
struct brw_vertex_program
*
877 brw_vertex_program(struct gl_vertex_program
*p
)
879 return (struct brw_vertex_program
*) p
;
882 static INLINE
const struct brw_vertex_program
*
883 brw_vertex_program_const(const struct gl_vertex_program
*p
)
885 return (const struct brw_vertex_program
*) p
;
888 static INLINE
struct brw_fragment_program
*
889 brw_fragment_program(struct gl_fragment_program
*p
)
891 return (struct brw_fragment_program
*) p
;
894 static INLINE
const struct brw_fragment_program
*
895 brw_fragment_program_const(const struct gl_fragment_program
*p
)
897 return (const struct brw_fragment_program
*) p
;
901 float convert_param(enum param_conversion conversion
, float param
)
909 switch (conversion
) {
910 case PARAM_NO_CONVERT
:
912 case PARAM_CONVERT_F2I
:
915 case PARAM_CONVERT_F2U
:
918 case PARAM_CONVERT_F2B
:
930 * Pre-gen6, the register file of the EUs was shared between threads,
931 * and each thread used some subset allocated on a 16-register block
932 * granularity. The unit states wanted these block counts.
935 brw_register_blocks(int reg_count
)
937 return ALIGN(reg_count
, 16) / 16 - 1;
940 static inline uint32_t
941 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
942 uint32_t prog_offset
)
944 struct intel_context
*intel
= &brw
->intel
;
946 if (intel
->gen
>= 5) {
947 /* Using state base address. */
951 drm_intel_bo_emit_reloc(intel
->batch
.bo
,
955 I915_GEM_DOMAIN_INSTRUCTION
, 0);
957 return brw
->cache
.bo
->offset
+ prog_offset
;
960 GLboolean
brw_do_cubemap_normalize(struct exec_list
*instructions
);