2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
38 #include "main/imports.h"
39 #include "main/macros.h"
41 #include "main/mtypes.h"
42 #include "brw_structs.h"
43 #include "intel_aub.h"
44 #include "program/prog_parameter.h"
48 /* Evil hack for using libdrm in a c++ compiler. */
53 #include <intel_bufmgr.h>
63 #include "intel_debug.h"
64 #include "intel_screen.h"
65 #include "intel_tex_obj.h"
66 #include "intel_resolve_map.h"
70 * URB - uniform resource buffer. A mid-sized buffer which is
71 * partitioned between the fixed function units and used for passing
72 * values (vertices, primitives, constants) between them.
74 * CURBE - constant URB entry. An urb region (entry) used to hold
75 * constant values which the fixed function units can be instructed to
76 * preload into the GRF when spawning a thread.
78 * VUE - vertex URB entry. An urb entry holding a vertex and usually
79 * a vertex header. The header contains control information and
80 * things like primitive type, Begin/end flags and clip codes.
82 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
83 * unit holding rasterization and interpolation parameters.
85 * GRF - general register file. One of several register files
86 * addressable by programmed threads. The inputs (r0, payload, curbe,
87 * urb) of the thread are preloaded to this area before the thread is
88 * spawned. The registers are individually 8 dwords wide and suitable
89 * for general usage. Registers holding thread input values are not
90 * special and may be overwritten.
92 * MRF - message register file. Threads communicate (and terminate)
93 * by sending messages. Message parameters are placed in contiguous
94 * MRF registers. All program output is via these messages. URB
95 * entries are populated by sending a message to the shared URB
96 * function containing the new data, together with a control word,
97 * often an unmodified copy of R0.
99 * R0 - GRF register 0. Typically holds control information used when
100 * sending messages to other threads.
102 * EU or GEN4 EU: The name of the programmable subsystem of the
103 * i965 hardware. Threads are executed by the EU, the registers
104 * described above are part of the EU architecture.
106 * Fixed function units:
108 * CS - Command streamer. Notional first unit, little software
109 * interaction. Holds the URB entries used for constant data, ie the
112 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
113 * this unit is responsible for pulling vertices out of vertex buffers
114 * in vram and injecting them into the processing pipe as VUEs. If
115 * enabled, it first passes them to a VS thread which is a good place
116 * for the driver to implement any active vertex shader.
118 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
119 * enabled, incoming strips etc are passed to GS threads in individual
120 * line/triangle/point units. The GS thread may perform arbitary
121 * computation and emit whatever primtives with whatever vertices it
122 * chooses. This makes GS an excellent place to implement GL's
123 * unfilled polygon modes, though of course it is capable of much
124 * more. Additionally, GS is used to translate away primitives not
125 * handled by latter units, including Quads and Lineloops.
127 * CS - Clipper. Mesa's clipping algorithms are imported to run on
128 * this unit. The fixed function part performs cliptesting against
129 * the 6 fixed clipplanes and makes descisions on whether or not the
130 * incoming primitive needs to be passed to a thread for clipping.
131 * User clip planes are handled via cooperation with the VS thread.
133 * SF - Strips Fans or Setup: Triangles are prepared for
134 * rasterization. Interpolation coefficients are calculated.
135 * Flatshading and two-side lighting usually performed here.
137 * WM - Windower. Interpolation of vertex attributes performed here.
138 * Fragment shader implemented here. SIMD aspects of EU taken full
139 * advantage of, as pixels are processed in blocks of 16.
141 * CC - Color Calculator. No EU threads associated with this unit.
142 * Handles blending and (presumably) depth and stencil testing.
147 struct brw_vs_prog_key
;
148 struct brw_vue_prog_key
;
149 struct brw_wm_prog_key
;
150 struct brw_wm_prog_data
;
151 struct brw_cs_prog_key
;
152 struct brw_cs_prog_data
;
156 BRW_COMPUTE_PIPELINE
,
163 BRW_CACHE_BLORP_BLIT_PROG
,
166 BRW_CACHE_FF_GS_PROG
,
175 /* brw_cache_ids must come first - see brw_state_cache.c */
176 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
177 BRW_STATE_FRAGMENT_PROGRAM
,
178 BRW_STATE_GEOMETRY_PROGRAM
,
179 BRW_STATE_VERTEX_PROGRAM
,
180 BRW_STATE_CURBE_OFFSETS
,
181 BRW_STATE_REDUCED_PRIMITIVE
,
186 BRW_STATE_VS_BINDING_TABLE
,
187 BRW_STATE_GS_BINDING_TABLE
,
188 BRW_STATE_PS_BINDING_TABLE
,
192 BRW_STATE_INDEX_BUFFER
,
193 BRW_STATE_VS_CONSTBUF
,
194 BRW_STATE_GS_CONSTBUF
,
195 BRW_STATE_PROGRAM_CACHE
,
196 BRW_STATE_STATE_BASE_ADDRESS
,
197 BRW_STATE_VUE_MAP_VS
,
198 BRW_STATE_VUE_MAP_GEOM_OUT
,
199 BRW_STATE_TRANSFORM_FEEDBACK
,
200 BRW_STATE_RASTERIZER_DISCARD
,
202 BRW_STATE_UNIFORM_BUFFER
,
203 BRW_STATE_ATOMIC_BUFFER
,
204 BRW_STATE_META_IN_PROGRESS
,
205 BRW_STATE_INTERPOLATION_MAP
,
206 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
207 BRW_STATE_NUM_SAMPLES
,
208 BRW_STATE_TEXTURE_BUFFER
,
209 BRW_STATE_GEN4_UNIT_STATE
,
213 BRW_STATE_SAMPLER_STATE_TABLE
,
214 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
215 BRW_STATE_COMPUTE_PROGRAM
,
220 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
222 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
223 * When the currently bound shader program differs from the previous draw
224 * call, these will be flagged. They cover brw->{stage}_program and
225 * ctx->{Stage}Program->_Current.
227 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
228 * driver perspective. Even if the same shader is bound at the API level,
229 * we may need to switch between multiple versions of that shader to handle
230 * changes in non-orthagonal state.
232 * Additionally, multiple shader programs may have identical vertex shaders
233 * (for example), or compile down to the same code in the backend. We combine
234 * those into a single program cache entry.
236 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
237 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
239 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
240 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
241 * use the normal state upload paths), but the cache is still used. To avoid
242 * polluting the brw_state_cache code with special cases, we retain the dirty
243 * bit for now. It should eventually be removed.
245 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_BLIT_PROG)
246 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
247 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
248 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
249 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
250 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
251 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
252 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
253 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
254 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
255 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
256 #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
257 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
258 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
259 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
260 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
261 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
262 #define BRW_NEW_VS_BINDING_TABLE (1ull << BRW_STATE_VS_BINDING_TABLE)
263 #define BRW_NEW_GS_BINDING_TABLE (1ull << BRW_STATE_GS_BINDING_TABLE)
264 #define BRW_NEW_PS_BINDING_TABLE (1ull << BRW_STATE_PS_BINDING_TABLE)
265 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
266 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
268 * Used for any batch entry with a relocated pointer that will be used
269 * by any 3D rendering.
271 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
272 /** \see brw.state.depth_region */
273 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
274 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
275 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
276 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
277 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
278 #define BRW_NEW_VUE_MAP_VS (1ull << BRW_STATE_VUE_MAP_VS)
279 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
280 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
281 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
282 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
283 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
284 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
285 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
286 #define BRW_NEW_INTERPOLATION_MAP (1ull << BRW_STATE_INTERPOLATION_MAP)
287 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
288 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
289 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
290 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
291 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
292 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
293 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
294 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
295 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
296 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
298 struct brw_state_flags
{
299 /** State update flags signalled by mesa internals */
302 * State update flags signalled as the result of brw_tracked_state updates
307 /** Subclass of Mesa vertex program */
308 struct brw_vertex_program
{
309 struct gl_vertex_program program
;
314 /** Subclass of Mesa geometry program */
315 struct brw_geometry_program
{
316 struct gl_geometry_program program
;
317 unsigned id
; /**< serial no. to identify geom progs, never re-used */
321 /** Subclass of Mesa fragment program */
322 struct brw_fragment_program
{
323 struct gl_fragment_program program
;
324 GLuint id
; /**< serial no. to identify frag progs, never re-used */
328 /** Subclass of Mesa compute program */
329 struct brw_compute_program
{
330 struct gl_compute_program program
;
331 unsigned id
; /**< serial no. to identify compute progs, never re-used */
336 struct gl_shader base
;
341 /* Note: If adding fields that need anything besides a normal memcmp() for
342 * comparing them, be sure to go fix brw_stage_prog_data_compare().
344 struct brw_stage_prog_data
{
346 /** size of our binding table. */
350 * surface indices for the various groups of surfaces
352 uint32_t pull_constants_start
;
353 uint32_t texture_start
;
354 uint32_t gather_texture_start
;
357 uint32_t image_start
;
358 uint32_t shader_time_start
;
362 GLuint nr_params
; /**< number of float params/constants */
363 GLuint nr_pull_params
;
365 unsigned curb_read_length
;
366 unsigned total_scratch
;
369 * Register where the thread expects to find input data from the URB
370 * (typically uniforms, followed by vertex or fragment attributes).
372 unsigned dispatch_grf_start_reg
;
374 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
376 /* Pointers to tracked values (only valid once
377 * _mesa_load_state_parameters has been called at runtime).
379 * These must be the last fields of the struct (see
380 * brw_stage_prog_data_compare()).
382 const gl_constant_value
**param
;
383 const gl_constant_value
**pull_param
;
386 /* Data about a particular attempt to compile a program. Note that
387 * there can be many of these, each in a different GL state
388 * corresponding to a different brw_wm_prog_key struct, with different
391 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
394 struct brw_wm_prog_data
{
395 struct brw_stage_prog_data base
;
397 GLuint num_varying_inputs
;
399 GLuint dispatch_grf_start_reg_16
;
401 GLuint reg_blocks_16
;
405 * surface indices the WM-specific surfaces
407 uint32_t render_target_start
;
411 uint8_t computed_depth_mode
;
415 bool uses_pos_offset
;
419 uint32_t prog_offset_16
;
422 * Mask of which interpolation modes are required by the fragment shader.
423 * Used in hardware setup on gen6+.
425 uint32_t barycentric_interp_modes
;
428 * Map from gl_varying_slot to the position within the FS setup data
429 * payload where the varying's attribute vertex deltas should be delivered.
430 * For varying slots that are not used by the FS, the value is -1.
432 int urb_setup
[VARYING_SLOT_MAX
];
435 /* Note: brw_cs_prog_data_compare() must be updated when adding fields to this
438 struct brw_cs_prog_data
{
439 struct brw_stage_prog_data base
;
441 GLuint dispatch_grf_start_reg_16
;
442 unsigned local_size
[3];
447 * Enum representing the i965-specific vertex results that don't correspond
448 * exactly to any element of gl_varying_slot. The values of this enum are
449 * assigned such that they don't conflict with gl_varying_slot.
453 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
454 BRW_VARYING_SLOT_PAD
,
456 * Technically this is not a varying but just a placeholder that
457 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
458 * builtin variable to be compiled correctly. see compile_sf_prog() for
461 BRW_VARYING_SLOT_PNTC
,
462 BRW_VARYING_SLOT_COUNT
467 * Data structure recording the relationship between the gl_varying_slot enum
468 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
469 * single octaword within the VUE (128 bits).
471 * Note that each BRW register contains 256 bits (2 octawords), so when
472 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
473 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
474 * in a vertex shader), each register corresponds to a single VUE slot, since
475 * it contains data for two separate vertices.
479 * Bitfield representing all varying slots that are (a) stored in this VUE
480 * map, and (b) actually written by the shader. Does not include any of
481 * the additional varying slots defined in brw_varying_slot.
483 GLbitfield64 slots_valid
;
486 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
487 * not stored in a slot (because they are not written, or because
488 * additional processing is applied before storing them in the VUE), the
491 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
494 * Map from VUE slot to gl_varying_slot value. For slots that do not
495 * directly correspond to a gl_varying_slot, the value comes from
498 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
499 * simplifies code that uses the value stored in slot_to_varying to
500 * create a bit mask).
502 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
505 * Total number of VUE slots in use
511 * Convert a VUE slot number into a byte offset within the VUE.
513 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
519 * Convert a vertex output (brw_varying_slot) into a byte offset within the
522 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
525 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
528 void brw_compute_vue_map(const struct brw_device_info
*devinfo
,
529 struct brw_vue_map
*vue_map
,
530 GLbitfield64 slots_valid
);
534 * Bitmask indicating which fragment shader inputs represent varyings (and
535 * hence have to be delivered to the fragment shader by the SF/SBE stage).
537 #define BRW_FS_VARYING_INPUT_MASK \
538 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
539 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
543 * Mapping of VUE map slots to interpolation modes.
545 struct interpolation_mode_map
{
546 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
549 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
551 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
552 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
558 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
560 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
561 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
568 struct brw_sf_prog_data
{
569 GLuint urb_read_length
;
572 /* Each vertex may have upto 12 attributes, 4 components each,
573 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
576 * Actually we use 4 for each, so call it 12 rows.
578 GLuint urb_entry_size
;
583 * We always program SF to start reading at an offset of 1 (2 varying slots)
584 * from the start of the vertex URB entry. This causes it to skip:
585 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
586 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
588 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
591 struct brw_clip_prog_data
{
592 GLuint curb_read_length
; /* user planes? */
594 GLuint urb_read_length
;
598 struct brw_ff_gs_prog_data
{
599 GLuint urb_read_length
;
603 * Gen6 transform feedback: Amount by which the streaming vertex buffer
604 * indices should be incremented each time the GS is invoked.
606 unsigned svbi_postincrement_value
;
609 enum shader_dispatch_mode
{
610 DISPATCH_MODE_4X1_SINGLE
= 0,
611 DISPATCH_MODE_4X2_DUAL_INSTANCE
= 1,
612 DISPATCH_MODE_4X2_DUAL_OBJECT
= 2,
613 DISPATCH_MODE_SIMD8
= 3,
616 /* Note: brw_vue_prog_data_compare() must be updated when adding fields to
619 struct brw_vue_prog_data
{
620 struct brw_stage_prog_data base
;
621 struct brw_vue_map vue_map
;
623 GLuint urb_read_length
;
626 /* Used for calculating urb partitions. In the VS, this is the size of the
627 * URB entry used for both input and output to the thread. In the GS, this
628 * is the size of the URB entry used for output.
630 GLuint urb_entry_size
;
632 enum shader_dispatch_mode dispatch_mode
;
636 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
639 struct brw_vs_prog_data
{
640 struct brw_vue_prog_data base
;
642 GLbitfield64 inputs_read
;
645 bool uses_instanceid
;
648 /** Number of texture sampler units */
649 #define BRW_MAX_TEX_UNIT 32
651 /** Max number of render targets in a shader */
652 #define BRW_MAX_DRAW_BUFFERS 8
654 /** Max number of atomic counter buffer objects in a shader */
655 #define BRW_MAX_ABO 16
657 /** Max number of image uniforms in a shader */
658 #define BRW_MAX_IMAGES 32
661 * Max number of binding table entries used for stream output.
663 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
664 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
666 * On Gen6, the size of transform feedback data is limited not by the number
667 * of components but by the number of binding table entries we set aside. We
668 * use one binding table entry for a float, one entry for a vector, and one
669 * entry per matrix column. Since the only way we can communicate our
670 * transform feedback capabilities to the client is via
671 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
672 * worst case, in which all the varyings are floats, so we use up one binding
673 * table entry per component. Therefore we need to set aside at least 64
674 * binding table entries for use by transform feedback.
676 * Note: since we don't currently pack varyings, it is currently impossible
677 * for the client to actually use up all of these binding table entries--if
678 * all of their varyings were floats, they would run out of varying slots and
679 * fail to link. But that's a bug, so it seems prudent to go ahead and
680 * allocate the number of binding table entries we will need once the bug is
683 #define BRW_MAX_SOL_BINDINGS 64
685 /** Maximum number of actual buffers used for stream output */
686 #define BRW_MAX_SOL_BUFFERS 4
688 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
689 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
693 2 /* shader time, pull constants */)
695 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
697 /* Note: brw_gs_prog_data_compare() must be updated when adding fields to
700 struct brw_gs_prog_data
702 struct brw_vue_prog_data base
;
705 * Size of an output vertex, measured in HWORDS (32 bytes).
707 unsigned output_vertex_size_hwords
;
709 unsigned output_topology
;
712 * Size of the control data (cut bits or StreamID bits), in hwords (32
713 * bytes). 0 if there is no control data.
715 unsigned control_data_header_size_hwords
;
718 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
719 * if the control data is StreamID bits, or
720 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
721 * Ignored if control_data_header_size is 0.
723 unsigned control_data_format
;
725 bool include_primitive_id
;
730 * Gen6 transform feedback enabled flag.
732 bool gen6_xfb_enabled
;
735 * Gen6: Provoking vertex convention for odd-numbered triangles
741 * Gen6: Number of varyings that are output to transform feedback.
743 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
746 * Gen6: Map from the index of a transform feedback binding table entry to the
747 * gl_varying_slot that should be streamed out through that binding table
750 unsigned char transform_feedback_bindings
[BRW_MAX_SOL_BINDINGS
];
753 * Gen6: Map from the index of a transform feedback binding table entry to the
754 * swizzles that should be used when streaming out data through that
755 * binding table entry.
757 unsigned char transform_feedback_swizzles
[BRW_MAX_SOL_BINDINGS
];
761 * Stride in bytes between shader_time entries.
763 * We separate entries by a cacheline to reduce traffic between EUs writing to
766 #define SHADER_TIME_STRIDE 64
768 struct brw_cache_item
{
770 * Effectively part of the key, cache_id identifies what kind of state
771 * buffer is involved, and also which dirty flag should set.
773 enum brw_cache_id cache_id
;
774 /** 32-bit hash of the key data */
776 GLuint key_size
; /* for variable-sized keys */
783 struct brw_cache_item
*next
;
787 typedef bool (*cache_aux_compare_func
)(const void *a
, const void *b
);
788 typedef void (*cache_aux_free_func
)(const void *aux
);
791 struct brw_context
*brw
;
793 struct brw_cache_item
**items
;
795 GLuint size
, n_items
;
797 uint32_t next_offset
;
801 * Optional functions used in determining whether the prog_data for a new
802 * cache item matches an existing cache item (in case there's relevant data
803 * outside of the prog_data). If NULL, a plain memcmp is done.
805 cache_aux_compare_func aux_compare
[BRW_MAX_CACHE
];
806 /** Optional functions for freeing other pointers attached to a prog_data. */
807 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
811 /* Considered adding a member to this struct to document which flags
812 * an update might raise so that ordering of the state atoms can be
813 * checked or derived at runtime. Dropped the idea in favor of having
814 * a debug mode where the state is monitored for flags which are
815 * raised that have already been tested against.
817 struct brw_tracked_state
{
818 struct brw_state_flags dirty
;
819 void (*emit
)( struct brw_context
*brw
);
822 enum shader_time_shader_type
{
831 struct brw_vertex_buffer
{
832 /** Buffer object containing the uploaded vertex data */
835 /** Byte stride between elements in the uploaded array */
839 struct brw_vertex_element
{
840 const struct gl_client_array
*glarray
;
844 /** Offset of the first element within the buffer object */
848 struct brw_query_object
{
849 struct gl_query_object Base
;
851 /** Last query BO associated with this query. */
854 /** Last index in bo with query data for this object. */
857 /** True if we know the batch has been flushed since we ended the query. */
867 struct intel_batchbuffer
{
868 /** Current batchbuffer being queued up. */
870 /** Last BO submitted to the hardware. Used for glFinish(). */
871 drm_intel_bo
*last_bo
;
874 uint16_t emit
, total
;
876 uint16_t reserved_space
;
880 #define BATCH_SZ (8192*sizeof(uint32_t))
882 uint32_t state_batch_offset
;
883 enum brw_gpu_ring ring
;
884 bool needs_sol_reset
;
892 #define BRW_MAX_XFB_STREAMS 4
894 struct brw_transform_feedback_object
{
895 struct gl_transform_feedback_object base
;
897 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
898 drm_intel_bo
*offset_bo
;
900 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
903 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
904 GLenum primitive_mode
;
907 * Count of primitives generated during this transform feedback operation.
910 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
911 drm_intel_bo
*prim_count_bo
;
912 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
916 * Number of vertices written between last Begin/EndTransformFeedback().
918 * Used to implement DrawTransformFeedback().
920 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
921 bool vertices_written_valid
;
925 * Data shared between each programmable stage in the pipeline (vs, gs, and
928 struct brw_stage_state
930 gl_shader_stage stage
;
931 struct brw_stage_prog_data
*prog_data
;
934 * Optional scratch buffer used to store spilled register values and
935 * variably-indexed GRF arrays.
937 drm_intel_bo
*scratch_bo
;
939 /** Offset in the program cache to the program */
940 uint32_t prog_offset
;
942 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
943 uint32_t state_offset
;
945 uint32_t push_const_offset
; /* Offset in the batchbuffer */
946 int push_const_size
; /* in 256-bit register increments */
948 /* Binding table: pointers to SURFACE_STATE entries. */
949 uint32_t bind_bo_offset
;
950 uint32_t surf_offset
[BRW_MAX_SURFACES
];
952 /** SAMPLER_STATE count and table offset */
953 uint32_t sampler_count
;
954 uint32_t sampler_offset
;
957 enum brw_predicate_state
{
958 /* The first two states are used if we can determine whether to draw
959 * without having to look at the values in the query object buffer. This
960 * will happen if there is no conditional render in progress, if the query
961 * object is already completed or if something else has already added
962 * samples to the preliminary result such as via a BLT command.
964 BRW_PREDICATE_STATE_RENDER
,
965 BRW_PREDICATE_STATE_DONT_RENDER
,
966 /* In this case whether to draw or not depends on the result of an
967 * MI_PREDICATE command so the predicate enable bit needs to be checked.
969 BRW_PREDICATE_STATE_USE_BIT
975 * brw_context is derived from gl_context.
979 struct gl_context ctx
; /**< base class, must be first field */
983 void (*update_texture_surface
)(struct gl_context
*ctx
,
985 uint32_t *surf_offset
,
987 uint32_t (*update_renderbuffer_surface
)(struct brw_context
*brw
,
988 struct gl_renderbuffer
*rb
,
989 bool layered
, unsigned unit
,
990 uint32_t surf_index
);
992 void (*emit_texture_surface_state
)(struct brw_context
*brw
,
993 struct intel_mipmap_tree
*mt
,
1001 uint32_t *surf_offset
,
1002 bool rw
, bool for_gather
);
1003 void (*emit_buffer_surface_state
)(struct brw_context
*brw
,
1004 uint32_t *out_offset
,
1006 unsigned buffer_offset
,
1007 unsigned surface_format
,
1008 unsigned buffer_size
,
1011 void (*emit_null_surface_state
)(struct brw_context
*brw
,
1015 uint32_t *out_offset
);
1018 * Send the appropriate state packets to configure depth, stencil, and
1019 * HiZ buffers (i965+ only)
1021 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
1022 struct intel_mipmap_tree
*depth_mt
,
1023 uint32_t depth_offset
,
1024 uint32_t depthbuffer_format
,
1025 uint32_t depth_surface_type
,
1026 struct intel_mipmap_tree
*stencil_mt
,
1027 bool hiz
, bool separate_stencil
,
1028 uint32_t width
, uint32_t height
,
1029 uint32_t tile_x
, uint32_t tile_y
);
1035 drm_intel_context
*hw_ctx
;
1037 /** BO for post-sync nonzero writes for gen6 workaround. */
1038 drm_intel_bo
*workaround_bo
;
1039 uint8_t pipe_controls_since_last_cs_stall
;
1042 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
1043 * and would need flushing before being used from another cache domain that
1044 * isn't coherent with it (i.e. the sampler).
1046 struct set
*render_cache
;
1049 * Number of resets observed in the system at context creation.
1051 * This is tracked in the context so that we can determine that another
1052 * reset has occurred.
1054 uint32_t reset_count
;
1056 struct intel_batchbuffer batch
;
1061 uint32_t next_offset
;
1065 * Set if rendering has occurred to the drawable's front buffer.
1067 * This is used in the DRI2 case to detect that glFlush should also copy
1068 * the contents of the fake front buffer to the real front buffer.
1070 bool front_buffer_dirty
;
1072 /** Framerate throttling: @{ */
1073 drm_intel_bo
*throttle_batch
[2];
1075 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
1076 * frame of rendering to complete. This gives a very precise cap to the
1077 * latency between input and output such that rendering never gets more
1078 * than a frame behind the user. (With the caveat that we technically are
1079 * not using the SwapBuffers itself as a barrier but the first batch
1080 * submitted afterwards, which may be immediately prior to the next
1083 bool need_swap_throttle
;
1085 /** General throttling, not caught by throttling between SwapBuffers */
1086 bool need_flush_throttle
;
1096 bool always_flush_batch
;
1097 bool always_flush_cache
;
1098 bool disable_throttling
;
1101 driOptionCache optionCache
;
1104 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
1106 GLenum reduced_primitive
;
1109 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
1110 * variable is set, this is the flag indicating to do expensive work that
1111 * might lead to a perf_debug() call.
1115 uint32_t max_gtt_map_object_size
;
1127 bool has_separate_stencil
;
1128 bool must_use_separate_stencil
;
1131 bool has_surface_tile_offset
;
1133 bool has_negative_rhw_bug
;
1137 bool use_resource_streamer
;
1140 * Some versions of Gen hardware don't do centroid interpolation correctly
1141 * on unlit pixels, causing incorrect values for derivatives near triangle
1142 * edges. Enabling this flag causes the fragment shader to use
1143 * non-centroid interpolation for unlit pixels, at the expense of two extra
1144 * fragment shader instructions.
1146 bool needs_unlit_centroid_workaround
;
1150 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
1153 enum brw_pipeline last_pipeline
;
1155 struct brw_cache cache
;
1157 /** IDs for meta stencil blit shader programs. */
1158 unsigned meta_stencil_blit_programs
[2];
1160 /* Whether a meta-operation is in progress. */
1161 bool meta_in_progress
;
1163 /* Whether the last depth/stencil packets were both NULL. */
1164 bool no_depth_or_stencil
;
1166 /* The last PMA stall bits programmed. */
1167 uint32_t pma_stall_bits
;
1170 /** The value of gl_BaseVertex for the current _mesa_prim. */
1174 * Buffer and offset used for GL_ARB_shader_draw_parameters
1175 * (for now, only gl_BaseVertex).
1177 drm_intel_bo
*draw_params_bo
;
1178 uint32_t draw_params_offset
;
1182 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
1183 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
1185 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
1189 /* Summary of size and varying of active arrays, so we can check
1190 * for changes to this state:
1192 unsigned int min_index
, max_index
;
1194 /* Offset from start of vertex buffer so we can avoid redefining
1195 * the same VB packed over and over again.
1197 unsigned int start_vertex_bias
;
1200 * Certain vertex attribute formats aren't natively handled by the
1201 * hardware and require special VS code to fix up their values.
1203 * These bitfields indicate which workarounds are needed.
1205 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
1210 * Index buffer for this draw_prims call.
1212 * Updates are signaled by BRW_NEW_INDICES.
1214 const struct _mesa_index_buffer
*ib
;
1216 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
1220 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
1221 * avoid re-uploading the IB packet over and over if we're actually
1222 * referencing the same index buffer.
1224 unsigned int start_vertex_offset
;
1227 /* Active vertex program:
1229 const struct gl_vertex_program
*vertex_program
;
1230 const struct gl_geometry_program
*geometry_program
;
1231 const struct gl_fragment_program
*fragment_program
;
1232 const struct gl_compute_program
*compute_program
;
1235 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
1236 * that we don't have to reemit that state every time we change FBOs.
1241 * Platform specific constants containing the maximum number of threads
1242 * for each pipeline stage.
1251 /* BRW_NEW_URB_ALLOCATIONS:
1254 GLuint vsize
; /* vertex size plus header in urb registers */
1255 GLuint gsize
; /* GS output size in urb registers */
1256 GLuint csize
; /* constant buffer size in urb registers */
1257 GLuint sfsize
; /* setup data size in urb registers */
1261 GLuint min_vs_entries
; /* Minimum number of VS entries */
1262 GLuint max_vs_entries
; /* Maximum number of VS entries */
1263 GLuint max_hs_entries
; /* Maximum number of HS entries */
1264 GLuint max_ds_entries
; /* Maximum number of DS entries */
1265 GLuint max_gs_entries
; /* Maximum number of GS entries */
1267 GLuint nr_vs_entries
;
1268 GLuint nr_gs_entries
;
1269 GLuint nr_clip_entries
;
1270 GLuint nr_sf_entries
;
1271 GLuint nr_cs_entries
;
1278 GLuint size
; /* Hardware URB size, in KB. */
1280 /* True if the most recently sent _3DSTATE_URB message allocated
1281 * URB space for the GS.
1287 /* BRW_NEW_CURBE_OFFSETS:
1290 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1291 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1299 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1300 * for upload to the CURBE.
1302 drm_intel_bo
*curbe_bo
;
1303 /** Offset within curbe_bo of space for current curbe entry */
1304 GLuint curbe_offset
;
1308 * Layout of vertex data exiting the vertex shader.
1310 * BRW_NEW_VUE_MAP_VS is flagged when this VUE map changes.
1312 struct brw_vue_map vue_map_vs
;
1315 * Layout of vertex data exiting the geometry portion of the pipleine.
1316 * This comes from the geometry shader if one exists, otherwise from the
1319 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1321 struct brw_vue_map vue_map_geom_out
;
1324 struct brw_stage_state base
;
1325 struct brw_vs_prog_data
*prog_data
;
1329 struct brw_stage_state base
;
1330 struct brw_gs_prog_data
*prog_data
;
1333 * True if the 3DSTATE_GS command most recently emitted to the 3D
1334 * pipeline enabled the GS; false otherwise.
1340 struct brw_ff_gs_prog_data
*prog_data
;
1343 /** Offset in the program cache to the CLIP program pre-gen6 */
1344 uint32_t prog_offset
;
1345 uint32_t state_offset
;
1347 uint32_t bind_bo_offset
;
1349 * Surface offsets for the binding table. We only need surfaces to
1350 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1351 * need in this case.
1353 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1357 struct brw_clip_prog_data
*prog_data
;
1359 /** Offset in the program cache to the CLIP program pre-gen6 */
1360 uint32_t prog_offset
;
1362 /* Offset in the batch to the CLIP state on pre-gen6. */
1363 uint32_t state_offset
;
1365 /* As of gen6, this is the offset in the batch to the CLIP VP,
1373 struct brw_sf_prog_data
*prog_data
;
1375 /** Offset in the program cache to the CLIP program pre-gen6 */
1376 uint32_t prog_offset
;
1377 uint32_t state_offset
;
1379 bool viewport_transform_enable
;
1383 struct brw_stage_state base
;
1384 struct brw_wm_prog_data
*prog_data
;
1389 * Buffer object used in place of multisampled null render targets on
1390 * Gen6. See brw_emit_null_surface_state().
1392 drm_intel_bo
*multisampled_null_render_target_bo
;
1393 uint32_t fast_clear_op
;
1397 struct brw_stage_state base
;
1398 struct brw_cs_prog_data
*prog_data
;
1401 /* RS hardware binding table */
1404 uint32_t next_offset
;
1408 uint32_t state_offset
;
1409 uint32_t blend_state_offset
;
1410 uint32_t depth_stencil_state_offset
;
1415 struct brw_query_object
*obj
;
1420 enum brw_predicate_state state
;
1425 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1426 const int *statistics_registers
;
1428 /** The number of active monitors using OA counters. */
1432 * A buffer object storing OA counter snapshots taken at the start and
1433 * end of each batch (creating "bookends" around the batch).
1435 drm_intel_bo
*bookend_bo
;
1437 /** The number of snapshots written to bookend_bo. */
1438 int bookend_snapshots
;
1441 * An array of monitors whose results haven't yet been assembled based on
1442 * the data in buffer objects.
1444 * These may be active, or have already ended. However, the results
1445 * have not been requested.
1447 struct brw_perf_monitor_object
**unresolved
;
1448 int unresolved_elements
;
1449 int unresolved_array_size
;
1452 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1453 * the counter which MI_REPORT_PERF_COUNT stores there.
1455 const int *oa_snapshot_layout
;
1457 /** Number of 32-bit entries in a hardware counter snapshot. */
1458 int entries_per_oa_snapshot
;
1461 int num_atoms
[BRW_NUM_PIPELINES
];
1462 const struct brw_tracked_state render_atoms
[57];
1463 const struct brw_tracked_state compute_atoms
[3];
1465 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1469 enum aub_state_struct_type type
;
1471 } *state_batch_list
;
1472 int state_batch_count
;
1474 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1475 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1477 /* Interpolation modes, one byte per vue slot.
1478 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1480 struct interpolation_mode_map interpolation_mode
;
1482 /* PrimitiveRestart */
1485 bool enable_cut_index
;
1488 /** Computed depth/stencil/hiz state from the current attached
1489 * renderbuffers, valid only during the drawing state upload loop after
1490 * brw_workaround_depthstencil_alignment().
1493 struct intel_mipmap_tree
*depth_mt
;
1494 struct intel_mipmap_tree
*stencil_mt
;
1496 /* Inter-tile (page-aligned) byte offsets. */
1497 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1498 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1499 uint32_t tile_x
, tile_y
;
1502 uint32_t num_instances
;
1509 enum shader_time_shader_type
*types
;
1510 struct shader_times
*cumulative
;
1516 struct brw_fast_clear_state
*fast_clear_state
;
1518 __DRIcontext
*driContext
;
1519 struct intel_screen
*intelScreen
;
1522 /*======================================================================
1525 void brwInitVtbl( struct brw_context
*brw
);
1528 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1530 /*======================================================================
1533 extern const char *const brw_vendor_string
;
1535 extern const char *brw_get_renderer_string(unsigned deviceID
);
1538 DRI_CONF_BO_REUSE_DISABLED
,
1539 DRI_CONF_BO_REUSE_ALL
1542 void intel_update_renderbuffers(__DRIcontext
*context
,
1543 __DRIdrawable
*drawable
);
1544 void intel_prepare_render(struct brw_context
*brw
);
1546 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1547 __DRIdrawable
*drawable
);
1549 GLboolean
brwCreateContext(gl_api api
,
1550 const struct gl_config
*mesaVis
,
1551 __DRIcontext
*driContextPriv
,
1552 unsigned major_version
,
1553 unsigned minor_version
,
1557 void *sharedContextPrivate
);
1559 /*======================================================================
1562 GLuint
brw_get_rb_for_slice(struct brw_context
*brw
,
1563 struct intel_mipmap_tree
*mt
,
1564 unsigned level
, unsigned layer
, bool flat
);
1566 void brw_meta_updownsample(struct brw_context
*brw
,
1567 struct intel_mipmap_tree
*src
,
1568 struct intel_mipmap_tree
*dst
);
1570 void brw_meta_fbo_stencil_blit(struct brw_context
*brw
,
1571 struct gl_framebuffer
*read_fb
,
1572 struct gl_framebuffer
*draw_fb
,
1573 GLfloat srcX0
, GLfloat srcY0
,
1574 GLfloat srcX1
, GLfloat srcY1
,
1575 GLfloat dstX0
, GLfloat dstY0
,
1576 GLfloat dstX1
, GLfloat dstY1
);
1578 void brw_meta_stencil_updownsample(struct brw_context
*brw
,
1579 struct intel_mipmap_tree
*src
,
1580 struct intel_mipmap_tree
*dst
);
1582 bool brw_meta_fast_clear(struct brw_context
*brw
,
1583 struct gl_framebuffer
*fb
,
1585 bool partial_clear
);
1588 brw_meta_resolve_color(struct brw_context
*brw
,
1589 struct intel_mipmap_tree
*mt
);
1591 brw_meta_fast_clear_free(struct brw_context
*brw
);
1594 /*======================================================================
1597 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1598 uint32_t depth_level
,
1599 uint32_t depth_layer
,
1600 struct intel_mipmap_tree
*stencil_mt
,
1601 uint32_t *out_tile_mask_x
,
1602 uint32_t *out_tile_mask_y
);
1603 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1604 GLbitfield clear_mask
);
1606 /* brw_object_purgeable.c */
1607 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1609 /*======================================================================
1612 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1613 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1614 void brw_emit_query_begin(struct brw_context
*brw
);
1615 void brw_emit_query_end(struct brw_context
*brw
);
1617 /** gen6_queryobj.c */
1618 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1619 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1620 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1621 void brw_store_register_mem64(struct brw_context
*brw
,
1622 drm_intel_bo
*bo
, uint32_t reg
, int idx
);
1624 /** brw_conditional_render.c */
1625 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1626 bool brw_check_conditional_render(struct brw_context
*brw
);
1628 /** intel_batchbuffer.c */
1629 void brw_load_register_mem(struct brw_context
*brw
,
1632 uint32_t read_domains
, uint32_t write_domain
,
1634 void brw_load_register_mem64(struct brw_context
*brw
,
1637 uint32_t read_domains
, uint32_t write_domain
,
1640 /*======================================================================
1643 void brw_debug_batch(struct brw_context
*brw
);
1644 void brw_annotate_aub(struct brw_context
*brw
);
1646 /*======================================================================
1649 void brw_validate_textures( struct brw_context
*brw
);
1652 /*======================================================================
1655 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1657 int brw_get_scratch_size(int size
);
1658 void brw_get_scratch_bo(struct brw_context
*brw
,
1659 drm_intel_bo
**scratch_bo
, int size
);
1660 void brw_init_shader_time(struct brw_context
*brw
);
1661 int brw_get_shader_time_index(struct brw_context
*brw
,
1662 struct gl_shader_program
*shader_prog
,
1663 struct gl_program
*prog
,
1664 enum shader_time_shader_type type
);
1665 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1666 void brw_destroy_shader_time(struct brw_context
*brw
);
1670 void brw_upload_urb_fence(struct brw_context
*brw
);
1674 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1676 /* brw_fs_reg_allocate.cpp
1678 void brw_fs_alloc_reg_sets(struct brw_compiler
*compiler
);
1680 /* brw_vec4_reg_allocate.cpp */
1681 void brw_vec4_alloc_reg_set(struct brw_compiler
*compiler
);
1684 int brw_disassemble_inst(FILE *file
, const struct brw_device_info
*devinfo
,
1685 struct brw_inst
*inst
, bool is_compacted
);
1688 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1690 /* brw_draw_upload.c */
1691 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1692 const struct gl_client_array
*glarray
);
1694 static inline unsigned
1695 brw_get_index_type(GLenum type
)
1697 assert((type
== GL_UNSIGNED_BYTE
)
1698 || (type
== GL_UNSIGNED_SHORT
)
1699 || (type
== GL_UNSIGNED_INT
));
1701 /* The possible values for type are GL_UNSIGNED_BYTE (0x1401),
1702 * GL_UNSIGNED_SHORT (0x1403), and GL_UNSIGNED_INT (0x1405) which we want
1703 * to map to scale factors of 0, 1, and 2, respectively. These scale
1704 * factors are then left-shfited by 8 to be in the correct position in the
1705 * CMD_INDEX_BUFFER packet.
1707 * Subtracting 0x1401 gives 0, 2, and 4. Shifting left by 7 afterwards
1708 * gives 0x00000000, 0x00000100, and 0x00000200. These just happen to be
1709 * the values the need to be written in the CMD_INDEX_BUFFER packet.
1711 return (type
- 0x1401) << 7;
1714 void brw_prepare_vertices(struct brw_context
*brw
);
1716 /* brw_wm_surface_state.c */
1717 void brw_init_surface_formats(struct brw_context
*brw
);
1718 void brw_create_constant_surface(struct brw_context
*brw
,
1722 uint32_t *out_offset
,
1724 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1726 uint32_t *surf_offset
);
1728 brw_update_sol_surface(struct brw_context
*brw
,
1729 struct gl_buffer_object
*buffer_obj
,
1730 uint32_t *out_offset
, unsigned num_vector_components
,
1731 unsigned stride_dwords
, unsigned offset_dwords
);
1732 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1733 struct gl_shader
*shader
,
1734 struct brw_stage_state
*stage_state
,
1735 struct brw_stage_prog_data
*prog_data
,
1737 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1738 struct gl_shader_program
*prog
,
1739 struct brw_stage_state
*stage_state
,
1740 struct brw_stage_prog_data
*prog_data
);
1742 /* brw_surface_formats.c */
1743 bool brw_render_target_supported(struct brw_context
*brw
,
1744 struct gl_renderbuffer
*rb
);
1745 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1747 /* brw_performance_monitor.c */
1748 void brw_init_performance_monitors(struct brw_context
*brw
);
1749 void brw_dump_perf_monitors(struct brw_context
*brw
);
1750 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1751 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1753 /* intel_buffer_objects.c */
1754 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1755 const char *bo_name
);
1756 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1757 const char *bo_name
);
1759 /* intel_extensions.c */
1760 extern void intelInitExtensions(struct gl_context
*ctx
);
1763 extern int intel_translate_shadow_compare_func(GLenum func
);
1764 extern int intel_translate_compare_func(GLenum func
);
1765 extern int intel_translate_stencil_op(GLenum op
);
1766 extern int intel_translate_logic_op(GLenum opcode
);
1768 /* intel_syncobj.c */
1769 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1772 struct gl_transform_feedback_object
*
1773 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1775 brw_delete_transform_feedback(struct gl_context
*ctx
,
1776 struct gl_transform_feedback_object
*obj
);
1778 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1779 struct gl_transform_feedback_object
*obj
);
1781 brw_end_transform_feedback(struct gl_context
*ctx
,
1782 struct gl_transform_feedback_object
*obj
);
1784 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1785 struct gl_transform_feedback_object
*obj
,
1788 /* gen7_sol_state.c */
1790 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1791 struct gl_transform_feedback_object
*obj
);
1793 gen7_end_transform_feedback(struct gl_context
*ctx
,
1794 struct gl_transform_feedback_object
*obj
);
1796 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1797 struct gl_transform_feedback_object
*obj
);
1799 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1800 struct gl_transform_feedback_object
*obj
);
1802 /* brw_blorp_blit.cpp */
1804 brw_blorp_framebuffer(struct brw_context
*brw
,
1805 struct gl_framebuffer
*readFb
,
1806 struct gl_framebuffer
*drawFb
,
1807 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1808 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1809 GLbitfield mask
, GLenum filter
);
1812 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1813 struct gl_renderbuffer
*src_rb
,
1814 struct gl_texture_image
*dst_image
,
1816 int srcX0
, int srcY0
,
1817 int dstX0
, int dstY0
,
1818 int width
, int height
);
1820 /* gen6_multisample_state.c */
1822 gen6_determine_sample_mask(struct brw_context
*brw
);
1825 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1826 unsigned num_samples
);
1828 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1830 gen6_get_sample_position(struct gl_context
*ctx
,
1831 struct gl_framebuffer
*fb
,
1835 gen6_set_sample_maps(struct gl_context
*ctx
);
1837 /* gen8_multisample_state.c */
1838 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1839 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1843 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1844 unsigned gs_size
, unsigned fs_size
);
1847 gen7_emit_urb_state(struct brw_context
*brw
,
1848 unsigned nr_vs_entries
, unsigned vs_size
,
1849 unsigned vs_start
, unsigned nr_gs_entries
,
1850 unsigned gs_size
, unsigned gs_start
);
1855 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1859 brw_init_compute_functions(struct dd_function_table
*functions
);
1861 /*======================================================================
1862 * Inline conversion functions. These are better-typed than the
1863 * macros used previously:
1865 static inline struct brw_context
*
1866 brw_context( struct gl_context
*ctx
)
1868 return (struct brw_context
*)ctx
;
1871 static inline struct brw_vertex_program
*
1872 brw_vertex_program(struct gl_vertex_program
*p
)
1874 return (struct brw_vertex_program
*) p
;
1877 static inline const struct brw_vertex_program
*
1878 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1880 return (const struct brw_vertex_program
*) p
;
1883 static inline struct brw_geometry_program
*
1884 brw_geometry_program(struct gl_geometry_program
*p
)
1886 return (struct brw_geometry_program
*) p
;
1889 static inline struct brw_fragment_program
*
1890 brw_fragment_program(struct gl_fragment_program
*p
)
1892 return (struct brw_fragment_program
*) p
;
1895 static inline const struct brw_fragment_program
*
1896 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1898 return (const struct brw_fragment_program
*) p
;
1901 static inline struct brw_compute_program
*
1902 brw_compute_program(struct gl_compute_program
*p
)
1904 return (struct brw_compute_program
*) p
;
1908 * Pre-gen6, the register file of the EUs was shared between threads,
1909 * and each thread used some subset allocated on a 16-register block
1910 * granularity. The unit states wanted these block counts.
1913 brw_register_blocks(int reg_count
)
1915 return ALIGN(reg_count
, 16) / 16 - 1;
1918 static inline uint32_t
1919 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1920 uint32_t prog_offset
)
1922 if (brw
->gen
>= 5) {
1923 /* Using state base address. */
1927 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1931 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1933 return brw
->cache
.bo
->offset64
+ prog_offset
;
1936 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1937 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1938 struct exec_list
*instructions
);
1939 bool brw_do_lower_unnormalized_offset(struct exec_list
*instructions
);
1941 struct opcode_desc
{
1947 extern const struct opcode_desc opcode_descs
[128];
1948 extern const char * const conditional_modifier
[16];
1951 brw_emit_depthbuffer(struct brw_context
*brw
);
1954 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1955 struct intel_mipmap_tree
*depth_mt
,
1956 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1957 uint32_t depth_surface_type
,
1958 struct intel_mipmap_tree
*stencil_mt
,
1959 bool hiz
, bool separate_stencil
,
1960 uint32_t width
, uint32_t height
,
1961 uint32_t tile_x
, uint32_t tile_y
);
1964 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1965 struct intel_mipmap_tree
*depth_mt
,
1966 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1967 uint32_t depth_surface_type
,
1968 struct intel_mipmap_tree
*stencil_mt
,
1969 bool hiz
, bool separate_stencil
,
1970 uint32_t width
, uint32_t height
,
1971 uint32_t tile_x
, uint32_t tile_y
);
1974 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1975 struct intel_mipmap_tree
*depth_mt
,
1976 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1977 uint32_t depth_surface_type
,
1978 struct intel_mipmap_tree
*stencil_mt
,
1979 bool hiz
, bool separate_stencil
,
1980 uint32_t width
, uint32_t height
,
1981 uint32_t tile_x
, uint32_t tile_y
);
1983 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1984 struct intel_mipmap_tree
*depth_mt
,
1985 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1986 uint32_t depth_surface_type
,
1987 struct intel_mipmap_tree
*stencil_mt
,
1988 bool hiz
, bool separate_stencil
,
1989 uint32_t width
, uint32_t height
,
1990 uint32_t tile_x
, uint32_t tile_y
);
1992 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1993 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);
1995 uint32_t get_hw_prim_for_gl_prim(int mode
);
1998 brw_setup_vue_key_clip_info(struct brw_context
*brw
,
1999 struct brw_vue_prog_key
*key
,
2000 bool program_uses_clip_distance
);
2003 gen6_upload_push_constants(struct brw_context
*brw
,
2004 const struct gl_program
*prog
,
2005 const struct brw_stage_prog_data
*prog_data
,
2006 struct brw_stage_state
*stage_state
,
2007 enum aub_state_struct_type type
);
2010 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
2011 const struct intel_mipmap_tree
*mt
);
2013 /* brw_pipe_control.c */
2014 int brw_init_pipe_control(struct brw_context
*brw
,
2015 const struct brw_device_info
*info
);
2016 void brw_fini_pipe_control(struct brw_context
*brw
);
2018 void brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
);
2019 void brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
2020 drm_intel_bo
*bo
, uint32_t offset
,
2021 uint32_t imm_lower
, uint32_t imm_upper
);
2022 void brw_emit_mi_flush(struct brw_context
*brw
);
2023 void brw_emit_post_sync_nonzero_flush(struct brw_context
*brw
);
2024 void brw_emit_depth_stall_flushes(struct brw_context
*brw
);
2025 void gen7_emit_vs_workaround_flush(struct brw_context
*brw
);
2026 void gen7_emit_cs_stall_flush(struct brw_context
*brw
);