2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
38 #include "main/imports.h"
39 #include "main/macros.h"
41 #include "main/mtypes.h"
42 #include "brw_structs.h"
43 #include "intel_aub.h"
44 #include "program/prog_parameter.h"
48 /* Evil hack for using libdrm in a c++ compiler. */
53 #include <intel_bufmgr.h>
63 #include "intel_debug.h"
64 #include "intel_screen.h"
65 #include "intel_tex_obj.h"
66 #include "intel_resolve_map.h"
70 * URB - uniform resource buffer. A mid-sized buffer which is
71 * partitioned between the fixed function units and used for passing
72 * values (vertices, primitives, constants) between them.
74 * CURBE - constant URB entry. An urb region (entry) used to hold
75 * constant values which the fixed function units can be instructed to
76 * preload into the GRF when spawning a thread.
78 * VUE - vertex URB entry. An urb entry holding a vertex and usually
79 * a vertex header. The header contains control information and
80 * things like primitive type, Begin/end flags and clip codes.
82 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
83 * unit holding rasterization and interpolation parameters.
85 * GRF - general register file. One of several register files
86 * addressable by programmed threads. The inputs (r0, payload, curbe,
87 * urb) of the thread are preloaded to this area before the thread is
88 * spawned. The registers are individually 8 dwords wide and suitable
89 * for general usage. Registers holding thread input values are not
90 * special and may be overwritten.
92 * MRF - message register file. Threads communicate (and terminate)
93 * by sending messages. Message parameters are placed in contiguous
94 * MRF registers. All program output is via these messages. URB
95 * entries are populated by sending a message to the shared URB
96 * function containing the new data, together with a control word,
97 * often an unmodified copy of R0.
99 * R0 - GRF register 0. Typically holds control information used when
100 * sending messages to other threads.
102 * EU or GEN4 EU: The name of the programmable subsystem of the
103 * i965 hardware. Threads are executed by the EU, the registers
104 * described above are part of the EU architecture.
106 * Fixed function units:
108 * CS - Command streamer. Notional first unit, little software
109 * interaction. Holds the URB entries used for constant data, ie the
112 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
113 * this unit is responsible for pulling vertices out of vertex buffers
114 * in vram and injecting them into the processing pipe as VUEs. If
115 * enabled, it first passes them to a VS thread which is a good place
116 * for the driver to implement any active vertex shader.
118 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
119 * enabled, incoming strips etc are passed to GS threads in individual
120 * line/triangle/point units. The GS thread may perform arbitary
121 * computation and emit whatever primtives with whatever vertices it
122 * chooses. This makes GS an excellent place to implement GL's
123 * unfilled polygon modes, though of course it is capable of much
124 * more. Additionally, GS is used to translate away primitives not
125 * handled by latter units, including Quads and Lineloops.
127 * CS - Clipper. Mesa's clipping algorithms are imported to run on
128 * this unit. The fixed function part performs cliptesting against
129 * the 6 fixed clipplanes and makes descisions on whether or not the
130 * incoming primitive needs to be passed to a thread for clipping.
131 * User clip planes are handled via cooperation with the VS thread.
133 * SF - Strips Fans or Setup: Triangles are prepared for
134 * rasterization. Interpolation coefficients are calculated.
135 * Flatshading and two-side lighting usually performed here.
137 * WM - Windower. Interpolation of vertex attributes performed here.
138 * Fragment shader implemented here. SIMD aspects of EU taken full
139 * advantage of, as pixels are processed in blocks of 16.
141 * CC - Color Calculator. No EU threads associated with this unit.
142 * Handles blending and (presumably) depth and stencil testing.
147 struct brw_vs_prog_key
;
148 struct brw_vue_prog_key
;
149 struct brw_wm_prog_key
;
150 struct brw_wm_prog_data
;
151 struct brw_cs_prog_key
;
152 struct brw_cs_prog_data
;
156 BRW_COMPUTE_PIPELINE
,
163 BRW_CACHE_BLORP_BLIT_PROG
,
166 BRW_CACHE_FF_GS_PROG
,
175 /* brw_cache_ids must come first - see brw_state_cache.c */
176 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
177 BRW_STATE_FRAGMENT_PROGRAM
,
178 BRW_STATE_GEOMETRY_PROGRAM
,
179 BRW_STATE_VERTEX_PROGRAM
,
180 BRW_STATE_CURBE_OFFSETS
,
181 BRW_STATE_REDUCED_PRIMITIVE
,
186 BRW_STATE_VS_BINDING_TABLE
,
187 BRW_STATE_GS_BINDING_TABLE
,
188 BRW_STATE_PS_BINDING_TABLE
,
192 BRW_STATE_INDEX_BUFFER
,
193 BRW_STATE_VS_CONSTBUF
,
194 BRW_STATE_GS_CONSTBUF
,
195 BRW_STATE_PROGRAM_CACHE
,
196 BRW_STATE_STATE_BASE_ADDRESS
,
197 BRW_STATE_VUE_MAP_GEOM_OUT
,
198 BRW_STATE_TRANSFORM_FEEDBACK
,
199 BRW_STATE_RASTERIZER_DISCARD
,
201 BRW_STATE_UNIFORM_BUFFER
,
202 BRW_STATE_ATOMIC_BUFFER
,
203 BRW_STATE_IMAGE_UNITS
,
204 BRW_STATE_META_IN_PROGRESS
,
205 BRW_STATE_INTERPOLATION_MAP
,
206 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
207 BRW_STATE_NUM_SAMPLES
,
208 BRW_STATE_TEXTURE_BUFFER
,
209 BRW_STATE_GEN4_UNIT_STATE
,
213 BRW_STATE_SAMPLER_STATE_TABLE
,
214 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
215 BRW_STATE_COMPUTE_PROGRAM
,
216 BRW_STATE_CS_WORK_GROUPS
,
221 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
223 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
224 * When the currently bound shader program differs from the previous draw
225 * call, these will be flagged. They cover brw->{stage}_program and
226 * ctx->{Stage}Program->_Current.
228 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
229 * driver perspective. Even if the same shader is bound at the API level,
230 * we may need to switch between multiple versions of that shader to handle
231 * changes in non-orthagonal state.
233 * Additionally, multiple shader programs may have identical vertex shaders
234 * (for example), or compile down to the same code in the backend. We combine
235 * those into a single program cache entry.
237 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
238 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
240 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
241 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
242 * use the normal state upload paths), but the cache is still used. To avoid
243 * polluting the brw_state_cache code with special cases, we retain the dirty
244 * bit for now. It should eventually be removed.
246 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_BLIT_PROG)
247 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
248 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
249 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
250 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
251 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
252 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
253 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
254 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
255 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
256 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
257 #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
258 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
259 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
260 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
261 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
262 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
263 #define BRW_NEW_VS_BINDING_TABLE (1ull << BRW_STATE_VS_BINDING_TABLE)
264 #define BRW_NEW_GS_BINDING_TABLE (1ull << BRW_STATE_GS_BINDING_TABLE)
265 #define BRW_NEW_PS_BINDING_TABLE (1ull << BRW_STATE_PS_BINDING_TABLE)
266 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
267 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
269 * Used for any batch entry with a relocated pointer that will be used
270 * by any 3D rendering.
272 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
273 /** \see brw.state.depth_region */
274 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
275 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
276 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
277 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
278 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
279 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
280 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
281 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
282 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
283 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
284 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
285 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
286 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
287 #define BRW_NEW_INTERPOLATION_MAP (1ull << BRW_STATE_INTERPOLATION_MAP)
288 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
289 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
290 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
291 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
292 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
293 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
294 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
295 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
296 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
297 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
298 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
300 struct brw_state_flags
{
301 /** State update flags signalled by mesa internals */
304 * State update flags signalled as the result of brw_tracked_state updates
309 /** Subclass of Mesa vertex program */
310 struct brw_vertex_program
{
311 struct gl_vertex_program program
;
316 /** Subclass of Mesa geometry program */
317 struct brw_geometry_program
{
318 struct gl_geometry_program program
;
319 unsigned id
; /**< serial no. to identify geom progs, never re-used */
323 /** Subclass of Mesa fragment program */
324 struct brw_fragment_program
{
325 struct gl_fragment_program program
;
326 GLuint id
; /**< serial no. to identify frag progs, never re-used */
330 /** Subclass of Mesa compute program */
331 struct brw_compute_program
{
332 struct gl_compute_program program
;
333 unsigned id
; /**< serial no. to identify compute progs, never re-used */
338 struct gl_shader base
;
343 struct brw_stage_prog_data
{
345 /** size of our binding table. */
349 * surface indices for the various groups of surfaces
351 uint32_t pull_constants_start
;
352 uint32_t texture_start
;
353 uint32_t gather_texture_start
;
356 uint32_t image_start
;
357 uint32_t shader_time_start
;
361 GLuint nr_params
; /**< number of float params/constants */
362 GLuint nr_pull_params
;
363 unsigned nr_image_params
;
365 unsigned curb_read_length
;
366 unsigned total_scratch
;
369 * Register where the thread expects to find input data from the URB
370 * (typically uniforms, followed by vertex or fragment attributes).
372 unsigned dispatch_grf_start_reg
;
374 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
376 /* Pointers to tracked values (only valid once
377 * _mesa_load_state_parameters has been called at runtime).
379 const gl_constant_value
**param
;
380 const gl_constant_value
**pull_param
;
382 /** Image metadata passed to the shader as uniforms. */
383 struct brw_image_param
*image_param
;
387 * Image metadata structure as laid out in the shader parameter
388 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
389 * able to use them. That's okay because the padding and any unused
390 * entries [most of them except when we're doing untyped surface
391 * access] will be removed by the uniform packing pass.
393 #define BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET 0
394 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 4
395 #define BRW_IMAGE_PARAM_SIZE_OFFSET 8
396 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 12
397 #define BRW_IMAGE_PARAM_TILING_OFFSET 16
398 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 20
399 #define BRW_IMAGE_PARAM_SIZE 24
401 struct brw_image_param
{
402 /** Surface binding table index. */
403 uint32_t surface_idx
;
405 /** Offset applied to the X and Y surface coordinates. */
408 /** Surface X, Y and Z dimensions. */
411 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
412 * pixels, vertical slice stride in pixels.
416 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
420 * Right shift to apply for bit 6 address swizzling. Two different
421 * swizzles can be specified and will be applied one after the other. The
422 * resulting address will be:
424 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
425 * (addr >> swizzling[1])))
427 * Use \c 0xff if any of the swizzles is not required.
429 uint32_t swizzling
[2];
432 /* Data about a particular attempt to compile a program. Note that
433 * there can be many of these, each in a different GL state
434 * corresponding to a different brw_wm_prog_key struct, with different
437 struct brw_wm_prog_data
{
438 struct brw_stage_prog_data base
;
440 GLuint num_varying_inputs
;
442 GLuint dispatch_grf_start_reg_16
;
444 GLuint reg_blocks_16
;
448 * surface indices the WM-specific surfaces
450 uint32_t render_target_start
;
454 uint8_t computed_depth_mode
;
456 bool early_fragment_tests
;
459 bool uses_pos_offset
;
463 uint32_t prog_offset_16
;
466 * Mask of which interpolation modes are required by the fragment shader.
467 * Used in hardware setup on gen6+.
469 uint32_t barycentric_interp_modes
;
472 * Map from gl_varying_slot to the position within the FS setup data
473 * payload where the varying's attribute vertex deltas should be delivered.
474 * For varying slots that are not used by the FS, the value is -1.
476 int urb_setup
[VARYING_SLOT_MAX
];
479 struct brw_cs_prog_data
{
480 struct brw_stage_prog_data base
;
482 GLuint dispatch_grf_start_reg_16
;
483 unsigned local_size
[3];
486 bool uses_num_work_groups
;
490 * surface indices the CS-specific surfaces
492 uint32_t work_groups_start
;
498 * Enum representing the i965-specific vertex results that don't correspond
499 * exactly to any element of gl_varying_slot. The values of this enum are
500 * assigned such that they don't conflict with gl_varying_slot.
504 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
505 BRW_VARYING_SLOT_PAD
,
507 * Technically this is not a varying but just a placeholder that
508 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
509 * builtin variable to be compiled correctly. see compile_sf_prog() for
512 BRW_VARYING_SLOT_PNTC
,
513 BRW_VARYING_SLOT_COUNT
518 * Data structure recording the relationship between the gl_varying_slot enum
519 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
520 * single octaword within the VUE (128 bits).
522 * Note that each BRW register contains 256 bits (2 octawords), so when
523 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
524 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
525 * in a vertex shader), each register corresponds to a single VUE slot, since
526 * it contains data for two separate vertices.
530 * Bitfield representing all varying slots that are (a) stored in this VUE
531 * map, and (b) actually written by the shader. Does not include any of
532 * the additional varying slots defined in brw_varying_slot.
534 GLbitfield64 slots_valid
;
537 * Is this VUE map for a separate shader pipeline?
539 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
540 * without the linker having a chance to dead code eliminate unused varyings.
542 * This means that we have to use a fixed slot layout, based on the output's
543 * location field, rather than assigning slots in a compact contiguous block.
548 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
549 * not stored in a slot (because they are not written, or because
550 * additional processing is applied before storing them in the VUE), the
553 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
556 * Map from VUE slot to gl_varying_slot value. For slots that do not
557 * directly correspond to a gl_varying_slot, the value comes from
560 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
561 * simplifies code that uses the value stored in slot_to_varying to
562 * create a bit mask).
564 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
567 * Total number of VUE slots in use
573 * Convert a VUE slot number into a byte offset within the VUE.
575 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
581 * Convert a vertex output (brw_varying_slot) into a byte offset within the
584 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
587 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
590 void brw_compute_vue_map(const struct brw_device_info
*devinfo
,
591 struct brw_vue_map
*vue_map
,
592 GLbitfield64 slots_valid
,
593 bool separate_shader
);
597 * Bitmask indicating which fragment shader inputs represent varyings (and
598 * hence have to be delivered to the fragment shader by the SF/SBE stage).
600 #define BRW_FS_VARYING_INPUT_MASK \
601 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
602 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
606 * Mapping of VUE map slots to interpolation modes.
608 struct interpolation_mode_map
{
609 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
612 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
614 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
615 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
621 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
623 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
624 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
631 struct brw_sf_prog_data
{
632 GLuint urb_read_length
;
635 /* Each vertex may have upto 12 attributes, 4 components each,
636 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
639 * Actually we use 4 for each, so call it 12 rows.
641 GLuint urb_entry_size
;
646 * We always program SF to start reading at an offset of 1 (2 varying slots)
647 * from the start of the vertex URB entry. This causes it to skip:
648 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
649 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
651 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
654 struct brw_clip_prog_data
{
655 GLuint curb_read_length
; /* user planes? */
657 GLuint urb_read_length
;
661 struct brw_ff_gs_prog_data
{
662 GLuint urb_read_length
;
666 * Gen6 transform feedback: Amount by which the streaming vertex buffer
667 * indices should be incremented each time the GS is invoked.
669 unsigned svbi_postincrement_value
;
672 enum shader_dispatch_mode
{
673 DISPATCH_MODE_4X1_SINGLE
= 0,
674 DISPATCH_MODE_4X2_DUAL_INSTANCE
= 1,
675 DISPATCH_MODE_4X2_DUAL_OBJECT
= 2,
676 DISPATCH_MODE_SIMD8
= 3,
679 struct brw_vue_prog_data
{
680 struct brw_stage_prog_data base
;
681 struct brw_vue_map vue_map
;
683 GLuint urb_read_length
;
686 /* Used for calculating urb partitions. In the VS, this is the size of the
687 * URB entry used for both input and output to the thread. In the GS, this
688 * is the size of the URB entry used for output.
690 GLuint urb_entry_size
;
692 enum shader_dispatch_mode dispatch_mode
;
696 struct brw_vs_prog_data
{
697 struct brw_vue_prog_data base
;
699 GLbitfield64 inputs_read
;
702 bool uses_instanceid
;
705 /** Number of texture sampler units */
706 #define BRW_MAX_TEX_UNIT 32
708 /** Max number of render targets in a shader */
709 #define BRW_MAX_DRAW_BUFFERS 8
711 /** Max number of UBOs in a shader */
712 #define BRW_MAX_UBO 12
714 /** Max number of SSBOs in a shader */
715 #define BRW_MAX_SSBO 12
717 /** Max number of atomic counter buffer objects in a shader */
718 #define BRW_MAX_ABO 16
720 /** Max number of image uniforms in a shader */
721 #define BRW_MAX_IMAGES 32
724 * Max number of binding table entries used for stream output.
726 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
727 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
729 * On Gen6, the size of transform feedback data is limited not by the number
730 * of components but by the number of binding table entries we set aside. We
731 * use one binding table entry for a float, one entry for a vector, and one
732 * entry per matrix column. Since the only way we can communicate our
733 * transform feedback capabilities to the client is via
734 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
735 * worst case, in which all the varyings are floats, so we use up one binding
736 * table entry per component. Therefore we need to set aside at least 64
737 * binding table entries for use by transform feedback.
739 * Note: since we don't currently pack varyings, it is currently impossible
740 * for the client to actually use up all of these binding table entries--if
741 * all of their varyings were floats, they would run out of varying slots and
742 * fail to link. But that's a bug, so it seems prudent to go ahead and
743 * allocate the number of binding table entries we will need once the bug is
746 #define BRW_MAX_SOL_BINDINGS 64
748 /** Maximum number of actual buffers used for stream output */
749 #define BRW_MAX_SOL_BUFFERS 4
751 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
752 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
757 2 + /* shader time, pull constants */ \
758 1 /* cs num work groups */)
760 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
762 struct brw_gs_prog_data
764 struct brw_vue_prog_data base
;
767 * Size of an output vertex, measured in HWORDS (32 bytes).
769 unsigned output_vertex_size_hwords
;
771 unsigned output_topology
;
774 * Size of the control data (cut bits or StreamID bits), in hwords (32
775 * bytes). 0 if there is no control data.
777 unsigned control_data_header_size_hwords
;
780 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
781 * if the control data is StreamID bits, or
782 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
783 * Ignored if control_data_header_size is 0.
785 unsigned control_data_format
;
787 bool include_primitive_id
;
790 * The number of vertices emitted, if constant - otherwise -1.
792 int static_vertex_count
;
797 * Gen6 transform feedback enabled flag.
799 bool gen6_xfb_enabled
;
802 * Gen6: Provoking vertex convention for odd-numbered triangles
808 * Gen6: Number of varyings that are output to transform feedback.
810 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
813 * Gen6: Map from the index of a transform feedback binding table entry to the
814 * gl_varying_slot that should be streamed out through that binding table
817 unsigned char transform_feedback_bindings
[BRW_MAX_SOL_BINDINGS
];
820 * Gen6: Map from the index of a transform feedback binding table entry to the
821 * swizzles that should be used when streaming out data through that
822 * binding table entry.
824 unsigned char transform_feedback_swizzles
[BRW_MAX_SOL_BINDINGS
];
828 * Stride in bytes between shader_time entries.
830 * We separate entries by a cacheline to reduce traffic between EUs writing to
833 #define SHADER_TIME_STRIDE 64
835 struct brw_cache_item
{
837 * Effectively part of the key, cache_id identifies what kind of state
838 * buffer is involved, and also which dirty flag should set.
840 enum brw_cache_id cache_id
;
841 /** 32-bit hash of the key data */
843 GLuint key_size
; /* for variable-sized keys */
850 struct brw_cache_item
*next
;
854 typedef void (*cache_aux_free_func
)(const void *aux
);
857 struct brw_context
*brw
;
859 struct brw_cache_item
**items
;
861 GLuint size
, n_items
;
863 uint32_t next_offset
;
866 /** Optional functions for freeing other pointers attached to a prog_data. */
867 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
871 /* Considered adding a member to this struct to document which flags
872 * an update might raise so that ordering of the state atoms can be
873 * checked or derived at runtime. Dropped the idea in favor of having
874 * a debug mode where the state is monitored for flags which are
875 * raised that have already been tested against.
877 struct brw_tracked_state
{
878 struct brw_state_flags dirty
;
879 void (*emit
)( struct brw_context
*brw
);
882 enum shader_time_shader_type
{
891 struct brw_vertex_buffer
{
892 /** Buffer object containing the uploaded vertex data */
895 /** Byte stride between elements in the uploaded array */
899 struct brw_vertex_element
{
900 const struct gl_client_array
*glarray
;
904 /** Offset of the first element within the buffer object */
908 struct brw_query_object
{
909 struct gl_query_object Base
;
911 /** Last query BO associated with this query. */
914 /** Last index in bo with query data for this object. */
917 /** True if we know the batch has been flushed since we ended the query. */
927 struct intel_batchbuffer
{
928 /** Current batchbuffer being queued up. */
930 /** Last BO submitted to the hardware. Used for glFinish(). */
931 drm_intel_bo
*last_bo
;
934 uint16_t emit
, total
;
936 uint16_t reserved_space
;
940 #define BATCH_SZ (8192*sizeof(uint32_t))
942 uint32_t state_batch_offset
;
943 enum brw_gpu_ring ring
;
944 bool needs_sol_reset
;
952 #define BRW_MAX_XFB_STREAMS 4
954 struct brw_transform_feedback_object
{
955 struct gl_transform_feedback_object base
;
957 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
958 drm_intel_bo
*offset_bo
;
960 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
963 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
964 GLenum primitive_mode
;
967 * Count of primitives generated during this transform feedback operation.
970 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
971 drm_intel_bo
*prim_count_bo
;
972 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
976 * Number of vertices written between last Begin/EndTransformFeedback().
978 * Used to implement DrawTransformFeedback().
980 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
981 bool vertices_written_valid
;
985 * Data shared between each programmable stage in the pipeline (vs, gs, and
988 struct brw_stage_state
990 gl_shader_stage stage
;
991 struct brw_stage_prog_data
*prog_data
;
994 * Optional scratch buffer used to store spilled register values and
995 * variably-indexed GRF arrays.
997 drm_intel_bo
*scratch_bo
;
999 /** Offset in the program cache to the program */
1000 uint32_t prog_offset
;
1002 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
1003 uint32_t state_offset
;
1005 uint32_t push_const_offset
; /* Offset in the batchbuffer */
1006 int push_const_size
; /* in 256-bit register increments */
1008 /* Binding table: pointers to SURFACE_STATE entries. */
1009 uint32_t bind_bo_offset
;
1010 uint32_t surf_offset
[BRW_MAX_SURFACES
];
1012 /** SAMPLER_STATE count and table offset */
1013 uint32_t sampler_count
;
1014 uint32_t sampler_offset
;
1017 enum brw_predicate_state
{
1018 /* The first two states are used if we can determine whether to draw
1019 * without having to look at the values in the query object buffer. This
1020 * will happen if there is no conditional render in progress, if the query
1021 * object is already completed or if something else has already added
1022 * samples to the preliminary result such as via a BLT command.
1024 BRW_PREDICATE_STATE_RENDER
,
1025 BRW_PREDICATE_STATE_DONT_RENDER
,
1026 /* In this case whether to draw or not depends on the result of an
1027 * MI_PREDICATE command so the predicate enable bit needs to be checked.
1029 BRW_PREDICATE_STATE_USE_BIT
1032 struct shader_times
;
1035 * brw_context is derived from gl_context.
1039 struct gl_context ctx
; /**< base class, must be first field */
1043 void (*update_texture_surface
)(struct gl_context
*ctx
,
1045 uint32_t *surf_offset
,
1047 uint32_t (*update_renderbuffer_surface
)(struct brw_context
*brw
,
1048 struct gl_renderbuffer
*rb
,
1049 bool layered
, unsigned unit
,
1050 uint32_t surf_index
);
1052 void (*emit_texture_surface_state
)(struct brw_context
*brw
,
1053 struct intel_mipmap_tree
*mt
,
1061 uint32_t *surf_offset
,
1062 bool rw
, bool for_gather
);
1063 void (*emit_buffer_surface_state
)(struct brw_context
*brw
,
1064 uint32_t *out_offset
,
1066 unsigned buffer_offset
,
1067 unsigned surface_format
,
1068 unsigned buffer_size
,
1071 void (*emit_null_surface_state
)(struct brw_context
*brw
,
1075 uint32_t *out_offset
);
1078 * Send the appropriate state packets to configure depth, stencil, and
1079 * HiZ buffers (i965+ only)
1081 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
1082 struct intel_mipmap_tree
*depth_mt
,
1083 uint32_t depth_offset
,
1084 uint32_t depthbuffer_format
,
1085 uint32_t depth_surface_type
,
1086 struct intel_mipmap_tree
*stencil_mt
,
1087 bool hiz
, bool separate_stencil
,
1088 uint32_t width
, uint32_t height
,
1089 uint32_t tile_x
, uint32_t tile_y
);
1095 drm_intel_context
*hw_ctx
;
1097 /** BO for post-sync nonzero writes for gen6 workaround. */
1098 drm_intel_bo
*workaround_bo
;
1099 uint8_t pipe_controls_since_last_cs_stall
;
1102 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
1103 * and would need flushing before being used from another cache domain that
1104 * isn't coherent with it (i.e. the sampler).
1106 struct set
*render_cache
;
1109 * Number of resets observed in the system at context creation.
1111 * This is tracked in the context so that we can determine that another
1112 * reset has occurred.
1114 uint32_t reset_count
;
1116 struct intel_batchbuffer batch
;
1121 uint32_t next_offset
;
1125 * Set if rendering has occurred to the drawable's front buffer.
1127 * This is used in the DRI2 case to detect that glFlush should also copy
1128 * the contents of the fake front buffer to the real front buffer.
1130 bool front_buffer_dirty
;
1132 /** Framerate throttling: @{ */
1133 drm_intel_bo
*throttle_batch
[2];
1135 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
1136 * frame of rendering to complete. This gives a very precise cap to the
1137 * latency between input and output such that rendering never gets more
1138 * than a frame behind the user. (With the caveat that we technically are
1139 * not using the SwapBuffers itself as a barrier but the first batch
1140 * submitted afterwards, which may be immediately prior to the next
1143 bool need_swap_throttle
;
1145 /** General throttling, not caught by throttling between SwapBuffers */
1146 bool need_flush_throttle
;
1156 bool always_flush_batch
;
1157 bool always_flush_cache
;
1158 bool disable_throttling
;
1161 driOptionCache optionCache
;
1164 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
1166 GLenum reduced_primitive
;
1169 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
1170 * variable is set, this is the flag indicating to do expensive work that
1171 * might lead to a perf_debug() call.
1175 uint32_t max_gtt_map_object_size
;
1187 bool has_separate_stencil
;
1188 bool must_use_separate_stencil
;
1191 bool has_surface_tile_offset
;
1193 bool has_negative_rhw_bug
;
1197 bool use_resource_streamer
;
1200 * Some versions of Gen hardware don't do centroid interpolation correctly
1201 * on unlit pixels, causing incorrect values for derivatives near triangle
1202 * edges. Enabling this flag causes the fragment shader to use
1203 * non-centroid interpolation for unlit pixels, at the expense of two extra
1204 * fragment shader instructions.
1206 bool needs_unlit_centroid_workaround
;
1210 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
1213 enum brw_pipeline last_pipeline
;
1215 struct brw_cache cache
;
1217 /** IDs for meta stencil blit shader programs. */
1218 unsigned meta_stencil_blit_programs
[2];
1220 /* Whether a meta-operation is in progress. */
1221 bool meta_in_progress
;
1223 /* Whether the last depth/stencil packets were both NULL. */
1224 bool no_depth_or_stencil
;
1226 /* The last PMA stall bits programmed. */
1227 uint32_t pma_stall_bits
;
1230 /** The value of gl_BaseVertex for the current _mesa_prim. */
1234 * Buffer and offset used for GL_ARB_shader_draw_parameters
1235 * (for now, only gl_BaseVertex).
1237 drm_intel_bo
*draw_params_bo
;
1238 uint32_t draw_params_offset
;
1243 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
1244 * an indirect call, and num_work_groups_offset is valid. Otherwise,
1245 * num_work_groups is set based on glDispatchCompute.
1247 drm_intel_bo
*num_work_groups_bo
;
1248 GLintptr num_work_groups_offset
;
1249 const GLuint
*num_work_groups
;
1253 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
1254 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
1256 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
1260 /* Summary of size and varying of active arrays, so we can check
1261 * for changes to this state:
1263 unsigned int min_index
, max_index
;
1265 /* Offset from start of vertex buffer so we can avoid redefining
1266 * the same VB packed over and over again.
1268 unsigned int start_vertex_bias
;
1271 * Certain vertex attribute formats aren't natively handled by the
1272 * hardware and require special VS code to fix up their values.
1274 * These bitfields indicate which workarounds are needed.
1276 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
1281 * Index buffer for this draw_prims call.
1283 * Updates are signaled by BRW_NEW_INDICES.
1285 const struct _mesa_index_buffer
*ib
;
1287 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
1291 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
1292 * avoid re-uploading the IB packet over and over if we're actually
1293 * referencing the same index buffer.
1295 unsigned int start_vertex_offset
;
1298 /* Active vertex program:
1300 const struct gl_vertex_program
*vertex_program
;
1301 const struct gl_geometry_program
*geometry_program
;
1302 const struct gl_fragment_program
*fragment_program
;
1303 const struct gl_compute_program
*compute_program
;
1306 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
1307 * that we don't have to reemit that state every time we change FBOs.
1312 * Platform specific constants containing the maximum number of threads
1313 * for each pipeline stage.
1315 unsigned max_vs_threads
;
1316 unsigned max_hs_threads
;
1317 unsigned max_ds_threads
;
1318 unsigned max_gs_threads
;
1319 unsigned max_wm_threads
;
1320 unsigned max_cs_threads
;
1322 /* BRW_NEW_URB_ALLOCATIONS:
1325 GLuint vsize
; /* vertex size plus header in urb registers */
1326 GLuint gsize
; /* GS output size in urb registers */
1327 GLuint csize
; /* constant buffer size in urb registers */
1328 GLuint sfsize
; /* setup data size in urb registers */
1332 GLuint min_vs_entries
; /* Minimum number of VS entries */
1333 GLuint max_vs_entries
; /* Maximum number of VS entries */
1334 GLuint max_hs_entries
; /* Maximum number of HS entries */
1335 GLuint max_ds_entries
; /* Maximum number of DS entries */
1336 GLuint max_gs_entries
; /* Maximum number of GS entries */
1338 GLuint nr_vs_entries
;
1339 GLuint nr_gs_entries
;
1340 GLuint nr_clip_entries
;
1341 GLuint nr_sf_entries
;
1342 GLuint nr_cs_entries
;
1349 GLuint size
; /* Hardware URB size, in KB. */
1351 /* True if the most recently sent _3DSTATE_URB message allocated
1352 * URB space for the GS.
1358 /* BRW_NEW_CURBE_OFFSETS:
1361 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1362 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1370 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1371 * for upload to the CURBE.
1373 drm_intel_bo
*curbe_bo
;
1374 /** Offset within curbe_bo of space for current curbe entry */
1375 GLuint curbe_offset
;
1379 * Layout of vertex data exiting the geometry portion of the pipleine.
1380 * This comes from the last enabled shader stage (GS, DS, or VS).
1382 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1384 struct brw_vue_map vue_map_geom_out
;
1387 struct brw_stage_state base
;
1388 struct brw_vs_prog_data
*prog_data
;
1392 struct brw_stage_state base
;
1393 struct brw_gs_prog_data
*prog_data
;
1396 * True if the 3DSTATE_GS command most recently emitted to the 3D
1397 * pipeline enabled the GS; false otherwise.
1403 struct brw_ff_gs_prog_data
*prog_data
;
1406 /** Offset in the program cache to the CLIP program pre-gen6 */
1407 uint32_t prog_offset
;
1408 uint32_t state_offset
;
1410 uint32_t bind_bo_offset
;
1412 * Surface offsets for the binding table. We only need surfaces to
1413 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1414 * need in this case.
1416 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1420 struct brw_clip_prog_data
*prog_data
;
1422 /** Offset in the program cache to the CLIP program pre-gen6 */
1423 uint32_t prog_offset
;
1425 /* Offset in the batch to the CLIP state on pre-gen6. */
1426 uint32_t state_offset
;
1428 /* As of gen6, this is the offset in the batch to the CLIP VP,
1436 struct brw_sf_prog_data
*prog_data
;
1438 /** Offset in the program cache to the CLIP program pre-gen6 */
1439 uint32_t prog_offset
;
1440 uint32_t state_offset
;
1442 bool viewport_transform_enable
;
1446 struct brw_stage_state base
;
1447 struct brw_wm_prog_data
*prog_data
;
1452 * Buffer object used in place of multisampled null render targets on
1453 * Gen6. See brw_emit_null_surface_state().
1455 drm_intel_bo
*multisampled_null_render_target_bo
;
1456 uint32_t fast_clear_op
;
1460 struct brw_stage_state base
;
1461 struct brw_cs_prog_data
*prog_data
;
1464 /* RS hardware binding table */
1467 uint32_t next_offset
;
1471 uint32_t state_offset
;
1472 uint32_t blend_state_offset
;
1473 uint32_t depth_stencil_state_offset
;
1478 struct brw_query_object
*obj
;
1483 enum brw_predicate_state state
;
1488 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1489 const int *statistics_registers
;
1491 /** The number of active monitors using OA counters. */
1495 * A buffer object storing OA counter snapshots taken at the start and
1496 * end of each batch (creating "bookends" around the batch).
1498 drm_intel_bo
*bookend_bo
;
1500 /** The number of snapshots written to bookend_bo. */
1501 int bookend_snapshots
;
1504 * An array of monitors whose results haven't yet been assembled based on
1505 * the data in buffer objects.
1507 * These may be active, or have already ended. However, the results
1508 * have not been requested.
1510 struct brw_perf_monitor_object
**unresolved
;
1511 int unresolved_elements
;
1512 int unresolved_array_size
;
1515 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1516 * the counter which MI_REPORT_PERF_COUNT stores there.
1518 const int *oa_snapshot_layout
;
1520 /** Number of 32-bit entries in a hardware counter snapshot. */
1521 int entries_per_oa_snapshot
;
1524 int num_atoms
[BRW_NUM_PIPELINES
];
1525 const struct brw_tracked_state render_atoms
[60];
1526 const struct brw_tracked_state compute_atoms
[8];
1528 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1532 enum aub_state_struct_type type
;
1534 } *state_batch_list
;
1535 int state_batch_count
;
1537 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1538 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1540 /* Interpolation modes, one byte per vue slot.
1541 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1543 struct interpolation_mode_map interpolation_mode
;
1545 /* PrimitiveRestart */
1548 bool enable_cut_index
;
1551 /** Computed depth/stencil/hiz state from the current attached
1552 * renderbuffers, valid only during the drawing state upload loop after
1553 * brw_workaround_depthstencil_alignment().
1556 struct intel_mipmap_tree
*depth_mt
;
1557 struct intel_mipmap_tree
*stencil_mt
;
1559 /* Inter-tile (page-aligned) byte offsets. */
1560 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1561 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1562 uint32_t tile_x
, tile_y
;
1565 uint32_t num_instances
;
1572 enum shader_time_shader_type
*types
;
1573 struct shader_times
*cumulative
;
1579 struct brw_fast_clear_state
*fast_clear_state
;
1581 __DRIcontext
*driContext
;
1582 struct intel_screen
*intelScreen
;
1585 /*======================================================================
1588 void brwInitVtbl( struct brw_context
*brw
);
1591 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1593 /*======================================================================
1596 extern const char *const brw_vendor_string
;
1598 extern const char *brw_get_renderer_string(unsigned deviceID
);
1601 DRI_CONF_BO_REUSE_DISABLED
,
1602 DRI_CONF_BO_REUSE_ALL
1605 void intel_update_renderbuffers(__DRIcontext
*context
,
1606 __DRIdrawable
*drawable
);
1607 void intel_prepare_render(struct brw_context
*brw
);
1609 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1610 __DRIdrawable
*drawable
);
1612 GLboolean
brwCreateContext(gl_api api
,
1613 const struct gl_config
*mesaVis
,
1614 __DRIcontext
*driContextPriv
,
1615 unsigned major_version
,
1616 unsigned minor_version
,
1620 void *sharedContextPrivate
);
1622 /*======================================================================
1625 GLuint
brw_get_rb_for_slice(struct brw_context
*brw
,
1626 struct intel_mipmap_tree
*mt
,
1627 unsigned level
, unsigned layer
, bool flat
);
1629 void brw_meta_updownsample(struct brw_context
*brw
,
1630 struct intel_mipmap_tree
*src
,
1631 struct intel_mipmap_tree
*dst
);
1633 void brw_meta_fbo_stencil_blit(struct brw_context
*brw
,
1634 struct gl_framebuffer
*read_fb
,
1635 struct gl_framebuffer
*draw_fb
,
1636 GLfloat srcX0
, GLfloat srcY0
,
1637 GLfloat srcX1
, GLfloat srcY1
,
1638 GLfloat dstX0
, GLfloat dstY0
,
1639 GLfloat dstX1
, GLfloat dstY1
);
1641 void brw_meta_stencil_updownsample(struct brw_context
*brw
,
1642 struct intel_mipmap_tree
*src
,
1643 struct intel_mipmap_tree
*dst
);
1645 bool brw_meta_fast_clear(struct brw_context
*brw
,
1646 struct gl_framebuffer
*fb
,
1648 bool partial_clear
);
1651 brw_meta_resolve_color(struct brw_context
*brw
,
1652 struct intel_mipmap_tree
*mt
);
1654 brw_meta_fast_clear_free(struct brw_context
*brw
);
1657 /*======================================================================
1660 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1661 uint32_t depth_level
,
1662 uint32_t depth_layer
,
1663 struct intel_mipmap_tree
*stencil_mt
,
1664 uint32_t *out_tile_mask_x
,
1665 uint32_t *out_tile_mask_y
);
1666 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1667 GLbitfield clear_mask
);
1669 /* brw_object_purgeable.c */
1670 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1672 /*======================================================================
1675 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1676 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1677 void brw_emit_query_begin(struct brw_context
*brw
);
1678 void brw_emit_query_end(struct brw_context
*brw
);
1680 /** gen6_queryobj.c */
1681 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1682 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1683 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1684 void brw_store_register_mem64(struct brw_context
*brw
,
1685 drm_intel_bo
*bo
, uint32_t reg
, int idx
);
1687 /** brw_conditional_render.c */
1688 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1689 bool brw_check_conditional_render(struct brw_context
*brw
);
1691 /** intel_batchbuffer.c */
1692 void brw_load_register_mem(struct brw_context
*brw
,
1695 uint32_t read_domains
, uint32_t write_domain
,
1697 void brw_load_register_mem64(struct brw_context
*brw
,
1700 uint32_t read_domains
, uint32_t write_domain
,
1703 /*======================================================================
1706 void brw_debug_batch(struct brw_context
*brw
);
1707 void brw_annotate_aub(struct brw_context
*brw
);
1709 /*======================================================================
1712 void brw_validate_textures( struct brw_context
*brw
);
1715 /*======================================================================
1718 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1720 int brw_get_scratch_size(int size
);
1721 void brw_get_scratch_bo(struct brw_context
*brw
,
1722 drm_intel_bo
**scratch_bo
, int size
);
1723 void brw_init_shader_time(struct brw_context
*brw
);
1724 int brw_get_shader_time_index(struct brw_context
*brw
,
1725 struct gl_shader_program
*shader_prog
,
1726 struct gl_program
*prog
,
1727 enum shader_time_shader_type type
);
1728 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1729 void brw_destroy_shader_time(struct brw_context
*brw
);
1733 void brw_upload_urb_fence(struct brw_context
*brw
);
1737 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1739 /* brw_fs_reg_allocate.cpp
1741 void brw_fs_alloc_reg_sets(struct brw_compiler
*compiler
);
1743 /* brw_vec4_reg_allocate.cpp */
1744 void brw_vec4_alloc_reg_set(struct brw_compiler
*compiler
);
1747 int brw_disassemble_inst(FILE *file
, const struct brw_device_info
*devinfo
,
1748 struct brw_inst
*inst
, bool is_compacted
);
1751 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1753 /* brw_draw_upload.c */
1754 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1755 const struct gl_client_array
*glarray
);
1757 static inline unsigned
1758 brw_get_index_type(GLenum type
)
1760 assert((type
== GL_UNSIGNED_BYTE
)
1761 || (type
== GL_UNSIGNED_SHORT
)
1762 || (type
== GL_UNSIGNED_INT
));
1764 /* The possible values for type are GL_UNSIGNED_BYTE (0x1401),
1765 * GL_UNSIGNED_SHORT (0x1403), and GL_UNSIGNED_INT (0x1405) which we want
1766 * to map to scale factors of 0, 1, and 2, respectively. These scale
1767 * factors are then left-shfited by 8 to be in the correct position in the
1768 * CMD_INDEX_BUFFER packet.
1770 * Subtracting 0x1401 gives 0, 2, and 4. Shifting left by 7 afterwards
1771 * gives 0x00000000, 0x00000100, and 0x00000200. These just happen to be
1772 * the values the need to be written in the CMD_INDEX_BUFFER packet.
1774 return (type
- 0x1401) << 7;
1777 void brw_prepare_vertices(struct brw_context
*brw
);
1779 /* brw_wm_surface_state.c */
1780 void brw_init_surface_formats(struct brw_context
*brw
);
1781 void brw_create_constant_surface(struct brw_context
*brw
,
1785 uint32_t *out_offset
,
1787 void brw_create_buffer_surface(struct brw_context
*brw
,
1791 uint32_t *out_offset
,
1793 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1795 uint32_t *surf_offset
);
1797 brw_update_sol_surface(struct brw_context
*brw
,
1798 struct gl_buffer_object
*buffer_obj
,
1799 uint32_t *out_offset
, unsigned num_vector_components
,
1800 unsigned stride_dwords
, unsigned offset_dwords
);
1801 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1802 struct gl_shader
*shader
,
1803 struct brw_stage_state
*stage_state
,
1804 struct brw_stage_prog_data
*prog_data
,
1806 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1807 struct gl_shader_program
*prog
,
1808 struct brw_stage_state
*stage_state
,
1809 struct brw_stage_prog_data
*prog_data
);
1810 void brw_upload_image_surfaces(struct brw_context
*brw
,
1811 struct gl_shader
*shader
,
1812 struct brw_stage_state
*stage_state
,
1813 struct brw_stage_prog_data
*prog_data
);
1815 /* brw_surface_formats.c */
1816 bool brw_render_target_supported(struct brw_context
*brw
,
1817 struct gl_renderbuffer
*rb
);
1818 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1819 mesa_format
brw_lower_mesa_image_format(const struct brw_device_info
*devinfo
,
1820 mesa_format format
);
1822 /* brw_performance_monitor.c */
1823 void brw_init_performance_monitors(struct brw_context
*brw
);
1824 void brw_dump_perf_monitors(struct brw_context
*brw
);
1825 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1826 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1828 /* intel_buffer_objects.c */
1829 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1830 const char *bo_name
);
1831 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1832 const char *bo_name
);
1834 /* intel_extensions.c */
1835 extern void intelInitExtensions(struct gl_context
*ctx
);
1838 extern int intel_translate_shadow_compare_func(GLenum func
);
1839 extern int intel_translate_compare_func(GLenum func
);
1840 extern int intel_translate_stencil_op(GLenum op
);
1841 extern int intel_translate_logic_op(GLenum opcode
);
1843 /* intel_syncobj.c */
1844 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1847 struct gl_transform_feedback_object
*
1848 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1850 brw_delete_transform_feedback(struct gl_context
*ctx
,
1851 struct gl_transform_feedback_object
*obj
);
1853 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1854 struct gl_transform_feedback_object
*obj
);
1856 brw_end_transform_feedback(struct gl_context
*ctx
,
1857 struct gl_transform_feedback_object
*obj
);
1859 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1860 struct gl_transform_feedback_object
*obj
,
1863 /* gen7_sol_state.c */
1865 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1866 struct gl_transform_feedback_object
*obj
);
1868 gen7_end_transform_feedback(struct gl_context
*ctx
,
1869 struct gl_transform_feedback_object
*obj
);
1871 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1872 struct gl_transform_feedback_object
*obj
);
1874 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1875 struct gl_transform_feedback_object
*obj
);
1877 /* brw_blorp_blit.cpp */
1879 brw_blorp_framebuffer(struct brw_context
*brw
,
1880 struct gl_framebuffer
*readFb
,
1881 struct gl_framebuffer
*drawFb
,
1882 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1883 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1884 GLbitfield mask
, GLenum filter
);
1887 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1888 struct gl_renderbuffer
*src_rb
,
1889 struct gl_texture_image
*dst_image
,
1891 int srcX0
, int srcY0
,
1892 int dstX0
, int dstY0
,
1893 int width
, int height
);
1895 /* gen6_multisample_state.c */
1897 gen6_determine_sample_mask(struct brw_context
*brw
);
1900 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1901 unsigned num_samples
);
1903 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1905 gen6_get_sample_position(struct gl_context
*ctx
,
1906 struct gl_framebuffer
*fb
,
1910 gen6_set_sample_maps(struct gl_context
*ctx
);
1912 /* gen8_multisample_state.c */
1913 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1914 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1918 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1919 unsigned gs_size
, unsigned fs_size
);
1922 gen7_emit_urb_state(struct brw_context
*brw
,
1923 unsigned nr_vs_entries
, unsigned vs_size
,
1924 unsigned vs_start
, unsigned nr_gs_entries
,
1925 unsigned gs_size
, unsigned gs_start
);
1930 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1934 brw_init_compute_functions(struct dd_function_table
*functions
);
1936 /*======================================================================
1937 * Inline conversion functions. These are better-typed than the
1938 * macros used previously:
1940 static inline struct brw_context
*
1941 brw_context( struct gl_context
*ctx
)
1943 return (struct brw_context
*)ctx
;
1946 static inline struct brw_vertex_program
*
1947 brw_vertex_program(struct gl_vertex_program
*p
)
1949 return (struct brw_vertex_program
*) p
;
1952 static inline const struct brw_vertex_program
*
1953 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1955 return (const struct brw_vertex_program
*) p
;
1958 static inline struct brw_geometry_program
*
1959 brw_geometry_program(struct gl_geometry_program
*p
)
1961 return (struct brw_geometry_program
*) p
;
1964 static inline struct brw_fragment_program
*
1965 brw_fragment_program(struct gl_fragment_program
*p
)
1967 return (struct brw_fragment_program
*) p
;
1970 static inline const struct brw_fragment_program
*
1971 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1973 return (const struct brw_fragment_program
*) p
;
1976 static inline struct brw_compute_program
*
1977 brw_compute_program(struct gl_compute_program
*p
)
1979 return (struct brw_compute_program
*) p
;
1983 * Pre-gen6, the register file of the EUs was shared between threads,
1984 * and each thread used some subset allocated on a 16-register block
1985 * granularity. The unit states wanted these block counts.
1988 brw_register_blocks(int reg_count
)
1990 return ALIGN(reg_count
, 16) / 16 - 1;
1993 static inline uint32_t
1994 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1995 uint32_t prog_offset
)
1997 if (brw
->gen
>= 5) {
1998 /* Using state base address. */
2002 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
2006 I915_GEM_DOMAIN_INSTRUCTION
, 0);
2008 return brw
->cache
.bo
->offset64
+ prog_offset
;
2011 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
2012 bool brw_lower_texture_gradients(struct brw_context
*brw
,
2013 struct exec_list
*instructions
);
2014 bool brw_do_lower_unnormalized_offset(struct exec_list
*instructions
);
2016 struct opcode_desc
{
2022 extern const struct opcode_desc opcode_descs
[128];
2023 extern const char * const conditional_modifier
[16];
2026 brw_emit_depthbuffer(struct brw_context
*brw
);
2029 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
2030 struct intel_mipmap_tree
*depth_mt
,
2031 uint32_t depth_offset
, uint32_t depthbuffer_format
,
2032 uint32_t depth_surface_type
,
2033 struct intel_mipmap_tree
*stencil_mt
,
2034 bool hiz
, bool separate_stencil
,
2035 uint32_t width
, uint32_t height
,
2036 uint32_t tile_x
, uint32_t tile_y
);
2039 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
2040 struct intel_mipmap_tree
*depth_mt
,
2041 uint32_t depth_offset
, uint32_t depthbuffer_format
,
2042 uint32_t depth_surface_type
,
2043 struct intel_mipmap_tree
*stencil_mt
,
2044 bool hiz
, bool separate_stencil
,
2045 uint32_t width
, uint32_t height
,
2046 uint32_t tile_x
, uint32_t tile_y
);
2049 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
2050 struct intel_mipmap_tree
*depth_mt
,
2051 uint32_t depth_offset
, uint32_t depthbuffer_format
,
2052 uint32_t depth_surface_type
,
2053 struct intel_mipmap_tree
*stencil_mt
,
2054 bool hiz
, bool separate_stencil
,
2055 uint32_t width
, uint32_t height
,
2056 uint32_t tile_x
, uint32_t tile_y
);
2058 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
2059 struct intel_mipmap_tree
*depth_mt
,
2060 uint32_t depth_offset
, uint32_t depthbuffer_format
,
2061 uint32_t depth_surface_type
,
2062 struct intel_mipmap_tree
*stencil_mt
,
2063 bool hiz
, bool separate_stencil
,
2064 uint32_t width
, uint32_t height
,
2065 uint32_t tile_x
, uint32_t tile_y
);
2067 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
2068 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);
2070 uint32_t get_hw_prim_for_gl_prim(int mode
);
2073 gen6_upload_push_constants(struct brw_context
*brw
,
2074 const struct gl_program
*prog
,
2075 const struct brw_stage_prog_data
*prog_data
,
2076 struct brw_stage_state
*stage_state
,
2077 enum aub_state_struct_type type
);
2080 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
2081 const struct intel_mipmap_tree
*mt
);
2083 /* brw_pipe_control.c */
2084 int brw_init_pipe_control(struct brw_context
*brw
,
2085 const struct brw_device_info
*info
);
2086 void brw_fini_pipe_control(struct brw_context
*brw
);
2088 void brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
);
2089 void brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
2090 drm_intel_bo
*bo
, uint32_t offset
,
2091 uint32_t imm_lower
, uint32_t imm_upper
);
2092 void brw_emit_mi_flush(struct brw_context
*brw
);
2093 void brw_emit_post_sync_nonzero_flush(struct brw_context
*brw
);
2094 void brw_emit_depth_stall_flushes(struct brw_context
*brw
);
2095 void gen7_emit_vs_workaround_flush(struct brw_context
*brw
);
2096 void gen7_emit_cs_stall_flush(struct brw_context
*brw
);