2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
38 #include "main/imports.h"
39 #include "main/macros.h"
41 #include "main/mtypes.h"
42 #include "brw_structs.h"
46 /* Evil hack for using libdrm in a c++ compiler. */
51 #include <intel_bufmgr.h>
61 #include "intel_debug.h"
62 #include "intel_screen.h"
63 #include "intel_tex_obj.h"
67 * URB - uniform resource buffer. A mid-sized buffer which is
68 * partitioned between the fixed function units and used for passing
69 * values (vertices, primitives, constants) between them.
71 * CURBE - constant URB entry. An urb region (entry) used to hold
72 * constant values which the fixed function units can be instructed to
73 * preload into the GRF when spawning a thread.
75 * VUE - vertex URB entry. An urb entry holding a vertex and usually
76 * a vertex header. The header contains control information and
77 * things like primitive type, Begin/end flags and clip codes.
79 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
80 * unit holding rasterization and interpolation parameters.
82 * GRF - general register file. One of several register files
83 * addressable by programmed threads. The inputs (r0, payload, curbe,
84 * urb) of the thread are preloaded to this area before the thread is
85 * spawned. The registers are individually 8 dwords wide and suitable
86 * for general usage. Registers holding thread input values are not
87 * special and may be overwritten.
89 * MRF - message register file. Threads communicate (and terminate)
90 * by sending messages. Message parameters are placed in contiguous
91 * MRF registers. All program output is via these messages. URB
92 * entries are populated by sending a message to the shared URB
93 * function containing the new data, together with a control word,
94 * often an unmodified copy of R0.
96 * R0 - GRF register 0. Typically holds control information used when
97 * sending messages to other threads.
99 * EU or GEN4 EU: The name of the programmable subsystem of the
100 * i965 hardware. Threads are executed by the EU, the registers
101 * described above are part of the EU architecture.
103 * Fixed function units:
105 * CS - Command streamer. Notional first unit, little software
106 * interaction. Holds the URB entries used for constant data, ie the
109 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
110 * this unit is responsible for pulling vertices out of vertex buffers
111 * in vram and injecting them into the processing pipe as VUEs. If
112 * enabled, it first passes them to a VS thread which is a good place
113 * for the driver to implement any active vertex shader.
115 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
116 * enabled, incoming strips etc are passed to GS threads in individual
117 * line/triangle/point units. The GS thread may perform arbitary
118 * computation and emit whatever primtives with whatever vertices it
119 * chooses. This makes GS an excellent place to implement GL's
120 * unfilled polygon modes, though of course it is capable of much
121 * more. Additionally, GS is used to translate away primitives not
122 * handled by latter units, including Quads and Lineloops.
124 * CS - Clipper. Mesa's clipping algorithms are imported to run on
125 * this unit. The fixed function part performs cliptesting against
126 * the 6 fixed clipplanes and makes descisions on whether or not the
127 * incoming primitive needs to be passed to a thread for clipping.
128 * User clip planes are handled via cooperation with the VS thread.
130 * SF - Strips Fans or Setup: Triangles are prepared for
131 * rasterization. Interpolation coefficients are calculated.
132 * Flatshading and two-side lighting usually performed here.
134 * WM - Windower. Interpolation of vertex attributes performed here.
135 * Fragment shader implemented here. SIMD aspects of EU taken full
136 * advantage of, as pixels are processed in blocks of 16.
138 * CC - Color Calculator. No EU threads associated with this unit.
139 * Handles blending and (presumably) depth and stencil testing.
142 #define INTEL_WRITE_PART 0x1
143 #define INTEL_WRITE_FULL 0x2
144 #define INTEL_READ 0x4
146 #define BRW_MAX_CURBE (32*16)
149 struct brw_instruction
;
150 struct brw_vs_prog_key
;
151 struct brw_vec4_prog_key
;
152 struct brw_wm_prog_key
;
153 struct brw_wm_prog_data
;
154 struct brw_perf_bo_layout
;
158 BRW_STATE_FRAGMENT_PROGRAM
,
159 BRW_STATE_GEOMETRY_PROGRAM
,
160 BRW_STATE_VERTEX_PROGRAM
,
161 BRW_STATE_CURBE_OFFSETS
,
162 BRW_STATE_REDUCED_PRIMITIVE
,
167 BRW_STATE_VS_BINDING_TABLE
,
168 BRW_STATE_GS_BINDING_TABLE
,
169 BRW_STATE_PS_BINDING_TABLE
,
173 BRW_STATE_INDEX_BUFFER
,
174 BRW_STATE_VS_CONSTBUF
,
175 BRW_STATE_GS_CONSTBUF
,
176 BRW_STATE_PROGRAM_CACHE
,
177 BRW_STATE_STATE_BASE_ADDRESS
,
178 BRW_STATE_VUE_MAP_VS
,
179 BRW_STATE_VUE_MAP_GEOM_OUT
,
180 BRW_STATE_TRANSFORM_FEEDBACK
,
181 BRW_STATE_RASTERIZER_DISCARD
,
183 BRW_STATE_UNIFORM_BUFFER
,
184 BRW_STATE_META_IN_PROGRESS
,
185 BRW_STATE_INTERPOLATION_MAP
,
186 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
190 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
191 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
192 #define BRW_NEW_GEOMETRY_PROGRAM (1 << BRW_STATE_GEOMETRY_PROGRAM)
193 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
194 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
195 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
196 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
197 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
198 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
199 #define BRW_NEW_SURFACES (1 << BRW_STATE_SURFACES)
200 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
201 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
202 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
203 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
204 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
206 * Used for any batch entry with a relocated pointer that will be used
207 * by any 3D rendering.
209 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
210 /** \see brw.state.depth_region */
211 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
212 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
213 #define BRW_NEW_GS_CONSTBUF (1 << BRW_STATE_GS_CONSTBUF)
214 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
215 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
216 #define BRW_NEW_VUE_MAP_VS (1 << BRW_STATE_VUE_MAP_VS)
217 #define BRW_NEW_VUE_MAP_GEOM_OUT (1 << BRW_STATE_VUE_MAP_GEOM_OUT)
218 #define BRW_NEW_TRANSFORM_FEEDBACK (1 << BRW_STATE_TRANSFORM_FEEDBACK)
219 #define BRW_NEW_RASTERIZER_DISCARD (1 << BRW_STATE_RASTERIZER_DISCARD)
220 #define BRW_NEW_STATS_WM (1 << BRW_STATE_STATS_WM)
221 #define BRW_NEW_UNIFORM_BUFFER (1 << BRW_STATE_UNIFORM_BUFFER)
222 #define BRW_NEW_META_IN_PROGRESS (1 << BRW_STATE_META_IN_PROGRESS)
223 #define BRW_NEW_INTERPOLATION_MAP (1 << BRW_STATE_INTERPOLATION_MAP)
224 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1 << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
226 struct brw_state_flags
{
227 /** State update flags signalled by mesa internals */
230 * State update flags signalled as the result of brw_tracked_state updates
233 /** State update flags signalled by brw_state_cache.c searches */
237 #define AUB_TRACE_TYPE_MASK 0x0000ff00
238 #define AUB_TRACE_TYPE_NOTYPE (0 << 8)
239 #define AUB_TRACE_TYPE_BATCH (1 << 8)
240 #define AUB_TRACE_TYPE_VERTEX_BUFFER (5 << 8)
241 #define AUB_TRACE_TYPE_2D_MAP (6 << 8)
242 #define AUB_TRACE_TYPE_CUBE_MAP (7 << 8)
243 #define AUB_TRACE_TYPE_VOLUME_MAP (9 << 8)
244 #define AUB_TRACE_TYPE_1D_MAP (10 << 8)
245 #define AUB_TRACE_TYPE_CONSTANT_BUFFER (11 << 8)
246 #define AUB_TRACE_TYPE_CONSTANT_URB (12 << 8)
247 #define AUB_TRACE_TYPE_INDEX_BUFFER (13 << 8)
248 #define AUB_TRACE_TYPE_GENERAL (14 << 8)
249 #define AUB_TRACE_TYPE_SURFACE (15 << 8)
252 * state_struct_type enum values are encoded with the top 16 bits representing
253 * the type to be delivered to the .aub file, and the bottom 16 bits
254 * representing the subtype. This macro performs the encoding.
256 #define ENCODE_SS_TYPE(type, subtype) (((type) << 16) | (subtype))
258 enum state_struct_type
{
259 AUB_TRACE_VS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 1),
260 AUB_TRACE_GS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 2),
261 AUB_TRACE_CLIP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 3),
262 AUB_TRACE_SF_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 4),
263 AUB_TRACE_WM_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 5),
264 AUB_TRACE_CC_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 6),
265 AUB_TRACE_CLIP_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 7),
266 AUB_TRACE_SF_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 8),
267 AUB_TRACE_CC_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x9),
268 AUB_TRACE_SAMPLER_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xa),
269 AUB_TRACE_KERNEL_INSTRUCTIONS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xb),
270 AUB_TRACE_SCRATCH_SPACE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xc),
271 AUB_TRACE_SAMPLER_DEFAULT_COLOR
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xd),
273 AUB_TRACE_SCISSOR_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x15),
274 AUB_TRACE_BLEND_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x16),
275 AUB_TRACE_DEPTH_STENCIL_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x17),
277 AUB_TRACE_VERTEX_BUFFER
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_VERTEX_BUFFER
, 0),
278 AUB_TRACE_BINDING_TABLE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x100),
279 AUB_TRACE_SURFACE_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x200),
280 AUB_TRACE_VS_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 0),
281 AUB_TRACE_WM_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 1),
285 * Decode a state_struct_type value to determine the type that should be
286 * stored in the .aub file.
288 static inline uint32_t AUB_TRACE_TYPE(enum state_struct_type ss_type
)
290 return (ss_type
& 0xFFFF0000) >> 16;
294 * Decode a state_struct_type value to determine the subtype that should be
295 * stored in the .aub file.
297 static inline uint32_t AUB_TRACE_SUBTYPE(enum state_struct_type ss_type
)
299 return ss_type
& 0xFFFF;
302 /** Subclass of Mesa vertex program */
303 struct brw_vertex_program
{
304 struct gl_vertex_program program
;
309 /** Subclass of Mesa geometry program */
310 struct brw_geometry_program
{
311 struct gl_geometry_program program
;
312 unsigned id
; /**< serial no. to identify geom progs, never re-used */
316 /** Subclass of Mesa fragment program */
317 struct brw_fragment_program
{
318 struct gl_fragment_program program
;
319 GLuint id
; /**< serial no. to identify frag progs, never re-used */
323 struct gl_shader base
;
327 /** Shader IR transformed for native compile, at link time. */
328 struct exec_list
*ir
;
331 /* Data about a particular attempt to compile a program. Note that
332 * there can be many of these, each in a different GL state
333 * corresponding to a different brw_wm_prog_key struct, with different
336 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
339 struct brw_wm_prog_data
{
340 GLuint curb_read_length
;
341 GLuint num_varying_inputs
;
343 GLuint first_curbe_grf
;
344 GLuint first_curbe_grf_16
;
346 GLuint reg_blocks_16
;
347 GLuint total_scratch
;
349 unsigned binding_table_size
;
351 GLuint nr_params
; /**< number of float params/constants */
352 GLuint nr_pull_params
;
355 uint32_t prog_offset_16
;
358 * Mask of which interpolation modes are required by the fragment shader.
359 * Used in hardware setup on gen6+.
361 uint32_t barycentric_interp_modes
;
364 * Map from gl_varying_slot to the position within the FS setup data
365 * payload where the varying's attribute vertex deltas should be delivered.
366 * For varying slots that are not used by the FS, the value is -1.
368 int urb_setup
[VARYING_SLOT_MAX
];
370 /* Pointers to tracked values (only valid once
371 * _mesa_load_state_parameters has been called at runtime).
373 * These must be the last fields of the struct (see
374 * brw_wm_prog_data_compare()).
377 const float **pull_param
;
381 * Enum representing the i965-specific vertex results that don't correspond
382 * exactly to any element of gl_varying_slot. The values of this enum are
383 * assigned such that they don't conflict with gl_varying_slot.
387 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
388 BRW_VARYING_SLOT_PAD
,
390 * Technically this is not a varying but just a placeholder that
391 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
392 * builtin variable to be compiled correctly. see compile_sf_prog() for
395 BRW_VARYING_SLOT_PNTC
,
396 BRW_VARYING_SLOT_COUNT
401 * Data structure recording the relationship between the gl_varying_slot enum
402 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
403 * single octaword within the VUE (128 bits).
405 * Note that each BRW register contains 256 bits (2 octawords), so when
406 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
407 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
408 * in a vertex shader), each register corresponds to a single VUE slot, since
409 * it contains data for two separate vertices.
413 * Bitfield representing all varying slots that are (a) stored in this VUE
414 * map, and (b) actually written by the shader. Does not include any of
415 * the additional varying slots defined in brw_varying_slot.
417 GLbitfield64 slots_valid
;
420 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
421 * not stored in a slot (because they are not written, or because
422 * additional processing is applied before storing them in the VUE), the
425 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
428 * Map from VUE slot to gl_varying_slot value. For slots that do not
429 * directly correspond to a gl_varying_slot, the value comes from
432 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
433 * simplifies code that uses the value stored in slot_to_varying to
434 * create a bit mask).
436 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
439 * Total number of VUE slots in use
445 * Convert a VUE slot number into a byte offset within the VUE.
447 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
453 * Convert a vertex output (brw_varying_slot) into a byte offset within the
456 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
459 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
462 void brw_compute_vue_map(struct brw_context
*brw
, struct brw_vue_map
*vue_map
,
463 GLbitfield64 slots_valid
);
467 * Bitmask indicating which fragment shader inputs represent varyings (and
468 * hence have to be delivered to the fragment shader by the SF/SBE stage).
470 #define BRW_FS_VARYING_INPUT_MASK \
471 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
472 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
476 * Mapping of VUE map slots to interpolation modes.
478 struct interpolation_mode_map
{
479 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
482 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
484 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
485 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
491 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
493 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
494 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
501 struct brw_sf_prog_data
{
502 GLuint urb_read_length
;
505 /* Each vertex may have upto 12 attributes, 4 components each,
506 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
509 * Actually we use 4 for each, so call it 12 rows.
511 GLuint urb_entry_size
;
516 * We always program SF to start reading at an offset of 1 (2 varying slots)
517 * from the start of the vertex URB entry. This causes it to skip:
518 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
519 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
521 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
524 struct brw_clip_prog_data
{
525 GLuint curb_read_length
; /* user planes? */
527 GLuint urb_read_length
;
531 struct brw_ff_gs_prog_data
{
532 GLuint urb_read_length
;
536 * Gen6 transform feedback: Amount by which the streaming vertex buffer
537 * indices should be incremented each time the GS is invoked.
539 unsigned svbi_postincrement_value
;
543 /* Note: brw_vec4_prog_data_compare() must be updated when adding fields to
546 struct brw_vec4_prog_data
{
547 struct brw_vue_map vue_map
;
550 * Register where the thread expects to find input data from the URB
551 * (typically uniforms, followed by per-vertex inputs).
553 unsigned dispatch_grf_start_reg
;
555 GLuint curb_read_length
;
556 GLuint urb_read_length
;
558 GLuint nr_params
; /**< number of float params/constants */
559 GLuint nr_pull_params
; /**< number of dwords referenced by pull_param[] */
560 GLuint total_scratch
;
562 /* Used for calculating urb partitions. In the VS, this is the size of the
563 * URB entry used for both input and output to the thread. In the GS, this
564 * is the size of the URB entry used for output.
566 GLuint urb_entry_size
;
568 unsigned binding_table_size
;
570 /* These pointers must appear last. See brw_vec4_prog_data_compare(). */
572 const float **pull_param
;
576 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
579 struct brw_vs_prog_data
{
580 struct brw_vec4_prog_data base
;
582 GLbitfield64 inputs_read
;
588 /* Note: brw_gs_prog_data_compare() must be updated when adding fields to
591 struct brw_gs_prog_data
593 struct brw_vec4_prog_data base
;
596 * Size of an output vertex, measured in HWORDS (32 bytes).
598 unsigned output_vertex_size_hwords
;
600 unsigned output_topology
;
603 * Size of the control data (cut bits or StreamID bits), in hwords (32
604 * bytes). 0 if there is no control data.
606 unsigned control_data_header_size_hwords
;
609 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
610 * if the control data is StreamID bits, or
611 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
612 * Ignored if control_data_header_size is 0.
614 unsigned control_data_format
;
616 bool include_primitive_id
;
619 /** Number of texture sampler units */
620 #define BRW_MAX_TEX_UNIT 16
622 /** Max number of render targets in a shader */
623 #define BRW_MAX_DRAW_BUFFERS 8
626 * Max number of binding table entries used for stream output.
628 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
629 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
631 * On Gen6, the size of transform feedback data is limited not by the number
632 * of components but by the number of binding table entries we set aside. We
633 * use one binding table entry for a float, one entry for a vector, and one
634 * entry per matrix column. Since the only way we can communicate our
635 * transform feedback capabilities to the client is via
636 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
637 * worst case, in which all the varyings are floats, so we use up one binding
638 * table entry per component. Therefore we need to set aside at least 64
639 * binding table entries for use by transform feedback.
641 * Note: since we don't currently pack varyings, it is currently impossible
642 * for the client to actually use up all of these binding table entries--if
643 * all of their varyings were floats, they would run out of varying slots and
644 * fail to link. But that's a bug, so it seems prudent to go ahead and
645 * allocate the number of binding table entries we will need once the bug is
648 #define BRW_MAX_SOL_BINDINGS 64
650 /** Maximum number of actual buffers used for stream output */
651 #define BRW_MAX_SOL_BUFFERS 4
654 * Helpers to create Surface Binding Table indexes for draw buffers,
655 * textures, and constant buffers.
657 * Shader threads access surfaces via numeric handles, rather than directly
658 * using pointers. The binding table maps these numeric handles to the
659 * address of the actual buffer.
661 * For example, a shader might ask to sample from "surface 7." In this case,
662 * bind[7] would contain a pointer to a texture.
664 * Currently, our WM binding tables are (arbitrarily) programmed as follows:
666 * +-------------------------------+
667 * | 0 | Draw buffer 0 |
670 * | 7 | Draw buffer 7 |
671 * |-----|-------------------------|
672 * | 8 | WM Pull Constant Buffer |
673 * |-----|-------------------------|
677 * | 24 | Texture 15 |
678 * |-----|-------------------------|
683 * |-----|-------------------------|
684 * | 37 | Shader time buffer |
685 * |-----|-------------------------|
686 * | 38 | Gather texture 0 |
689 * | 53 | Gather texture 15 |
690 * +-------------------------------+
692 * Our VS (and Gen7 GS) binding tables are programmed as follows:
694 * +-----+-------------------------+
695 * | 0 | Pull Constant Buffer |
696 * +-----+-------------------------+
700 * | 16 | Texture 15 |
701 * +-----+-------------------------+
706 * |-----|-------------------------|
707 * | 29 | Shader time buffer |
708 * |-----|-------------------------|
709 * | 30 | Gather texture 0 |
712 * | 45 | Gather texture 15 |
713 * +-------------------------------+
715 * Our (gen6) GS binding tables are programmed as follows:
717 * +-----+-------------------------+
718 * | 0 | SOL Binding 0 |
721 * | 63 | SOL Binding 63 |
722 * +-----+-------------------------+
724 #define SURF_INDEX_DRAW(d) (d)
725 #define SURF_INDEX_FRAG_CONST_BUFFER (BRW_MAX_DRAW_BUFFERS + 1)
726 #define SURF_INDEX_TEXTURE(t) (BRW_MAX_DRAW_BUFFERS + 2 + (t))
727 #define SURF_INDEX_WM_UBO(u) (SURF_INDEX_TEXTURE(BRW_MAX_TEX_UNIT) + u)
728 #define SURF_INDEX_WM_SHADER_TIME (SURF_INDEX_WM_UBO(12))
729 #define SURF_INDEX_GATHER_TEXTURE(t) (SURF_INDEX_WM_SHADER_TIME + 1 + (t))
730 /** Maximum size of the binding table. */
731 #define BRW_MAX_WM_SURFACES (SURF_INDEX_GATHER_TEXTURE(BRW_MAX_TEX_UNIT))
733 #define SURF_INDEX_VEC4_CONST_BUFFER (0)
734 #define SURF_INDEX_VEC4_TEXTURE(t) (SURF_INDEX_VEC4_CONST_BUFFER + 1 + (t))
735 #define SURF_INDEX_VEC4_UBO(u) (SURF_INDEX_VEC4_TEXTURE(BRW_MAX_TEX_UNIT) + u)
736 #define SURF_INDEX_VEC4_SHADER_TIME (SURF_INDEX_VEC4_UBO(12))
737 #define SURF_INDEX_VEC4_GATHER_TEXTURE(t) (SURF_INDEX_VEC4_SHADER_TIME + 1 + (t))
738 #define BRW_MAX_VEC4_SURFACES (SURF_INDEX_VEC4_GATHER_TEXTURE(BRW_MAX_TEX_UNIT))
740 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
741 #define BRW_MAX_GEN6_GS_SURFACES SURF_INDEX_GEN6_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
744 * Stride in bytes between shader_time entries.
746 * We separate entries by a cacheline to reduce traffic between EUs writing to
749 #define SHADER_TIME_STRIDE 64
756 BRW_BLORP_CONST_COLOR_PROG
,
761 BRW_SF_UNIT
, /* scissor state on gen6 */
774 struct brw_cache_item
{
776 * Effectively part of the key, cache_id identifies what kind of state
777 * buffer is involved, and also which brw->state.dirty.cache flag should
778 * be set when this cache item is chosen.
780 enum brw_cache_id cache_id
;
781 /** 32-bit hash of the key data */
783 GLuint key_size
; /* for variable-sized keys */
790 struct brw_cache_item
*next
;
794 typedef bool (*cache_aux_compare_func
)(const void *a
, const void *b
);
795 typedef void (*cache_aux_free_func
)(const void *aux
);
798 struct brw_context
*brw
;
800 struct brw_cache_item
**items
;
802 GLuint size
, n_items
;
804 uint32_t next_offset
;
808 * Optional functions used in determining whether the prog_data for a new
809 * cache item matches an existing cache item (in case there's relevant data
810 * outside of the prog_data). If NULL, a plain memcmp is done.
812 cache_aux_compare_func aux_compare
[BRW_MAX_CACHE
];
813 /** Optional functions for freeing other pointers attached to a prog_data. */
814 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
818 /* Considered adding a member to this struct to document which flags
819 * an update might raise so that ordering of the state atoms can be
820 * checked or derived at runtime. Dropped the idea in favor of having
821 * a debug mode where the state is monitored for flags which are
822 * raised that have already been tested against.
824 struct brw_tracked_state
{
825 struct brw_state_flags dirty
;
826 void (*emit
)( struct brw_context
*brw
);
829 enum shader_time_shader_type
{
842 /* Flags for brw->state.cache.
844 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
845 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
846 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
847 #define CACHE_NEW_BLORP_BLIT_PROG (1<<BRW_BLORP_BLIT_PROG)
848 #define CACHE_NEW_BLORP_CONST_COLOR_PROG (1<<BRW_BLORP_CONST_COLOR_PROG)
849 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
850 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
851 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
852 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
853 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
854 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
855 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
856 #define CACHE_NEW_FF_GS_UNIT (1<<BRW_FF_GS_UNIT)
857 #define CACHE_NEW_FF_GS_PROG (1<<BRW_FF_GS_PROG)
858 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
859 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
860 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
861 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
863 struct brw_cached_batch_item
{
864 struct header
*header
;
866 struct brw_cached_batch_item
*next
;
869 struct brw_vertex_buffer
{
870 /** Buffer object containing the uploaded vertex data */
873 /** Byte stride between elements in the uploaded array */
877 struct brw_vertex_element
{
878 const struct gl_client_array
*glarray
;
882 /** The corresponding Mesa vertex attribute */
883 gl_vert_attrib attrib
;
884 /** Offset of the first element within the buffer object */
888 struct brw_query_object
{
889 struct gl_query_object Base
;
891 /** Last query BO associated with this query. */
894 /** Last index in bo with query data for this object. */
898 struct intel_sync_object
{
899 struct gl_sync_object Base
;
901 /** Batch associated with this sync object */
905 struct intel_batchbuffer
{
906 /** Current batchbuffer being queued up. */
908 /** Last BO submitted to the hardware. Used for glFinish(). */
909 drm_intel_bo
*last_bo
;
910 /** BO for post-sync nonzero writes for gen6 workaround. */
911 drm_intel_bo
*workaround_bo
;
912 bool need_workaround_flush
;
914 struct cached_batch_item
*cached_items
;
916 uint16_t emit
, total
;
917 uint16_t used
, reserved_space
;
920 #define BATCH_SZ (8192*sizeof(uint32_t))
922 uint32_t state_batch_offset
;
924 bool needs_sol_reset
;
933 * Data shared between brw_context::vs and brw_context::gs
935 struct brw_stage_state
938 * Optional scratch buffer used to store spilled register values and
939 * variably-indexed GRF arrays.
941 drm_intel_bo
*scratch_bo
;
943 /** Pull constant buffer */
944 drm_intel_bo
*const_bo
;
946 /** Offset in the program cache to the program */
947 uint32_t prog_offset
;
949 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
950 uint32_t state_offset
;
952 uint32_t push_const_offset
; /* Offset in the batchbuffer */
953 int push_const_size
; /* in 256-bit register increments */
955 /* Binding table: pointers to SURFACE_STATE entries. */
956 uint32_t bind_bo_offset
;
957 uint32_t surf_offset
[BRW_MAX_WM_SURFACES
];
959 /** SAMPLER_STATE count and table offset */
960 uint32_t sampler_count
;
961 uint32_t sampler_offset
;
963 /** Offsets in the batch to sampler default colors (texture border color) */
964 uint32_t sdc_offset
[BRW_MAX_TEX_UNIT
];
969 * brw_context is derived from gl_context.
973 struct gl_context ctx
; /**< base class, must be first field */
977 void (*destroy
) (struct brw_context
* brw
);
978 void (*finish_batch
) (struct brw_context
* brw
);
979 void (*new_batch
) (struct brw_context
* brw
);
981 void (*update_texture_surface
)(struct gl_context
*ctx
,
983 uint32_t *surf_offset
,
985 void (*update_renderbuffer_surface
)(struct brw_context
*brw
,
986 struct gl_renderbuffer
*rb
,
989 void (*update_null_renderbuffer_surface
)(struct brw_context
*brw
,
991 void (*create_constant_surface
)(struct brw_context
*brw
,
995 uint32_t *out_offset
,
998 /** Upload a SAMPLER_STATE table. */
999 void (*upload_sampler_state_table
)(struct brw_context
*brw
,
1000 struct gl_program
*prog
,
1001 uint32_t sampler_count
,
1002 uint32_t *sst_offset
,
1003 uint32_t *sdc_offset
);
1006 * Send the appropriate state packets to configure depth, stencil, and
1007 * HiZ buffers (i965+ only)
1009 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
1010 struct intel_mipmap_tree
*depth_mt
,
1011 uint32_t depth_offset
,
1012 uint32_t depthbuffer_format
,
1013 uint32_t depth_surface_type
,
1014 struct intel_mipmap_tree
*stencil_mt
,
1015 bool hiz
, bool separate_stencil
,
1016 uint32_t width
, uint32_t height
,
1017 uint32_t tile_x
, uint32_t tile_y
);
1023 drm_intel_context
*hw_ctx
;
1025 struct intel_batchbuffer batch
;
1031 uint32_t buffer_len
;
1032 uint32_t buffer_offset
;
1037 * Set if rendering has occured to the drawable's front buffer.
1039 * This is used in the DRI2 case to detect that glFlush should also copy
1040 * the contents of the fake front buffer to the real front buffer.
1042 bool front_buffer_dirty
;
1045 * Track whether front-buffer rendering is currently enabled
1047 * A separate flag is used to track this in order to support MRT more
1050 bool is_front_buffer_rendering
;
1053 * Track whether front-buffer is the current read target.
1055 * This is closely associated with is_front_buffer_rendering, but may
1056 * be set separately. The DRI2 fake front buffer must be referenced
1059 bool is_front_buffer_reading
;
1061 /** Framerate throttling: @{ */
1062 drm_intel_bo
*first_post_swapbuffers_batch
;
1073 bool always_flush_batch
;
1074 bool always_flush_cache
;
1075 bool disable_throttling
;
1077 bool disable_derivative_optimization
;
1079 driOptionCache optionCache
;
1082 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
1084 GLenum reduced_primitive
;
1087 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
1088 * variable is set, this is the flag indicating to do expensive work that
1089 * might lead to a perf_debug() call.
1093 uint32_t max_gtt_map_object_size
;
1103 bool has_separate_stencil
;
1104 bool must_use_separate_stencil
;
1107 bool has_surface_tile_offset
;
1109 bool has_negative_rhw_bug
;
1113 * Some versions of Gen hardware don't do centroid interpolation correctly
1114 * on unlit pixels, causing incorrect values for derivatives near triangle
1115 * edges. Enabling this flag causes the fragment shader to use
1116 * non-centroid interpolation for unlit pixels, at the expense of two extra
1117 * fragment shader instructions.
1119 bool needs_unlit_centroid_workaround
;
1123 struct brw_state_flags dirty
;
1126 struct brw_cache cache
;
1127 struct brw_cached_batch_item
*cached_batch_items
;
1129 /* Whether a meta-operation is in progress. */
1130 bool meta_in_progress
;
1133 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
1134 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
1136 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
1140 /* Summary of size and varying of active arrays, so we can check
1141 * for changes to this state:
1143 unsigned int min_index
, max_index
;
1145 /* Offset from start of vertex buffer so we can avoid redefining
1146 * the same VB packed over and over again.
1148 unsigned int start_vertex_bias
;
1153 * Index buffer for this draw_prims call.
1155 * Updates are signaled by BRW_NEW_INDICES.
1157 const struct _mesa_index_buffer
*ib
;
1159 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
1163 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
1164 * avoid re-uploading the IB packet over and over if we're actually
1165 * referencing the same index buffer.
1167 unsigned int start_vertex_offset
;
1170 /* Active vertex program:
1172 const struct gl_vertex_program
*vertex_program
;
1173 const struct gl_geometry_program
*geometry_program
;
1174 const struct gl_fragment_program
*fragment_program
;
1176 /* hw-dependent 3DSTATE_VF_STATISTICS opcode */
1177 uint32_t CMD_VF_STATISTICS
;
1178 /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
1179 uint32_t CMD_PIPELINE_SELECT
;
1182 * Platform specific constants containing the maximum number of threads
1183 * for each pipeline stage.
1189 /* BRW_NEW_URB_ALLOCATIONS:
1192 GLuint vsize
; /* vertex size plus header in urb registers */
1193 GLuint csize
; /* constant buffer size in urb registers */
1194 GLuint sfsize
; /* setup data size in urb registers */
1198 GLuint min_vs_entries
; /* Minimum number of VS entries */
1199 GLuint max_vs_entries
; /* Maximum number of VS entries */
1200 GLuint max_gs_entries
; /* Maximum number of GS entries */
1202 GLuint nr_vs_entries
;
1203 GLuint nr_gs_entries
;
1204 GLuint nr_clip_entries
;
1205 GLuint nr_sf_entries
;
1206 GLuint nr_cs_entries
;
1213 GLuint size
; /* Hardware URB size, in KB. */
1215 /* gen6: True if the most recently sent _3DSTATE_URB message allocated
1216 * URB space for the GS.
1218 bool gen6_gs_previously_active
;
1222 /* BRW_NEW_CURBE_OFFSETS:
1225 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1226 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1233 drm_intel_bo
*curbe_bo
;
1234 /** Offset within curbe_bo of space for current curbe entry */
1235 GLuint curbe_offset
;
1236 /** Offset within curbe_bo of space for next curbe entry */
1237 GLuint curbe_next_offset
;
1240 * Copy of the last set of CURBEs uploaded. Frequently we'll end up
1241 * in brw_curbe.c with the same set of constant data to be uploaded,
1242 * so we'd rather not upload new constants in that case (it can cause
1243 * a pipeline bubble since only up to 4 can be pipelined at a time).
1247 * Allocation for where to calculate the next set of CURBEs.
1248 * It's a hot enough path that malloc/free of that data matters.
1255 * Layout of vertex data exiting the vertex shader.
1257 * BRW_NEW_VUE_MAP_VS is flagged when this VUE map changes.
1259 struct brw_vue_map vue_map_vs
;
1262 * Layout of vertex data exiting the geometry portion of the pipleine.
1263 * This comes from the geometry shader if one exists, otherwise from the
1266 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1268 struct brw_vue_map vue_map_geom_out
;
1271 * Data structures used by all vec4 program compiles (not specific to any
1272 * particular program).
1275 struct ra_regs
*regs
;
1278 * Array of the ra classes for the unaligned contiguous register
1284 * Mapping for register-allocated objects in *regs to the first
1285 * GRF for that object.
1287 uint8_t *ra_reg_to_grf
;
1291 struct brw_stage_state base
;
1292 struct brw_vs_prog_data
*prog_data
;
1296 struct brw_stage_state base
;
1297 struct brw_gs_prog_data
*prog_data
;
1301 struct brw_ff_gs_prog_data
*prog_data
;
1304 /** Offset in the program cache to the CLIP program pre-gen6 */
1305 uint32_t prog_offset
;
1306 uint32_t state_offset
;
1308 uint32_t bind_bo_offset
;
1309 uint32_t surf_offset
[BRW_MAX_GEN6_GS_SURFACES
];
1313 struct brw_clip_prog_data
*prog_data
;
1315 /** Offset in the program cache to the CLIP program pre-gen6 */
1316 uint32_t prog_offset
;
1318 /* Offset in the batch to the CLIP state on pre-gen6. */
1319 uint32_t state_offset
;
1321 /* As of gen6, this is the offset in the batch to the CLIP VP,
1329 struct brw_sf_prog_data
*prog_data
;
1331 /** Offset in the program cache to the CLIP program pre-gen6 */
1332 uint32_t prog_offset
;
1333 uint32_t state_offset
;
1338 struct brw_stage_state base
;
1339 struct brw_wm_prog_data
*prog_data
;
1344 * Buffer object used in place of multisampled null render targets on
1345 * Gen6. See brw_update_null_renderbuffer_surface().
1347 drm_intel_bo
*multisampled_null_render_target_bo
;
1350 struct ra_regs
*regs
;
1353 * Array of the ra classes for the unaligned contiguous register
1354 * block sizes used, indexed by register size.
1359 * Mapping for register-allocated objects in *regs to the first
1360 * GRF for that object.
1362 uint8_t *ra_reg_to_grf
;
1365 * ra class for the aligned pairs we use for PLN, which doesn't
1366 * appear in *classes.
1368 int aligned_pairs_class
;
1374 uint32_t state_offset
;
1375 uint32_t blend_state_offset
;
1376 uint32_t depth_stencil_state_offset
;
1381 struct brw_query_object
*obj
;
1386 /* A map describing which counters are stored at a particular 32-bit
1387 * offset in the buffer object.
1389 const struct brw_perf_bo_layout
*bo_layout
;
1391 /* Number of 32-bit entries in the buffer object. */
1396 const struct brw_tracked_state
**atoms
;
1398 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1402 enum state_struct_type type
;
1403 } *state_batch_list
;
1404 int state_batch_count
;
1406 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1407 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1409 /* Interpolation modes, one byte per vue slot.
1410 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1412 struct interpolation_mode_map interpolation_mode
;
1414 /* PrimitiveRestart */
1417 bool enable_cut_index
;
1420 /** Computed depth/stencil/hiz state from the current attached
1421 * renderbuffers, valid only during the drawing state upload loop after
1422 * brw_workaround_depthstencil_alignment().
1425 struct intel_mipmap_tree
*depth_mt
;
1426 struct intel_mipmap_tree
*stencil_mt
;
1428 /* Inter-tile (page-aligned) byte offsets. */
1429 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1430 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1431 uint32_t tile_x
, tile_y
;
1434 uint32_t num_instances
;
1439 struct gl_shader_program
**shader_programs
;
1440 struct gl_program
**programs
;
1441 enum shader_time_shader_type
*types
;
1442 uint64_t *cumulative
;
1448 __DRIcontext
*driContext
;
1449 struct intel_screen
*intelScreen
;
1450 void (*saved_viewport
)(struct gl_context
*ctx
,
1451 GLint x
, GLint y
, GLsizei width
, GLsizei height
);
1455 is_power_of_two(uint32_t value
)
1457 return (value
& (value
- 1)) == 0;
1460 /*======================================================================
1463 void brwInitVtbl( struct brw_context
*brw
);
1466 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1468 /*======================================================================
1471 extern void intelFinish(struct gl_context
* ctx
);
1474 DRI_CONF_BO_REUSE_DISABLED
,
1475 DRI_CONF_BO_REUSE_ALL
1478 void intel_update_renderbuffers(__DRIcontext
*context
,
1479 __DRIdrawable
*drawable
);
1480 void intel_prepare_render(struct brw_context
*brw
);
1482 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1483 __DRIdrawable
*drawable
);
1485 bool brwCreateContext(gl_api api
,
1486 const struct gl_config
*mesaVis
,
1487 __DRIcontext
*driContextPriv
,
1488 unsigned major_version
,
1489 unsigned minor_version
,
1492 void *sharedContextPrivate
);
1494 /*======================================================================
1497 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1498 uint32_t depth_level
,
1499 uint32_t depth_layer
,
1500 struct intel_mipmap_tree
*stencil_mt
,
1501 uint32_t *out_tile_mask_x
,
1502 uint32_t *out_tile_mask_y
);
1503 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1504 GLbitfield clear_mask
);
1506 /* brw_object_purgeable.c */
1507 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1509 /*======================================================================
1512 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1513 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1514 void brw_emit_query_begin(struct brw_context
*brw
);
1515 void brw_emit_query_end(struct brw_context
*brw
);
1517 /** gen6_queryobj.c */
1518 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1520 /*======================================================================
1523 void brw_debug_batch(struct brw_context
*brw
);
1524 void brw_annotate_aub(struct brw_context
*brw
);
1526 /*======================================================================
1529 void brw_validate_textures( struct brw_context
*brw
);
1532 /*======================================================================
1535 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1537 int brw_get_scratch_size(int size
);
1538 void brw_get_scratch_bo(struct brw_context
*brw
,
1539 drm_intel_bo
**scratch_bo
, int size
);
1540 void brw_init_shader_time(struct brw_context
*brw
);
1541 int brw_get_shader_time_index(struct brw_context
*brw
,
1542 struct gl_shader_program
*shader_prog
,
1543 struct gl_program
*prog
,
1544 enum shader_time_shader_type type
);
1545 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1546 void brw_destroy_shader_time(struct brw_context
*brw
);
1550 void brw_upload_urb_fence(struct brw_context
*brw
);
1554 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1556 /* brw_fs_reg_allocate.cpp
1558 void brw_fs_alloc_reg_sets(struct brw_context
*brw
);
1560 /* brw_vec4_reg_allocate.cpp */
1561 void brw_vec4_alloc_reg_set(struct brw_context
*brw
);
1564 int brw_disasm (FILE *file
, struct brw_instruction
*inst
, int gen
);
1567 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1569 /* brw_draw_upload.c */
1570 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1571 const struct gl_client_array
*glarray
);
1572 unsigned brw_get_index_type(GLenum type
);
1574 /* brw_wm_surface_state.c */
1575 void brw_init_surface_formats(struct brw_context
*brw
);
1577 brw_update_sol_surface(struct brw_context
*brw
,
1578 struct gl_buffer_object
*buffer_obj
,
1579 uint32_t *out_offset
, unsigned num_vector_components
,
1580 unsigned stride_dwords
, unsigned offset_dwords
);
1581 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1582 struct gl_shader
*shader
,
1583 uint32_t *surf_offsets
);
1585 /* brw_surface_formats.c */
1586 bool brw_is_hiz_depth_format(struct brw_context
*ctx
, gl_format format
);
1587 bool brw_render_target_supported(struct brw_context
*brw
,
1588 struct gl_renderbuffer
*rb
);
1590 /* brw_performance_monitor.c */
1591 void brw_init_performance_monitors(struct brw_context
*brw
);
1593 /* intel_extensions.c */
1594 extern void intelInitExtensions(struct gl_context
*ctx
);
1597 extern int intel_translate_shadow_compare_func(GLenum func
);
1598 extern int intel_translate_compare_func(GLenum func
);
1599 extern int intel_translate_stencil_op(GLenum op
);
1600 extern int intel_translate_logic_op(GLenum opcode
);
1602 /* intel_syncobj.c */
1603 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1607 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1608 struct gl_transform_feedback_object
*obj
);
1610 brw_end_transform_feedback(struct gl_context
*ctx
,
1611 struct gl_transform_feedback_object
*obj
);
1613 /* gen7_sol_state.c */
1615 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1616 struct gl_transform_feedback_object
*obj
);
1618 gen7_end_transform_feedback(struct gl_context
*ctx
,
1619 struct gl_transform_feedback_object
*obj
);
1621 /* brw_blorp_blit.cpp */
1623 brw_blorp_framebuffer(struct brw_context
*brw
,
1624 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1625 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1626 GLbitfield mask
, GLenum filter
);
1629 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1630 struct gl_renderbuffer
*src_rb
,
1631 struct gl_texture_image
*dst_image
,
1633 int srcX0
, int srcY0
,
1634 int dstX0
, int dstY0
,
1635 int width
, int height
);
1637 /* gen6_multisample_state.c */
1639 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1640 unsigned num_samples
);
1642 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
,
1643 unsigned num_samples
, float coverage
,
1644 bool coverage_invert
, unsigned sample_mask
);
1646 gen6_get_sample_position(struct gl_context
*ctx
,
1647 struct gl_framebuffer
*fb
,
1653 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1654 unsigned gs_size
, unsigned fs_size
);
1657 gen7_emit_urb_state(struct brw_context
*brw
,
1658 unsigned nr_vs_entries
, unsigned vs_size
,
1659 unsigned vs_start
, unsigned nr_gs_entries
,
1660 unsigned gs_size
, unsigned gs_start
);
1664 /*======================================================================
1665 * Inline conversion functions. These are better-typed than the
1666 * macros used previously:
1668 static INLINE
struct brw_context
*
1669 brw_context( struct gl_context
*ctx
)
1671 return (struct brw_context
*)ctx
;
1674 static INLINE
struct brw_vertex_program
*
1675 brw_vertex_program(struct gl_vertex_program
*p
)
1677 return (struct brw_vertex_program
*) p
;
1680 static INLINE
const struct brw_vertex_program
*
1681 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1683 return (const struct brw_vertex_program
*) p
;
1686 static INLINE
struct brw_fragment_program
*
1687 brw_fragment_program(struct gl_fragment_program
*p
)
1689 return (struct brw_fragment_program
*) p
;
1692 static INLINE
const struct brw_fragment_program
*
1693 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1695 return (const struct brw_fragment_program
*) p
;
1699 * Pre-gen6, the register file of the EUs was shared between threads,
1700 * and each thread used some subset allocated on a 16-register block
1701 * granularity. The unit states wanted these block counts.
1704 brw_register_blocks(int reg_count
)
1706 return ALIGN(reg_count
, 16) / 16 - 1;
1709 static inline uint32_t
1710 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1711 uint32_t prog_offset
)
1713 if (brw
->gen
>= 5) {
1714 /* Using state base address. */
1718 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1722 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1724 return brw
->cache
.bo
->offset
+ prog_offset
;
1727 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1728 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1729 struct exec_list
*instructions
);
1731 struct opcode_desc
{
1737 extern const struct opcode_desc opcode_descs
[128];
1740 brw_emit_depthbuffer(struct brw_context
*brw
);
1743 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1744 struct intel_mipmap_tree
*depth_mt
,
1745 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1746 uint32_t depth_surface_type
,
1747 struct intel_mipmap_tree
*stencil_mt
,
1748 bool hiz
, bool separate_stencil
,
1749 uint32_t width
, uint32_t height
,
1750 uint32_t tile_x
, uint32_t tile_y
);
1753 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1754 struct intel_mipmap_tree
*depth_mt
,
1755 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1756 uint32_t depth_surface_type
,
1757 struct intel_mipmap_tree
*stencil_mt
,
1758 bool hiz
, bool separate_stencil
,
1759 uint32_t width
, uint32_t height
,
1760 uint32_t tile_x
, uint32_t tile_y
);
1762 extern const GLuint prim_to_hw_prim
[GL_TRIANGLE_STRIP_ADJACENCY
+1];
1765 brw_setup_vec4_key_clip_info(struct brw_context
*brw
,
1766 struct brw_vec4_prog_key
*key
,
1767 bool program_uses_clip_distance
);
1770 gen6_upload_vec4_push_constants(struct brw_context
*brw
,
1771 const struct gl_program
*prog
,
1772 const struct brw_vec4_prog_data
*prog_data
,
1773 struct brw_stage_state
*stage_state
,
1774 enum state_struct_type type
);
1776 /* ================================================================
1777 * From linux kernel i386 header files, copes with odd sizes better
1778 * than COPY_DWORDS would:
1779 * XXX Put this in src/mesa/main/imports.h ???
1781 #if defined(i386) || defined(__i386__)
1782 static INLINE
void * __memcpy(void * to
, const void * from
, size_t n
)
1785 __asm__
__volatile__(
1790 "1:\ttestb $1,%b4\n\t"
1794 : "=&c" (d0
), "=&D" (d1
), "=&S" (d2
)
1795 :"0" (n
/4), "q" (n
),"1" ((long) to
),"2" ((long) from
)
1800 #define __memcpy(a,b,c) memcpy(a,b,c)