2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
37 #include "main/macros.h"
38 #include "main/mtypes.h"
39 #include "brw_structs.h"
40 #include "brw_compiler.h"
41 #include "intel_aub.h"
44 #include "blorp/blorp.h"
48 /* Evil hack for using libdrm in a c++ compiler. */
52 #include <intel_bufmgr.h>
61 #include "intel_debug.h"
62 #include "intel_screen.h"
63 #include "intel_tex_obj.h"
64 #include "intel_resolve_map.h"
68 * URB - uniform resource buffer. A mid-sized buffer which is
69 * partitioned between the fixed function units and used for passing
70 * values (vertices, primitives, constants) between them.
72 * CURBE - constant URB entry. An urb region (entry) used to hold
73 * constant values which the fixed function units can be instructed to
74 * preload into the GRF when spawning a thread.
76 * VUE - vertex URB entry. An urb entry holding a vertex and usually
77 * a vertex header. The header contains control information and
78 * things like primitive type, Begin/end flags and clip codes.
80 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
81 * unit holding rasterization and interpolation parameters.
83 * GRF - general register file. One of several register files
84 * addressable by programmed threads. The inputs (r0, payload, curbe,
85 * urb) of the thread are preloaded to this area before the thread is
86 * spawned. The registers are individually 8 dwords wide and suitable
87 * for general usage. Registers holding thread input values are not
88 * special and may be overwritten.
90 * MRF - message register file. Threads communicate (and terminate)
91 * by sending messages. Message parameters are placed in contiguous
92 * MRF registers. All program output is via these messages. URB
93 * entries are populated by sending a message to the shared URB
94 * function containing the new data, together with a control word,
95 * often an unmodified copy of R0.
97 * R0 - GRF register 0. Typically holds control information used when
98 * sending messages to other threads.
100 * EU or GEN4 EU: The name of the programmable subsystem of the
101 * i965 hardware. Threads are executed by the EU, the registers
102 * described above are part of the EU architecture.
104 * Fixed function units:
106 * CS - Command streamer. Notional first unit, little software
107 * interaction. Holds the URB entries used for constant data, ie the
110 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
111 * this unit is responsible for pulling vertices out of vertex buffers
112 * in vram and injecting them into the processing pipe as VUEs. If
113 * enabled, it first passes them to a VS thread which is a good place
114 * for the driver to implement any active vertex shader.
116 * HS - Hull Shader (Tessellation Control Shader)
118 * TE - Tessellation Engine (Tessellation Primitive Generation)
120 * DS - Domain Shader (Tessellation Evaluation Shader)
122 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
123 * enabled, incoming strips etc are passed to GS threads in individual
124 * line/triangle/point units. The GS thread may perform arbitary
125 * computation and emit whatever primtives with whatever vertices it
126 * chooses. This makes GS an excellent place to implement GL's
127 * unfilled polygon modes, though of course it is capable of much
128 * more. Additionally, GS is used to translate away primitives not
129 * handled by latter units, including Quads and Lineloops.
131 * CS - Clipper. Mesa's clipping algorithms are imported to run on
132 * this unit. The fixed function part performs cliptesting against
133 * the 6 fixed clipplanes and makes descisions on whether or not the
134 * incoming primitive needs to be passed to a thread for clipping.
135 * User clip planes are handled via cooperation with the VS thread.
137 * SF - Strips Fans or Setup: Triangles are prepared for
138 * rasterization. Interpolation coefficients are calculated.
139 * Flatshading and two-side lighting usually performed here.
141 * WM - Windower. Interpolation of vertex attributes performed here.
142 * Fragment shader implemented here. SIMD aspects of EU taken full
143 * advantage of, as pixels are processed in blocks of 16.
145 * CC - Color Calculator. No EU threads associated with this unit.
146 * Handles blending and (presumably) depth and stencil testing.
151 struct brw_vs_prog_key
;
152 struct brw_vue_prog_key
;
153 struct brw_wm_prog_key
;
154 struct brw_wm_prog_data
;
155 struct brw_cs_prog_key
;
156 struct brw_cs_prog_data
;
160 BRW_COMPUTE_PIPELINE
,
167 BRW_CACHE_BLORP_PROG
,
170 BRW_CACHE_FF_GS_PROG
,
181 /* brw_cache_ids must come first - see brw_program_cache.c */
182 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
183 BRW_STATE_FRAGMENT_PROGRAM
,
184 BRW_STATE_GEOMETRY_PROGRAM
,
185 BRW_STATE_TESS_PROGRAMS
,
186 BRW_STATE_VERTEX_PROGRAM
,
187 BRW_STATE_CURBE_OFFSETS
,
188 BRW_STATE_REDUCED_PRIMITIVE
,
189 BRW_STATE_PATCH_PRIMITIVE
,
194 BRW_STATE_BINDING_TABLE_POINTERS
,
197 BRW_STATE_DEFAULT_TESS_LEVELS
,
199 BRW_STATE_INDEX_BUFFER
,
200 BRW_STATE_VS_CONSTBUF
,
201 BRW_STATE_TCS_CONSTBUF
,
202 BRW_STATE_TES_CONSTBUF
,
203 BRW_STATE_GS_CONSTBUF
,
204 BRW_STATE_PROGRAM_CACHE
,
205 BRW_STATE_STATE_BASE_ADDRESS
,
206 BRW_STATE_VUE_MAP_GEOM_OUT
,
207 BRW_STATE_TRANSFORM_FEEDBACK
,
208 BRW_STATE_RASTERIZER_DISCARD
,
210 BRW_STATE_UNIFORM_BUFFER
,
211 BRW_STATE_ATOMIC_BUFFER
,
212 BRW_STATE_IMAGE_UNITS
,
213 BRW_STATE_META_IN_PROGRESS
,
214 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
215 BRW_STATE_NUM_SAMPLES
,
216 BRW_STATE_TEXTURE_BUFFER
,
217 BRW_STATE_GEN4_UNIT_STATE
,
221 BRW_STATE_SAMPLER_STATE_TABLE
,
222 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
223 BRW_STATE_COMPUTE_PROGRAM
,
224 BRW_STATE_CS_WORK_GROUPS
,
228 BRW_STATE_VIEWPORT_COUNT
,
229 BRW_STATE_CONSERVATIVE_RASTERIZATION
,
234 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
236 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
237 * When the currently bound shader program differs from the previous draw
238 * call, these will be flagged. They cover brw->{stage}_program and
239 * ctx->{Stage}Program->_Current.
241 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
242 * driver perspective. Even if the same shader is bound at the API level,
243 * we may need to switch between multiple versions of that shader to handle
244 * changes in non-orthagonal state.
246 * Additionally, multiple shader programs may have identical vertex shaders
247 * (for example), or compile down to the same code in the backend. We combine
248 * those into a single program cache entry.
250 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
251 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
253 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
254 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
255 * use the normal state upload paths), but the cache is still used. To avoid
256 * polluting the brw_program_cache code with special cases, we retain the
257 * dirty bit for now. It should eventually be removed.
259 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_PROG)
260 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
261 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
262 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
263 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
264 #define BRW_NEW_TCS_PROG_DATA (1ull << BRW_CACHE_TCS_PROG)
265 #define BRW_NEW_TES_PROG_DATA (1ull << BRW_CACHE_TES_PROG)
266 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
267 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
268 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
269 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
270 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
271 #define BRW_NEW_TESS_PROGRAMS (1ull << BRW_STATE_TESS_PROGRAMS)
272 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
273 #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
274 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
275 #define BRW_NEW_PATCH_PRIMITIVE (1ull << BRW_STATE_PATCH_PRIMITIVE)
276 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
277 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
278 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
279 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
280 #define BRW_NEW_BINDING_TABLE_POINTERS (1ull << BRW_STATE_BINDING_TABLE_POINTERS)
281 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
282 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
283 #define BRW_NEW_DEFAULT_TESS_LEVELS (1ull << BRW_STATE_DEFAULT_TESS_LEVELS)
285 * Used for any batch entry with a relocated pointer that will be used
286 * by any 3D rendering.
288 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
289 /** \see brw.state.depth_region */
290 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
291 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
292 #define BRW_NEW_TCS_CONSTBUF (1ull << BRW_STATE_TCS_CONSTBUF)
293 #define BRW_NEW_TES_CONSTBUF (1ull << BRW_STATE_TES_CONSTBUF)
294 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
295 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
296 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
297 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
298 #define BRW_NEW_VIEWPORT_COUNT (1ull << BRW_STATE_VIEWPORT_COUNT)
299 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
300 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
301 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
302 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
303 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
304 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
305 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
306 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
307 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
308 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
309 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
310 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
311 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
312 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
313 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
314 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
315 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
316 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
317 #define BRW_NEW_URB_SIZE (1ull << BRW_STATE_URB_SIZE)
318 #define BRW_NEW_CC_STATE (1ull << BRW_STATE_CC_STATE)
319 #define BRW_NEW_BLORP (1ull << BRW_STATE_BLORP)
320 #define BRW_NEW_CONSERVATIVE_RASTERIZATION (1ull << BRW_STATE_CONSERVATIVE_RASTERIZATION)
322 struct brw_state_flags
{
323 /** State update flags signalled by mesa internals */
326 * State update flags signalled as the result of brw_tracked_state updates
332 /** Subclass of Mesa program */
334 struct gl_program program
;
342 * Bitmask indicating which fragment shader inputs represent varyings (and
343 * hence have to be delivered to the fragment shader by the SF/SBE stage).
345 #define BRW_FS_VARYING_INPUT_MASK \
346 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
347 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
350 struct brw_sf_prog_data
{
351 GLuint urb_read_length
;
354 /* Each vertex may have upto 12 attributes, 4 components each,
355 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
358 * Actually we use 4 for each, so call it 12 rows.
360 GLuint urb_entry_size
;
365 * We always program SF to start reading at an offset of 1 (2 varying slots)
366 * from the start of the vertex URB entry. This causes it to skip:
367 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
368 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
370 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
373 struct brw_clip_prog_data
{
374 GLuint curb_read_length
; /* user planes? */
376 GLuint urb_read_length
;
380 struct brw_ff_gs_prog_data
{
381 GLuint urb_read_length
;
385 * Gen6 transform feedback: Amount by which the streaming vertex buffer
386 * indices should be incremented each time the GS is invoked.
388 unsigned svbi_postincrement_value
;
391 /** Number of texture sampler units */
392 #define BRW_MAX_TEX_UNIT 32
394 /** Max number of render targets in a shader */
395 #define BRW_MAX_DRAW_BUFFERS 8
397 /** Max number of UBOs in a shader */
398 #define BRW_MAX_UBO 14
400 /** Max number of SSBOs in a shader */
401 #define BRW_MAX_SSBO 12
403 /** Max number of atomic counter buffer objects in a shader */
404 #define BRW_MAX_ABO 16
406 /** Max number of image uniforms in a shader */
407 #define BRW_MAX_IMAGES 32
410 * Max number of binding table entries used for stream output.
412 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
413 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
415 * On Gen6, the size of transform feedback data is limited not by the number
416 * of components but by the number of binding table entries we set aside. We
417 * use one binding table entry for a float, one entry for a vector, and one
418 * entry per matrix column. Since the only way we can communicate our
419 * transform feedback capabilities to the client is via
420 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
421 * worst case, in which all the varyings are floats, so we use up one binding
422 * table entry per component. Therefore we need to set aside at least 64
423 * binding table entries for use by transform feedback.
425 * Note: since we don't currently pack varyings, it is currently impossible
426 * for the client to actually use up all of these binding table entries--if
427 * all of their varyings were floats, they would run out of varying slots and
428 * fail to link. But that's a bug, so it seems prudent to go ahead and
429 * allocate the number of binding table entries we will need once the bug is
432 #define BRW_MAX_SOL_BINDINGS 64
434 /** Maximum number of actual buffers used for stream output */
435 #define BRW_MAX_SOL_BUFFERS 4
437 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
438 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
443 2 + /* shader time, pull constants */ \
444 1 /* cs num work groups */)
446 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
449 * Stride in bytes between shader_time entries.
451 * We separate entries by a cacheline to reduce traffic between EUs writing to
454 #define SHADER_TIME_STRIDE 64
457 struct brw_context
*brw
;
459 struct brw_cache_item
**items
;
461 GLuint size
, n_items
;
463 uint32_t next_offset
;
468 /* Considered adding a member to this struct to document which flags
469 * an update might raise so that ordering of the state atoms can be
470 * checked or derived at runtime. Dropped the idea in favor of having
471 * a debug mode where the state is monitored for flags which are
472 * raised that have already been tested against.
474 struct brw_tracked_state
{
475 struct brw_state_flags dirty
;
476 void (*emit
)( struct brw_context
*brw
);
479 enum shader_time_shader_type
{
490 struct brw_vertex_buffer
{
491 /** Buffer object containing the uploaded vertex data */
495 /** Byte stride between elements in the uploaded array */
499 struct brw_vertex_element
{
500 const struct gl_vertex_array
*glarray
;
504 /** Offset of the first element within the buffer object */
508 struct brw_query_object
{
509 struct gl_query_object Base
;
511 /** Last query BO associated with this query. */
514 /** Last index in bo with query data for this object. */
517 /** True if we know the batch has been flushed since we ended the query. */
527 struct intel_batchbuffer
{
528 /** Current batchbuffer being queued up. */
530 /** Last BO submitted to the hardware. Used for glFinish(). */
531 drm_intel_bo
*last_bo
;
534 uint16_t emit
, total
;
536 uint16_t reserved_space
;
540 #define BATCH_SZ (8192*sizeof(uint32_t))
542 uint32_t state_batch_offset
;
543 enum brw_gpu_ring ring
;
544 bool needs_sol_reset
;
545 bool state_base_address_emitted
;
553 #define MAX_GS_INPUT_VERTICES 6
555 #define BRW_MAX_XFB_STREAMS 4
557 struct brw_transform_feedback_object
{
558 struct gl_transform_feedback_object base
;
560 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
561 drm_intel_bo
*offset_bo
;
563 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
566 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
567 GLenum primitive_mode
;
570 * Count of primitives generated during this transform feedback operation.
573 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
574 drm_intel_bo
*prim_count_bo
;
575 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
579 * Number of vertices written between last Begin/EndTransformFeedback().
581 * Used to implement DrawTransformFeedback().
583 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
584 bool vertices_written_valid
;
588 * Data shared between each programmable stage in the pipeline (vs, gs, and
591 struct brw_stage_state
593 gl_shader_stage stage
;
594 struct brw_stage_prog_data
*prog_data
;
597 * Optional scratch buffer used to store spilled register values and
598 * variably-indexed GRF arrays.
600 * The contents of this buffer are short-lived so the same memory can be
601 * re-used at will for multiple shader programs (executed by the same fixed
602 * function). However reusing a scratch BO for which shader invocations
603 * are still in flight with a per-thread scratch slot size other than the
604 * original can cause threads with different scratch slot size and FFTID
605 * (which may be executed in parallel depending on the shader stage and
606 * hardware generation) to map to an overlapping region of the scratch
607 * space, which can potentially lead to mutual scratch space corruption.
608 * For that reason if you borrow this scratch buffer you should only be
609 * using the slot size given by the \c per_thread_scratch member below,
610 * unless you're taking additional measures to synchronize thread execution
611 * across slot size changes.
613 drm_intel_bo
*scratch_bo
;
616 * Scratch slot size allocated for each thread in the buffer object given
619 uint32_t per_thread_scratch
;
621 /** Offset in the program cache to the program */
622 uint32_t prog_offset
;
624 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
625 uint32_t state_offset
;
627 uint32_t push_const_offset
; /* Offset in the batchbuffer */
628 int push_const_size
; /* in 256-bit register increments */
630 /* Binding table: pointers to SURFACE_STATE entries. */
631 uint32_t bind_bo_offset
;
632 uint32_t surf_offset
[BRW_MAX_SURFACES
];
634 /** SAMPLER_STATE count and table offset */
635 uint32_t sampler_count
;
636 uint32_t sampler_offset
;
639 enum brw_predicate_state
{
640 /* The first two states are used if we can determine whether to draw
641 * without having to look at the values in the query object buffer. This
642 * will happen if there is no conditional render in progress, if the query
643 * object is already completed or if something else has already added
644 * samples to the preliminary result such as via a BLT command.
646 BRW_PREDICATE_STATE_RENDER
,
647 BRW_PREDICATE_STATE_DONT_RENDER
,
648 /* In this case whether to draw or not depends on the result of an
649 * MI_PREDICATE command so the predicate enable bit needs to be checked.
651 BRW_PREDICATE_STATE_USE_BIT
656 struct gen_l3_config
;
659 * brw_context is derived from gl_context.
663 struct gl_context ctx
; /**< base class, must be first field */
667 uint32_t (*update_renderbuffer_surface
)(struct brw_context
*brw
,
668 struct gl_renderbuffer
*rb
,
669 uint32_t flags
, unsigned unit
,
670 uint32_t surf_index
);
671 void (*emit_null_surface_state
)(struct brw_context
*brw
,
675 uint32_t *out_offset
);
678 * Send the appropriate state packets to configure depth, stencil, and
679 * HiZ buffers (i965+ only)
681 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
682 struct intel_mipmap_tree
*depth_mt
,
683 uint32_t depth_offset
,
684 uint32_t depthbuffer_format
,
685 uint32_t depth_surface_type
,
686 struct intel_mipmap_tree
*stencil_mt
,
687 bool hiz
, bool separate_stencil
,
688 uint32_t width
, uint32_t height
,
689 uint32_t tile_x
, uint32_t tile_y
);
695 drm_intel_context
*hw_ctx
;
697 /** BO for post-sync nonzero writes for gen6 workaround. */
698 drm_intel_bo
*workaround_bo
;
699 uint8_t pipe_controls_since_last_cs_stall
;
702 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
703 * and would need flushing before being used from another cache domain that
704 * isn't coherent with it (i.e. the sampler).
706 struct set
*render_cache
;
709 * Number of resets observed in the system at context creation.
711 * This is tracked in the context so that we can determine that another
712 * reset has occurred.
714 uint32_t reset_count
;
716 struct intel_batchbuffer batch
;
721 uint32_t next_offset
;
725 * Set if rendering has occurred to the drawable's front buffer.
727 * This is used in the DRI2 case to detect that glFlush should also copy
728 * the contents of the fake front buffer to the real front buffer.
730 bool front_buffer_dirty
;
732 /** Framerate throttling: @{ */
733 drm_intel_bo
*throttle_batch
[2];
735 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
736 * frame of rendering to complete. This gives a very precise cap to the
737 * latency between input and output such that rendering never gets more
738 * than a frame behind the user. (With the caveat that we technically are
739 * not using the SwapBuffers itself as a barrier but the first batch
740 * submitted afterwards, which may be immediately prior to the next
743 bool need_swap_throttle
;
745 /** General throttling, not caught by throttling between SwapBuffers */
746 bool need_flush_throttle
;
756 bool always_flush_batch
;
757 bool always_flush_cache
;
758 bool disable_throttling
;
760 bool dual_color_blend_by_location
;
762 driOptionCache optionCache
;
765 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
767 GLenum reduced_primitive
;
770 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
771 * variable is set, this is the flag indicating to do expensive work that
772 * might lead to a perf_debug() call.
776 uint64_t max_gtt_map_object_size
;
788 bool has_separate_stencil
;
789 bool must_use_separate_stencil
;
792 bool has_surface_tile_offset
;
794 bool has_negative_rhw_bug
;
798 bool use_resource_streamer
;
801 * Some versions of Gen hardware don't do centroid interpolation correctly
802 * on unlit pixels, causing incorrect values for derivatives near triangle
803 * edges. Enabling this flag causes the fragment shader to use
804 * non-centroid interpolation for unlit pixels, at the expense of two extra
805 * fragment shader instructions.
807 bool needs_unlit_centroid_workaround
;
809 struct isl_device isl_dev
;
811 struct blorp_context blorp
;
815 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
818 enum brw_pipeline last_pipeline
;
820 struct brw_cache cache
;
822 /** IDs for meta stencil blit shader programs. */
823 struct gl_shader_program
*meta_stencil_blit_programs
[2];
825 /* Whether a meta-operation is in progress. */
826 bool meta_in_progress
;
828 /* Whether the last depth/stencil packets were both NULL. */
829 bool no_depth_or_stencil
;
831 /* The last PMA stall bits programmed. */
832 uint32_t pma_stall_bits
;
836 /** The value of gl_BaseVertex for the current _mesa_prim. */
839 /** The value of gl_BaseInstance for the current _mesa_prim. */
844 * Buffer and offset used for GL_ARB_shader_draw_parameters
845 * (for now, only gl_BaseVertex).
847 drm_intel_bo
*draw_params_bo
;
848 uint32_t draw_params_offset
;
851 * The value of gl_DrawID for the current _mesa_prim. This always comes
852 * in from it's own vertex buffer since it's not part of the indirect
856 drm_intel_bo
*draw_id_bo
;
857 uint32_t draw_id_offset
;
862 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
863 * an indirect call, and num_work_groups_offset is valid. Otherwise,
864 * num_work_groups is set based on glDispatchCompute.
866 drm_intel_bo
*num_work_groups_bo
;
867 GLintptr num_work_groups_offset
;
868 const GLuint
*num_work_groups
;
872 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
873 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
875 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
879 /* Summary of size and varying of active arrays, so we can check
880 * for changes to this state:
882 bool index_bounds_valid
;
883 unsigned int min_index
, max_index
;
885 /* Offset from start of vertex buffer so we can avoid redefining
886 * the same VB packed over and over again.
888 unsigned int start_vertex_bias
;
891 * Certain vertex attribute formats aren't natively handled by the
892 * hardware and require special VS code to fix up their values.
894 * These bitfields indicate which workarounds are needed.
896 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
901 * Index buffer for this draw_prims call.
903 * Updates are signaled by BRW_NEW_INDICES.
905 const struct _mesa_index_buffer
*ib
;
907 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
912 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
913 * avoid re-uploading the IB packet over and over if we're actually
914 * referencing the same index buffer.
916 unsigned int start_vertex_offset
;
919 /* Active vertex program:
921 const struct gl_program
*vertex_program
;
922 const struct gl_program
*geometry_program
;
923 const struct gl_program
*tess_ctrl_program
;
924 const struct gl_program
*tess_eval_program
;
925 const struct gl_program
*fragment_program
;
926 const struct gl_program
*compute_program
;
929 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
930 * that we don't have to reemit that state every time we change FBOs.
934 /* BRW_NEW_URB_ALLOCATIONS:
937 GLuint vsize
; /* vertex size plus header in urb registers */
938 GLuint gsize
; /* GS output size in urb registers */
939 GLuint hsize
; /* Tessellation control output size in urb registers */
940 GLuint dsize
; /* Tessellation evaluation output size in urb registers */
941 GLuint csize
; /* constant buffer size in urb registers */
942 GLuint sfsize
; /* setup data size in urb registers */
946 GLuint nr_vs_entries
;
947 GLuint nr_hs_entries
;
948 GLuint nr_ds_entries
;
949 GLuint nr_gs_entries
;
950 GLuint nr_clip_entries
;
951 GLuint nr_sf_entries
;
952 GLuint nr_cs_entries
;
962 * URB size in the current configuration. The units this is expressed
963 * in are somewhat inconsistent, see gen_device_info::urb::size.
965 * FINISHME: Represent the URB size consistently in KB on all platforms.
969 /* True if the most recently sent _3DSTATE_URB message allocated
970 * URB space for the GS.
974 /* True if the most recently sent _3DSTATE_URB message allocated
975 * URB space for the HS and DS.
981 /* BRW_NEW_CURBE_OFFSETS:
984 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
985 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
993 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
994 * for upload to the CURBE.
996 drm_intel_bo
*curbe_bo
;
997 /** Offset within curbe_bo of space for current curbe entry */
1002 * Layout of vertex data exiting the geometry portion of the pipleine.
1003 * This comes from the last enabled shader stage (GS, DS, or VS).
1005 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1007 struct brw_vue_map vue_map_geom_out
;
1010 struct brw_stage_state base
;
1014 struct brw_stage_state base
;
1017 * True if the 3DSTATE_HS command most recently emitted to the 3D
1018 * pipeline enabled the HS; false otherwise.
1024 struct brw_stage_state base
;
1027 * True if the 3DSTATE_DS command most recently emitted to the 3D
1028 * pipeline enabled the DS; false otherwise.
1034 struct brw_stage_state base
;
1037 * True if the 3DSTATE_GS command most recently emitted to the 3D
1038 * pipeline enabled the GS; false otherwise.
1044 struct brw_ff_gs_prog_data
*prog_data
;
1047 /** Offset in the program cache to the CLIP program pre-gen6 */
1048 uint32_t prog_offset
;
1049 uint32_t state_offset
;
1051 uint32_t bind_bo_offset
;
1053 * Surface offsets for the binding table. We only need surfaces to
1054 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1055 * need in this case.
1057 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1061 struct brw_clip_prog_data
*prog_data
;
1063 /** Offset in the program cache to the CLIP program pre-gen6 */
1064 uint32_t prog_offset
;
1066 /* Offset in the batch to the CLIP state on pre-gen6. */
1067 uint32_t state_offset
;
1069 /* As of gen6, this is the offset in the batch to the CLIP VP,
1075 * The number of viewports to use. If gl_ViewportIndex is written,
1076 * we can have up to ctx->Const.MaxViewports viewports. If not,
1077 * the viewport index is always 0, so we can only emit one.
1079 uint8_t viewport_count
;
1084 struct brw_sf_prog_data
*prog_data
;
1086 /** Offset in the program cache to the CLIP program pre-gen6 */
1087 uint32_t prog_offset
;
1088 uint32_t state_offset
;
1090 bool viewport_transform_enable
;
1094 struct brw_stage_state base
;
1099 * Buffer object used in place of multisampled null render targets on
1100 * Gen6. See brw_emit_null_surface_state().
1102 drm_intel_bo
*multisampled_null_render_target_bo
;
1103 uint32_t fast_clear_op
;
1109 struct brw_stage_state base
;
1112 /* RS hardware binding table */
1115 uint32_t next_offset
;
1119 uint32_t state_offset
;
1120 uint32_t blend_state_offset
;
1121 uint32_t depth_stencil_state_offset
;
1126 struct brw_query_object
*obj
;
1131 enum brw_predicate_state state
;
1135 int num_atoms
[BRW_NUM_PIPELINES
];
1136 const struct brw_tracked_state render_atoms
[76];
1137 const struct brw_tracked_state compute_atoms
[11];
1139 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1143 enum aub_state_struct_type type
;
1145 } *state_batch_list
;
1146 int state_batch_count
;
1148 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1149 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1151 /* PrimitiveRestart */
1154 bool enable_cut_index
;
1157 /** Computed depth/stencil/hiz state from the current attached
1158 * renderbuffers, valid only during the drawing state upload loop after
1159 * brw_workaround_depthstencil_alignment().
1162 struct intel_mipmap_tree
*depth_mt
;
1163 struct intel_mipmap_tree
*stencil_mt
;
1165 /* Inter-tile (page-aligned) byte offsets. */
1166 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1167 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1168 uint32_t tile_x
, tile_y
;
1171 uint32_t num_instances
;
1176 const struct gen_l3_config
*config
;
1183 enum shader_time_shader_type
*types
;
1184 struct shader_times
*cumulative
;
1190 struct brw_fast_clear_state
*fast_clear_state
;
1192 /* Array of flags telling if auxiliary buffer is disabled for corresponding
1193 * renderbuffer. If draw_aux_buffer_disabled[i] is set then use of
1194 * auxiliary buffer for gl_framebuffer::_ColorDrawBuffers[i] is
1196 * This is needed in case the same underlying buffer is also configured
1197 * to be sampled but with a format that the sampling engine can't treat
1198 * compressed or fast cleared.
1200 bool draw_aux_buffer_disabled
[MAX_DRAW_BUFFERS
];
1202 __DRIcontext
*driContext
;
1203 struct intel_screen
*screen
;
1207 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1209 /*======================================================================
1212 extern const char *const brw_vendor_string
;
1215 brw_get_renderer_string(const struct intel_screen
*screen
);
1218 DRI_CONF_BO_REUSE_DISABLED
,
1219 DRI_CONF_BO_REUSE_ALL
1222 void intel_update_renderbuffers(__DRIcontext
*context
,
1223 __DRIdrawable
*drawable
);
1224 void intel_prepare_render(struct brw_context
*brw
);
1226 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1227 __DRIdrawable
*drawable
);
1229 GLboolean
brwCreateContext(gl_api api
,
1230 const struct gl_config
*mesaVis
,
1231 __DRIcontext
*driContextPriv
,
1232 unsigned major_version
,
1233 unsigned minor_version
,
1237 void *sharedContextPrivate
);
1239 /*======================================================================
1243 brw_meta_resolve_color(struct brw_context
*brw
,
1244 struct intel_mipmap_tree
*mt
);
1246 /*======================================================================
1249 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1250 uint32_t depth_level
,
1251 uint32_t depth_layer
,
1252 struct intel_mipmap_tree
*stencil_mt
,
1253 uint32_t *out_tile_mask_x
,
1254 uint32_t *out_tile_mask_y
);
1255 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1256 GLbitfield clear_mask
);
1258 /* brw_object_purgeable.c */
1259 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1261 /*======================================================================
1264 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1265 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1266 void brw_emit_query_begin(struct brw_context
*brw
);
1267 void brw_emit_query_end(struct brw_context
*brw
);
1268 void brw_query_counter(struct gl_context
*ctx
, struct gl_query_object
*q
);
1269 bool brw_is_query_pipelined(struct brw_query_object
*query
);
1271 /** gen6_queryobj.c */
1272 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1273 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1274 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1276 /** hsw_queryobj.c */
1277 void hsw_init_queryobj_functions(struct dd_function_table
*functions
);
1279 /** brw_conditional_render.c */
1280 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1281 bool brw_check_conditional_render(struct brw_context
*brw
);
1283 /** intel_batchbuffer.c */
1284 void brw_load_register_mem(struct brw_context
*brw
,
1287 uint32_t read_domains
, uint32_t write_domain
,
1289 void brw_load_register_mem64(struct brw_context
*brw
,
1292 uint32_t read_domains
, uint32_t write_domain
,
1294 void brw_store_register_mem32(struct brw_context
*brw
,
1295 drm_intel_bo
*bo
, uint32_t reg
, uint32_t offset
);
1296 void brw_store_register_mem64(struct brw_context
*brw
,
1297 drm_intel_bo
*bo
, uint32_t reg
, uint32_t offset
);
1298 void brw_load_register_imm32(struct brw_context
*brw
,
1299 uint32_t reg
, uint32_t imm
);
1300 void brw_load_register_imm64(struct brw_context
*brw
,
1301 uint32_t reg
, uint64_t imm
);
1302 void brw_load_register_reg(struct brw_context
*brw
, uint32_t src
,
1304 void brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
,
1306 void brw_store_data_imm32(struct brw_context
*brw
, drm_intel_bo
*bo
,
1307 uint32_t offset
, uint32_t imm
);
1308 void brw_store_data_imm64(struct brw_context
*brw
, drm_intel_bo
*bo
,
1309 uint32_t offset
, uint64_t imm
);
1311 /*======================================================================
1314 void brw_debug_batch(struct brw_context
*brw
);
1315 void brw_annotate_aub(struct brw_context
*brw
);
1317 /*======================================================================
1318 * intel_tex_validate.c
1320 void brw_validate_textures( struct brw_context
*brw
);
1323 /*======================================================================
1327 key_debug(struct brw_context
*brw
, const char *name
, int a
, int b
)
1330 perf_debug(" %s %d->%d\n", name
, a
, b
);
1336 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1338 /* Per-thread scratch space is a power-of-two multiple of 1KB. */
1340 brw_get_scratch_size(int size
)
1342 return MAX2(1024, util_next_power_of_two(size
));
1344 void brw_get_scratch_bo(struct brw_context
*brw
,
1345 drm_intel_bo
**scratch_bo
, int size
);
1346 void brw_alloc_stage_scratch(struct brw_context
*brw
,
1347 struct brw_stage_state
*stage_state
,
1348 unsigned per_thread_size
,
1349 unsigned thread_count
);
1350 void brw_init_shader_time(struct brw_context
*brw
);
1351 int brw_get_shader_time_index(struct brw_context
*brw
,
1352 struct gl_program
*prog
,
1353 enum shader_time_shader_type type
,
1355 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1356 void brw_destroy_shader_time(struct brw_context
*brw
);
1360 void brw_upload_urb_fence(struct brw_context
*brw
);
1364 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1366 /* brw_fs_reg_allocate.cpp
1368 void brw_fs_alloc_reg_sets(struct brw_compiler
*compiler
);
1370 /* brw_vec4_reg_allocate.cpp */
1371 void brw_vec4_alloc_reg_set(struct brw_compiler
*compiler
);
1374 int brw_disassemble_inst(FILE *file
, const struct gen_device_info
*devinfo
,
1375 struct brw_inst
*inst
, bool is_compacted
);
1378 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1380 /* brw_draw_upload.c */
1381 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1382 const struct gl_vertex_array
*glarray
);
1384 static inline unsigned
1385 brw_get_index_type(GLenum type
)
1387 assert((type
== GL_UNSIGNED_BYTE
)
1388 || (type
== GL_UNSIGNED_SHORT
)
1389 || (type
== GL_UNSIGNED_INT
));
1391 /* The possible values for type are GL_UNSIGNED_BYTE (0x1401),
1392 * GL_UNSIGNED_SHORT (0x1403), and GL_UNSIGNED_INT (0x1405) which we want
1393 * to map to scale factors of 0, 1, and 2, respectively. These scale
1394 * factors are then left-shfited by 8 to be in the correct position in the
1395 * CMD_INDEX_BUFFER packet.
1397 * Subtracting 0x1401 gives 0, 2, and 4. Shifting left by 7 afterwards
1398 * gives 0x00000000, 0x00000100, and 0x00000200. These just happen to be
1399 * the values the need to be written in the CMD_INDEX_BUFFER packet.
1401 return (type
- 0x1401) << 7;
1404 void brw_prepare_vertices(struct brw_context
*brw
);
1406 /* brw_wm_surface_state.c */
1407 void brw_init_surface_formats(struct brw_context
*brw
);
1408 void brw_create_constant_surface(struct brw_context
*brw
,
1412 uint32_t *out_offset
);
1413 void brw_create_buffer_surface(struct brw_context
*brw
,
1417 uint32_t *out_offset
);
1418 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1420 uint32_t *surf_offset
);
1422 brw_update_sol_surface(struct brw_context
*brw
,
1423 struct gl_buffer_object
*buffer_obj
,
1424 uint32_t *out_offset
, unsigned num_vector_components
,
1425 unsigned stride_dwords
, unsigned offset_dwords
);
1426 void brw_upload_ubo_surfaces(struct brw_context
*brw
, struct gl_program
*prog
,
1427 struct brw_stage_state
*stage_state
,
1428 struct brw_stage_prog_data
*prog_data
);
1429 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1430 const struct gl_program
*prog
,
1431 struct brw_stage_state
*stage_state
,
1432 struct brw_stage_prog_data
*prog_data
);
1433 void brw_upload_image_surfaces(struct brw_context
*brw
,
1434 const struct gl_program
*prog
,
1435 struct brw_stage_state
*stage_state
,
1436 struct brw_stage_prog_data
*prog_data
);
1438 /* brw_surface_formats.c */
1439 bool brw_render_target_supported(struct brw_context
*brw
,
1440 struct gl_renderbuffer
*rb
);
1441 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1443 /* intel_buffer_objects.c */
1444 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1445 const char *bo_name
);
1446 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1447 const char *bo_name
);
1449 /* intel_extensions.c */
1450 extern void intelInitExtensions(struct gl_context
*ctx
);
1453 extern int intel_translate_shadow_compare_func(GLenum func
);
1454 extern int intel_translate_compare_func(GLenum func
);
1455 extern int intel_translate_stencil_op(GLenum op
);
1456 extern int intel_translate_logic_op(GLenum opcode
);
1459 void brw_init_syncobj_functions(struct dd_function_table
*functions
);
1462 struct gl_transform_feedback_object
*
1463 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1465 brw_delete_transform_feedback(struct gl_context
*ctx
,
1466 struct gl_transform_feedback_object
*obj
);
1468 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1469 struct gl_transform_feedback_object
*obj
);
1471 brw_end_transform_feedback(struct gl_context
*ctx
,
1472 struct gl_transform_feedback_object
*obj
);
1474 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1475 struct gl_transform_feedback_object
*obj
,
1478 /* gen7_sol_state.c */
1480 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1481 struct gl_transform_feedback_object
*obj
);
1483 gen7_end_transform_feedback(struct gl_context
*ctx
,
1484 struct gl_transform_feedback_object
*obj
);
1486 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1487 struct gl_transform_feedback_object
*obj
);
1489 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1490 struct gl_transform_feedback_object
*obj
);
1494 hsw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1495 struct gl_transform_feedback_object
*obj
);
1497 hsw_end_transform_feedback(struct gl_context
*ctx
,
1498 struct gl_transform_feedback_object
*obj
);
1500 hsw_pause_transform_feedback(struct gl_context
*ctx
,
1501 struct gl_transform_feedback_object
*obj
);
1503 hsw_resume_transform_feedback(struct gl_context
*ctx
,
1504 struct gl_transform_feedback_object
*obj
);
1506 /* brw_blorp_blit.cpp */
1508 brw_blorp_framebuffer(struct brw_context
*brw
,
1509 struct gl_framebuffer
*readFb
,
1510 struct gl_framebuffer
*drawFb
,
1511 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1512 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1513 GLbitfield mask
, GLenum filter
);
1516 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1517 struct gl_renderbuffer
*src_rb
,
1518 struct gl_texture_image
*dst_image
,
1520 int srcX0
, int srcY0
,
1521 int dstX0
, int dstY0
,
1522 int width
, int height
);
1524 /* gen6_multisample_state.c */
1526 gen6_determine_sample_mask(struct brw_context
*brw
);
1529 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1530 unsigned num_samples
);
1532 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1534 gen6_get_sample_position(struct gl_context
*ctx
,
1535 struct gl_framebuffer
*fb
,
1539 gen6_set_sample_maps(struct gl_context
*ctx
);
1541 /* gen8_multisample_state.c */
1542 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1543 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1547 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1548 unsigned hs_size
, unsigned ds_size
,
1549 unsigned gs_size
, unsigned fs_size
);
1552 gen6_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1553 bool gs_present
, unsigned gs_size
);
1555 gen7_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1556 bool gs_present
, bool tess_present
);
1560 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1562 brw_check_for_reset(struct brw_context
*brw
);
1566 brw_init_compute_functions(struct dd_function_table
*functions
);
1568 /*======================================================================
1569 * Inline conversion functions. These are better-typed than the
1570 * macros used previously:
1572 static inline struct brw_context
*
1573 brw_context( struct gl_context
*ctx
)
1575 return (struct brw_context
*)ctx
;
1578 static inline struct brw_program
*
1579 brw_program(struct gl_program
*p
)
1581 return (struct brw_program
*) p
;
1584 static inline const struct brw_program
*
1585 brw_program_const(const struct gl_program
*p
)
1587 return (const struct brw_program
*) p
;
1591 * Pre-gen6, the register file of the EUs was shared between threads,
1592 * and each thread used some subset allocated on a 16-register block
1593 * granularity. The unit states wanted these block counts.
1596 brw_register_blocks(int reg_count
)
1598 return ALIGN(reg_count
, 16) / 16 - 1;
1601 static inline uint32_t
1602 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1603 uint32_t prog_offset
)
1605 if (brw
->gen
>= 5) {
1606 /* Using state base address. */
1610 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1614 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1616 return brw
->cache
.bo
->offset64
+ prog_offset
;
1619 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1621 extern const char * const conditional_modifier
[16];
1622 extern const char *const pred_ctrl_align16
[16];
1625 brw_depth_writes_enabled(const struct brw_context
*brw
)
1627 const struct gl_context
*ctx
= &brw
->ctx
;
1629 /* We consider depth writes disabled if the depth function is GL_EQUAL,
1630 * because it would just overwrite the existing depth value with itself.
1632 * These bonus depth writes not only use bandwidth, but they also can
1633 * prevent early depth processing. For example, if the pixel shader
1634 * discards, the hardware must invoke the to determine whether or not
1635 * to do the depth write. If writes are disabled, we may still be able
1636 * to do the depth test before the shader, and skip the shader execution.
1638 * The Broadwell 3DSTATE_WM_DEPTH_STENCIL documentation also contains
1639 * a programming note saying to disable depth writes for EQUAL.
1641 return ctx
->Depth
.Test
&& ctx
->Depth
.Mask
&& ctx
->Depth
.Func
!= GL_EQUAL
;
1645 brw_emit_depthbuffer(struct brw_context
*brw
);
1648 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1649 struct intel_mipmap_tree
*depth_mt
,
1650 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1651 uint32_t depth_surface_type
,
1652 struct intel_mipmap_tree
*stencil_mt
,
1653 bool hiz
, bool separate_stencil
,
1654 uint32_t width
, uint32_t height
,
1655 uint32_t tile_x
, uint32_t tile_y
);
1658 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1659 struct intel_mipmap_tree
*depth_mt
,
1660 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1661 uint32_t depth_surface_type
,
1662 struct intel_mipmap_tree
*stencil_mt
,
1663 bool hiz
, bool separate_stencil
,
1664 uint32_t width
, uint32_t height
,
1665 uint32_t tile_x
, uint32_t tile_y
);
1668 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1669 struct intel_mipmap_tree
*depth_mt
,
1670 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1671 uint32_t depth_surface_type
,
1672 struct intel_mipmap_tree
*stencil_mt
,
1673 bool hiz
, bool separate_stencil
,
1674 uint32_t width
, uint32_t height
,
1675 uint32_t tile_x
, uint32_t tile_y
);
1677 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1678 struct intel_mipmap_tree
*depth_mt
,
1679 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1680 uint32_t depth_surface_type
,
1681 struct intel_mipmap_tree
*stencil_mt
,
1682 bool hiz
, bool separate_stencil
,
1683 uint32_t width
, uint32_t height
,
1684 uint32_t tile_x
, uint32_t tile_y
);
1686 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1687 unsigned int level
, unsigned int layer
, enum blorp_hiz_op op
);
1689 uint32_t get_hw_prim_for_gl_prim(int mode
);
1692 gen6_upload_push_constants(struct brw_context
*brw
,
1693 const struct gl_program
*prog
,
1694 const struct brw_stage_prog_data
*prog_data
,
1695 struct brw_stage_state
*stage_state
,
1696 enum aub_state_struct_type type
);
1699 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
1700 const struct intel_mipmap_tree
*mt
);
1702 /* brw_pipe_control.c */
1703 int brw_init_pipe_control(struct brw_context
*brw
,
1704 const struct gen_device_info
*info
);
1705 void brw_fini_pipe_control(struct brw_context
*brw
);
1707 void brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
);
1708 void brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
1709 drm_intel_bo
*bo
, uint32_t offset
,
1710 uint32_t imm_lower
, uint32_t imm_upper
);
1711 void brw_emit_mi_flush(struct brw_context
*brw
);
1712 void brw_emit_post_sync_nonzero_flush(struct brw_context
*brw
);
1713 void brw_emit_depth_stall_flushes(struct brw_context
*brw
);
1714 void gen7_emit_vs_workaround_flush(struct brw_context
*brw
);
1715 void gen7_emit_cs_stall_flush(struct brw_context
*brw
);
1717 /* brw_queryformat.c */
1718 void brw_query_internal_format(struct gl_context
*ctx
, GLenum target
,
1719 GLenum internalFormat
, GLenum pname
,