2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
36 #include "intel_context.h"
37 #include "brw_structs.h"
38 #include "main/imports.h"
39 #include "main/macros.h"
47 * URB - uniform resource buffer. A mid-sized buffer which is
48 * partitioned between the fixed function units and used for passing
49 * values (vertices, primitives, constants) between them.
51 * CURBE - constant URB entry. An urb region (entry) used to hold
52 * constant values which the fixed function units can be instructed to
53 * preload into the GRF when spawning a thread.
55 * VUE - vertex URB entry. An urb entry holding a vertex and usually
56 * a vertex header. The header contains control information and
57 * things like primitive type, Begin/end flags and clip codes.
59 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
60 * unit holding rasterization and interpolation parameters.
62 * GRF - general register file. One of several register files
63 * addressable by programmed threads. The inputs (r0, payload, curbe,
64 * urb) of the thread are preloaded to this area before the thread is
65 * spawned. The registers are individually 8 dwords wide and suitable
66 * for general usage. Registers holding thread input values are not
67 * special and may be overwritten.
69 * MRF - message register file. Threads communicate (and terminate)
70 * by sending messages. Message parameters are placed in contiguous
71 * MRF registers. All program output is via these messages. URB
72 * entries are populated by sending a message to the shared URB
73 * function containing the new data, together with a control word,
74 * often an unmodified copy of R0.
76 * R0 - GRF register 0. Typically holds control information used when
77 * sending messages to other threads.
79 * EU or GEN4 EU: The name of the programmable subsystem of the
80 * i965 hardware. Threads are executed by the EU, the registers
81 * described above are part of the EU architecture.
83 * Fixed function units:
85 * CS - Command streamer. Notional first unit, little software
86 * interaction. Holds the URB entries used for constant data, ie the
89 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
90 * this unit is responsible for pulling vertices out of vertex buffers
91 * in vram and injecting them into the processing pipe as VUEs. If
92 * enabled, it first passes them to a VS thread which is a good place
93 * for the driver to implement any active vertex shader.
95 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
96 * enabled, incoming strips etc are passed to GS threads in individual
97 * line/triangle/point units. The GS thread may perform arbitary
98 * computation and emit whatever primtives with whatever vertices it
99 * chooses. This makes GS an excellent place to implement GL's
100 * unfilled polygon modes, though of course it is capable of much
101 * more. Additionally, GS is used to translate away primitives not
102 * handled by latter units, including Quads and Lineloops.
104 * CS - Clipper. Mesa's clipping algorithms are imported to run on
105 * this unit. The fixed function part performs cliptesting against
106 * the 6 fixed clipplanes and makes descisions on whether or not the
107 * incoming primitive needs to be passed to a thread for clipping.
108 * User clip planes are handled via cooperation with the VS thread.
110 * SF - Strips Fans or Setup: Triangles are prepared for
111 * rasterization. Interpolation coefficients are calculated.
112 * Flatshading and two-side lighting usually performed here.
114 * WM - Windower. Interpolation of vertex attributes performed here.
115 * Fragment shader implemented here. SIMD aspects of EU taken full
116 * advantage of, as pixels are processed in blocks of 16.
118 * CC - Color Calculator. No EU threads associated with this unit.
119 * Handles blending and (presumably) depth and stencil testing.
123 #define BRW_MAX_CURBE (32*16)
126 struct brw_instruction
;
127 struct brw_vs_prog_key
;
128 struct brw_wm_prog_key
;
129 struct brw_wm_prog_data
;
133 BRW_STATE_FRAGMENT_PROGRAM
,
134 BRW_STATE_VERTEX_PROGRAM
,
135 BRW_STATE_CURBE_OFFSETS
,
136 BRW_STATE_REDUCED_PRIMITIVE
,
141 BRW_STATE_VS_BINDING_TABLE
,
142 BRW_STATE_GS_BINDING_TABLE
,
143 BRW_STATE_PS_BINDING_TABLE
,
147 BRW_STATE_INDEX_BUFFER
,
148 BRW_STATE_VS_CONSTBUF
,
149 BRW_STATE_PROGRAM_CACHE
,
150 BRW_STATE_STATE_BASE_ADDRESS
,
151 BRW_STATE_SOL_INDICES
,
152 BRW_STATE_VUE_MAP_GEOM_OUT
,
155 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
156 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
157 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
158 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
159 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
160 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
161 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
162 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
163 #define BRW_NEW_SURFACES (1 << BRW_STATE_SURFACES)
164 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
165 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
166 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
167 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
168 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
170 * Used for any batch entry with a relocated pointer that will be used
171 * by any 3D rendering.
173 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
174 /** \see brw.state.depth_region */
175 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
176 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
177 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
178 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
179 #define BRW_NEW_SOL_INDICES (1 << BRW_STATE_SOL_INDICES)
180 #define BRW_NEW_VUE_MAP_GEOM_OUT (1 << BRW_STATE_VUE_MAP_GEOM_OUT)
182 struct brw_state_flags
{
183 /** State update flags signalled by mesa internals */
186 * State update flags signalled as the result of brw_tracked_state updates
189 /** State update flags signalled by brw_state_cache.c searches */
193 #define AUB_TRACE_TYPE_MASK 0x0000ff00
194 #define AUB_TRACE_TYPE_NOTYPE (0 << 8)
195 #define AUB_TRACE_TYPE_BATCH (1 << 8)
196 #define AUB_TRACE_TYPE_VERTEX_BUFFER (5 << 8)
197 #define AUB_TRACE_TYPE_2D_MAP (6 << 8)
198 #define AUB_TRACE_TYPE_CUBE_MAP (7 << 8)
199 #define AUB_TRACE_TYPE_VOLUME_MAP (9 << 8)
200 #define AUB_TRACE_TYPE_1D_MAP (10 << 8)
201 #define AUB_TRACE_TYPE_CONSTANT_BUFFER (11 << 8)
202 #define AUB_TRACE_TYPE_CONSTANT_URB (12 << 8)
203 #define AUB_TRACE_TYPE_INDEX_BUFFER (13 << 8)
204 #define AUB_TRACE_TYPE_GENERAL (14 << 8)
205 #define AUB_TRACE_TYPE_SURFACE (15 << 8)
208 * state_struct_type enum values are encoded with the top 16 bits representing
209 * the type to be delivered to the .aub file, and the bottom 16 bits
210 * representing the subtype. This macro performs the encoding.
212 #define ENCODE_SS_TYPE(type, subtype) (((type) << 16) | (subtype))
214 enum state_struct_type
{
215 AUB_TRACE_VS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 1),
216 AUB_TRACE_GS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 2),
217 AUB_TRACE_CLIP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 3),
218 AUB_TRACE_SF_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 4),
219 AUB_TRACE_WM_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 5),
220 AUB_TRACE_CC_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 6),
221 AUB_TRACE_CLIP_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 7),
222 AUB_TRACE_SF_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 8),
223 AUB_TRACE_CC_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x9),
224 AUB_TRACE_SAMPLER_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xa),
225 AUB_TRACE_KERNEL_INSTRUCTIONS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xb),
226 AUB_TRACE_SCRATCH_SPACE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xc),
227 AUB_TRACE_SAMPLER_DEFAULT_COLOR
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xd),
229 AUB_TRACE_SCISSOR_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x15),
230 AUB_TRACE_BLEND_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x16),
231 AUB_TRACE_DEPTH_STENCIL_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x17),
233 AUB_TRACE_VERTEX_BUFFER
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_VERTEX_BUFFER
, 0),
234 AUB_TRACE_BINDING_TABLE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x100),
235 AUB_TRACE_SURFACE_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x200),
236 AUB_TRACE_VS_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 0),
237 AUB_TRACE_WM_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 1),
241 * Decode a state_struct_type value to determine the type that should be
242 * stored in the .aub file.
244 static inline uint32_t AUB_TRACE_TYPE(enum state_struct_type ss_type
)
246 return (ss_type
& 0xFFFF0000) >> 16;
250 * Decode a state_struct_type value to determine the subtype that should be
251 * stored in the .aub file.
253 static inline uint32_t AUB_TRACE_SUBTYPE(enum state_struct_type ss_type
)
255 return ss_type
& 0xFFFF;
258 /** Subclass of Mesa vertex program */
259 struct brw_vertex_program
{
260 struct gl_vertex_program program
;
265 /** Subclass of Mesa fragment program */
266 struct brw_fragment_program
{
267 struct gl_fragment_program program
;
268 GLuint id
; /**< serial no. to identify frag progs, never re-used */
272 struct gl_shader base
;
276 /** Shader IR transformed for native compile, at link time. */
277 struct exec_list
*ir
;
280 /* Data about a particular attempt to compile a program. Note that
281 * there can be many of these, each in a different GL state
282 * corresponding to a different brw_wm_prog_key struct, with different
285 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
288 struct brw_wm_prog_data
{
289 GLuint curb_read_length
;
290 GLuint urb_read_length
;
292 GLuint first_curbe_grf
;
293 GLuint first_curbe_grf_16
;
295 GLuint reg_blocks_16
;
296 GLuint total_scratch
;
298 GLuint nr_params
; /**< number of float params/constants */
299 GLuint nr_pull_params
;
302 uint32_t prog_offset_16
;
305 * Mask of which interpolation modes are required by the fragment shader.
306 * Used in hardware setup on gen6+.
308 uint32_t barycentric_interp_modes
;
310 /* Pointers to tracked values (only valid once
311 * _mesa_load_state_parameters has been called at runtime).
313 * These must be the last fields of the struct (see
314 * brw_wm_prog_data_compare()).
317 const float **pull_param
;
321 * Enum representing the i965-specific vertex results that don't correspond
322 * exactly to any element of gl_varying_slot. The values of this enum are
323 * assigned such that they don't conflict with gl_varying_slot.
327 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
328 BRW_VARYING_SLOT_POS_DUPLICATE
,
329 BRW_VARYING_SLOT_PAD
,
331 * Technically this is not a varying but just a placeholder that
332 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
333 * builtin variable to be compiled correctly. see compile_sf_prog() for
336 BRW_VARYING_SLOT_PNTC
,
337 BRW_VARYING_SLOT_COUNT
342 * Data structure recording the relationship between the gl_varying_slot enum
343 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
344 * single octaword within the VUE (128 bits).
346 * Note that each BRW register contains 256 bits (2 octawords), so when
347 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
348 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
349 * in a vertex shader), each register corresponds to a single VUE slot, since
350 * it contains data for two separate vertices.
354 * Bitfield representing all varying slots that are (a) stored in this VUE
355 * map, and (b) actually written by the shader. Does not include any of
356 * the additional varying slots defined in brw_varying_slot.
358 GLbitfield64 slots_valid
;
361 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
362 * not stored in a slot (because they are not written, or because
363 * additional processing is applied before storing them in the VUE), the
366 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
369 * Map from VUE slot to gl_varying_slot value. For slots that do not
370 * directly correspond to a gl_varying_slot, the value comes from
373 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
374 * simplifies code that uses the value stored in slot_to_varying to
375 * create a bit mask).
377 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
380 * Total number of VUE slots in use
386 * Convert a VUE slot number into a byte offset within the VUE.
388 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
394 * Convert a vertex output (brw_varying_slot) into a byte offset within the
397 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
400 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
404 struct brw_sf_prog_data
{
405 GLuint urb_read_length
;
408 /* Each vertex may have upto 12 attributes, 4 components each,
409 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
412 * Actually we use 4 for each, so call it 12 rows.
414 GLuint urb_entry_size
;
417 struct brw_clip_prog_data
{
418 GLuint curb_read_length
; /* user planes? */
420 GLuint urb_read_length
;
424 struct brw_gs_prog_data
{
425 GLuint urb_read_length
;
429 * Gen6 transform feedback: Amount by which the streaming vertex buffer
430 * indices should be incremented each time the GS is invoked.
432 unsigned svbi_postincrement_value
;
435 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
438 struct brw_vs_prog_data
{
439 struct brw_vue_map vue_map
;
441 GLuint curb_read_length
;
442 GLuint urb_read_length
;
444 GLuint nr_params
; /**< number of float params/constants */
445 GLuint nr_pull_params
; /**< number of dwords referenced by pull_param[] */
446 GLuint total_scratch
;
448 GLbitfield64 inputs_read
;
450 /* Used for calculating urb partitions:
452 GLuint urb_entry_size
;
458 /* These pointers must appear last. See brw_vs_prog_data_compare(). */
460 const float **pull_param
;
463 /** Number of texture sampler units */
464 #define BRW_MAX_TEX_UNIT 16
466 /** Max number of render targets in a shader */
467 #define BRW_MAX_DRAW_BUFFERS 8
470 * Max number of binding table entries used for stream output.
472 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
473 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
475 * On Gen6, the size of transform feedback data is limited not by the number
476 * of components but by the number of binding table entries we set aside. We
477 * use one binding table entry for a float, one entry for a vector, and one
478 * entry per matrix column. Since the only way we can communicate our
479 * transform feedback capabilities to the client is via
480 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
481 * worst case, in which all the varyings are floats, so we use up one binding
482 * table entry per component. Therefore we need to set aside at least 64
483 * binding table entries for use by transform feedback.
485 * Note: since we don't currently pack varyings, it is currently impossible
486 * for the client to actually use up all of these binding table entries--if
487 * all of their varyings were floats, they would run out of varying slots and
488 * fail to link. But that's a bug, so it seems prudent to go ahead and
489 * allocate the number of binding table entries we will need once the bug is
492 #define BRW_MAX_SOL_BINDINGS 64
494 /** Maximum number of actual buffers used for stream output */
495 #define BRW_MAX_SOL_BUFFERS 4
497 #define BRW_MAX_WM_UBOS 12
498 #define BRW_MAX_VS_UBOS 12
501 * Helpers to create Surface Binding Table indexes for draw buffers,
502 * textures, and constant buffers.
504 * Shader threads access surfaces via numeric handles, rather than directly
505 * using pointers. The binding table maps these numeric handles to the
506 * address of the actual buffer.
508 * For example, a shader might ask to sample from "surface 7." In this case,
509 * bind[7] would contain a pointer to a texture.
511 * Currently, our WM binding tables are (arbitrarily) programmed as follows:
513 * +-------------------------------+
514 * | 0 | Draw buffer 0 |
517 * | 7 | Draw buffer 7 |
518 * |-----|-------------------------|
519 * | 8 | WM Pull Constant Buffer |
520 * |-----|-------------------------|
524 * | 24 | Texture 15 |
525 * |-----|-------------------------|
530 * +-------------------------------+
532 * Our VS binding tables are programmed as follows:
534 * +-----+-------------------------+
535 * | 0 | VS Pull Constant Buffer |
536 * +-----+-------------------------+
540 * | 16 | Texture 15 |
541 * +-----+-------------------------+
546 * +-------------------------------+
548 * Our (gen6) GS binding tables are programmed as follows:
550 * +-----+-------------------------+
551 * | 0 | SOL Binding 0 |
554 * | 63 | SOL Binding 63 |
555 * +-----+-------------------------+
557 * Note that nothing actually uses the SURF_INDEX_DRAW macro, so it has to be
558 * the identity function or things will break. We do want to keep draw buffers
559 * first so we can use headerless render target writes for RT 0.
561 #define SURF_INDEX_DRAW(d) (d)
562 #define SURF_INDEX_FRAG_CONST_BUFFER (BRW_MAX_DRAW_BUFFERS + 1)
563 #define SURF_INDEX_TEXTURE(t) (BRW_MAX_DRAW_BUFFERS + 2 + (t))
564 #define SURF_INDEX_WM_UBO(u) (SURF_INDEX_TEXTURE(BRW_MAX_TEX_UNIT) + u)
565 #define SURF_INDEX_WM_SHADER_TIME (SURF_INDEX_WM_UBO(12))
566 /** Maximum size of the binding table. */
567 #define BRW_MAX_WM_SURFACES (SURF_INDEX_WM_SHADER_TIME + 1)
569 #define SURF_INDEX_VERT_CONST_BUFFER (0)
570 #define SURF_INDEX_VS_TEXTURE(t) (SURF_INDEX_VERT_CONST_BUFFER + 1 + (t))
571 #define SURF_INDEX_VS_UBO(u) (SURF_INDEX_VS_TEXTURE(BRW_MAX_TEX_UNIT) + u)
572 #define SURF_INDEX_VS_SHADER_TIME (SURF_INDEX_VS_UBO(12))
573 #define BRW_MAX_VS_SURFACES (SURF_INDEX_VS_SHADER_TIME + 1)
575 #define SURF_INDEX_SOL_BINDING(t) ((t))
576 #define BRW_MAX_GS_SURFACES SURF_INDEX_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
579 * Stride in bytes between shader_time entries.
581 * We separate entries by a cacheline to reduce traffic between EUs writing to
584 #define SHADER_TIME_STRIDE 64
588 BRW_DEPTH_STENCIL_STATE
,
589 BRW_COLOR_CALC_STATE
,
598 BRW_SF_UNIT
, /* scissor state on gen6 */
610 struct brw_cache_item
{
612 * Effectively part of the key, cache_id identifies what kind of state
613 * buffer is involved, and also which brw->state.dirty.cache flag should
614 * be set when this cache item is chosen.
616 enum brw_cache_id cache_id
;
617 /** 32-bit hash of the key data */
619 GLuint key_size
; /* for variable-sized keys */
626 struct brw_cache_item
*next
;
630 typedef bool (*cache_aux_compare_func
)(const void *a
, const void *b
,
631 int aux_size
, const void *key
);
632 typedef void (*cache_aux_free_func
)(const void *aux
);
635 struct brw_context
*brw
;
637 struct brw_cache_item
**items
;
639 GLuint size
, n_items
;
641 uint32_t next_offset
;
645 * Optional functions used in determining whether the prog_data for a new
646 * cache item matches an existing cache item (in case there's relevant data
647 * outside of the prog_data). If NULL, a plain memcmp is done.
649 cache_aux_compare_func aux_compare
[BRW_MAX_CACHE
];
650 /** Optional functions for freeing other pointers attached to a prog_data. */
651 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
655 /* Considered adding a member to this struct to document which flags
656 * an update might raise so that ordering of the state atoms can be
657 * checked or derived at runtime. Dropped the idea in favor of having
658 * a debug mode where the state is monitored for flags which are
659 * raised that have already been tested against.
661 struct brw_tracked_state
{
662 struct brw_state_flags dirty
;
663 void (*emit
)( struct brw_context
*brw
);
666 enum shader_time_shader_type
{
679 /* Flags for brw->state.cache.
681 #define CACHE_NEW_BLEND_STATE (1<<BRW_BLEND_STATE)
682 #define CACHE_NEW_DEPTH_STENCIL_STATE (1<<BRW_DEPTH_STENCIL_STATE)
683 #define CACHE_NEW_COLOR_CALC_STATE (1<<BRW_COLOR_CALC_STATE)
684 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
685 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
686 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
687 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
688 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
689 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
690 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
691 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
692 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
693 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
694 #define CACHE_NEW_GS_UNIT (1<<BRW_GS_UNIT)
695 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
696 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
697 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
698 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
700 struct brw_cached_batch_item
{
701 struct header
*header
;
703 struct brw_cached_batch_item
*next
;
708 /* Protect against a future where VERT_ATTRIB_MAX > 32. Wouldn't life
709 * be easier if C allowed arrays of packed elements?
711 #define ATTRIB_BIT_DWORDS ((VERT_ATTRIB_MAX+31)/32)
713 struct brw_vertex_buffer
{
714 /** Buffer object containing the uploaded vertex data */
717 /** Byte stride between elements in the uploaded array */
721 struct brw_vertex_element
{
722 const struct gl_client_array
*glarray
;
726 /** The corresponding Mesa vertex attribute */
727 gl_vert_attrib attrib
;
728 /** Offset of the first element within the buffer object */
732 struct brw_query_object
{
733 struct gl_query_object Base
;
735 /** Last query BO associated with this query. */
738 /** Last index in bo with query data for this object. */
744 * brw_context is derived from intel_context.
748 struct intel_context intel
; /**< base class, must be first field */
749 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
751 bool emit_state_always
;
752 bool has_surface_tile_offset
;
754 bool has_negative_rhw_bug
;
755 bool has_aa_line_parameters
;
760 * Some versions of Gen hardware don't do centroid interpolation correctly
761 * on unlit pixels, causing incorrect values for derivatives near triangle
762 * edges. Enabling this flag causes the fragment shader to use
763 * non-centroid interpolation for unlit pixels, at the expense of two extra
764 * fragment shader instructions.
766 bool needs_unlit_centroid_workaround
;
769 struct brw_state_flags dirty
;
772 struct brw_cache cache
;
773 struct brw_cached_batch_item
*cached_batch_items
;
776 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
777 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
779 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
783 /* Summary of size and varying of active arrays, so we can check
784 * for changes to this state:
786 unsigned int min_index
, max_index
;
788 /* Offset from start of vertex buffer so we can avoid redefining
789 * the same VB packed over and over again.
791 unsigned int start_vertex_bias
;
796 * Index buffer for this draw_prims call.
798 * Updates are signaled by BRW_NEW_INDICES.
800 const struct _mesa_index_buffer
*ib
;
802 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
806 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
807 * avoid re-uploading the IB packet over and over if we're actually
808 * referencing the same index buffer.
810 unsigned int start_vertex_offset
;
813 /* Active vertex program:
815 const struct gl_vertex_program
*vertex_program
;
816 const struct gl_fragment_program
*fragment_program
;
818 /* hw-dependent 3DSTATE_VF_STATISTICS opcode */
819 uint32_t CMD_VF_STATISTICS
;
820 /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
821 uint32_t CMD_PIPELINE_SELECT
;
824 * Platform specific constants containing the maximum number of threads
825 * for each pipeline stage.
831 /* BRW_NEW_URB_ALLOCATIONS:
834 GLuint vsize
; /* vertex size plus header in urb registers */
835 GLuint csize
; /* constant buffer size in urb registers */
836 GLuint sfsize
; /* setup data size in urb registers */
840 GLuint max_vs_entries
; /* Maximum number of VS entries */
841 GLuint max_gs_entries
; /* Maximum number of GS entries */
843 GLuint nr_vs_entries
;
844 GLuint nr_gs_entries
;
845 GLuint nr_clip_entries
;
846 GLuint nr_sf_entries
;
847 GLuint nr_cs_entries
;
854 GLuint size
; /* Hardware URB size, in KB. */
856 /* gen6: True if the most recently sent _3DSTATE_URB message allocated
857 * URB space for the GS.
859 bool gen6_gs_previously_active
;
863 /* BRW_NEW_CURBE_OFFSETS:
866 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
867 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
874 drm_intel_bo
*curbe_bo
;
875 /** Offset within curbe_bo of space for current curbe entry */
877 /** Offset within curbe_bo of space for next curbe entry */
878 GLuint curbe_next_offset
;
881 * Copy of the last set of CURBEs uploaded. Frequently we'll end up
882 * in brw_curbe.c with the same set of constant data to be uploaded,
883 * so we'd rather not upload new constants in that case (it can cause
884 * a pipeline bubble since only up to 4 can be pipelined at a time).
888 * Allocation for where to calculate the next set of CURBEs.
889 * It's a hot enough path that malloc/free of that data matters.
895 /** SAMPLER_STATE count and offset */
902 * Layout of vertex data exiting the geometry portion of the pipleine.
903 * This comes from the geometry shader if one exists, otherwise from the
906 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
908 struct brw_vue_map vue_map_geom_out
;
911 struct brw_vs_prog_data
*prog_data
;
913 drm_intel_bo
*scratch_bo
;
914 drm_intel_bo
*const_bo
;
915 /** Offset in the program cache to the VS program */
916 uint32_t prog_offset
;
917 uint32_t state_offset
;
919 uint32_t push_const_offset
; /* Offset in the batchbuffer */
920 int push_const_size
; /* in 256-bit register increments */
922 /** @{ register allocator */
924 struct ra_regs
*regs
;
927 * Array of the ra classes for the unaligned contiguous register
933 * Mapping for register-allocated objects in *regs to the first
934 * GRF for that object.
936 uint8_t *ra_reg_to_grf
;
939 uint32_t bind_bo_offset
;
940 uint32_t surf_offset
[BRW_MAX_VS_SURFACES
];
944 struct brw_gs_prog_data
*prog_data
;
947 /** Offset in the program cache to the CLIP program pre-gen6 */
948 uint32_t prog_offset
;
949 uint32_t state_offset
;
951 uint32_t bind_bo_offset
;
952 uint32_t surf_offset
[BRW_MAX_GS_SURFACES
];
956 struct brw_clip_prog_data
*prog_data
;
958 /** Offset in the program cache to the CLIP program pre-gen6 */
959 uint32_t prog_offset
;
961 /* Offset in the batch to the CLIP state on pre-gen6. */
962 uint32_t state_offset
;
964 /* As of gen6, this is the offset in the batch to the CLIP VP,
972 struct brw_sf_prog_data
*prog_data
;
974 /** Offset in the program cache to the CLIP program pre-gen6 */
975 uint32_t prog_offset
;
976 uint32_t state_offset
;
981 struct brw_wm_prog_data
*prog_data
;
983 /** offsets in the batch to sampler default colors (texture border color)
985 uint32_t sdc_offset
[BRW_MAX_TEX_UNIT
];
989 drm_intel_bo
*scratch_bo
;
992 * Buffer object used in place of multisampled null render targets on
993 * Gen6. See brw_update_null_renderbuffer_surface().
995 drm_intel_bo
*multisampled_null_render_target_bo
;
997 /** Offset in the program cache to the WM program */
998 uint32_t prog_offset
;
1000 uint32_t state_offset
; /* offset in batchbuffer to pre-gen6 WM state */
1002 drm_intel_bo
*const_bo
; /* pull constant buffer. */
1004 * This is offset in the batch to the push constants on gen6.
1006 * Pre-gen6, push constants live in the CURBE.
1008 uint32_t push_const_offset
;
1010 /** Binding table of pointers to surf_bo entries */
1011 uint32_t bind_bo_offset
;
1012 uint32_t surf_offset
[BRW_MAX_WM_SURFACES
];
1015 struct ra_regs
*regs
;
1017 /** Array of the ra classes for the unaligned contiguous
1018 * register block sizes used.
1023 * Mapping for register-allocated objects in *regs to the first
1024 * GRF for that object.
1026 uint8_t *ra_reg_to_grf
;
1029 * ra class for the aligned pairs we use for PLN, which doesn't
1030 * appear in *classes.
1032 int aligned_pairs_class
;
1038 uint32_t state_offset
;
1039 uint32_t blend_state_offset
;
1040 uint32_t depth_stencil_state_offset
;
1045 struct brw_query_object
*obj
;
1050 const struct brw_tracked_state
**atoms
;
1052 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1056 enum state_struct_type type
;
1057 } *state_batch_list
;
1058 int state_batch_count
;
1060 struct brw_sol_state
{
1061 uint32_t svbi_0_starting_index
;
1062 uint32_t svbi_0_max_index
;
1063 uint32_t offset_0_batch_start
;
1064 uint32_t primitives_generated
;
1065 uint32_t primitives_written
;
1066 bool counting_primitives_generated
;
1067 bool counting_primitives_written
;
1070 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1071 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1073 /* PrimitiveRestart */
1076 bool enable_cut_index
;
1079 /** Computed depth/stencil/hiz state from the current attached
1080 * renderbuffers, valid only during the drawing state upload loop after
1081 * brw_workaround_depthstencil_alignment().
1084 struct intel_mipmap_tree
*depth_mt
;
1085 struct intel_mipmap_tree
*stencil_mt
;
1086 struct intel_mipmap_tree
*hiz_mt
;
1088 /* Inter-tile (page-aligned) byte offsets. */
1089 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1090 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1091 uint32_t tile_x
, tile_y
;
1094 uint32_t num_instances
;
1099 struct gl_shader_program
**shader_programs
;
1100 struct gl_program
**programs
;
1101 enum shader_time_shader_type
*types
;
1102 uint64_t *cumulative
;
1109 /*======================================================================
1112 void brwInitVtbl( struct brw_context
*brw
);
1114 /*======================================================================
1117 bool brwCreateContext(int api
,
1118 const struct gl_config
*mesaVis
,
1119 __DRIcontext
*driContextPriv
,
1120 unsigned major_version
,
1121 unsigned minor_version
,
1124 void *sharedContextPrivate
);
1126 /*======================================================================
1129 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1130 struct intel_mipmap_tree
*stencil_mt
,
1131 uint32_t *out_tile_mask_x
,
1132 uint32_t *out_tile_mask_y
);
1133 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1134 GLbitfield clear_mask
);
1136 /*======================================================================
1139 void brw_init_queryobj_functions(struct dd_function_table
*functions
);
1140 void brw_emit_query_begin(struct brw_context
*brw
);
1141 void brw_emit_query_end(struct brw_context
*brw
);
1143 /*======================================================================
1146 void brw_debug_batch(struct intel_context
*intel
);
1147 void brw_annotate_aub(struct intel_context
*intel
);
1149 /*======================================================================
1152 void brw_validate_textures( struct brw_context
*brw
);
1155 /*======================================================================
1158 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1160 int brw_get_scratch_size(int size
);
1161 void brw_get_scratch_bo(struct intel_context
*intel
,
1162 drm_intel_bo
**scratch_bo
, int size
);
1163 void brw_init_shader_time(struct brw_context
*brw
);
1164 int brw_get_shader_time_index(struct brw_context
*brw
,
1165 struct gl_shader_program
*shader_prog
,
1166 struct gl_program
*prog
,
1167 enum shader_time_shader_type type
);
1168 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1169 void brw_destroy_shader_time(struct brw_context
*brw
);
1173 void brw_upload_urb_fence(struct brw_context
*brw
);
1177 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1179 /* brw_fs_reg_allocate.cpp
1181 void brw_fs_alloc_reg_sets(struct brw_context
*brw
);
1184 int brw_disasm (FILE *file
, struct brw_instruction
*inst
, int gen
);
1187 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1189 /* brw_wm_surface_state.c */
1190 void brw_init_surface_formats(struct brw_context
*brw
);
1192 brw_update_sol_surface(struct brw_context
*brw
,
1193 struct gl_buffer_object
*buffer_obj
,
1194 uint32_t *out_offset
, unsigned num_vector_components
,
1195 unsigned stride_dwords
, unsigned offset_dwords
);
1196 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1197 struct gl_shader
*shader
,
1198 uint32_t *surf_offsets
);
1202 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1203 struct gl_transform_feedback_object
*obj
);
1205 brw_end_transform_feedback(struct gl_context
*ctx
,
1206 struct gl_transform_feedback_object
*obj
);
1208 /* gen7_sol_state.c */
1210 gen7_end_transform_feedback(struct gl_context
*ctx
,
1211 struct gl_transform_feedback_object
*obj
);
1213 /* brw_blorp_blit.cpp */
1215 brw_blorp_framebuffer(struct intel_context
*intel
,
1216 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1217 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1218 GLbitfield mask
, GLenum filter
);
1221 brw_blorp_copytexsubimage(struct intel_context
*intel
,
1222 struct gl_renderbuffer
*src_rb
,
1223 struct gl_texture_image
*dst_image
,
1224 int srcX0
, int srcY0
,
1225 int dstX0
, int dstY0
,
1226 int width
, int height
);
1228 /* gen6_multisample_state.c */
1230 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1231 unsigned num_samples
);
1233 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
,
1234 unsigned num_samples
, float coverage
,
1235 bool coverage_invert
, unsigned sample_mask
);
1237 gen6_get_sample_position(struct gl_context
*ctx
,
1238 struct gl_framebuffer
*fb
,
1244 gen7_allocate_push_constants(struct brw_context
*brw
);
1247 gen7_emit_urb_state(struct brw_context
*brw
, GLuint nr_vs_entries
,
1248 GLuint vs_size
, GLuint vs_start
);
1252 /*======================================================================
1253 * Inline conversion functions. These are better-typed than the
1254 * macros used previously:
1256 static INLINE
struct brw_context
*
1257 brw_context( struct gl_context
*ctx
)
1259 return (struct brw_context
*)ctx
;
1262 static INLINE
struct brw_vertex_program
*
1263 brw_vertex_program(struct gl_vertex_program
*p
)
1265 return (struct brw_vertex_program
*) p
;
1268 static INLINE
const struct brw_vertex_program
*
1269 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1271 return (const struct brw_vertex_program
*) p
;
1274 static INLINE
struct brw_fragment_program
*
1275 brw_fragment_program(struct gl_fragment_program
*p
)
1277 return (struct brw_fragment_program
*) p
;
1280 static INLINE
const struct brw_fragment_program
*
1281 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1283 return (const struct brw_fragment_program
*) p
;
1287 * Pre-gen6, the register file of the EUs was shared between threads,
1288 * and each thread used some subset allocated on a 16-register block
1289 * granularity. The unit states wanted these block counts.
1292 brw_register_blocks(int reg_count
)
1294 return ALIGN(reg_count
, 16) / 16 - 1;
1297 static inline uint32_t
1298 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1299 uint32_t prog_offset
)
1301 struct intel_context
*intel
= &brw
->intel
;
1303 if (intel
->gen
>= 5) {
1304 /* Using state base address. */
1308 drm_intel_bo_emit_reloc(intel
->batch
.bo
,
1312 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1314 return brw
->cache
.bo
->offset
+ prog_offset
;
1317 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1318 bool brw_lower_texture_gradients(struct exec_list
*instructions
);
1320 struct opcode_desc
{
1326 extern const struct opcode_desc opcode_descs
[128];
1329 brw_emit_depthbuffer(struct brw_context
*brw
);
1332 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1333 struct intel_mipmap_tree
*depth_mt
,
1334 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1335 uint32_t depth_surface_type
,
1336 struct intel_mipmap_tree
*stencil_mt
,
1337 struct intel_mipmap_tree
*hiz_mt
,
1338 bool separate_stencil
, uint32_t width
,
1339 uint32_t height
, uint32_t tile_x
, uint32_t tile_y
);
1342 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1343 struct intel_mipmap_tree
*depth_mt
,
1344 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1345 uint32_t depth_surface_type
,
1346 struct intel_mipmap_tree
*stencil_mt
,
1347 struct intel_mipmap_tree
*hiz_mt
,
1348 bool separate_stencil
, uint32_t width
,
1349 uint32_t height
, uint32_t tile_x
, uint32_t tile_y
);