2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
37 #include "main/macros.h"
38 #include "main/mtypes.h"
39 #include "brw_structs.h"
40 #include "brw_compiler.h"
41 #include "intel_aub.h"
45 /* Evil hack for using libdrm in a c++ compiler. */
49 #include <intel_bufmgr.h>
58 #include "intel_debug.h"
59 #include "intel_screen.h"
60 #include "intel_tex_obj.h"
61 #include "intel_resolve_map.h"
65 * URB - uniform resource buffer. A mid-sized buffer which is
66 * partitioned between the fixed function units and used for passing
67 * values (vertices, primitives, constants) between them.
69 * CURBE - constant URB entry. An urb region (entry) used to hold
70 * constant values which the fixed function units can be instructed to
71 * preload into the GRF when spawning a thread.
73 * VUE - vertex URB entry. An urb entry holding a vertex and usually
74 * a vertex header. The header contains control information and
75 * things like primitive type, Begin/end flags and clip codes.
77 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
78 * unit holding rasterization and interpolation parameters.
80 * GRF - general register file. One of several register files
81 * addressable by programmed threads. The inputs (r0, payload, curbe,
82 * urb) of the thread are preloaded to this area before the thread is
83 * spawned. The registers are individually 8 dwords wide and suitable
84 * for general usage. Registers holding thread input values are not
85 * special and may be overwritten.
87 * MRF - message register file. Threads communicate (and terminate)
88 * by sending messages. Message parameters are placed in contiguous
89 * MRF registers. All program output is via these messages. URB
90 * entries are populated by sending a message to the shared URB
91 * function containing the new data, together with a control word,
92 * often an unmodified copy of R0.
94 * R0 - GRF register 0. Typically holds control information used when
95 * sending messages to other threads.
97 * EU or GEN4 EU: The name of the programmable subsystem of the
98 * i965 hardware. Threads are executed by the EU, the registers
99 * described above are part of the EU architecture.
101 * Fixed function units:
103 * CS - Command streamer. Notional first unit, little software
104 * interaction. Holds the URB entries used for constant data, ie the
107 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
108 * this unit is responsible for pulling vertices out of vertex buffers
109 * in vram and injecting them into the processing pipe as VUEs. If
110 * enabled, it first passes them to a VS thread which is a good place
111 * for the driver to implement any active vertex shader.
113 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
114 * enabled, incoming strips etc are passed to GS threads in individual
115 * line/triangle/point units. The GS thread may perform arbitary
116 * computation and emit whatever primtives with whatever vertices it
117 * chooses. This makes GS an excellent place to implement GL's
118 * unfilled polygon modes, though of course it is capable of much
119 * more. Additionally, GS is used to translate away primitives not
120 * handled by latter units, including Quads and Lineloops.
122 * CS - Clipper. Mesa's clipping algorithms are imported to run on
123 * this unit. The fixed function part performs cliptesting against
124 * the 6 fixed clipplanes and makes descisions on whether or not the
125 * incoming primitive needs to be passed to a thread for clipping.
126 * User clip planes are handled via cooperation with the VS thread.
128 * SF - Strips Fans or Setup: Triangles are prepared for
129 * rasterization. Interpolation coefficients are calculated.
130 * Flatshading and two-side lighting usually performed here.
132 * WM - Windower. Interpolation of vertex attributes performed here.
133 * Fragment shader implemented here. SIMD aspects of EU taken full
134 * advantage of, as pixels are processed in blocks of 16.
136 * CC - Color Calculator. No EU threads associated with this unit.
137 * Handles blending and (presumably) depth and stencil testing.
142 struct brw_vs_prog_key
;
143 struct brw_vue_prog_key
;
144 struct brw_wm_prog_key
;
145 struct brw_wm_prog_data
;
146 struct brw_cs_prog_key
;
147 struct brw_cs_prog_data
;
151 BRW_COMPUTE_PIPELINE
,
158 BRW_CACHE_BLORP_BLIT_PROG
,
161 BRW_CACHE_FF_GS_PROG
,
170 /* brw_cache_ids must come first - see brw_state_cache.c */
171 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
172 BRW_STATE_FRAGMENT_PROGRAM
,
173 BRW_STATE_GEOMETRY_PROGRAM
,
174 BRW_STATE_VERTEX_PROGRAM
,
175 BRW_STATE_CURBE_OFFSETS
,
176 BRW_STATE_REDUCED_PRIMITIVE
,
181 BRW_STATE_BINDING_TABLE_POINTERS
,
185 BRW_STATE_INDEX_BUFFER
,
186 BRW_STATE_VS_CONSTBUF
,
187 BRW_STATE_GS_CONSTBUF
,
188 BRW_STATE_PROGRAM_CACHE
,
189 BRW_STATE_STATE_BASE_ADDRESS
,
190 BRW_STATE_VUE_MAP_GEOM_OUT
,
191 BRW_STATE_TRANSFORM_FEEDBACK
,
192 BRW_STATE_RASTERIZER_DISCARD
,
194 BRW_STATE_UNIFORM_BUFFER
,
195 BRW_STATE_ATOMIC_BUFFER
,
196 BRW_STATE_IMAGE_UNITS
,
197 BRW_STATE_META_IN_PROGRESS
,
198 BRW_STATE_INTERPOLATION_MAP
,
199 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
200 BRW_STATE_NUM_SAMPLES
,
201 BRW_STATE_TEXTURE_BUFFER
,
202 BRW_STATE_GEN4_UNIT_STATE
,
206 BRW_STATE_SAMPLER_STATE_TABLE
,
207 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
208 BRW_STATE_COMPUTE_PROGRAM
,
209 BRW_STATE_CS_WORK_GROUPS
,
214 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
216 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
217 * When the currently bound shader program differs from the previous draw
218 * call, these will be flagged. They cover brw->{stage}_program and
219 * ctx->{Stage}Program->_Current.
221 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
222 * driver perspective. Even if the same shader is bound at the API level,
223 * we may need to switch between multiple versions of that shader to handle
224 * changes in non-orthagonal state.
226 * Additionally, multiple shader programs may have identical vertex shaders
227 * (for example), or compile down to the same code in the backend. We combine
228 * those into a single program cache entry.
230 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
231 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
233 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
234 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
235 * use the normal state upload paths), but the cache is still used. To avoid
236 * polluting the brw_state_cache code with special cases, we retain the dirty
237 * bit for now. It should eventually be removed.
239 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_BLIT_PROG)
240 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
241 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
242 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
243 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
244 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
245 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
246 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
247 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
248 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
249 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
250 #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
251 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
252 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
253 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
254 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
255 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
256 #define BRW_NEW_BINDING_TABLE_POINTERS (1ull << BRW_STATE_BINDING_TABLE_POINTERS)
257 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
258 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
260 * Used for any batch entry with a relocated pointer that will be used
261 * by any 3D rendering.
263 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
264 /** \see brw.state.depth_region */
265 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
266 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
267 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
268 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
269 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
270 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
271 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
272 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
273 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
274 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
275 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
276 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
277 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
278 #define BRW_NEW_INTERPOLATION_MAP (1ull << BRW_STATE_INTERPOLATION_MAP)
279 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
280 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
281 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
282 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
283 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
284 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
285 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
286 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
287 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
288 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
289 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
291 struct brw_state_flags
{
292 /** State update flags signalled by mesa internals */
295 * State update flags signalled as the result of brw_tracked_state updates
300 /** Subclass of Mesa vertex program */
301 struct brw_vertex_program
{
302 struct gl_vertex_program program
;
307 /** Subclass of Mesa geometry program */
308 struct brw_geometry_program
{
309 struct gl_geometry_program program
;
310 unsigned id
; /**< serial no. to identify geom progs, never re-used */
314 /** Subclass of Mesa fragment program */
315 struct brw_fragment_program
{
316 struct gl_fragment_program program
;
317 GLuint id
; /**< serial no. to identify frag progs, never re-used */
321 /** Subclass of Mesa compute program */
322 struct brw_compute_program
{
323 struct gl_compute_program program
;
324 unsigned id
; /**< serial no. to identify compute progs, never re-used */
329 struct gl_shader base
;
335 * Bitmask indicating which fragment shader inputs represent varyings (and
336 * hence have to be delivered to the fragment shader by the SF/SBE stage).
338 #define BRW_FS_VARYING_INPUT_MASK \
339 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
340 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
344 * Mapping of VUE map slots to interpolation modes.
346 struct interpolation_mode_map
{
347 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
350 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
352 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
353 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
359 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
361 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
362 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
369 struct brw_sf_prog_data
{
370 GLuint urb_read_length
;
373 /* Each vertex may have upto 12 attributes, 4 components each,
374 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
377 * Actually we use 4 for each, so call it 12 rows.
379 GLuint urb_entry_size
;
384 * We always program SF to start reading at an offset of 1 (2 varying slots)
385 * from the start of the vertex URB entry. This causes it to skip:
386 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
387 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
389 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
392 struct brw_clip_prog_data
{
393 GLuint curb_read_length
; /* user planes? */
395 GLuint urb_read_length
;
399 struct brw_ff_gs_prog_data
{
400 GLuint urb_read_length
;
404 * Gen6 transform feedback: Amount by which the streaming vertex buffer
405 * indices should be incremented each time the GS is invoked.
407 unsigned svbi_postincrement_value
;
410 /** Number of texture sampler units */
411 #define BRW_MAX_TEX_UNIT 32
413 /** Max number of render targets in a shader */
414 #define BRW_MAX_DRAW_BUFFERS 8
416 /** Max number of UBOs in a shader */
417 #define BRW_MAX_UBO 14
419 /** Max number of SSBOs in a shader */
420 #define BRW_MAX_SSBO 12
422 /** Max number of atomic counter buffer objects in a shader */
423 #define BRW_MAX_ABO 16
425 /** Max number of image uniforms in a shader */
426 #define BRW_MAX_IMAGES 32
429 * Max number of binding table entries used for stream output.
431 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
432 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
434 * On Gen6, the size of transform feedback data is limited not by the number
435 * of components but by the number of binding table entries we set aside. We
436 * use one binding table entry for a float, one entry for a vector, and one
437 * entry per matrix column. Since the only way we can communicate our
438 * transform feedback capabilities to the client is via
439 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
440 * worst case, in which all the varyings are floats, so we use up one binding
441 * table entry per component. Therefore we need to set aside at least 64
442 * binding table entries for use by transform feedback.
444 * Note: since we don't currently pack varyings, it is currently impossible
445 * for the client to actually use up all of these binding table entries--if
446 * all of their varyings were floats, they would run out of varying slots and
447 * fail to link. But that's a bug, so it seems prudent to go ahead and
448 * allocate the number of binding table entries we will need once the bug is
451 #define BRW_MAX_SOL_BINDINGS 64
453 /** Maximum number of actual buffers used for stream output */
454 #define BRW_MAX_SOL_BUFFERS 4
456 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
457 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
462 2 + /* shader time, pull constants */ \
463 1 /* cs num work groups */)
465 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
468 * Stride in bytes between shader_time entries.
470 * We separate entries by a cacheline to reduce traffic between EUs writing to
473 #define SHADER_TIME_STRIDE 64
475 struct brw_cache_item
{
477 * Effectively part of the key, cache_id identifies what kind of state
478 * buffer is involved, and also which dirty flag should set.
480 enum brw_cache_id cache_id
;
481 /** 32-bit hash of the key data */
483 GLuint key_size
; /* for variable-sized keys */
490 struct brw_cache_item
*next
;
495 struct brw_context
*brw
;
497 struct brw_cache_item
**items
;
499 GLuint size
, n_items
;
501 uint32_t next_offset
;
506 /* Considered adding a member to this struct to document which flags
507 * an update might raise so that ordering of the state atoms can be
508 * checked or derived at runtime. Dropped the idea in favor of having
509 * a debug mode where the state is monitored for flags which are
510 * raised that have already been tested against.
512 struct brw_tracked_state
{
513 struct brw_state_flags dirty
;
514 void (*emit
)( struct brw_context
*brw
);
517 enum shader_time_shader_type
{
528 struct brw_vertex_buffer
{
529 /** Buffer object containing the uploaded vertex data */
532 /** Byte stride between elements in the uploaded array */
536 struct brw_vertex_element
{
537 const struct gl_client_array
*glarray
;
541 /** Offset of the first element within the buffer object */
545 struct brw_query_object
{
546 struct gl_query_object Base
;
548 /** Last query BO associated with this query. */
551 /** Last index in bo with query data for this object. */
554 /** True if we know the batch has been flushed since we ended the query. */
564 struct intel_batchbuffer
{
565 /** Current batchbuffer being queued up. */
567 /** Last BO submitted to the hardware. Used for glFinish(). */
568 drm_intel_bo
*last_bo
;
571 uint16_t emit
, total
;
573 uint16_t reserved_space
;
577 #define BATCH_SZ (8192*sizeof(uint32_t))
579 uint32_t state_batch_offset
;
580 enum brw_gpu_ring ring
;
581 bool needs_sol_reset
;
589 #define MAX_GS_INPUT_VERTICES 6
591 #define BRW_MAX_XFB_STREAMS 4
593 struct brw_transform_feedback_object
{
594 struct gl_transform_feedback_object base
;
596 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
597 drm_intel_bo
*offset_bo
;
599 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
602 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
603 GLenum primitive_mode
;
606 * Count of primitives generated during this transform feedback operation.
609 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
610 drm_intel_bo
*prim_count_bo
;
611 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
615 * Number of vertices written between last Begin/EndTransformFeedback().
617 * Used to implement DrawTransformFeedback().
619 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
620 bool vertices_written_valid
;
624 * Data shared between each programmable stage in the pipeline (vs, gs, and
627 struct brw_stage_state
629 gl_shader_stage stage
;
630 struct brw_stage_prog_data
*prog_data
;
633 * Optional scratch buffer used to store spilled register values and
634 * variably-indexed GRF arrays.
636 drm_intel_bo
*scratch_bo
;
638 /** Offset in the program cache to the program */
639 uint32_t prog_offset
;
641 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
642 uint32_t state_offset
;
644 uint32_t push_const_offset
; /* Offset in the batchbuffer */
645 int push_const_size
; /* in 256-bit register increments */
647 /* Binding table: pointers to SURFACE_STATE entries. */
648 uint32_t bind_bo_offset
;
649 uint32_t surf_offset
[BRW_MAX_SURFACES
];
651 /** SAMPLER_STATE count and table offset */
652 uint32_t sampler_count
;
653 uint32_t sampler_offset
;
656 enum brw_predicate_state
{
657 /* The first two states are used if we can determine whether to draw
658 * without having to look at the values in the query object buffer. This
659 * will happen if there is no conditional render in progress, if the query
660 * object is already completed or if something else has already added
661 * samples to the preliminary result such as via a BLT command.
663 BRW_PREDICATE_STATE_RENDER
,
664 BRW_PREDICATE_STATE_DONT_RENDER
,
665 /* In this case whether to draw or not depends on the result of an
666 * MI_PREDICATE command so the predicate enable bit needs to be checked.
668 BRW_PREDICATE_STATE_USE_BIT
674 * brw_context is derived from gl_context.
678 struct gl_context ctx
; /**< base class, must be first field */
682 void (*update_texture_surface
)(struct gl_context
*ctx
,
684 uint32_t *surf_offset
,
686 uint32_t (*update_renderbuffer_surface
)(struct brw_context
*brw
,
687 struct gl_renderbuffer
*rb
,
688 bool layered
, unsigned unit
,
689 uint32_t surf_index
);
691 void (*emit_texture_surface_state
)(struct brw_context
*brw
,
692 struct intel_mipmap_tree
*mt
,
700 uint32_t *surf_offset
,
701 bool rw
, bool for_gather
);
702 void (*emit_buffer_surface_state
)(struct brw_context
*brw
,
703 uint32_t *out_offset
,
705 unsigned buffer_offset
,
706 unsigned surface_format
,
707 unsigned buffer_size
,
710 void (*emit_null_surface_state
)(struct brw_context
*brw
,
714 uint32_t *out_offset
);
717 * Send the appropriate state packets to configure depth, stencil, and
718 * HiZ buffers (i965+ only)
720 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
721 struct intel_mipmap_tree
*depth_mt
,
722 uint32_t depth_offset
,
723 uint32_t depthbuffer_format
,
724 uint32_t depth_surface_type
,
725 struct intel_mipmap_tree
*stencil_mt
,
726 bool hiz
, bool separate_stencil
,
727 uint32_t width
, uint32_t height
,
728 uint32_t tile_x
, uint32_t tile_y
);
734 drm_intel_context
*hw_ctx
;
736 /** BO for post-sync nonzero writes for gen6 workaround. */
737 drm_intel_bo
*workaround_bo
;
738 uint8_t pipe_controls_since_last_cs_stall
;
741 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
742 * and would need flushing before being used from another cache domain that
743 * isn't coherent with it (i.e. the sampler).
745 struct set
*render_cache
;
748 * Number of resets observed in the system at context creation.
750 * This is tracked in the context so that we can determine that another
751 * reset has occurred.
753 uint32_t reset_count
;
755 struct intel_batchbuffer batch
;
760 uint32_t next_offset
;
764 * Set if rendering has occurred to the drawable's front buffer.
766 * This is used in the DRI2 case to detect that glFlush should also copy
767 * the contents of the fake front buffer to the real front buffer.
769 bool front_buffer_dirty
;
771 /** Framerate throttling: @{ */
772 drm_intel_bo
*throttle_batch
[2];
774 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
775 * frame of rendering to complete. This gives a very precise cap to the
776 * latency between input and output such that rendering never gets more
777 * than a frame behind the user. (With the caveat that we technically are
778 * not using the SwapBuffers itself as a barrier but the first batch
779 * submitted afterwards, which may be immediately prior to the next
782 bool need_swap_throttle
;
784 /** General throttling, not caught by throttling between SwapBuffers */
785 bool need_flush_throttle
;
795 bool always_flush_batch
;
796 bool always_flush_cache
;
797 bool disable_throttling
;
800 driOptionCache optionCache
;
803 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
805 GLenum reduced_primitive
;
808 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
809 * variable is set, this is the flag indicating to do expensive work that
810 * might lead to a perf_debug() call.
814 uint32_t max_gtt_map_object_size
;
826 bool has_separate_stencil
;
827 bool must_use_separate_stencil
;
830 bool has_surface_tile_offset
;
832 bool has_negative_rhw_bug
;
836 bool use_resource_streamer
;
839 * Some versions of Gen hardware don't do centroid interpolation correctly
840 * on unlit pixels, causing incorrect values for derivatives near triangle
841 * edges. Enabling this flag causes the fragment shader to use
842 * non-centroid interpolation for unlit pixels, at the expense of two extra
843 * fragment shader instructions.
845 bool needs_unlit_centroid_workaround
;
849 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
852 enum brw_pipeline last_pipeline
;
854 struct brw_cache cache
;
856 /** IDs for meta stencil blit shader programs. */
857 unsigned meta_stencil_blit_programs
[2];
859 /* Whether a meta-operation is in progress. */
860 bool meta_in_progress
;
862 /* Whether the last depth/stencil packets were both NULL. */
863 bool no_depth_or_stencil
;
865 /* The last PMA stall bits programmed. */
866 uint32_t pma_stall_bits
;
869 /** The value of gl_BaseVertex for the current _mesa_prim. */
873 * Buffer and offset used for GL_ARB_shader_draw_parameters
874 * (for now, only gl_BaseVertex).
876 drm_intel_bo
*draw_params_bo
;
877 uint32_t draw_params_offset
;
882 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
883 * an indirect call, and num_work_groups_offset is valid. Otherwise,
884 * num_work_groups is set based on glDispatchCompute.
886 drm_intel_bo
*num_work_groups_bo
;
887 GLintptr num_work_groups_offset
;
888 const GLuint
*num_work_groups
;
892 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
893 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
895 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
899 /* Summary of size and varying of active arrays, so we can check
900 * for changes to this state:
902 unsigned int min_index
, max_index
;
904 /* Offset from start of vertex buffer so we can avoid redefining
905 * the same VB packed over and over again.
907 unsigned int start_vertex_bias
;
910 * Certain vertex attribute formats aren't natively handled by the
911 * hardware and require special VS code to fix up their values.
913 * These bitfields indicate which workarounds are needed.
915 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
920 * Index buffer for this draw_prims call.
922 * Updates are signaled by BRW_NEW_INDICES.
924 const struct _mesa_index_buffer
*ib
;
926 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
930 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
931 * avoid re-uploading the IB packet over and over if we're actually
932 * referencing the same index buffer.
934 unsigned int start_vertex_offset
;
937 /* Active vertex program:
939 const struct gl_vertex_program
*vertex_program
;
940 const struct gl_geometry_program
*geometry_program
;
941 const struct gl_fragment_program
*fragment_program
;
942 const struct gl_compute_program
*compute_program
;
945 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
946 * that we don't have to reemit that state every time we change FBOs.
951 * Platform specific constants containing the maximum number of threads
952 * for each pipeline stage.
954 unsigned max_vs_threads
;
955 unsigned max_hs_threads
;
956 unsigned max_ds_threads
;
957 unsigned max_gs_threads
;
958 unsigned max_wm_threads
;
959 unsigned max_cs_threads
;
961 /* BRW_NEW_URB_ALLOCATIONS:
964 GLuint vsize
; /* vertex size plus header in urb registers */
965 GLuint gsize
; /* GS output size in urb registers */
966 GLuint csize
; /* constant buffer size in urb registers */
967 GLuint sfsize
; /* setup data size in urb registers */
971 GLuint min_vs_entries
; /* Minimum number of VS entries */
972 GLuint max_vs_entries
; /* Maximum number of VS entries */
973 GLuint max_hs_entries
; /* Maximum number of HS entries */
974 GLuint max_ds_entries
; /* Maximum number of DS entries */
975 GLuint max_gs_entries
; /* Maximum number of GS entries */
977 GLuint nr_vs_entries
;
978 GLuint nr_gs_entries
;
979 GLuint nr_clip_entries
;
980 GLuint nr_sf_entries
;
981 GLuint nr_cs_entries
;
988 GLuint size
; /* Hardware URB size, in KB. */
990 /* True if the most recently sent _3DSTATE_URB message allocated
991 * URB space for the GS.
997 /* BRW_NEW_CURBE_OFFSETS:
1000 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1001 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1009 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1010 * for upload to the CURBE.
1012 drm_intel_bo
*curbe_bo
;
1013 /** Offset within curbe_bo of space for current curbe entry */
1014 GLuint curbe_offset
;
1018 * Layout of vertex data exiting the geometry portion of the pipleine.
1019 * This comes from the last enabled shader stage (GS, DS, or VS).
1021 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1023 struct brw_vue_map vue_map_geom_out
;
1026 struct brw_stage_state base
;
1027 struct brw_vs_prog_data
*prog_data
;
1031 struct brw_stage_state base
;
1032 struct brw_gs_prog_data
*prog_data
;
1035 * True if the 3DSTATE_GS command most recently emitted to the 3D
1036 * pipeline enabled the GS; false otherwise.
1042 struct brw_ff_gs_prog_data
*prog_data
;
1045 /** Offset in the program cache to the CLIP program pre-gen6 */
1046 uint32_t prog_offset
;
1047 uint32_t state_offset
;
1049 uint32_t bind_bo_offset
;
1051 * Surface offsets for the binding table. We only need surfaces to
1052 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1053 * need in this case.
1055 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1059 struct brw_clip_prog_data
*prog_data
;
1061 /** Offset in the program cache to the CLIP program pre-gen6 */
1062 uint32_t prog_offset
;
1064 /* Offset in the batch to the CLIP state on pre-gen6. */
1065 uint32_t state_offset
;
1067 /* As of gen6, this is the offset in the batch to the CLIP VP,
1075 struct brw_sf_prog_data
*prog_data
;
1077 /** Offset in the program cache to the CLIP program pre-gen6 */
1078 uint32_t prog_offset
;
1079 uint32_t state_offset
;
1081 bool viewport_transform_enable
;
1085 struct brw_stage_state base
;
1086 struct brw_wm_prog_data
*prog_data
;
1091 * Buffer object used in place of multisampled null render targets on
1092 * Gen6. See brw_emit_null_surface_state().
1094 drm_intel_bo
*multisampled_null_render_target_bo
;
1095 uint32_t fast_clear_op
;
1101 struct brw_stage_state base
;
1102 struct brw_cs_prog_data
*prog_data
;
1105 /* RS hardware binding table */
1108 uint32_t next_offset
;
1112 uint32_t state_offset
;
1113 uint32_t blend_state_offset
;
1114 uint32_t depth_stencil_state_offset
;
1119 struct brw_query_object
*obj
;
1124 enum brw_predicate_state state
;
1129 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1130 const int *statistics_registers
;
1132 /** The number of active monitors using OA counters. */
1136 * A buffer object storing OA counter snapshots taken at the start and
1137 * end of each batch (creating "bookends" around the batch).
1139 drm_intel_bo
*bookend_bo
;
1141 /** The number of snapshots written to bookend_bo. */
1142 int bookend_snapshots
;
1145 * An array of monitors whose results haven't yet been assembled based on
1146 * the data in buffer objects.
1148 * These may be active, or have already ended. However, the results
1149 * have not been requested.
1151 struct brw_perf_monitor_object
**unresolved
;
1152 int unresolved_elements
;
1153 int unresolved_array_size
;
1156 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1157 * the counter which MI_REPORT_PERF_COUNT stores there.
1159 const int *oa_snapshot_layout
;
1161 /** Number of 32-bit entries in a hardware counter snapshot. */
1162 int entries_per_oa_snapshot
;
1165 int num_atoms
[BRW_NUM_PIPELINES
];
1166 const struct brw_tracked_state render_atoms
[60];
1167 const struct brw_tracked_state compute_atoms
[9];
1169 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1173 enum aub_state_struct_type type
;
1175 } *state_batch_list
;
1176 int state_batch_count
;
1178 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1179 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1181 /* Interpolation modes, one byte per vue slot.
1182 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1184 struct interpolation_mode_map interpolation_mode
;
1186 /* PrimitiveRestart */
1189 bool enable_cut_index
;
1192 /** Computed depth/stencil/hiz state from the current attached
1193 * renderbuffers, valid only during the drawing state upload loop after
1194 * brw_workaround_depthstencil_alignment().
1197 struct intel_mipmap_tree
*depth_mt
;
1198 struct intel_mipmap_tree
*stencil_mt
;
1200 /* Inter-tile (page-aligned) byte offsets. */
1201 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1202 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1203 uint32_t tile_x
, tile_y
;
1206 uint32_t num_instances
;
1213 enum shader_time_shader_type
*types
;
1214 struct shader_times
*cumulative
;
1220 struct brw_fast_clear_state
*fast_clear_state
;
1222 __DRIcontext
*driContext
;
1223 struct intel_screen
*intelScreen
;
1226 /*======================================================================
1229 void brwInitVtbl( struct brw_context
*brw
);
1232 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1234 /*======================================================================
1237 extern const char *const brw_vendor_string
;
1239 extern const char *brw_get_renderer_string(unsigned deviceID
);
1242 DRI_CONF_BO_REUSE_DISABLED
,
1243 DRI_CONF_BO_REUSE_ALL
1246 void intel_update_renderbuffers(__DRIcontext
*context
,
1247 __DRIdrawable
*drawable
);
1248 void intel_prepare_render(struct brw_context
*brw
);
1250 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1251 __DRIdrawable
*drawable
);
1253 GLboolean
brwCreateContext(gl_api api
,
1254 const struct gl_config
*mesaVis
,
1255 __DRIcontext
*driContextPriv
,
1256 unsigned major_version
,
1257 unsigned minor_version
,
1261 void *sharedContextPrivate
);
1263 /*======================================================================
1266 GLuint
brw_get_rb_for_slice(struct brw_context
*brw
,
1267 struct intel_mipmap_tree
*mt
,
1268 unsigned level
, unsigned layer
, bool flat
);
1270 void brw_meta_updownsample(struct brw_context
*brw
,
1271 struct intel_mipmap_tree
*src
,
1272 struct intel_mipmap_tree
*dst
);
1274 void brw_meta_fbo_stencil_blit(struct brw_context
*brw
,
1275 struct gl_framebuffer
*read_fb
,
1276 struct gl_framebuffer
*draw_fb
,
1277 GLfloat srcX0
, GLfloat srcY0
,
1278 GLfloat srcX1
, GLfloat srcY1
,
1279 GLfloat dstX0
, GLfloat dstY0
,
1280 GLfloat dstX1
, GLfloat dstY1
);
1282 void brw_meta_stencil_updownsample(struct brw_context
*brw
,
1283 struct intel_mipmap_tree
*src
,
1284 struct intel_mipmap_tree
*dst
);
1286 bool brw_meta_fast_clear(struct brw_context
*brw
,
1287 struct gl_framebuffer
*fb
,
1289 bool partial_clear
);
1292 brw_meta_resolve_color(struct brw_context
*brw
,
1293 struct intel_mipmap_tree
*mt
);
1295 brw_meta_fast_clear_free(struct brw_context
*brw
);
1298 /*======================================================================
1301 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1302 uint32_t depth_level
,
1303 uint32_t depth_layer
,
1304 struct intel_mipmap_tree
*stencil_mt
,
1305 uint32_t *out_tile_mask_x
,
1306 uint32_t *out_tile_mask_y
);
1307 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1308 GLbitfield clear_mask
);
1310 /* brw_object_purgeable.c */
1311 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1313 /*======================================================================
1316 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1317 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1318 void brw_emit_query_begin(struct brw_context
*brw
);
1319 void brw_emit_query_end(struct brw_context
*brw
);
1321 /** gen6_queryobj.c */
1322 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1323 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1324 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1325 void brw_store_register_mem64(struct brw_context
*brw
,
1326 drm_intel_bo
*bo
, uint32_t reg
, int idx
);
1328 /** brw_conditional_render.c */
1329 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1330 bool brw_check_conditional_render(struct brw_context
*brw
);
1332 /** intel_batchbuffer.c */
1333 void brw_load_register_mem(struct brw_context
*brw
,
1336 uint32_t read_domains
, uint32_t write_domain
,
1338 void brw_load_register_mem64(struct brw_context
*brw
,
1341 uint32_t read_domains
, uint32_t write_domain
,
1344 /*======================================================================
1347 void brw_debug_batch(struct brw_context
*brw
);
1348 void brw_annotate_aub(struct brw_context
*brw
);
1350 /*======================================================================
1353 void brw_validate_textures( struct brw_context
*brw
);
1356 /*======================================================================
1359 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1361 /* Per-thread scratch space is a power-of-two multiple of 1KB. */
1363 brw_get_scratch_size(int size
)
1365 return util_next_power_of_two(size
| 1023);
1367 void brw_get_scratch_bo(struct brw_context
*brw
,
1368 drm_intel_bo
**scratch_bo
, int size
);
1369 void brw_init_shader_time(struct brw_context
*brw
);
1370 int brw_get_shader_time_index(struct brw_context
*brw
,
1371 struct gl_shader_program
*shader_prog
,
1372 struct gl_program
*prog
,
1373 enum shader_time_shader_type type
);
1374 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1375 void brw_destroy_shader_time(struct brw_context
*brw
);
1379 void brw_upload_urb_fence(struct brw_context
*brw
);
1383 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1385 /* brw_fs_reg_allocate.cpp
1387 void brw_fs_alloc_reg_sets(struct brw_compiler
*compiler
);
1389 /* brw_vec4_reg_allocate.cpp */
1390 void brw_vec4_alloc_reg_set(struct brw_compiler
*compiler
);
1393 int brw_disassemble_inst(FILE *file
, const struct brw_device_info
*devinfo
,
1394 struct brw_inst
*inst
, bool is_compacted
);
1397 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1399 /* brw_draw_upload.c */
1400 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1401 const struct gl_client_array
*glarray
);
1403 static inline unsigned
1404 brw_get_index_type(GLenum type
)
1406 assert((type
== GL_UNSIGNED_BYTE
)
1407 || (type
== GL_UNSIGNED_SHORT
)
1408 || (type
== GL_UNSIGNED_INT
));
1410 /* The possible values for type are GL_UNSIGNED_BYTE (0x1401),
1411 * GL_UNSIGNED_SHORT (0x1403), and GL_UNSIGNED_INT (0x1405) which we want
1412 * to map to scale factors of 0, 1, and 2, respectively. These scale
1413 * factors are then left-shfited by 8 to be in the correct position in the
1414 * CMD_INDEX_BUFFER packet.
1416 * Subtracting 0x1401 gives 0, 2, and 4. Shifting left by 7 afterwards
1417 * gives 0x00000000, 0x00000100, and 0x00000200. These just happen to be
1418 * the values the need to be written in the CMD_INDEX_BUFFER packet.
1420 return (type
- 0x1401) << 7;
1423 void brw_prepare_vertices(struct brw_context
*brw
);
1425 /* brw_wm_surface_state.c */
1426 void brw_init_surface_formats(struct brw_context
*brw
);
1427 void brw_create_constant_surface(struct brw_context
*brw
,
1431 uint32_t *out_offset
,
1433 void brw_create_buffer_surface(struct brw_context
*brw
,
1437 uint32_t *out_offset
,
1439 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1441 uint32_t *surf_offset
);
1443 brw_update_sol_surface(struct brw_context
*brw
,
1444 struct gl_buffer_object
*buffer_obj
,
1445 uint32_t *out_offset
, unsigned num_vector_components
,
1446 unsigned stride_dwords
, unsigned offset_dwords
);
1447 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1448 struct gl_shader
*shader
,
1449 struct brw_stage_state
*stage_state
,
1450 struct brw_stage_prog_data
*prog_data
,
1452 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1453 struct gl_shader
*shader
,
1454 struct brw_stage_state
*stage_state
,
1455 struct brw_stage_prog_data
*prog_data
);
1456 void brw_upload_image_surfaces(struct brw_context
*brw
,
1457 struct gl_shader
*shader
,
1458 struct brw_stage_state
*stage_state
,
1459 struct brw_stage_prog_data
*prog_data
);
1461 /* brw_surface_formats.c */
1462 bool brw_render_target_supported(struct brw_context
*brw
,
1463 struct gl_renderbuffer
*rb
);
1464 bool brw_losslessly_compressible_format(struct brw_context
*brw
,
1465 uint32_t brw_format
);
1466 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1467 mesa_format
brw_lower_mesa_image_format(const struct brw_device_info
*devinfo
,
1468 mesa_format format
);
1470 /* brw_performance_monitor.c */
1471 void brw_init_performance_monitors(struct brw_context
*brw
);
1472 void brw_dump_perf_monitors(struct brw_context
*brw
);
1473 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1474 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1476 /* intel_buffer_objects.c */
1477 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1478 const char *bo_name
);
1479 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1480 const char *bo_name
);
1482 /* intel_extensions.c */
1483 extern void intelInitExtensions(struct gl_context
*ctx
);
1486 extern int intel_translate_shadow_compare_func(GLenum func
);
1487 extern int intel_translate_compare_func(GLenum func
);
1488 extern int intel_translate_stencil_op(GLenum op
);
1489 extern int intel_translate_logic_op(GLenum opcode
);
1491 /* intel_syncobj.c */
1492 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1495 struct gl_transform_feedback_object
*
1496 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1498 brw_delete_transform_feedback(struct gl_context
*ctx
,
1499 struct gl_transform_feedback_object
*obj
);
1501 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1502 struct gl_transform_feedback_object
*obj
);
1504 brw_end_transform_feedback(struct gl_context
*ctx
,
1505 struct gl_transform_feedback_object
*obj
);
1507 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1508 struct gl_transform_feedback_object
*obj
,
1511 /* gen7_sol_state.c */
1513 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1514 struct gl_transform_feedback_object
*obj
);
1516 gen7_end_transform_feedback(struct gl_context
*ctx
,
1517 struct gl_transform_feedback_object
*obj
);
1519 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1520 struct gl_transform_feedback_object
*obj
);
1522 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1523 struct gl_transform_feedback_object
*obj
);
1525 /* brw_blorp_blit.cpp */
1527 brw_blorp_framebuffer(struct brw_context
*brw
,
1528 struct gl_framebuffer
*readFb
,
1529 struct gl_framebuffer
*drawFb
,
1530 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1531 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1532 GLbitfield mask
, GLenum filter
);
1535 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1536 struct gl_renderbuffer
*src_rb
,
1537 struct gl_texture_image
*dst_image
,
1539 int srcX0
, int srcY0
,
1540 int dstX0
, int dstY0
,
1541 int width
, int height
);
1543 /* gen6_multisample_state.c */
1545 gen6_determine_sample_mask(struct brw_context
*brw
);
1548 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1549 unsigned num_samples
);
1551 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1553 gen6_get_sample_position(struct gl_context
*ctx
,
1554 struct gl_framebuffer
*fb
,
1558 gen6_set_sample_maps(struct gl_context
*ctx
);
1560 /* gen8_multisample_state.c */
1561 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1562 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1566 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1567 unsigned gs_size
, unsigned fs_size
);
1570 gen7_emit_urb_state(struct brw_context
*brw
,
1571 unsigned nr_vs_entries
, unsigned vs_size
,
1572 unsigned vs_start
, unsigned nr_gs_entries
,
1573 unsigned gs_size
, unsigned gs_start
);
1578 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1582 brw_init_compute_functions(struct dd_function_table
*functions
);
1584 /*======================================================================
1585 * Inline conversion functions. These are better-typed than the
1586 * macros used previously:
1588 static inline struct brw_context
*
1589 brw_context( struct gl_context
*ctx
)
1591 return (struct brw_context
*)ctx
;
1594 static inline struct brw_vertex_program
*
1595 brw_vertex_program(struct gl_vertex_program
*p
)
1597 return (struct brw_vertex_program
*) p
;
1600 static inline const struct brw_vertex_program
*
1601 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1603 return (const struct brw_vertex_program
*) p
;
1606 static inline struct brw_geometry_program
*
1607 brw_geometry_program(struct gl_geometry_program
*p
)
1609 return (struct brw_geometry_program
*) p
;
1612 static inline struct brw_fragment_program
*
1613 brw_fragment_program(struct gl_fragment_program
*p
)
1615 return (struct brw_fragment_program
*) p
;
1618 static inline const struct brw_fragment_program
*
1619 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1621 return (const struct brw_fragment_program
*) p
;
1624 static inline struct brw_compute_program
*
1625 brw_compute_program(struct gl_compute_program
*p
)
1627 return (struct brw_compute_program
*) p
;
1631 * Pre-gen6, the register file of the EUs was shared between threads,
1632 * and each thread used some subset allocated on a 16-register block
1633 * granularity. The unit states wanted these block counts.
1636 brw_register_blocks(int reg_count
)
1638 return ALIGN(reg_count
, 16) / 16 - 1;
1641 static inline uint32_t
1642 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1643 uint32_t prog_offset
)
1645 if (brw
->gen
>= 5) {
1646 /* Using state base address. */
1650 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1654 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1656 return brw
->cache
.bo
->offset64
+ prog_offset
;
1659 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1660 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1661 struct exec_list
*instructions
);
1662 bool brw_do_lower_unnormalized_offset(struct exec_list
*instructions
);
1664 struct opcode_desc
{
1670 extern const struct opcode_desc opcode_descs
[128];
1671 extern const char * const conditional_modifier
[16];
1672 extern const char *const pred_ctrl_align16
[16];
1675 brw_emit_depthbuffer(struct brw_context
*brw
);
1678 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1679 struct intel_mipmap_tree
*depth_mt
,
1680 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1681 uint32_t depth_surface_type
,
1682 struct intel_mipmap_tree
*stencil_mt
,
1683 bool hiz
, bool separate_stencil
,
1684 uint32_t width
, uint32_t height
,
1685 uint32_t tile_x
, uint32_t tile_y
);
1688 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1689 struct intel_mipmap_tree
*depth_mt
,
1690 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1691 uint32_t depth_surface_type
,
1692 struct intel_mipmap_tree
*stencil_mt
,
1693 bool hiz
, bool separate_stencil
,
1694 uint32_t width
, uint32_t height
,
1695 uint32_t tile_x
, uint32_t tile_y
);
1698 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1699 struct intel_mipmap_tree
*depth_mt
,
1700 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1701 uint32_t depth_surface_type
,
1702 struct intel_mipmap_tree
*stencil_mt
,
1703 bool hiz
, bool separate_stencil
,
1704 uint32_t width
, uint32_t height
,
1705 uint32_t tile_x
, uint32_t tile_y
);
1707 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1708 struct intel_mipmap_tree
*depth_mt
,
1709 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1710 uint32_t depth_surface_type
,
1711 struct intel_mipmap_tree
*stencil_mt
,
1712 bool hiz
, bool separate_stencil
,
1713 uint32_t width
, uint32_t height
,
1714 uint32_t tile_x
, uint32_t tile_y
);
1716 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1717 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);
1719 uint32_t get_hw_prim_for_gl_prim(int mode
);
1722 gen6_upload_push_constants(struct brw_context
*brw
,
1723 const struct gl_program
*prog
,
1724 const struct brw_stage_prog_data
*prog_data
,
1725 struct brw_stage_state
*stage_state
,
1726 enum aub_state_struct_type type
);
1729 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
1730 const struct intel_mipmap_tree
*mt
);
1732 /* brw_pipe_control.c */
1733 int brw_init_pipe_control(struct brw_context
*brw
,
1734 const struct brw_device_info
*info
);
1735 void brw_fini_pipe_control(struct brw_context
*brw
);
1737 void brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
);
1738 void brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
1739 drm_intel_bo
*bo
, uint32_t offset
,
1740 uint32_t imm_lower
, uint32_t imm_upper
);
1741 void brw_emit_mi_flush(struct brw_context
*brw
);
1742 void brw_emit_post_sync_nonzero_flush(struct brw_context
*brw
);
1743 void brw_emit_depth_stall_flushes(struct brw_context
*brw
);
1744 void gen7_emit_vs_workaround_flush(struct brw_context
*brw
);
1745 void gen7_emit_cs_stall_flush(struct brw_context
*brw
);