2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
37 #include "main/macros.h"
38 #include "main/mtypes.h"
39 #include "brw_structs.h"
40 #include "brw_compiler.h"
41 #include "intel_aub.h"
44 #include "blorp/blorp.h"
46 #include <intel_bufmgr.h>
48 #include "intel_debug.h"
49 #include "intel_screen.h"
50 #include "intel_tex_obj.h"
51 #include "intel_resolve_map.h"
58 * URB - uniform resource buffer. A mid-sized buffer which is
59 * partitioned between the fixed function units and used for passing
60 * values (vertices, primitives, constants) between them.
62 * CURBE - constant URB entry. An urb region (entry) used to hold
63 * constant values which the fixed function units can be instructed to
64 * preload into the GRF when spawning a thread.
66 * VUE - vertex URB entry. An urb entry holding a vertex and usually
67 * a vertex header. The header contains control information and
68 * things like primitive type, Begin/end flags and clip codes.
70 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
71 * unit holding rasterization and interpolation parameters.
73 * GRF - general register file. One of several register files
74 * addressable by programmed threads. The inputs (r0, payload, curbe,
75 * urb) of the thread are preloaded to this area before the thread is
76 * spawned. The registers are individually 8 dwords wide and suitable
77 * for general usage. Registers holding thread input values are not
78 * special and may be overwritten.
80 * MRF - message register file. Threads communicate (and terminate)
81 * by sending messages. Message parameters are placed in contiguous
82 * MRF registers. All program output is via these messages. URB
83 * entries are populated by sending a message to the shared URB
84 * function containing the new data, together with a control word,
85 * often an unmodified copy of R0.
87 * R0 - GRF register 0. Typically holds control information used when
88 * sending messages to other threads.
90 * EU or GEN4 EU: The name of the programmable subsystem of the
91 * i965 hardware. Threads are executed by the EU, the registers
92 * described above are part of the EU architecture.
94 * Fixed function units:
96 * CS - Command streamer. Notional first unit, little software
97 * interaction. Holds the URB entries used for constant data, ie the
100 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
101 * this unit is responsible for pulling vertices out of vertex buffers
102 * in vram and injecting them into the processing pipe as VUEs. If
103 * enabled, it first passes them to a VS thread which is a good place
104 * for the driver to implement any active vertex shader.
106 * HS - Hull Shader (Tessellation Control Shader)
108 * TE - Tessellation Engine (Tessellation Primitive Generation)
110 * DS - Domain Shader (Tessellation Evaluation Shader)
112 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
113 * enabled, incoming strips etc are passed to GS threads in individual
114 * line/triangle/point units. The GS thread may perform arbitary
115 * computation and emit whatever primtives with whatever vertices it
116 * chooses. This makes GS an excellent place to implement GL's
117 * unfilled polygon modes, though of course it is capable of much
118 * more. Additionally, GS is used to translate away primitives not
119 * handled by latter units, including Quads and Lineloops.
121 * CS - Clipper. Mesa's clipping algorithms are imported to run on
122 * this unit. The fixed function part performs cliptesting against
123 * the 6 fixed clipplanes and makes descisions on whether or not the
124 * incoming primitive needs to be passed to a thread for clipping.
125 * User clip planes are handled via cooperation with the VS thread.
127 * SF - Strips Fans or Setup: Triangles are prepared for
128 * rasterization. Interpolation coefficients are calculated.
129 * Flatshading and two-side lighting usually performed here.
131 * WM - Windower. Interpolation of vertex attributes performed here.
132 * Fragment shader implemented here. SIMD aspects of EU taken full
133 * advantage of, as pixels are processed in blocks of 16.
135 * CC - Color Calculator. No EU threads associated with this unit.
136 * Handles blending and (presumably) depth and stencil testing.
141 struct brw_vs_prog_key
;
142 struct brw_vue_prog_key
;
143 struct brw_wm_prog_key
;
144 struct brw_wm_prog_data
;
145 struct brw_cs_prog_key
;
146 struct brw_cs_prog_data
;
150 BRW_COMPUTE_PIPELINE
,
157 BRW_CACHE_BLORP_PROG
,
160 BRW_CACHE_FF_GS_PROG
,
171 /* brw_cache_ids must come first - see brw_program_cache.c */
172 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
173 BRW_STATE_FRAGMENT_PROGRAM
,
174 BRW_STATE_GEOMETRY_PROGRAM
,
175 BRW_STATE_TESS_PROGRAMS
,
176 BRW_STATE_VERTEX_PROGRAM
,
177 BRW_STATE_CURBE_OFFSETS
,
178 BRW_STATE_REDUCED_PRIMITIVE
,
179 BRW_STATE_PATCH_PRIMITIVE
,
184 BRW_STATE_BINDING_TABLE_POINTERS
,
187 BRW_STATE_DEFAULT_TESS_LEVELS
,
189 BRW_STATE_INDEX_BUFFER
,
190 BRW_STATE_VS_CONSTBUF
,
191 BRW_STATE_TCS_CONSTBUF
,
192 BRW_STATE_TES_CONSTBUF
,
193 BRW_STATE_GS_CONSTBUF
,
194 BRW_STATE_PROGRAM_CACHE
,
195 BRW_STATE_STATE_BASE_ADDRESS
,
196 BRW_STATE_VUE_MAP_GEOM_OUT
,
197 BRW_STATE_TRANSFORM_FEEDBACK
,
198 BRW_STATE_RASTERIZER_DISCARD
,
200 BRW_STATE_UNIFORM_BUFFER
,
201 BRW_STATE_ATOMIC_BUFFER
,
202 BRW_STATE_IMAGE_UNITS
,
203 BRW_STATE_META_IN_PROGRESS
,
204 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
205 BRW_STATE_NUM_SAMPLES
,
206 BRW_STATE_TEXTURE_BUFFER
,
207 BRW_STATE_GEN4_UNIT_STATE
,
211 BRW_STATE_SAMPLER_STATE_TABLE
,
212 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
213 BRW_STATE_COMPUTE_PROGRAM
,
214 BRW_STATE_CS_WORK_GROUPS
,
218 BRW_STATE_VIEWPORT_COUNT
,
219 BRW_STATE_CONSERVATIVE_RASTERIZATION
,
224 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
226 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
227 * When the currently bound shader program differs from the previous draw
228 * call, these will be flagged. They cover brw->{stage}_program and
229 * ctx->{Stage}Program->_Current.
231 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
232 * driver perspective. Even if the same shader is bound at the API level,
233 * we may need to switch between multiple versions of that shader to handle
234 * changes in non-orthagonal state.
236 * Additionally, multiple shader programs may have identical vertex shaders
237 * (for example), or compile down to the same code in the backend. We combine
238 * those into a single program cache entry.
240 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
241 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
243 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
244 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
245 * use the normal state upload paths), but the cache is still used. To avoid
246 * polluting the brw_program_cache code with special cases, we retain the
247 * dirty bit for now. It should eventually be removed.
249 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_PROG)
250 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
251 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
252 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
253 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
254 #define BRW_NEW_TCS_PROG_DATA (1ull << BRW_CACHE_TCS_PROG)
255 #define BRW_NEW_TES_PROG_DATA (1ull << BRW_CACHE_TES_PROG)
256 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
257 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
258 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
259 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
260 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
261 #define BRW_NEW_TESS_PROGRAMS (1ull << BRW_STATE_TESS_PROGRAMS)
262 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
263 #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
264 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
265 #define BRW_NEW_PATCH_PRIMITIVE (1ull << BRW_STATE_PATCH_PRIMITIVE)
266 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
267 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
268 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
269 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
270 #define BRW_NEW_BINDING_TABLE_POINTERS (1ull << BRW_STATE_BINDING_TABLE_POINTERS)
271 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
272 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
273 #define BRW_NEW_DEFAULT_TESS_LEVELS (1ull << BRW_STATE_DEFAULT_TESS_LEVELS)
275 * Used for any batch entry with a relocated pointer that will be used
276 * by any 3D rendering.
278 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
279 /** \see brw.state.depth_region */
280 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
281 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
282 #define BRW_NEW_TCS_CONSTBUF (1ull << BRW_STATE_TCS_CONSTBUF)
283 #define BRW_NEW_TES_CONSTBUF (1ull << BRW_STATE_TES_CONSTBUF)
284 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
285 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
286 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
287 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
288 #define BRW_NEW_VIEWPORT_COUNT (1ull << BRW_STATE_VIEWPORT_COUNT)
289 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
290 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
291 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
292 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
293 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
294 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
295 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
296 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
297 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
298 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
299 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
300 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
301 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
302 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
303 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
304 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
305 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
306 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
307 #define BRW_NEW_URB_SIZE (1ull << BRW_STATE_URB_SIZE)
308 #define BRW_NEW_CC_STATE (1ull << BRW_STATE_CC_STATE)
309 #define BRW_NEW_BLORP (1ull << BRW_STATE_BLORP)
310 #define BRW_NEW_CONSERVATIVE_RASTERIZATION (1ull << BRW_STATE_CONSERVATIVE_RASTERIZATION)
312 struct brw_state_flags
{
313 /** State update flags signalled by mesa internals */
316 * State update flags signalled as the result of brw_tracked_state updates
322 /** Subclass of Mesa program */
324 struct gl_program program
;
331 struct brw_sf_prog_data
{
332 GLuint urb_read_length
;
335 /* Each vertex may have upto 12 attributes, 4 components each,
336 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
339 * Actually we use 4 for each, so call it 12 rows.
341 GLuint urb_entry_size
;
345 struct brw_clip_prog_data
{
346 GLuint curb_read_length
; /* user planes? */
348 GLuint urb_read_length
;
352 struct brw_ff_gs_prog_data
{
353 GLuint urb_read_length
;
357 * Gen6 transform feedback: Amount by which the streaming vertex buffer
358 * indices should be incremented each time the GS is invoked.
360 unsigned svbi_postincrement_value
;
363 /** Number of texture sampler units */
364 #define BRW_MAX_TEX_UNIT 32
366 /** Max number of render targets in a shader */
367 #define BRW_MAX_DRAW_BUFFERS 8
369 /** Max number of UBOs in a shader */
370 #define BRW_MAX_UBO 14
372 /** Max number of SSBOs in a shader */
373 #define BRW_MAX_SSBO 12
375 /** Max number of atomic counter buffer objects in a shader */
376 #define BRW_MAX_ABO 16
378 /** Max number of image uniforms in a shader */
379 #define BRW_MAX_IMAGES 32
382 * Max number of binding table entries used for stream output.
384 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
385 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
387 * On Gen6, the size of transform feedback data is limited not by the number
388 * of components but by the number of binding table entries we set aside. We
389 * use one binding table entry for a float, one entry for a vector, and one
390 * entry per matrix column. Since the only way we can communicate our
391 * transform feedback capabilities to the client is via
392 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
393 * worst case, in which all the varyings are floats, so we use up one binding
394 * table entry per component. Therefore we need to set aside at least 64
395 * binding table entries for use by transform feedback.
397 * Note: since we don't currently pack varyings, it is currently impossible
398 * for the client to actually use up all of these binding table entries--if
399 * all of their varyings were floats, they would run out of varying slots and
400 * fail to link. But that's a bug, so it seems prudent to go ahead and
401 * allocate the number of binding table entries we will need once the bug is
404 #define BRW_MAX_SOL_BINDINGS 64
406 /** Maximum number of actual buffers used for stream output */
407 #define BRW_MAX_SOL_BUFFERS 4
409 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
410 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
415 2 + /* shader time, pull constants */ \
416 1 /* cs num work groups */)
418 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
421 * Stride in bytes between shader_time entries.
423 * We separate entries by a cacheline to reduce traffic between EUs writing to
426 #define SHADER_TIME_STRIDE 64
429 struct brw_context
*brw
;
431 struct brw_cache_item
**items
;
433 GLuint size
, n_items
;
435 uint32_t next_offset
;
440 /* Considered adding a member to this struct to document which flags
441 * an update might raise so that ordering of the state atoms can be
442 * checked or derived at runtime. Dropped the idea in favor of having
443 * a debug mode where the state is monitored for flags which are
444 * raised that have already been tested against.
446 struct brw_tracked_state
{
447 struct brw_state_flags dirty
;
448 void (*emit
)( struct brw_context
*brw
);
451 enum shader_time_shader_type
{
462 struct brw_vertex_buffer
{
463 /** Buffer object containing the uploaded vertex data */
467 /** Byte stride between elements in the uploaded array */
471 struct brw_vertex_element
{
472 const struct gl_vertex_array
*glarray
;
476 /** Offset of the first element within the buffer object */
480 struct brw_query_object
{
481 struct gl_query_object Base
;
483 /** Last query BO associated with this query. */
486 /** Last index in bo with query data for this object. */
489 /** True if we know the batch has been flushed since we ended the query. */
499 struct intel_batchbuffer
{
500 /** Current batchbuffer being queued up. */
502 /** Last BO submitted to the hardware. Used for glFinish(). */
503 drm_intel_bo
*last_bo
;
506 uint16_t emit
, total
;
508 uint16_t reserved_space
;
512 #define BATCH_SZ (8192*sizeof(uint32_t))
514 uint32_t state_batch_offset
;
515 enum brw_gpu_ring ring
;
516 bool needs_sol_reset
;
517 bool state_base_address_emitted
;
525 #define BRW_MAX_XFB_STREAMS 4
527 struct brw_transform_feedback_object
{
528 struct gl_transform_feedback_object base
;
530 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
531 drm_intel_bo
*offset_bo
;
533 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
536 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
537 GLenum primitive_mode
;
540 * The maximum number of vertices that we can write without overflowing
541 * any of the buffers currently being used for transform feedback.
546 * Count of primitives generated during this transform feedback operation.
549 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
550 drm_intel_bo
*prim_count_bo
;
551 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
555 * Number of vertices written between last Begin/EndTransformFeedback().
557 * Used to implement DrawTransformFeedback().
559 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
560 bool vertices_written_valid
;
564 * Data shared between each programmable stage in the pipeline (vs, gs, and
567 struct brw_stage_state
569 gl_shader_stage stage
;
570 struct brw_stage_prog_data
*prog_data
;
573 * Optional scratch buffer used to store spilled register values and
574 * variably-indexed GRF arrays.
576 * The contents of this buffer are short-lived so the same memory can be
577 * re-used at will for multiple shader programs (executed by the same fixed
578 * function). However reusing a scratch BO for which shader invocations
579 * are still in flight with a per-thread scratch slot size other than the
580 * original can cause threads with different scratch slot size and FFTID
581 * (which may be executed in parallel depending on the shader stage and
582 * hardware generation) to map to an overlapping region of the scratch
583 * space, which can potentially lead to mutual scratch space corruption.
584 * For that reason if you borrow this scratch buffer you should only be
585 * using the slot size given by the \c per_thread_scratch member below,
586 * unless you're taking additional measures to synchronize thread execution
587 * across slot size changes.
589 drm_intel_bo
*scratch_bo
;
592 * Scratch slot size allocated for each thread in the buffer object given
595 uint32_t per_thread_scratch
;
597 /** Offset in the program cache to the program */
598 uint32_t prog_offset
;
600 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
601 uint32_t state_offset
;
603 uint32_t push_const_offset
; /* Offset in the batchbuffer */
604 int push_const_size
; /* in 256-bit register increments */
606 /* Binding table: pointers to SURFACE_STATE entries. */
607 uint32_t bind_bo_offset
;
608 uint32_t surf_offset
[BRW_MAX_SURFACES
];
610 /** SAMPLER_STATE count and table offset */
611 uint32_t sampler_count
;
612 uint32_t sampler_offset
;
615 enum brw_predicate_state
{
616 /* The first two states are used if we can determine whether to draw
617 * without having to look at the values in the query object buffer. This
618 * will happen if there is no conditional render in progress, if the query
619 * object is already completed or if something else has already added
620 * samples to the preliminary result such as via a BLT command.
622 BRW_PREDICATE_STATE_RENDER
,
623 BRW_PREDICATE_STATE_DONT_RENDER
,
624 /* In this case whether to draw or not depends on the result of an
625 * MI_PREDICATE command so the predicate enable bit needs to be checked.
627 BRW_PREDICATE_STATE_USE_BIT
632 struct gen_l3_config
;
634 enum brw_query_kind
{
638 struct brw_perf_query_info
640 enum brw_query_kind kind
;
642 struct brw_perf_query_counter
*counters
;
648 * brw_context is derived from gl_context.
652 struct gl_context ctx
; /**< base class, must be first field */
656 uint32_t (*update_renderbuffer_surface
)(struct brw_context
*brw
,
657 struct gl_renderbuffer
*rb
,
658 uint32_t flags
, unsigned unit
,
659 uint32_t surf_index
);
660 void (*emit_null_surface_state
)(struct brw_context
*brw
,
664 uint32_t *out_offset
);
667 * Send the appropriate state packets to configure depth, stencil, and
668 * HiZ buffers (i965+ only)
670 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
671 struct intel_mipmap_tree
*depth_mt
,
672 uint32_t depth_offset
,
673 uint32_t depthbuffer_format
,
674 uint32_t depth_surface_type
,
675 struct intel_mipmap_tree
*stencil_mt
,
676 bool hiz
, bool separate_stencil
,
677 uint32_t width
, uint32_t height
,
678 uint32_t tile_x
, uint32_t tile_y
);
684 drm_intel_context
*hw_ctx
;
686 /** BO for post-sync nonzero writes for gen6 workaround. */
687 drm_intel_bo
*workaround_bo
;
688 uint8_t pipe_controls_since_last_cs_stall
;
691 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
692 * and would need flushing before being used from another cache domain that
693 * isn't coherent with it (i.e. the sampler).
695 struct set
*render_cache
;
698 * Number of resets observed in the system at context creation.
700 * This is tracked in the context so that we can determine that another
701 * reset has occurred.
703 uint32_t reset_count
;
705 struct intel_batchbuffer batch
;
710 uint32_t next_offset
;
714 * Set if rendering has occurred to the drawable's front buffer.
716 * This is used in the DRI2 case to detect that glFlush should also copy
717 * the contents of the fake front buffer to the real front buffer.
719 bool front_buffer_dirty
;
721 /** Framerate throttling: @{ */
722 drm_intel_bo
*throttle_batch
[2];
724 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
725 * frame of rendering to complete. This gives a very precise cap to the
726 * latency between input and output such that rendering never gets more
727 * than a frame behind the user. (With the caveat that we technically are
728 * not using the SwapBuffers itself as a barrier but the first batch
729 * submitted afterwards, which may be immediately prior to the next
732 bool need_swap_throttle
;
734 /** General throttling, not caught by throttling between SwapBuffers */
735 bool need_flush_throttle
;
745 bool always_flush_batch
;
746 bool always_flush_cache
;
747 bool disable_throttling
;
749 bool dual_color_blend_by_location
;
751 driOptionCache optionCache
;
754 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
756 GLenum reduced_primitive
;
759 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
760 * variable is set, this is the flag indicating to do expensive work that
761 * might lead to a perf_debug() call.
765 uint64_t max_gtt_map_object_size
;
777 bool has_separate_stencil
;
778 bool must_use_separate_stencil
;
781 bool has_surface_tile_offset
;
783 bool has_negative_rhw_bug
;
787 bool use_resource_streamer
;
790 * Some versions of Gen hardware don't do centroid interpolation correctly
791 * on unlit pixels, causing incorrect values for derivatives near triangle
792 * edges. Enabling this flag causes the fragment shader to use
793 * non-centroid interpolation for unlit pixels, at the expense of two extra
794 * fragment shader instructions.
796 bool needs_unlit_centroid_workaround
;
798 struct isl_device isl_dev
;
800 struct blorp_context blorp
;
804 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
807 enum brw_pipeline last_pipeline
;
809 struct brw_cache cache
;
811 /** IDs for meta stencil blit shader programs. */
812 struct gl_shader_program
*meta_stencil_blit_programs
[2];
814 /* Whether a meta-operation is in progress. */
815 bool meta_in_progress
;
817 /* Whether the last depth/stencil packets were both NULL. */
818 bool no_depth_or_stencil
;
820 /* The last PMA stall bits programmed. */
821 uint32_t pma_stall_bits
;
825 /** The value of gl_BaseVertex for the current _mesa_prim. */
828 /** The value of gl_BaseInstance for the current _mesa_prim. */
833 * Buffer and offset used for GL_ARB_shader_draw_parameters
834 * (for now, only gl_BaseVertex).
836 drm_intel_bo
*draw_params_bo
;
837 uint32_t draw_params_offset
;
840 * The value of gl_DrawID for the current _mesa_prim. This always comes
841 * in from it's own vertex buffer since it's not part of the indirect
845 drm_intel_bo
*draw_id_bo
;
846 uint32_t draw_id_offset
;
851 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
852 * an indirect call, and num_work_groups_offset is valid. Otherwise,
853 * num_work_groups is set based on glDispatchCompute.
855 drm_intel_bo
*num_work_groups_bo
;
856 GLintptr num_work_groups_offset
;
857 const GLuint
*num_work_groups
;
861 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
862 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
864 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
868 /* Summary of size and varying of active arrays, so we can check
869 * for changes to this state:
871 bool index_bounds_valid
;
872 unsigned int min_index
, max_index
;
874 /* Offset from start of vertex buffer so we can avoid redefining
875 * the same VB packed over and over again.
877 unsigned int start_vertex_bias
;
880 * Certain vertex attribute formats aren't natively handled by the
881 * hardware and require special VS code to fix up their values.
883 * These bitfields indicate which workarounds are needed.
885 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
890 * Index buffer for this draw_prims call.
892 * Updates are signaled by BRW_NEW_INDICES.
894 const struct _mesa_index_buffer
*ib
;
896 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
901 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
902 * avoid re-uploading the IB packet over and over if we're actually
903 * referencing the same index buffer.
905 unsigned int start_vertex_offset
;
908 /* Active vertex program:
910 const struct gl_program
*vertex_program
;
911 const struct gl_program
*geometry_program
;
912 const struct gl_program
*tess_ctrl_program
;
913 const struct gl_program
*tess_eval_program
;
914 const struct gl_program
*fragment_program
;
915 const struct gl_program
*compute_program
;
918 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
919 * that we don't have to reemit that state every time we change FBOs.
923 /* BRW_NEW_URB_ALLOCATIONS:
926 GLuint vsize
; /* vertex size plus header in urb registers */
927 GLuint gsize
; /* GS output size in urb registers */
928 GLuint hsize
; /* Tessellation control output size in urb registers */
929 GLuint dsize
; /* Tessellation evaluation output size in urb registers */
930 GLuint csize
; /* constant buffer size in urb registers */
931 GLuint sfsize
; /* setup data size in urb registers */
935 GLuint nr_vs_entries
;
936 GLuint nr_hs_entries
;
937 GLuint nr_ds_entries
;
938 GLuint nr_gs_entries
;
939 GLuint nr_clip_entries
;
940 GLuint nr_sf_entries
;
941 GLuint nr_cs_entries
;
951 * URB size in the current configuration. The units this is expressed
952 * in are somewhat inconsistent, see gen_device_info::urb::size.
954 * FINISHME: Represent the URB size consistently in KB on all platforms.
958 /* True if the most recently sent _3DSTATE_URB message allocated
959 * URB space for the GS.
963 /* True if the most recently sent _3DSTATE_URB message allocated
964 * URB space for the HS and DS.
970 /* BRW_NEW_CURBE_OFFSETS:
973 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
974 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
982 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
983 * for upload to the CURBE.
985 drm_intel_bo
*curbe_bo
;
986 /** Offset within curbe_bo of space for current curbe entry */
991 * Layout of vertex data exiting the geometry portion of the pipleine.
992 * This comes from the last enabled shader stage (GS, DS, or VS).
994 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
996 struct brw_vue_map vue_map_geom_out
;
999 struct brw_stage_state base
;
1003 struct brw_stage_state base
;
1006 * True if the 3DSTATE_HS command most recently emitted to the 3D
1007 * pipeline enabled the HS; false otherwise.
1013 struct brw_stage_state base
;
1016 * True if the 3DSTATE_DS command most recently emitted to the 3D
1017 * pipeline enabled the DS; false otherwise.
1023 struct brw_stage_state base
;
1026 * True if the 3DSTATE_GS command most recently emitted to the 3D
1027 * pipeline enabled the GS; false otherwise.
1033 struct brw_ff_gs_prog_data
*prog_data
;
1036 /** Offset in the program cache to the CLIP program pre-gen6 */
1037 uint32_t prog_offset
;
1038 uint32_t state_offset
;
1040 uint32_t bind_bo_offset
;
1042 * Surface offsets for the binding table. We only need surfaces to
1043 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1044 * need in this case.
1046 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1050 struct brw_clip_prog_data
*prog_data
;
1052 /** Offset in the program cache to the CLIP program pre-gen6 */
1053 uint32_t prog_offset
;
1055 /* Offset in the batch to the CLIP state on pre-gen6. */
1056 uint32_t state_offset
;
1058 /* As of gen6, this is the offset in the batch to the CLIP VP,
1064 * The number of viewports to use. If gl_ViewportIndex is written,
1065 * we can have up to ctx->Const.MaxViewports viewports. If not,
1066 * the viewport index is always 0, so we can only emit one.
1068 uint8_t viewport_count
;
1073 struct brw_sf_prog_data
*prog_data
;
1075 /** Offset in the program cache to the CLIP program pre-gen6 */
1076 uint32_t prog_offset
;
1077 uint32_t state_offset
;
1079 bool viewport_transform_enable
;
1083 struct brw_stage_state base
;
1088 * Buffer object used in place of multisampled null render targets on
1089 * Gen6. See brw_emit_null_surface_state().
1091 drm_intel_bo
*multisampled_null_render_target_bo
;
1092 uint32_t fast_clear_op
;
1098 struct brw_stage_state base
;
1101 /* RS hardware binding table */
1104 uint32_t next_offset
;
1108 uint32_t state_offset
;
1109 uint32_t blend_state_offset
;
1110 uint32_t depth_stencil_state_offset
;
1115 struct brw_query_object
*obj
;
1120 enum brw_predicate_state state
;
1125 struct brw_perf_query_info
*queries
;
1128 int n_active_pipeline_stats_queries
;
1131 int num_atoms
[BRW_NUM_PIPELINES
];
1132 const struct brw_tracked_state render_atoms
[76];
1133 const struct brw_tracked_state compute_atoms
[11];
1135 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1139 enum aub_state_struct_type type
;
1141 } *state_batch_list
;
1142 int state_batch_count
;
1144 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1145 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1147 /* PrimitiveRestart */
1150 bool enable_cut_index
;
1153 /** Computed depth/stencil/hiz state from the current attached
1154 * renderbuffers, valid only during the drawing state upload loop after
1155 * brw_workaround_depthstencil_alignment().
1158 struct intel_mipmap_tree
*depth_mt
;
1159 struct intel_mipmap_tree
*stencil_mt
;
1161 /* Inter-tile (page-aligned) byte offsets. */
1162 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1163 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1164 uint32_t tile_x
, tile_y
;
1167 uint32_t num_instances
;
1172 const struct gen_l3_config
*config
;
1179 enum shader_time_shader_type
*types
;
1180 struct shader_times
*cumulative
;
1186 struct brw_fast_clear_state
*fast_clear_state
;
1188 /* Array of flags telling if auxiliary buffer is disabled for corresponding
1189 * renderbuffer. If draw_aux_buffer_disabled[i] is set then use of
1190 * auxiliary buffer for gl_framebuffer::_ColorDrawBuffers[i] is
1192 * This is needed in case the same underlying buffer is also configured
1193 * to be sampled but with a format that the sampling engine can't treat
1194 * compressed or fast cleared.
1196 bool draw_aux_buffer_disabled
[MAX_DRAW_BUFFERS
];
1198 __DRIcontext
*driContext
;
1199 struct intel_screen
*screen
;
1203 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1205 /*======================================================================
1208 extern const char *const brw_vendor_string
;
1211 brw_get_renderer_string(const struct intel_screen
*screen
);
1214 DRI_CONF_BO_REUSE_DISABLED
,
1215 DRI_CONF_BO_REUSE_ALL
1218 void intel_update_renderbuffers(__DRIcontext
*context
,
1219 __DRIdrawable
*drawable
);
1220 void intel_prepare_render(struct brw_context
*brw
);
1222 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1223 __DRIdrawable
*drawable
);
1225 GLboolean
brwCreateContext(gl_api api
,
1226 const struct gl_config
*mesaVis
,
1227 __DRIcontext
*driContextPriv
,
1228 unsigned major_version
,
1229 unsigned minor_version
,
1233 void *sharedContextPrivate
);
1235 /*======================================================================
1239 brw_meta_resolve_color(struct brw_context
*brw
,
1240 struct intel_mipmap_tree
*mt
);
1242 /*======================================================================
1245 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1246 GLbitfield clear_mask
);
1248 /* brw_object_purgeable.c */
1249 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1251 /*======================================================================
1254 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1255 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1256 void brw_emit_query_begin(struct brw_context
*brw
);
1257 void brw_emit_query_end(struct brw_context
*brw
);
1258 void brw_query_counter(struct gl_context
*ctx
, struct gl_query_object
*q
);
1259 bool brw_is_query_pipelined(struct brw_query_object
*query
);
1261 /** gen6_queryobj.c */
1262 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1263 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1264 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1266 /** hsw_queryobj.c */
1267 void hsw_overflow_result_to_gpr0(struct brw_context
*brw
,
1268 struct brw_query_object
*query
,
1270 void hsw_init_queryobj_functions(struct dd_function_table
*functions
);
1272 /** brw_conditional_render.c */
1273 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1274 bool brw_check_conditional_render(struct brw_context
*brw
);
1276 /** intel_batchbuffer.c */
1277 void brw_load_register_mem(struct brw_context
*brw
,
1280 uint32_t read_domains
, uint32_t write_domain
,
1282 void brw_load_register_mem64(struct brw_context
*brw
,
1285 uint32_t read_domains
, uint32_t write_domain
,
1287 void brw_store_register_mem32(struct brw_context
*brw
,
1288 drm_intel_bo
*bo
, uint32_t reg
, uint32_t offset
);
1289 void brw_store_register_mem64(struct brw_context
*brw
,
1290 drm_intel_bo
*bo
, uint32_t reg
, uint32_t offset
);
1291 void brw_load_register_imm32(struct brw_context
*brw
,
1292 uint32_t reg
, uint32_t imm
);
1293 void brw_load_register_imm64(struct brw_context
*brw
,
1294 uint32_t reg
, uint64_t imm
);
1295 void brw_load_register_reg(struct brw_context
*brw
, uint32_t src
,
1297 void brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
,
1299 void brw_store_data_imm32(struct brw_context
*brw
, drm_intel_bo
*bo
,
1300 uint32_t offset
, uint32_t imm
);
1301 void brw_store_data_imm64(struct brw_context
*brw
, drm_intel_bo
*bo
,
1302 uint32_t offset
, uint64_t imm
);
1304 /*======================================================================
1307 void brw_debug_batch(struct brw_context
*brw
);
1308 void brw_annotate_aub(struct brw_context
*brw
);
1310 /*======================================================================
1311 * intel_tex_validate.c
1313 void brw_validate_textures( struct brw_context
*brw
);
1316 /*======================================================================
1320 key_debug(struct brw_context
*brw
, const char *name
, int a
, int b
)
1323 perf_debug(" %s %d->%d\n", name
, a
, b
);
1329 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1331 void brw_get_scratch_bo(struct brw_context
*brw
,
1332 drm_intel_bo
**scratch_bo
, int size
);
1333 void brw_alloc_stage_scratch(struct brw_context
*brw
,
1334 struct brw_stage_state
*stage_state
,
1335 unsigned per_thread_size
,
1336 unsigned thread_count
);
1337 void brw_init_shader_time(struct brw_context
*brw
);
1338 int brw_get_shader_time_index(struct brw_context
*brw
,
1339 struct gl_program
*prog
,
1340 enum shader_time_shader_type type
,
1342 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1343 void brw_destroy_shader_time(struct brw_context
*brw
);
1347 void brw_upload_urb_fence(struct brw_context
*brw
);
1351 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1354 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1356 /* brw_draw_upload.c */
1357 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1358 const struct gl_vertex_array
*glarray
);
1360 static inline unsigned
1361 brw_get_index_type(GLenum type
)
1363 assert((type
== GL_UNSIGNED_BYTE
)
1364 || (type
== GL_UNSIGNED_SHORT
)
1365 || (type
== GL_UNSIGNED_INT
));
1367 /* The possible values for type are GL_UNSIGNED_BYTE (0x1401),
1368 * GL_UNSIGNED_SHORT (0x1403), and GL_UNSIGNED_INT (0x1405) which we want
1369 * to map to scale factors of 0, 1, and 2, respectively. These scale
1370 * factors are then left-shfited by 8 to be in the correct position in the
1371 * CMD_INDEX_BUFFER packet.
1373 * Subtracting 0x1401 gives 0, 2, and 4. Shifting left by 7 afterwards
1374 * gives 0x00000000, 0x00000100, and 0x00000200. These just happen to be
1375 * the values the need to be written in the CMD_INDEX_BUFFER packet.
1377 return (type
- 0x1401) << 7;
1380 void brw_prepare_vertices(struct brw_context
*brw
);
1382 /* brw_wm_surface_state.c */
1383 void brw_init_surface_formats(struct brw_context
*brw
);
1384 void brw_create_constant_surface(struct brw_context
*brw
,
1388 uint32_t *out_offset
);
1389 void brw_create_buffer_surface(struct brw_context
*brw
,
1393 uint32_t *out_offset
);
1394 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1396 uint32_t *surf_offset
);
1398 brw_update_sol_surface(struct brw_context
*brw
,
1399 struct gl_buffer_object
*buffer_obj
,
1400 uint32_t *out_offset
, unsigned num_vector_components
,
1401 unsigned stride_dwords
, unsigned offset_dwords
);
1402 void brw_upload_ubo_surfaces(struct brw_context
*brw
, struct gl_program
*prog
,
1403 struct brw_stage_state
*stage_state
,
1404 struct brw_stage_prog_data
*prog_data
);
1405 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1406 const struct gl_program
*prog
,
1407 struct brw_stage_state
*stage_state
,
1408 struct brw_stage_prog_data
*prog_data
);
1409 void brw_upload_image_surfaces(struct brw_context
*brw
,
1410 const struct gl_program
*prog
,
1411 struct brw_stage_state
*stage_state
,
1412 struct brw_stage_prog_data
*prog_data
);
1414 /* brw_surface_formats.c */
1415 bool brw_render_target_supported(struct brw_context
*brw
,
1416 struct gl_renderbuffer
*rb
);
1417 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1419 /* brw_performance_query.c */
1420 void brw_init_performance_queries(struct brw_context
*brw
);
1422 /* intel_buffer_objects.c */
1423 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1424 const char *bo_name
);
1425 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1426 const char *bo_name
);
1428 /* intel_extensions.c */
1429 extern void intelInitExtensions(struct gl_context
*ctx
);
1432 extern int intel_translate_shadow_compare_func(GLenum func
);
1433 extern int intel_translate_compare_func(GLenum func
);
1434 extern int intel_translate_stencil_op(GLenum op
);
1435 extern int intel_translate_logic_op(GLenum opcode
);
1438 void brw_init_syncobj_functions(struct dd_function_table
*functions
);
1441 struct gl_transform_feedback_object
*
1442 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1444 brw_delete_transform_feedback(struct gl_context
*ctx
,
1445 struct gl_transform_feedback_object
*obj
);
1447 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1448 struct gl_transform_feedback_object
*obj
);
1450 brw_end_transform_feedback(struct gl_context
*ctx
,
1451 struct gl_transform_feedback_object
*obj
);
1453 brw_pause_transform_feedback(struct gl_context
*ctx
,
1454 struct gl_transform_feedback_object
*obj
);
1456 brw_resume_transform_feedback(struct gl_context
*ctx
,
1457 struct gl_transform_feedback_object
*obj
);
1459 brw_save_primitives_written_counters(struct brw_context
*brw
,
1460 struct brw_transform_feedback_object
*obj
);
1462 brw_compute_xfb_vertices_written(struct brw_context
*brw
,
1463 struct brw_transform_feedback_object
*obj
);
1465 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1466 struct gl_transform_feedback_object
*obj
,
1469 /* gen7_sol_state.c */
1471 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1472 struct gl_transform_feedback_object
*obj
);
1474 gen7_end_transform_feedback(struct gl_context
*ctx
,
1475 struct gl_transform_feedback_object
*obj
);
1477 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1478 struct gl_transform_feedback_object
*obj
);
1480 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1481 struct gl_transform_feedback_object
*obj
);
1485 hsw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1486 struct gl_transform_feedback_object
*obj
);
1488 hsw_end_transform_feedback(struct gl_context
*ctx
,
1489 struct gl_transform_feedback_object
*obj
);
1491 hsw_pause_transform_feedback(struct gl_context
*ctx
,
1492 struct gl_transform_feedback_object
*obj
);
1494 hsw_resume_transform_feedback(struct gl_context
*ctx
,
1495 struct gl_transform_feedback_object
*obj
);
1497 /* brw_blorp_blit.cpp */
1499 brw_blorp_framebuffer(struct brw_context
*brw
,
1500 struct gl_framebuffer
*readFb
,
1501 struct gl_framebuffer
*drawFb
,
1502 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1503 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1504 GLbitfield mask
, GLenum filter
);
1507 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1508 struct gl_renderbuffer
*src_rb
,
1509 struct gl_texture_image
*dst_image
,
1511 int srcX0
, int srcY0
,
1512 int dstX0
, int dstY0
,
1513 int width
, int height
);
1515 /* gen6_multisample_state.c */
1517 gen6_determine_sample_mask(struct brw_context
*brw
);
1520 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1521 unsigned num_samples
);
1523 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1525 gen6_get_sample_position(struct gl_context
*ctx
,
1526 struct gl_framebuffer
*fb
,
1530 gen6_set_sample_maps(struct gl_context
*ctx
);
1532 /* gen8_multisample_state.c */
1533 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1534 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1538 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1539 unsigned hs_size
, unsigned ds_size
,
1540 unsigned gs_size
, unsigned fs_size
);
1543 gen6_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1544 bool gs_present
, unsigned gs_size
);
1546 gen7_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1547 bool gs_present
, bool tess_present
);
1551 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1553 brw_check_for_reset(struct brw_context
*brw
);
1557 brw_init_compute_functions(struct dd_function_table
*functions
);
1559 /*======================================================================
1560 * Inline conversion functions. These are better-typed than the
1561 * macros used previously:
1563 static inline struct brw_context
*
1564 brw_context( struct gl_context
*ctx
)
1566 return (struct brw_context
*)ctx
;
1569 static inline struct brw_program
*
1570 brw_program(struct gl_program
*p
)
1572 return (struct brw_program
*) p
;
1575 static inline const struct brw_program
*
1576 brw_program_const(const struct gl_program
*p
)
1578 return (const struct brw_program
*) p
;
1582 * Pre-gen6, the register file of the EUs was shared between threads,
1583 * and each thread used some subset allocated on a 16-register block
1584 * granularity. The unit states wanted these block counts.
1587 brw_register_blocks(int reg_count
)
1589 return ALIGN(reg_count
, 16) / 16 - 1;
1592 static inline uint32_t
1593 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1594 uint32_t prog_offset
)
1596 if (brw
->gen
>= 5) {
1597 /* Using state base address. */
1601 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1605 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1607 return brw
->cache
.bo
->offset64
+ prog_offset
;
1610 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1613 brw_depth_writes_enabled(const struct brw_context
*brw
)
1615 const struct gl_context
*ctx
= &brw
->ctx
;
1617 /* We consider depth writes disabled if the depth function is GL_EQUAL,
1618 * because it would just overwrite the existing depth value with itself.
1620 * These bonus depth writes not only use bandwidth, but they also can
1621 * prevent early depth processing. For example, if the pixel shader
1622 * discards, the hardware must invoke the to determine whether or not
1623 * to do the depth write. If writes are disabled, we may still be able
1624 * to do the depth test before the shader, and skip the shader execution.
1626 * The Broadwell 3DSTATE_WM_DEPTH_STENCIL documentation also contains
1627 * a programming note saying to disable depth writes for EQUAL.
1629 return ctx
->Depth
.Test
&& ctx
->Depth
.Mask
&& ctx
->Depth
.Func
!= GL_EQUAL
;
1633 brw_emit_depthbuffer(struct brw_context
*brw
);
1636 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1637 struct intel_mipmap_tree
*depth_mt
,
1638 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1639 uint32_t depth_surface_type
,
1640 struct intel_mipmap_tree
*stencil_mt
,
1641 bool hiz
, bool separate_stencil
,
1642 uint32_t width
, uint32_t height
,
1643 uint32_t tile_x
, uint32_t tile_y
);
1646 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1647 struct intel_mipmap_tree
*depth_mt
,
1648 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1649 uint32_t depth_surface_type
,
1650 struct intel_mipmap_tree
*stencil_mt
,
1651 bool hiz
, bool separate_stencil
,
1652 uint32_t width
, uint32_t height
,
1653 uint32_t tile_x
, uint32_t tile_y
);
1656 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1657 struct intel_mipmap_tree
*depth_mt
,
1658 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1659 uint32_t depth_surface_type
,
1660 struct intel_mipmap_tree
*stencil_mt
,
1661 bool hiz
, bool separate_stencil
,
1662 uint32_t width
, uint32_t height
,
1663 uint32_t tile_x
, uint32_t tile_y
);
1665 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1666 struct intel_mipmap_tree
*depth_mt
,
1667 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1668 uint32_t depth_surface_type
,
1669 struct intel_mipmap_tree
*stencil_mt
,
1670 bool hiz
, bool separate_stencil
,
1671 uint32_t width
, uint32_t height
,
1672 uint32_t tile_x
, uint32_t tile_y
);
1674 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1675 unsigned int level
, unsigned int layer
, enum blorp_hiz_op op
);
1677 uint32_t get_hw_prim_for_gl_prim(int mode
);
1680 gen6_upload_push_constants(struct brw_context
*brw
,
1681 const struct gl_program
*prog
,
1682 const struct brw_stage_prog_data
*prog_data
,
1683 struct brw_stage_state
*stage_state
,
1684 enum aub_state_struct_type type
);
1687 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
1688 const struct intel_mipmap_tree
*mt
);
1690 /* brw_pipe_control.c */
1691 int brw_init_pipe_control(struct brw_context
*brw
,
1692 const struct gen_device_info
*info
);
1693 void brw_fini_pipe_control(struct brw_context
*brw
);
1695 void brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
);
1696 void brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
1697 drm_intel_bo
*bo
, uint32_t offset
,
1698 uint32_t imm_lower
, uint32_t imm_upper
);
1699 void brw_emit_mi_flush(struct brw_context
*brw
);
1700 void brw_emit_post_sync_nonzero_flush(struct brw_context
*brw
);
1701 void brw_emit_depth_stall_flushes(struct brw_context
*brw
);
1702 void gen7_emit_vs_workaround_flush(struct brw_context
*brw
);
1703 void gen7_emit_cs_stall_flush(struct brw_context
*brw
);
1705 /* brw_queryformat.c */
1706 void brw_query_internal_format(struct gl_context
*ctx
, GLenum target
,
1707 GLenum internalFormat
, GLenum pname
,