2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
36 #include "intel_context.h"
37 #include "brw_structs.h"
38 #include "main/imports.h"
39 #include "main/macros.h"
47 * URB - uniform resource buffer. A mid-sized buffer which is
48 * partitioned between the fixed function units and used for passing
49 * values (vertices, primitives, constants) between them.
51 * CURBE - constant URB entry. An urb region (entry) used to hold
52 * constant values which the fixed function units can be instructed to
53 * preload into the GRF when spawning a thread.
55 * VUE - vertex URB entry. An urb entry holding a vertex and usually
56 * a vertex header. The header contains control information and
57 * things like primitive type, Begin/end flags and clip codes.
59 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
60 * unit holding rasterization and interpolation parameters.
62 * GRF - general register file. One of several register files
63 * addressable by programmed threads. The inputs (r0, payload, curbe,
64 * urb) of the thread are preloaded to this area before the thread is
65 * spawned. The registers are individually 8 dwords wide and suitable
66 * for general usage. Registers holding thread input values are not
67 * special and may be overwritten.
69 * MRF - message register file. Threads communicate (and terminate)
70 * by sending messages. Message parameters are placed in contiguous
71 * MRF registers. All program output is via these messages. URB
72 * entries are populated by sending a message to the shared URB
73 * function containing the new data, together with a control word,
74 * often an unmodified copy of R0.
76 * R0 - GRF register 0. Typically holds control information used when
77 * sending messages to other threads.
79 * EU or GEN4 EU: The name of the programmable subsystem of the
80 * i965 hardware. Threads are executed by the EU, the registers
81 * described above are part of the EU architecture.
83 * Fixed function units:
85 * CS - Command streamer. Notional first unit, little software
86 * interaction. Holds the URB entries used for constant data, ie the
89 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
90 * this unit is responsible for pulling vertices out of vertex buffers
91 * in vram and injecting them into the processing pipe as VUEs. If
92 * enabled, it first passes them to a VS thread which is a good place
93 * for the driver to implement any active vertex shader.
95 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
96 * enabled, incoming strips etc are passed to GS threads in individual
97 * line/triangle/point units. The GS thread may perform arbitary
98 * computation and emit whatever primtives with whatever vertices it
99 * chooses. This makes GS an excellent place to implement GL's
100 * unfilled polygon modes, though of course it is capable of much
101 * more. Additionally, GS is used to translate away primitives not
102 * handled by latter units, including Quads and Lineloops.
104 * CS - Clipper. Mesa's clipping algorithms are imported to run on
105 * this unit. The fixed function part performs cliptesting against
106 * the 6 fixed clipplanes and makes descisions on whether or not the
107 * incoming primitive needs to be passed to a thread for clipping.
108 * User clip planes are handled via cooperation with the VS thread.
110 * SF - Strips Fans or Setup: Triangles are prepared for
111 * rasterization. Interpolation coefficients are calculated.
112 * Flatshading and two-side lighting usually performed here.
114 * WM - Windower. Interpolation of vertex attributes performed here.
115 * Fragment shader implemented here. SIMD aspects of EU taken full
116 * advantage of, as pixels are processed in blocks of 16.
118 * CC - Color Calculator. No EU threads associated with this unit.
119 * Handles blending and (presumably) depth and stencil testing.
123 #define BRW_MAX_CURBE (32*16)
126 struct brw_instruction
;
127 struct brw_vs_prog_key
;
128 struct brw_wm_prog_key
;
129 struct brw_wm_prog_data
;
133 BRW_STATE_FRAGMENT_PROGRAM
,
134 BRW_STATE_VERTEX_PROGRAM
,
135 BRW_STATE_CURBE_OFFSETS
,
136 BRW_STATE_REDUCED_PRIMITIVE
,
141 BRW_STATE_VS_BINDING_TABLE
,
142 BRW_STATE_GS_BINDING_TABLE
,
143 BRW_STATE_PS_BINDING_TABLE
,
147 BRW_STATE_INDEX_BUFFER
,
148 BRW_STATE_VS_CONSTBUF
,
149 BRW_STATE_PROGRAM_CACHE
,
150 BRW_STATE_STATE_BASE_ADDRESS
,
151 BRW_STATE_SOL_INDICES
,
152 BRW_STATE_VUE_MAP_GEOM_OUT
,
153 BRW_STATE_TRANSFORM_FEEDBACK
,
154 BRW_STATE_RASTERIZER_DISCARD
,
158 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
159 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
160 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
161 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
162 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
163 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
164 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
165 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
166 #define BRW_NEW_SURFACES (1 << BRW_STATE_SURFACES)
167 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
168 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
169 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
170 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
171 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
173 * Used for any batch entry with a relocated pointer that will be used
174 * by any 3D rendering.
176 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
177 /** \see brw.state.depth_region */
178 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
179 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
180 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
181 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
182 #define BRW_NEW_SOL_INDICES (1 << BRW_STATE_SOL_INDICES)
183 #define BRW_NEW_VUE_MAP_GEOM_OUT (1 << BRW_STATE_VUE_MAP_GEOM_OUT)
184 #define BRW_NEW_TRANSFORM_FEEDBACK (1 << BRW_STATE_TRANSFORM_FEEDBACK)
185 #define BRW_NEW_RASTERIZER_DISCARD (1 << BRW_STATE_RASTERIZER_DISCARD)
186 #define BRW_NEW_STATS_WM (1 << BRW_STATE_STATS_WM)
188 struct brw_state_flags
{
189 /** State update flags signalled by mesa internals */
192 * State update flags signalled as the result of brw_tracked_state updates
195 /** State update flags signalled by brw_state_cache.c searches */
199 #define AUB_TRACE_TYPE_MASK 0x0000ff00
200 #define AUB_TRACE_TYPE_NOTYPE (0 << 8)
201 #define AUB_TRACE_TYPE_BATCH (1 << 8)
202 #define AUB_TRACE_TYPE_VERTEX_BUFFER (5 << 8)
203 #define AUB_TRACE_TYPE_2D_MAP (6 << 8)
204 #define AUB_TRACE_TYPE_CUBE_MAP (7 << 8)
205 #define AUB_TRACE_TYPE_VOLUME_MAP (9 << 8)
206 #define AUB_TRACE_TYPE_1D_MAP (10 << 8)
207 #define AUB_TRACE_TYPE_CONSTANT_BUFFER (11 << 8)
208 #define AUB_TRACE_TYPE_CONSTANT_URB (12 << 8)
209 #define AUB_TRACE_TYPE_INDEX_BUFFER (13 << 8)
210 #define AUB_TRACE_TYPE_GENERAL (14 << 8)
211 #define AUB_TRACE_TYPE_SURFACE (15 << 8)
214 * state_struct_type enum values are encoded with the top 16 bits representing
215 * the type to be delivered to the .aub file, and the bottom 16 bits
216 * representing the subtype. This macro performs the encoding.
218 #define ENCODE_SS_TYPE(type, subtype) (((type) << 16) | (subtype))
220 enum state_struct_type
{
221 AUB_TRACE_VS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 1),
222 AUB_TRACE_GS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 2),
223 AUB_TRACE_CLIP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 3),
224 AUB_TRACE_SF_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 4),
225 AUB_TRACE_WM_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 5),
226 AUB_TRACE_CC_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 6),
227 AUB_TRACE_CLIP_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 7),
228 AUB_TRACE_SF_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 8),
229 AUB_TRACE_CC_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x9),
230 AUB_TRACE_SAMPLER_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xa),
231 AUB_TRACE_KERNEL_INSTRUCTIONS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xb),
232 AUB_TRACE_SCRATCH_SPACE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xc),
233 AUB_TRACE_SAMPLER_DEFAULT_COLOR
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xd),
235 AUB_TRACE_SCISSOR_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x15),
236 AUB_TRACE_BLEND_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x16),
237 AUB_TRACE_DEPTH_STENCIL_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x17),
239 AUB_TRACE_VERTEX_BUFFER
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_VERTEX_BUFFER
, 0),
240 AUB_TRACE_BINDING_TABLE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x100),
241 AUB_TRACE_SURFACE_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x200),
242 AUB_TRACE_VS_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 0),
243 AUB_TRACE_WM_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 1),
247 * Decode a state_struct_type value to determine the type that should be
248 * stored in the .aub file.
250 static inline uint32_t AUB_TRACE_TYPE(enum state_struct_type ss_type
)
252 return (ss_type
& 0xFFFF0000) >> 16;
256 * Decode a state_struct_type value to determine the subtype that should be
257 * stored in the .aub file.
259 static inline uint32_t AUB_TRACE_SUBTYPE(enum state_struct_type ss_type
)
261 return ss_type
& 0xFFFF;
264 /** Subclass of Mesa vertex program */
265 struct brw_vertex_program
{
266 struct gl_vertex_program program
;
271 /** Subclass of Mesa fragment program */
272 struct brw_fragment_program
{
273 struct gl_fragment_program program
;
274 GLuint id
; /**< serial no. to identify frag progs, never re-used */
278 struct gl_shader base
;
282 /** Shader IR transformed for native compile, at link time. */
283 struct exec_list
*ir
;
286 /* Data about a particular attempt to compile a program. Note that
287 * there can be many of these, each in a different GL state
288 * corresponding to a different brw_wm_prog_key struct, with different
291 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
294 struct brw_wm_prog_data
{
295 GLuint curb_read_length
;
296 GLuint urb_read_length
;
298 GLuint first_curbe_grf
;
299 GLuint first_curbe_grf_16
;
301 GLuint reg_blocks_16
;
302 GLuint total_scratch
;
304 GLuint nr_params
; /**< number of float params/constants */
305 GLuint nr_pull_params
;
308 uint32_t prog_offset_16
;
311 * Mask of which interpolation modes are required by the fragment shader.
312 * Used in hardware setup on gen6+.
314 uint32_t barycentric_interp_modes
;
316 /* Pointers to tracked values (only valid once
317 * _mesa_load_state_parameters has been called at runtime).
319 * These must be the last fields of the struct (see
320 * brw_wm_prog_data_compare()).
323 const float **pull_param
;
327 * Enum representing the i965-specific vertex results that don't correspond
328 * exactly to any element of gl_varying_slot. The values of this enum are
329 * assigned such that they don't conflict with gl_varying_slot.
333 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
334 BRW_VARYING_SLOT_POS_DUPLICATE
,
335 BRW_VARYING_SLOT_PAD
,
337 * Technically this is not a varying but just a placeholder that
338 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
339 * builtin variable to be compiled correctly. see compile_sf_prog() for
342 BRW_VARYING_SLOT_PNTC
,
343 BRW_VARYING_SLOT_COUNT
348 * Data structure recording the relationship between the gl_varying_slot enum
349 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
350 * single octaword within the VUE (128 bits).
352 * Note that each BRW register contains 256 bits (2 octawords), so when
353 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
354 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
355 * in a vertex shader), each register corresponds to a single VUE slot, since
356 * it contains data for two separate vertices.
360 * Bitfield representing all varying slots that are (a) stored in this VUE
361 * map, and (b) actually written by the shader. Does not include any of
362 * the additional varying slots defined in brw_varying_slot.
364 GLbitfield64 slots_valid
;
367 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
368 * not stored in a slot (because they are not written, or because
369 * additional processing is applied before storing them in the VUE), the
372 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
375 * Map from VUE slot to gl_varying_slot value. For slots that do not
376 * directly correspond to a gl_varying_slot, the value comes from
379 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
380 * simplifies code that uses the value stored in slot_to_varying to
381 * create a bit mask).
383 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
386 * Total number of VUE slots in use
392 * Convert a VUE slot number into a byte offset within the VUE.
394 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
400 * Convert a vertex output (brw_varying_slot) into a byte offset within the
403 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
406 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
409 void brw_compute_vue_map(struct brw_context
*brw
, struct brw_vue_map
*vue_map
,
410 GLbitfield64 slots_valid
, bool userclip_active
);
413 struct brw_sf_prog_data
{
414 GLuint urb_read_length
;
417 /* Each vertex may have upto 12 attributes, 4 components each,
418 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
421 * Actually we use 4 for each, so call it 12 rows.
423 GLuint urb_entry_size
;
426 struct brw_clip_prog_data
{
427 GLuint curb_read_length
; /* user planes? */
429 GLuint urb_read_length
;
433 struct brw_gs_prog_data
{
434 GLuint urb_read_length
;
438 * Gen6 transform feedback: Amount by which the streaming vertex buffer
439 * indices should be incremented each time the GS is invoked.
441 unsigned svbi_postincrement_value
;
445 /* Note: brw_vec4_prog_data_compare() must be updated when adding fields to
448 struct brw_vec4_prog_data
{
449 struct brw_vue_map vue_map
;
451 GLuint curb_read_length
;
452 GLuint urb_read_length
;
454 GLuint nr_params
; /**< number of float params/constants */
455 GLuint nr_pull_params
; /**< number of dwords referenced by pull_param[] */
456 GLuint total_scratch
;
458 /* Used for calculating urb partitions. In the VS, this is the size of the
459 * URB entry used for both input and output to the thread. In the GS, this
460 * is the size of the URB entry used for output.
462 GLuint urb_entry_size
;
466 /* These pointers must appear last. See brw_vec4_prog_data_compare(). */
468 const float **pull_param
;
472 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
475 struct brw_vs_prog_data
{
476 struct brw_vec4_prog_data base
;
478 GLbitfield64 inputs_read
;
483 /** Number of texture sampler units */
484 #define BRW_MAX_TEX_UNIT 16
486 /** Max number of render targets in a shader */
487 #define BRW_MAX_DRAW_BUFFERS 8
490 * Max number of binding table entries used for stream output.
492 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
493 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
495 * On Gen6, the size of transform feedback data is limited not by the number
496 * of components but by the number of binding table entries we set aside. We
497 * use one binding table entry for a float, one entry for a vector, and one
498 * entry per matrix column. Since the only way we can communicate our
499 * transform feedback capabilities to the client is via
500 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
501 * worst case, in which all the varyings are floats, so we use up one binding
502 * table entry per component. Therefore we need to set aside at least 64
503 * binding table entries for use by transform feedback.
505 * Note: since we don't currently pack varyings, it is currently impossible
506 * for the client to actually use up all of these binding table entries--if
507 * all of their varyings were floats, they would run out of varying slots and
508 * fail to link. But that's a bug, so it seems prudent to go ahead and
509 * allocate the number of binding table entries we will need once the bug is
512 #define BRW_MAX_SOL_BINDINGS 64
514 /** Maximum number of actual buffers used for stream output */
515 #define BRW_MAX_SOL_BUFFERS 4
517 #define BRW_MAX_WM_UBOS 12
518 #define BRW_MAX_VS_UBOS 12
521 * Helpers to create Surface Binding Table indexes for draw buffers,
522 * textures, and constant buffers.
524 * Shader threads access surfaces via numeric handles, rather than directly
525 * using pointers. The binding table maps these numeric handles to the
526 * address of the actual buffer.
528 * For example, a shader might ask to sample from "surface 7." In this case,
529 * bind[7] would contain a pointer to a texture.
531 * Currently, our WM binding tables are (arbitrarily) programmed as follows:
533 * +-------------------------------+
534 * | 0 | Draw buffer 0 |
537 * | 7 | Draw buffer 7 |
538 * |-----|-------------------------|
539 * | 8 | WM Pull Constant Buffer |
540 * |-----|-------------------------|
544 * | 24 | Texture 15 |
545 * |-----|-------------------------|
550 * +-------------------------------+
552 * Our VS binding tables are programmed as follows:
554 * +-----+-------------------------+
555 * | 0 | VS Pull Constant Buffer |
556 * +-----+-------------------------+
560 * | 16 | Texture 15 |
561 * +-----+-------------------------+
566 * +-------------------------------+
568 * Our (gen6) GS binding tables are programmed as follows:
570 * +-----+-------------------------+
571 * | 0 | SOL Binding 0 |
574 * | 63 | SOL Binding 63 |
575 * +-----+-------------------------+
577 * Note that nothing actually uses the SURF_INDEX_DRAW macro, so it has to be
578 * the identity function or things will break. We do want to keep draw buffers
579 * first so we can use headerless render target writes for RT 0.
581 #define SURF_INDEX_DRAW(d) (d)
582 #define SURF_INDEX_FRAG_CONST_BUFFER (BRW_MAX_DRAW_BUFFERS + 1)
583 #define SURF_INDEX_TEXTURE(t) (BRW_MAX_DRAW_BUFFERS + 2 + (t))
584 #define SURF_INDEX_WM_UBO(u) (SURF_INDEX_TEXTURE(BRW_MAX_TEX_UNIT) + u)
585 #define SURF_INDEX_WM_SHADER_TIME (SURF_INDEX_WM_UBO(12))
586 /** Maximum size of the binding table. */
587 #define BRW_MAX_WM_SURFACES (SURF_INDEX_WM_SHADER_TIME + 1)
589 #define SURF_INDEX_VERT_CONST_BUFFER (0)
590 #define SURF_INDEX_VS_TEXTURE(t) (SURF_INDEX_VERT_CONST_BUFFER + 1 + (t))
591 #define SURF_INDEX_VS_UBO(u) (SURF_INDEX_VS_TEXTURE(BRW_MAX_TEX_UNIT) + u)
592 #define SURF_INDEX_VS_SHADER_TIME (SURF_INDEX_VS_UBO(12))
593 #define BRW_MAX_VS_SURFACES (SURF_INDEX_VS_SHADER_TIME + 1)
595 #define SURF_INDEX_SOL_BINDING(t) ((t))
596 #define BRW_MAX_GS_SURFACES SURF_INDEX_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
599 * Stride in bytes between shader_time entries.
601 * We separate entries by a cacheline to reduce traffic between EUs writing to
604 #define SHADER_TIME_STRIDE 64
608 BRW_DEPTH_STENCIL_STATE
,
609 BRW_COLOR_CALC_STATE
,
614 BRW_BLORP_CLEAR_PROG
,
619 BRW_SF_UNIT
, /* scissor state on gen6 */
631 struct brw_cache_item
{
633 * Effectively part of the key, cache_id identifies what kind of state
634 * buffer is involved, and also which brw->state.dirty.cache flag should
635 * be set when this cache item is chosen.
637 enum brw_cache_id cache_id
;
638 /** 32-bit hash of the key data */
640 GLuint key_size
; /* for variable-sized keys */
647 struct brw_cache_item
*next
;
651 typedef bool (*cache_aux_compare_func
)(const void *a
, const void *b
,
652 int aux_size
, const void *key
);
653 typedef void (*cache_aux_free_func
)(const void *aux
);
656 struct brw_context
*brw
;
658 struct brw_cache_item
**items
;
660 GLuint size
, n_items
;
662 uint32_t next_offset
;
666 * Optional functions used in determining whether the prog_data for a new
667 * cache item matches an existing cache item (in case there's relevant data
668 * outside of the prog_data). If NULL, a plain memcmp is done.
670 cache_aux_compare_func aux_compare
[BRW_MAX_CACHE
];
671 /** Optional functions for freeing other pointers attached to a prog_data. */
672 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
676 /* Considered adding a member to this struct to document which flags
677 * an update might raise so that ordering of the state atoms can be
678 * checked or derived at runtime. Dropped the idea in favor of having
679 * a debug mode where the state is monitored for flags which are
680 * raised that have already been tested against.
682 struct brw_tracked_state
{
683 struct brw_state_flags dirty
;
684 void (*emit
)( struct brw_context
*brw
);
687 enum shader_time_shader_type
{
700 /* Flags for brw->state.cache.
702 #define CACHE_NEW_BLEND_STATE (1<<BRW_BLEND_STATE)
703 #define CACHE_NEW_DEPTH_STENCIL_STATE (1<<BRW_DEPTH_STENCIL_STATE)
704 #define CACHE_NEW_COLOR_CALC_STATE (1<<BRW_COLOR_CALC_STATE)
705 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
706 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
707 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
708 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
709 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
710 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
711 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
712 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
713 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
714 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
715 #define CACHE_NEW_GS_UNIT (1<<BRW_GS_UNIT)
716 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
717 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
718 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
719 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
721 struct brw_cached_batch_item
{
722 struct header
*header
;
724 struct brw_cached_batch_item
*next
;
729 /* Protect against a future where VERT_ATTRIB_MAX > 32. Wouldn't life
730 * be easier if C allowed arrays of packed elements?
732 #define ATTRIB_BIT_DWORDS ((VERT_ATTRIB_MAX+31)/32)
734 struct brw_vertex_buffer
{
735 /** Buffer object containing the uploaded vertex data */
738 /** Byte stride between elements in the uploaded array */
742 struct brw_vertex_element
{
743 const struct gl_client_array
*glarray
;
747 /** The corresponding Mesa vertex attribute */
748 gl_vert_attrib attrib
;
749 /** Offset of the first element within the buffer object */
753 struct brw_query_object
{
754 struct gl_query_object Base
;
756 /** Last query BO associated with this query. */
759 /** Last index in bo with query data for this object. */
765 * brw_context is derived from intel_context.
769 struct intel_context intel
; /**< base class, must be first field */
770 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
772 bool emit_state_always
;
773 bool has_surface_tile_offset
;
775 bool has_negative_rhw_bug
;
776 bool has_aa_line_parameters
;
781 * Some versions of Gen hardware don't do centroid interpolation correctly
782 * on unlit pixels, causing incorrect values for derivatives near triangle
783 * edges. Enabling this flag causes the fragment shader to use
784 * non-centroid interpolation for unlit pixels, at the expense of two extra
785 * fragment shader instructions.
787 bool needs_unlit_centroid_workaround
;
790 struct brw_state_flags dirty
;
793 struct brw_cache cache
;
794 struct brw_cached_batch_item
*cached_batch_items
;
797 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
798 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
800 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
804 /* Summary of size and varying of active arrays, so we can check
805 * for changes to this state:
807 unsigned int min_index
, max_index
;
809 /* Offset from start of vertex buffer so we can avoid redefining
810 * the same VB packed over and over again.
812 unsigned int start_vertex_bias
;
817 * Index buffer for this draw_prims call.
819 * Updates are signaled by BRW_NEW_INDICES.
821 const struct _mesa_index_buffer
*ib
;
823 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
827 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
828 * avoid re-uploading the IB packet over and over if we're actually
829 * referencing the same index buffer.
831 unsigned int start_vertex_offset
;
834 /* Active vertex program:
836 const struct gl_vertex_program
*vertex_program
;
837 const struct gl_fragment_program
*fragment_program
;
839 /* hw-dependent 3DSTATE_VF_STATISTICS opcode */
840 uint32_t CMD_VF_STATISTICS
;
841 /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
842 uint32_t CMD_PIPELINE_SELECT
;
845 * Platform specific constants containing the maximum number of threads
846 * for each pipeline stage.
852 /* BRW_NEW_URB_ALLOCATIONS:
855 GLuint vsize
; /* vertex size plus header in urb registers */
856 GLuint csize
; /* constant buffer size in urb registers */
857 GLuint sfsize
; /* setup data size in urb registers */
861 GLuint max_vs_entries
; /* Maximum number of VS entries */
862 GLuint max_gs_entries
; /* Maximum number of GS entries */
864 GLuint nr_vs_entries
;
865 GLuint nr_gs_entries
;
866 GLuint nr_clip_entries
;
867 GLuint nr_sf_entries
;
868 GLuint nr_cs_entries
;
875 GLuint size
; /* Hardware URB size, in KB. */
877 /* gen6: True if the most recently sent _3DSTATE_URB message allocated
878 * URB space for the GS.
880 bool gen6_gs_previously_active
;
884 /* BRW_NEW_CURBE_OFFSETS:
887 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
888 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
895 drm_intel_bo
*curbe_bo
;
896 /** Offset within curbe_bo of space for current curbe entry */
898 /** Offset within curbe_bo of space for next curbe entry */
899 GLuint curbe_next_offset
;
902 * Copy of the last set of CURBEs uploaded. Frequently we'll end up
903 * in brw_curbe.c with the same set of constant data to be uploaded,
904 * so we'd rather not upload new constants in that case (it can cause
905 * a pipeline bubble since only up to 4 can be pipelined at a time).
909 * Allocation for where to calculate the next set of CURBEs.
910 * It's a hot enough path that malloc/free of that data matters.
916 /** SAMPLER_STATE count and offset */
923 * Layout of vertex data exiting the geometry portion of the pipleine.
924 * This comes from the geometry shader if one exists, otherwise from the
927 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
929 struct brw_vue_map vue_map_geom_out
;
932 struct brw_vs_prog_data
*prog_data
;
934 drm_intel_bo
*scratch_bo
;
935 drm_intel_bo
*const_bo
;
936 /** Offset in the program cache to the VS program */
937 uint32_t prog_offset
;
938 uint32_t state_offset
;
940 uint32_t push_const_offset
; /* Offset in the batchbuffer */
941 int push_const_size
; /* in 256-bit register increments */
943 /** @{ register allocator */
945 struct ra_regs
*regs
;
948 * Array of the ra classes for the unaligned contiguous register
954 * Mapping for register-allocated objects in *regs to the first
955 * GRF for that object.
957 uint8_t *ra_reg_to_grf
;
960 uint32_t bind_bo_offset
;
961 uint32_t surf_offset
[BRW_MAX_VS_SURFACES
];
965 struct brw_gs_prog_data
*prog_data
;
968 /** Offset in the program cache to the CLIP program pre-gen6 */
969 uint32_t prog_offset
;
970 uint32_t state_offset
;
972 uint32_t bind_bo_offset
;
973 uint32_t surf_offset
[BRW_MAX_GS_SURFACES
];
977 struct brw_clip_prog_data
*prog_data
;
979 /** Offset in the program cache to the CLIP program pre-gen6 */
980 uint32_t prog_offset
;
982 /* Offset in the batch to the CLIP state on pre-gen6. */
983 uint32_t state_offset
;
985 /* As of gen6, this is the offset in the batch to the CLIP VP,
993 struct brw_sf_prog_data
*prog_data
;
995 /** Offset in the program cache to the CLIP program pre-gen6 */
996 uint32_t prog_offset
;
997 uint32_t state_offset
;
1002 struct brw_wm_prog_data
*prog_data
;
1004 /** offsets in the batch to sampler default colors (texture border color)
1006 uint32_t sdc_offset
[BRW_MAX_TEX_UNIT
];
1010 drm_intel_bo
*scratch_bo
;
1013 * Buffer object used in place of multisampled null render targets on
1014 * Gen6. See brw_update_null_renderbuffer_surface().
1016 drm_intel_bo
*multisampled_null_render_target_bo
;
1018 /** Offset in the program cache to the WM program */
1019 uint32_t prog_offset
;
1021 uint32_t state_offset
; /* offset in batchbuffer to pre-gen6 WM state */
1023 drm_intel_bo
*const_bo
; /* pull constant buffer. */
1025 * This is offset in the batch to the push constants on gen6.
1027 * Pre-gen6, push constants live in the CURBE.
1029 uint32_t push_const_offset
;
1031 /** Binding table of pointers to surf_bo entries */
1032 uint32_t bind_bo_offset
;
1033 uint32_t surf_offset
[BRW_MAX_WM_SURFACES
];
1036 struct ra_regs
*regs
;
1038 /** Array of the ra classes for the unaligned contiguous
1039 * register block sizes used.
1044 * Mapping for register-allocated objects in *regs to the first
1045 * GRF for that object.
1047 uint8_t *ra_reg_to_grf
;
1050 * ra class for the aligned pairs we use for PLN, which doesn't
1051 * appear in *classes.
1053 int aligned_pairs_class
;
1059 uint32_t state_offset
;
1060 uint32_t blend_state_offset
;
1061 uint32_t depth_stencil_state_offset
;
1066 struct brw_query_object
*obj
;
1071 const struct brw_tracked_state
**atoms
;
1073 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1077 enum state_struct_type type
;
1078 } *state_batch_list
;
1079 int state_batch_count
;
1081 struct brw_sol_state
{
1082 uint32_t svbi_0_starting_index
;
1083 uint32_t svbi_0_max_index
;
1084 uint32_t offset_0_batch_start
;
1085 uint32_t primitives_generated
;
1086 uint32_t primitives_written
;
1087 bool counting_primitives_generated
;
1088 bool counting_primitives_written
;
1091 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1092 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1094 /* PrimitiveRestart */
1097 bool enable_cut_index
;
1100 /** Computed depth/stencil/hiz state from the current attached
1101 * renderbuffers, valid only during the drawing state upload loop after
1102 * brw_workaround_depthstencil_alignment().
1105 struct intel_mipmap_tree
*depth_mt
;
1106 struct intel_mipmap_tree
*stencil_mt
;
1108 /* Inter-tile (page-aligned) byte offsets. */
1109 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1110 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1111 uint32_t tile_x
, tile_y
;
1114 uint32_t num_instances
;
1119 struct gl_shader_program
**shader_programs
;
1120 struct gl_program
**programs
;
1121 enum shader_time_shader_type
*types
;
1122 uint64_t *cumulative
;
1129 /*======================================================================
1132 void brwInitVtbl( struct brw_context
*brw
);
1134 /*======================================================================
1137 bool brwCreateContext(int api
,
1138 const struct gl_config
*mesaVis
,
1139 __DRIcontext
*driContextPriv
,
1140 unsigned major_version
,
1141 unsigned minor_version
,
1144 void *sharedContextPrivate
);
1146 /*======================================================================
1149 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1150 uint32_t depth_level
,
1151 uint32_t depth_layer
,
1152 struct intel_mipmap_tree
*stencil_mt
,
1153 uint32_t *out_tile_mask_x
,
1154 uint32_t *out_tile_mask_y
);
1155 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1156 GLbitfield clear_mask
);
1158 /*======================================================================
1161 void brw_init_queryobj_functions(struct dd_function_table
*functions
);
1162 void brw_emit_query_begin(struct brw_context
*brw
);
1163 void brw_emit_query_end(struct brw_context
*brw
);
1165 /*======================================================================
1168 void brw_debug_batch(struct intel_context
*intel
);
1169 void brw_annotate_aub(struct intel_context
*intel
);
1171 /*======================================================================
1174 void brw_validate_textures( struct brw_context
*brw
);
1177 /*======================================================================
1180 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1182 int brw_get_scratch_size(int size
);
1183 void brw_get_scratch_bo(struct intel_context
*intel
,
1184 drm_intel_bo
**scratch_bo
, int size
);
1185 void brw_init_shader_time(struct brw_context
*brw
);
1186 int brw_get_shader_time_index(struct brw_context
*brw
,
1187 struct gl_shader_program
*shader_prog
,
1188 struct gl_program
*prog
,
1189 enum shader_time_shader_type type
);
1190 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1191 void brw_destroy_shader_time(struct brw_context
*brw
);
1195 void brw_upload_urb_fence(struct brw_context
*brw
);
1199 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1201 /* brw_fs_reg_allocate.cpp
1203 void brw_fs_alloc_reg_sets(struct brw_context
*brw
);
1206 int brw_disasm (FILE *file
, struct brw_instruction
*inst
, int gen
);
1209 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1211 /* brw_wm_surface_state.c */
1212 void brw_init_surface_formats(struct brw_context
*brw
);
1214 brw_update_sol_surface(struct brw_context
*brw
,
1215 struct gl_buffer_object
*buffer_obj
,
1216 uint32_t *out_offset
, unsigned num_vector_components
,
1217 unsigned stride_dwords
, unsigned offset_dwords
);
1218 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1219 struct gl_shader
*shader
,
1220 uint32_t *surf_offsets
);
1224 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1225 struct gl_transform_feedback_object
*obj
);
1227 brw_end_transform_feedback(struct gl_context
*ctx
,
1228 struct gl_transform_feedback_object
*obj
);
1230 /* gen7_sol_state.c */
1232 gen7_end_transform_feedback(struct gl_context
*ctx
,
1233 struct gl_transform_feedback_object
*obj
);
1235 /* brw_blorp_blit.cpp */
1237 brw_blorp_framebuffer(struct intel_context
*intel
,
1238 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1239 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1240 GLbitfield mask
, GLenum filter
);
1243 brw_blorp_copytexsubimage(struct intel_context
*intel
,
1244 struct gl_renderbuffer
*src_rb
,
1245 struct gl_texture_image
*dst_image
,
1246 int srcX0
, int srcY0
,
1247 int dstX0
, int dstY0
,
1248 int width
, int height
);
1250 /* gen6_multisample_state.c */
1252 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1253 unsigned num_samples
);
1255 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
,
1256 unsigned num_samples
, float coverage
,
1257 bool coverage_invert
, unsigned sample_mask
);
1259 gen6_get_sample_position(struct gl_context
*ctx
,
1260 struct gl_framebuffer
*fb
,
1266 gen7_allocate_push_constants(struct brw_context
*brw
);
1269 gen7_emit_urb_state(struct brw_context
*brw
, GLuint nr_vs_entries
,
1270 GLuint vs_size
, GLuint vs_start
);
1274 /*======================================================================
1275 * Inline conversion functions. These are better-typed than the
1276 * macros used previously:
1278 static INLINE
struct brw_context
*
1279 brw_context( struct gl_context
*ctx
)
1281 return (struct brw_context
*)ctx
;
1284 static INLINE
struct brw_vertex_program
*
1285 brw_vertex_program(struct gl_vertex_program
*p
)
1287 return (struct brw_vertex_program
*) p
;
1290 static INLINE
const struct brw_vertex_program
*
1291 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1293 return (const struct brw_vertex_program
*) p
;
1296 static INLINE
struct brw_fragment_program
*
1297 brw_fragment_program(struct gl_fragment_program
*p
)
1299 return (struct brw_fragment_program
*) p
;
1302 static INLINE
const struct brw_fragment_program
*
1303 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1305 return (const struct brw_fragment_program
*) p
;
1309 * Pre-gen6, the register file of the EUs was shared between threads,
1310 * and each thread used some subset allocated on a 16-register block
1311 * granularity. The unit states wanted these block counts.
1314 brw_register_blocks(int reg_count
)
1316 return ALIGN(reg_count
, 16) / 16 - 1;
1319 static inline uint32_t
1320 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1321 uint32_t prog_offset
)
1323 struct intel_context
*intel
= &brw
->intel
;
1325 if (intel
->gen
>= 5) {
1326 /* Using state base address. */
1330 drm_intel_bo_emit_reloc(intel
->batch
.bo
,
1334 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1336 return brw
->cache
.bo
->offset
+ prog_offset
;
1339 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1340 bool brw_lower_texture_gradients(struct intel_context
*intel
,
1341 struct exec_list
*instructions
);
1343 struct opcode_desc
{
1349 extern const struct opcode_desc opcode_descs
[128];
1352 brw_emit_depthbuffer(struct brw_context
*brw
);
1355 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1356 struct intel_mipmap_tree
*depth_mt
,
1357 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1358 uint32_t depth_surface_type
,
1359 struct intel_mipmap_tree
*stencil_mt
,
1360 bool hiz
, bool separate_stencil
,
1361 uint32_t width
, uint32_t height
,
1362 uint32_t tile_x
, uint32_t tile_y
);
1365 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1366 struct intel_mipmap_tree
*depth_mt
,
1367 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1368 uint32_t depth_surface_type
,
1369 struct intel_mipmap_tree
*stencil_mt
,
1370 bool hiz
, bool separate_stencil
,
1371 uint32_t width
, uint32_t height
,
1372 uint32_t tile_x
, uint32_t tile_y
);