2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
38 #include "main/imports.h"
39 #include "main/macros.h"
41 #include "main/mtypes.h"
42 #include "brw_structs.h"
43 #include "brw_compiler.h"
44 #include "intel_aub.h"
45 #include "program/prog_parameter.h"
49 /* Evil hack for using libdrm in a c++ compiler. */
54 #include <intel_bufmgr.h>
64 #include "intel_debug.h"
65 #include "intel_screen.h"
66 #include "intel_tex_obj.h"
67 #include "intel_resolve_map.h"
71 * URB - uniform resource buffer. A mid-sized buffer which is
72 * partitioned between the fixed function units and used for passing
73 * values (vertices, primitives, constants) between them.
75 * CURBE - constant URB entry. An urb region (entry) used to hold
76 * constant values which the fixed function units can be instructed to
77 * preload into the GRF when spawning a thread.
79 * VUE - vertex URB entry. An urb entry holding a vertex and usually
80 * a vertex header. The header contains control information and
81 * things like primitive type, Begin/end flags and clip codes.
83 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
84 * unit holding rasterization and interpolation parameters.
86 * GRF - general register file. One of several register files
87 * addressable by programmed threads. The inputs (r0, payload, curbe,
88 * urb) of the thread are preloaded to this area before the thread is
89 * spawned. The registers are individually 8 dwords wide and suitable
90 * for general usage. Registers holding thread input values are not
91 * special and may be overwritten.
93 * MRF - message register file. Threads communicate (and terminate)
94 * by sending messages. Message parameters are placed in contiguous
95 * MRF registers. All program output is via these messages. URB
96 * entries are populated by sending a message to the shared URB
97 * function containing the new data, together with a control word,
98 * often an unmodified copy of R0.
100 * R0 - GRF register 0. Typically holds control information used when
101 * sending messages to other threads.
103 * EU or GEN4 EU: The name of the programmable subsystem of the
104 * i965 hardware. Threads are executed by the EU, the registers
105 * described above are part of the EU architecture.
107 * Fixed function units:
109 * CS - Command streamer. Notional first unit, little software
110 * interaction. Holds the URB entries used for constant data, ie the
113 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
114 * this unit is responsible for pulling vertices out of vertex buffers
115 * in vram and injecting them into the processing pipe as VUEs. If
116 * enabled, it first passes them to a VS thread which is a good place
117 * for the driver to implement any active vertex shader.
119 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
120 * enabled, incoming strips etc are passed to GS threads in individual
121 * line/triangle/point units. The GS thread may perform arbitary
122 * computation and emit whatever primtives with whatever vertices it
123 * chooses. This makes GS an excellent place to implement GL's
124 * unfilled polygon modes, though of course it is capable of much
125 * more. Additionally, GS is used to translate away primitives not
126 * handled by latter units, including Quads and Lineloops.
128 * CS - Clipper. Mesa's clipping algorithms are imported to run on
129 * this unit. The fixed function part performs cliptesting against
130 * the 6 fixed clipplanes and makes descisions on whether or not the
131 * incoming primitive needs to be passed to a thread for clipping.
132 * User clip planes are handled via cooperation with the VS thread.
134 * SF - Strips Fans or Setup: Triangles are prepared for
135 * rasterization. Interpolation coefficients are calculated.
136 * Flatshading and two-side lighting usually performed here.
138 * WM - Windower. Interpolation of vertex attributes performed here.
139 * Fragment shader implemented here. SIMD aspects of EU taken full
140 * advantage of, as pixels are processed in blocks of 16.
142 * CC - Color Calculator. No EU threads associated with this unit.
143 * Handles blending and (presumably) depth and stencil testing.
148 struct brw_vs_prog_key
;
149 struct brw_vue_prog_key
;
150 struct brw_wm_prog_key
;
151 struct brw_wm_prog_data
;
152 struct brw_cs_prog_key
;
153 struct brw_cs_prog_data
;
157 BRW_COMPUTE_PIPELINE
,
164 BRW_CACHE_BLORP_BLIT_PROG
,
167 BRW_CACHE_FF_GS_PROG
,
176 /* brw_cache_ids must come first - see brw_state_cache.c */
177 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
178 BRW_STATE_FRAGMENT_PROGRAM
,
179 BRW_STATE_GEOMETRY_PROGRAM
,
180 BRW_STATE_VERTEX_PROGRAM
,
181 BRW_STATE_CURBE_OFFSETS
,
182 BRW_STATE_REDUCED_PRIMITIVE
,
187 BRW_STATE_VS_BINDING_TABLE
,
188 BRW_STATE_GS_BINDING_TABLE
,
189 BRW_STATE_PS_BINDING_TABLE
,
193 BRW_STATE_INDEX_BUFFER
,
194 BRW_STATE_VS_CONSTBUF
,
195 BRW_STATE_GS_CONSTBUF
,
196 BRW_STATE_PROGRAM_CACHE
,
197 BRW_STATE_STATE_BASE_ADDRESS
,
198 BRW_STATE_VUE_MAP_GEOM_OUT
,
199 BRW_STATE_TRANSFORM_FEEDBACK
,
200 BRW_STATE_RASTERIZER_DISCARD
,
202 BRW_STATE_UNIFORM_BUFFER
,
203 BRW_STATE_ATOMIC_BUFFER
,
204 BRW_STATE_IMAGE_UNITS
,
205 BRW_STATE_META_IN_PROGRESS
,
206 BRW_STATE_INTERPOLATION_MAP
,
207 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
208 BRW_STATE_NUM_SAMPLES
,
209 BRW_STATE_TEXTURE_BUFFER
,
210 BRW_STATE_GEN4_UNIT_STATE
,
214 BRW_STATE_SAMPLER_STATE_TABLE
,
215 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
216 BRW_STATE_COMPUTE_PROGRAM
,
217 BRW_STATE_CS_WORK_GROUPS
,
222 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
224 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
225 * When the currently bound shader program differs from the previous draw
226 * call, these will be flagged. They cover brw->{stage}_program and
227 * ctx->{Stage}Program->_Current.
229 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
230 * driver perspective. Even if the same shader is bound at the API level,
231 * we may need to switch between multiple versions of that shader to handle
232 * changes in non-orthagonal state.
234 * Additionally, multiple shader programs may have identical vertex shaders
235 * (for example), or compile down to the same code in the backend. We combine
236 * those into a single program cache entry.
238 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
239 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
241 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
242 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
243 * use the normal state upload paths), but the cache is still used. To avoid
244 * polluting the brw_state_cache code with special cases, we retain the dirty
245 * bit for now. It should eventually be removed.
247 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_BLIT_PROG)
248 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
249 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
250 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
251 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
252 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
253 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
254 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
255 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
256 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
257 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
258 #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
259 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
260 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
261 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
262 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
263 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
264 #define BRW_NEW_VS_BINDING_TABLE (1ull << BRW_STATE_VS_BINDING_TABLE)
265 #define BRW_NEW_GS_BINDING_TABLE (1ull << BRW_STATE_GS_BINDING_TABLE)
266 #define BRW_NEW_PS_BINDING_TABLE (1ull << BRW_STATE_PS_BINDING_TABLE)
267 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
268 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
270 * Used for any batch entry with a relocated pointer that will be used
271 * by any 3D rendering.
273 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
274 /** \see brw.state.depth_region */
275 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
276 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
277 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
278 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
279 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
280 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
281 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
282 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
283 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
284 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
285 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
286 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
287 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
288 #define BRW_NEW_INTERPOLATION_MAP (1ull << BRW_STATE_INTERPOLATION_MAP)
289 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
290 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
291 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
292 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
293 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
294 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
295 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
296 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
297 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
298 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
299 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
301 struct brw_state_flags
{
302 /** State update flags signalled by mesa internals */
305 * State update flags signalled as the result of brw_tracked_state updates
310 /** Subclass of Mesa vertex program */
311 struct brw_vertex_program
{
312 struct gl_vertex_program program
;
317 /** Subclass of Mesa geometry program */
318 struct brw_geometry_program
{
319 struct gl_geometry_program program
;
320 unsigned id
; /**< serial no. to identify geom progs, never re-used */
324 /** Subclass of Mesa fragment program */
325 struct brw_fragment_program
{
326 struct gl_fragment_program program
;
327 GLuint id
; /**< serial no. to identify frag progs, never re-used */
331 /** Subclass of Mesa compute program */
332 struct brw_compute_program
{
333 struct gl_compute_program program
;
334 unsigned id
; /**< serial no. to identify compute progs, never re-used */
339 struct gl_shader base
;
345 * Bitmask indicating which fragment shader inputs represent varyings (and
346 * hence have to be delivered to the fragment shader by the SF/SBE stage).
348 #define BRW_FS_VARYING_INPUT_MASK \
349 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
350 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
354 * Mapping of VUE map slots to interpolation modes.
356 struct interpolation_mode_map
{
357 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
360 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
362 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
363 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
369 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
371 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
372 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
379 struct brw_sf_prog_data
{
380 GLuint urb_read_length
;
383 /* Each vertex may have upto 12 attributes, 4 components each,
384 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
387 * Actually we use 4 for each, so call it 12 rows.
389 GLuint urb_entry_size
;
394 * We always program SF to start reading at an offset of 1 (2 varying slots)
395 * from the start of the vertex URB entry. This causes it to skip:
396 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
397 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
399 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
402 struct brw_clip_prog_data
{
403 GLuint curb_read_length
; /* user planes? */
405 GLuint urb_read_length
;
409 struct brw_ff_gs_prog_data
{
410 GLuint urb_read_length
;
414 * Gen6 transform feedback: Amount by which the streaming vertex buffer
415 * indices should be incremented each time the GS is invoked.
417 unsigned svbi_postincrement_value
;
420 /** Number of texture sampler units */
421 #define BRW_MAX_TEX_UNIT 32
423 /** Max number of render targets in a shader */
424 #define BRW_MAX_DRAW_BUFFERS 8
426 /** Max number of UBOs in a shader */
427 #define BRW_MAX_UBO 12
429 /** Max number of SSBOs in a shader */
430 #define BRW_MAX_SSBO 12
432 /** Max number of atomic counter buffer objects in a shader */
433 #define BRW_MAX_ABO 16
435 /** Max number of image uniforms in a shader */
436 #define BRW_MAX_IMAGES 32
439 * Max number of binding table entries used for stream output.
441 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
442 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
444 * On Gen6, the size of transform feedback data is limited not by the number
445 * of components but by the number of binding table entries we set aside. We
446 * use one binding table entry for a float, one entry for a vector, and one
447 * entry per matrix column. Since the only way we can communicate our
448 * transform feedback capabilities to the client is via
449 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
450 * worst case, in which all the varyings are floats, so we use up one binding
451 * table entry per component. Therefore we need to set aside at least 64
452 * binding table entries for use by transform feedback.
454 * Note: since we don't currently pack varyings, it is currently impossible
455 * for the client to actually use up all of these binding table entries--if
456 * all of their varyings were floats, they would run out of varying slots and
457 * fail to link. But that's a bug, so it seems prudent to go ahead and
458 * allocate the number of binding table entries we will need once the bug is
461 #define BRW_MAX_SOL_BINDINGS 64
463 /** Maximum number of actual buffers used for stream output */
464 #define BRW_MAX_SOL_BUFFERS 4
466 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
467 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
472 2 + /* shader time, pull constants */ \
473 1 /* cs num work groups */)
475 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
478 * Stride in bytes between shader_time entries.
480 * We separate entries by a cacheline to reduce traffic between EUs writing to
483 #define SHADER_TIME_STRIDE 64
485 struct brw_cache_item
{
487 * Effectively part of the key, cache_id identifies what kind of state
488 * buffer is involved, and also which dirty flag should set.
490 enum brw_cache_id cache_id
;
491 /** 32-bit hash of the key data */
493 GLuint key_size
; /* for variable-sized keys */
500 struct brw_cache_item
*next
;
505 struct brw_context
*brw
;
507 struct brw_cache_item
**items
;
509 GLuint size
, n_items
;
511 uint32_t next_offset
;
516 /* Considered adding a member to this struct to document which flags
517 * an update might raise so that ordering of the state atoms can be
518 * checked or derived at runtime. Dropped the idea in favor of having
519 * a debug mode where the state is monitored for flags which are
520 * raised that have already been tested against.
522 struct brw_tracked_state
{
523 struct brw_state_flags dirty
;
524 void (*emit
)( struct brw_context
*brw
);
527 enum shader_time_shader_type
{
536 struct brw_vertex_buffer
{
537 /** Buffer object containing the uploaded vertex data */
540 /** Byte stride between elements in the uploaded array */
544 struct brw_vertex_element
{
545 const struct gl_client_array
*glarray
;
549 /** Offset of the first element within the buffer object */
553 struct brw_query_object
{
554 struct gl_query_object Base
;
556 /** Last query BO associated with this query. */
559 /** Last index in bo with query data for this object. */
562 /** True if we know the batch has been flushed since we ended the query. */
572 struct intel_batchbuffer
{
573 /** Current batchbuffer being queued up. */
575 /** Last BO submitted to the hardware. Used for glFinish(). */
576 drm_intel_bo
*last_bo
;
579 uint16_t emit
, total
;
581 uint16_t reserved_space
;
585 #define BATCH_SZ (8192*sizeof(uint32_t))
587 uint32_t state_batch_offset
;
588 enum brw_gpu_ring ring
;
589 bool needs_sol_reset
;
597 #define MAX_GS_INPUT_VERTICES 6
599 #define BRW_MAX_XFB_STREAMS 4
601 struct brw_transform_feedback_object
{
602 struct gl_transform_feedback_object base
;
604 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
605 drm_intel_bo
*offset_bo
;
607 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
610 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
611 GLenum primitive_mode
;
614 * Count of primitives generated during this transform feedback operation.
617 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
618 drm_intel_bo
*prim_count_bo
;
619 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
623 * Number of vertices written between last Begin/EndTransformFeedback().
625 * Used to implement DrawTransformFeedback().
627 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
628 bool vertices_written_valid
;
632 * Data shared between each programmable stage in the pipeline (vs, gs, and
635 struct brw_stage_state
637 gl_shader_stage stage
;
638 struct brw_stage_prog_data
*prog_data
;
641 * Optional scratch buffer used to store spilled register values and
642 * variably-indexed GRF arrays.
644 drm_intel_bo
*scratch_bo
;
646 /** Offset in the program cache to the program */
647 uint32_t prog_offset
;
649 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
650 uint32_t state_offset
;
652 uint32_t push_const_offset
; /* Offset in the batchbuffer */
653 int push_const_size
; /* in 256-bit register increments */
655 /* Binding table: pointers to SURFACE_STATE entries. */
656 uint32_t bind_bo_offset
;
657 uint32_t surf_offset
[BRW_MAX_SURFACES
];
659 /** SAMPLER_STATE count and table offset */
660 uint32_t sampler_count
;
661 uint32_t sampler_offset
;
664 enum brw_predicate_state
{
665 /* The first two states are used if we can determine whether to draw
666 * without having to look at the values in the query object buffer. This
667 * will happen if there is no conditional render in progress, if the query
668 * object is already completed or if something else has already added
669 * samples to the preliminary result such as via a BLT command.
671 BRW_PREDICATE_STATE_RENDER
,
672 BRW_PREDICATE_STATE_DONT_RENDER
,
673 /* In this case whether to draw or not depends on the result of an
674 * MI_PREDICATE command so the predicate enable bit needs to be checked.
676 BRW_PREDICATE_STATE_USE_BIT
682 * brw_context is derived from gl_context.
686 struct gl_context ctx
; /**< base class, must be first field */
690 void (*update_texture_surface
)(struct gl_context
*ctx
,
692 uint32_t *surf_offset
,
694 uint32_t (*update_renderbuffer_surface
)(struct brw_context
*brw
,
695 struct gl_renderbuffer
*rb
,
696 bool layered
, unsigned unit
,
697 uint32_t surf_index
);
699 void (*emit_texture_surface_state
)(struct brw_context
*brw
,
700 struct intel_mipmap_tree
*mt
,
708 uint32_t *surf_offset
,
709 bool rw
, bool for_gather
);
710 void (*emit_buffer_surface_state
)(struct brw_context
*brw
,
711 uint32_t *out_offset
,
713 unsigned buffer_offset
,
714 unsigned surface_format
,
715 unsigned buffer_size
,
718 void (*emit_null_surface_state
)(struct brw_context
*brw
,
722 uint32_t *out_offset
);
725 * Send the appropriate state packets to configure depth, stencil, and
726 * HiZ buffers (i965+ only)
728 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
729 struct intel_mipmap_tree
*depth_mt
,
730 uint32_t depth_offset
,
731 uint32_t depthbuffer_format
,
732 uint32_t depth_surface_type
,
733 struct intel_mipmap_tree
*stencil_mt
,
734 bool hiz
, bool separate_stencil
,
735 uint32_t width
, uint32_t height
,
736 uint32_t tile_x
, uint32_t tile_y
);
742 drm_intel_context
*hw_ctx
;
744 /** BO for post-sync nonzero writes for gen6 workaround. */
745 drm_intel_bo
*workaround_bo
;
746 uint8_t pipe_controls_since_last_cs_stall
;
749 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
750 * and would need flushing before being used from another cache domain that
751 * isn't coherent with it (i.e. the sampler).
753 struct set
*render_cache
;
756 * Number of resets observed in the system at context creation.
758 * This is tracked in the context so that we can determine that another
759 * reset has occurred.
761 uint32_t reset_count
;
763 struct intel_batchbuffer batch
;
768 uint32_t next_offset
;
772 * Set if rendering has occurred to the drawable's front buffer.
774 * This is used in the DRI2 case to detect that glFlush should also copy
775 * the contents of the fake front buffer to the real front buffer.
777 bool front_buffer_dirty
;
779 /** Framerate throttling: @{ */
780 drm_intel_bo
*throttle_batch
[2];
782 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
783 * frame of rendering to complete. This gives a very precise cap to the
784 * latency between input and output such that rendering never gets more
785 * than a frame behind the user. (With the caveat that we technically are
786 * not using the SwapBuffers itself as a barrier but the first batch
787 * submitted afterwards, which may be immediately prior to the next
790 bool need_swap_throttle
;
792 /** General throttling, not caught by throttling between SwapBuffers */
793 bool need_flush_throttle
;
803 bool always_flush_batch
;
804 bool always_flush_cache
;
805 bool disable_throttling
;
808 driOptionCache optionCache
;
811 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
813 GLenum reduced_primitive
;
816 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
817 * variable is set, this is the flag indicating to do expensive work that
818 * might lead to a perf_debug() call.
822 uint32_t max_gtt_map_object_size
;
834 bool has_separate_stencil
;
835 bool must_use_separate_stencil
;
838 bool has_surface_tile_offset
;
840 bool has_negative_rhw_bug
;
844 bool use_resource_streamer
;
847 * Some versions of Gen hardware don't do centroid interpolation correctly
848 * on unlit pixels, causing incorrect values for derivatives near triangle
849 * edges. Enabling this flag causes the fragment shader to use
850 * non-centroid interpolation for unlit pixels, at the expense of two extra
851 * fragment shader instructions.
853 bool needs_unlit_centroid_workaround
;
857 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
860 enum brw_pipeline last_pipeline
;
862 struct brw_cache cache
;
864 /** IDs for meta stencil blit shader programs. */
865 unsigned meta_stencil_blit_programs
[2];
867 /* Whether a meta-operation is in progress. */
868 bool meta_in_progress
;
870 /* Whether the last depth/stencil packets were both NULL. */
871 bool no_depth_or_stencil
;
873 /* The last PMA stall bits programmed. */
874 uint32_t pma_stall_bits
;
877 /** The value of gl_BaseVertex for the current _mesa_prim. */
881 * Buffer and offset used for GL_ARB_shader_draw_parameters
882 * (for now, only gl_BaseVertex).
884 drm_intel_bo
*draw_params_bo
;
885 uint32_t draw_params_offset
;
890 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
891 * an indirect call, and num_work_groups_offset is valid. Otherwise,
892 * num_work_groups is set based on glDispatchCompute.
894 drm_intel_bo
*num_work_groups_bo
;
895 GLintptr num_work_groups_offset
;
896 const GLuint
*num_work_groups
;
900 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
901 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
903 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
907 /* Summary of size and varying of active arrays, so we can check
908 * for changes to this state:
910 unsigned int min_index
, max_index
;
912 /* Offset from start of vertex buffer so we can avoid redefining
913 * the same VB packed over and over again.
915 unsigned int start_vertex_bias
;
918 * Certain vertex attribute formats aren't natively handled by the
919 * hardware and require special VS code to fix up their values.
921 * These bitfields indicate which workarounds are needed.
923 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
928 * Index buffer for this draw_prims call.
930 * Updates are signaled by BRW_NEW_INDICES.
932 const struct _mesa_index_buffer
*ib
;
934 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
938 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
939 * avoid re-uploading the IB packet over and over if we're actually
940 * referencing the same index buffer.
942 unsigned int start_vertex_offset
;
945 /* Active vertex program:
947 const struct gl_vertex_program
*vertex_program
;
948 const struct gl_geometry_program
*geometry_program
;
949 const struct gl_fragment_program
*fragment_program
;
950 const struct gl_compute_program
*compute_program
;
953 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
954 * that we don't have to reemit that state every time we change FBOs.
959 * Platform specific constants containing the maximum number of threads
960 * for each pipeline stage.
962 unsigned max_vs_threads
;
963 unsigned max_hs_threads
;
964 unsigned max_ds_threads
;
965 unsigned max_gs_threads
;
966 unsigned max_wm_threads
;
967 unsigned max_cs_threads
;
969 /* BRW_NEW_URB_ALLOCATIONS:
972 GLuint vsize
; /* vertex size plus header in urb registers */
973 GLuint gsize
; /* GS output size in urb registers */
974 GLuint csize
; /* constant buffer size in urb registers */
975 GLuint sfsize
; /* setup data size in urb registers */
979 GLuint min_vs_entries
; /* Minimum number of VS entries */
980 GLuint max_vs_entries
; /* Maximum number of VS entries */
981 GLuint max_hs_entries
; /* Maximum number of HS entries */
982 GLuint max_ds_entries
; /* Maximum number of DS entries */
983 GLuint max_gs_entries
; /* Maximum number of GS entries */
985 GLuint nr_vs_entries
;
986 GLuint nr_gs_entries
;
987 GLuint nr_clip_entries
;
988 GLuint nr_sf_entries
;
989 GLuint nr_cs_entries
;
996 GLuint size
; /* Hardware URB size, in KB. */
998 /* True if the most recently sent _3DSTATE_URB message allocated
999 * URB space for the GS.
1005 /* BRW_NEW_CURBE_OFFSETS:
1008 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1009 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1017 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1018 * for upload to the CURBE.
1020 drm_intel_bo
*curbe_bo
;
1021 /** Offset within curbe_bo of space for current curbe entry */
1022 GLuint curbe_offset
;
1026 * Layout of vertex data exiting the geometry portion of the pipleine.
1027 * This comes from the last enabled shader stage (GS, DS, or VS).
1029 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1031 struct brw_vue_map vue_map_geom_out
;
1034 struct brw_stage_state base
;
1035 struct brw_vs_prog_data
*prog_data
;
1039 struct brw_stage_state base
;
1040 struct brw_gs_prog_data
*prog_data
;
1043 * True if the 3DSTATE_GS command most recently emitted to the 3D
1044 * pipeline enabled the GS; false otherwise.
1050 struct brw_ff_gs_prog_data
*prog_data
;
1053 /** Offset in the program cache to the CLIP program pre-gen6 */
1054 uint32_t prog_offset
;
1055 uint32_t state_offset
;
1057 uint32_t bind_bo_offset
;
1059 * Surface offsets for the binding table. We only need surfaces to
1060 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1061 * need in this case.
1063 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1067 struct brw_clip_prog_data
*prog_data
;
1069 /** Offset in the program cache to the CLIP program pre-gen6 */
1070 uint32_t prog_offset
;
1072 /* Offset in the batch to the CLIP state on pre-gen6. */
1073 uint32_t state_offset
;
1075 /* As of gen6, this is the offset in the batch to the CLIP VP,
1083 struct brw_sf_prog_data
*prog_data
;
1085 /** Offset in the program cache to the CLIP program pre-gen6 */
1086 uint32_t prog_offset
;
1087 uint32_t state_offset
;
1089 bool viewport_transform_enable
;
1093 struct brw_stage_state base
;
1094 struct brw_wm_prog_data
*prog_data
;
1099 * Buffer object used in place of multisampled null render targets on
1100 * Gen6. See brw_emit_null_surface_state().
1102 drm_intel_bo
*multisampled_null_render_target_bo
;
1103 uint32_t fast_clear_op
;
1109 struct brw_stage_state base
;
1110 struct brw_cs_prog_data
*prog_data
;
1113 /* RS hardware binding table */
1116 uint32_t next_offset
;
1120 uint32_t state_offset
;
1121 uint32_t blend_state_offset
;
1122 uint32_t depth_stencil_state_offset
;
1127 struct brw_query_object
*obj
;
1132 enum brw_predicate_state state
;
1137 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1138 const int *statistics_registers
;
1140 /** The number of active monitors using OA counters. */
1144 * A buffer object storing OA counter snapshots taken at the start and
1145 * end of each batch (creating "bookends" around the batch).
1147 drm_intel_bo
*bookend_bo
;
1149 /** The number of snapshots written to bookend_bo. */
1150 int bookend_snapshots
;
1153 * An array of monitors whose results haven't yet been assembled based on
1154 * the data in buffer objects.
1156 * These may be active, or have already ended. However, the results
1157 * have not been requested.
1159 struct brw_perf_monitor_object
**unresolved
;
1160 int unresolved_elements
;
1161 int unresolved_array_size
;
1164 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1165 * the counter which MI_REPORT_PERF_COUNT stores there.
1167 const int *oa_snapshot_layout
;
1169 /** Number of 32-bit entries in a hardware counter snapshot. */
1170 int entries_per_oa_snapshot
;
1173 int num_atoms
[BRW_NUM_PIPELINES
];
1174 const struct brw_tracked_state render_atoms
[60];
1175 const struct brw_tracked_state compute_atoms
[9];
1177 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1181 enum aub_state_struct_type type
;
1183 } *state_batch_list
;
1184 int state_batch_count
;
1186 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1187 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1189 /* Interpolation modes, one byte per vue slot.
1190 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1192 struct interpolation_mode_map interpolation_mode
;
1194 /* PrimitiveRestart */
1197 bool enable_cut_index
;
1200 /** Computed depth/stencil/hiz state from the current attached
1201 * renderbuffers, valid only during the drawing state upload loop after
1202 * brw_workaround_depthstencil_alignment().
1205 struct intel_mipmap_tree
*depth_mt
;
1206 struct intel_mipmap_tree
*stencil_mt
;
1208 /* Inter-tile (page-aligned) byte offsets. */
1209 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1210 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1211 uint32_t tile_x
, tile_y
;
1214 uint32_t num_instances
;
1221 enum shader_time_shader_type
*types
;
1222 struct shader_times
*cumulative
;
1228 struct brw_fast_clear_state
*fast_clear_state
;
1230 __DRIcontext
*driContext
;
1231 struct intel_screen
*intelScreen
;
1234 /*======================================================================
1237 void brwInitVtbl( struct brw_context
*brw
);
1240 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1242 /*======================================================================
1245 extern const char *const brw_vendor_string
;
1247 extern const char *brw_get_renderer_string(unsigned deviceID
);
1250 DRI_CONF_BO_REUSE_DISABLED
,
1251 DRI_CONF_BO_REUSE_ALL
1254 void intel_update_renderbuffers(__DRIcontext
*context
,
1255 __DRIdrawable
*drawable
);
1256 void intel_prepare_render(struct brw_context
*brw
);
1258 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1259 __DRIdrawable
*drawable
);
1261 GLboolean
brwCreateContext(gl_api api
,
1262 const struct gl_config
*mesaVis
,
1263 __DRIcontext
*driContextPriv
,
1264 unsigned major_version
,
1265 unsigned minor_version
,
1269 void *sharedContextPrivate
);
1271 /*======================================================================
1274 GLuint
brw_get_rb_for_slice(struct brw_context
*brw
,
1275 struct intel_mipmap_tree
*mt
,
1276 unsigned level
, unsigned layer
, bool flat
);
1278 void brw_meta_updownsample(struct brw_context
*brw
,
1279 struct intel_mipmap_tree
*src
,
1280 struct intel_mipmap_tree
*dst
);
1282 void brw_meta_fbo_stencil_blit(struct brw_context
*brw
,
1283 struct gl_framebuffer
*read_fb
,
1284 struct gl_framebuffer
*draw_fb
,
1285 GLfloat srcX0
, GLfloat srcY0
,
1286 GLfloat srcX1
, GLfloat srcY1
,
1287 GLfloat dstX0
, GLfloat dstY0
,
1288 GLfloat dstX1
, GLfloat dstY1
);
1290 void brw_meta_stencil_updownsample(struct brw_context
*brw
,
1291 struct intel_mipmap_tree
*src
,
1292 struct intel_mipmap_tree
*dst
);
1294 bool brw_meta_fast_clear(struct brw_context
*brw
,
1295 struct gl_framebuffer
*fb
,
1297 bool partial_clear
);
1300 brw_meta_resolve_color(struct brw_context
*brw
,
1301 struct intel_mipmap_tree
*mt
);
1303 brw_meta_fast_clear_free(struct brw_context
*brw
);
1306 /*======================================================================
1309 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1310 uint32_t depth_level
,
1311 uint32_t depth_layer
,
1312 struct intel_mipmap_tree
*stencil_mt
,
1313 uint32_t *out_tile_mask_x
,
1314 uint32_t *out_tile_mask_y
);
1315 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1316 GLbitfield clear_mask
);
1318 /* brw_object_purgeable.c */
1319 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1321 /*======================================================================
1324 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1325 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1326 void brw_emit_query_begin(struct brw_context
*brw
);
1327 void brw_emit_query_end(struct brw_context
*brw
);
1329 /** gen6_queryobj.c */
1330 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1331 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1332 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1333 void brw_store_register_mem64(struct brw_context
*brw
,
1334 drm_intel_bo
*bo
, uint32_t reg
, int idx
);
1336 /** brw_conditional_render.c */
1337 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1338 bool brw_check_conditional_render(struct brw_context
*brw
);
1340 /** intel_batchbuffer.c */
1341 void brw_load_register_mem(struct brw_context
*brw
,
1344 uint32_t read_domains
, uint32_t write_domain
,
1346 void brw_load_register_mem64(struct brw_context
*brw
,
1349 uint32_t read_domains
, uint32_t write_domain
,
1352 /*======================================================================
1355 void brw_debug_batch(struct brw_context
*brw
);
1356 void brw_annotate_aub(struct brw_context
*brw
);
1358 /*======================================================================
1361 void brw_validate_textures( struct brw_context
*brw
);
1364 /*======================================================================
1367 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1369 /* Per-thread scratch space is a power-of-two multiple of 1KB. */
1371 brw_get_scratch_size(int size
)
1373 return util_next_power_of_two(size
| 1023);
1375 void brw_get_scratch_bo(struct brw_context
*brw
,
1376 drm_intel_bo
**scratch_bo
, int size
);
1377 void brw_init_shader_time(struct brw_context
*brw
);
1378 int brw_get_shader_time_index(struct brw_context
*brw
,
1379 struct gl_shader_program
*shader_prog
,
1380 struct gl_program
*prog
,
1381 enum shader_time_shader_type type
);
1382 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1383 void brw_destroy_shader_time(struct brw_context
*brw
);
1387 void brw_upload_urb_fence(struct brw_context
*brw
);
1391 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1393 /* brw_fs_reg_allocate.cpp
1395 void brw_fs_alloc_reg_sets(struct brw_compiler
*compiler
);
1397 /* brw_vec4_reg_allocate.cpp */
1398 void brw_vec4_alloc_reg_set(struct brw_compiler
*compiler
);
1401 int brw_disassemble_inst(FILE *file
, const struct brw_device_info
*devinfo
,
1402 struct brw_inst
*inst
, bool is_compacted
);
1405 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1407 /* brw_draw_upload.c */
1408 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1409 const struct gl_client_array
*glarray
);
1411 static inline unsigned
1412 brw_get_index_type(GLenum type
)
1414 assert((type
== GL_UNSIGNED_BYTE
)
1415 || (type
== GL_UNSIGNED_SHORT
)
1416 || (type
== GL_UNSIGNED_INT
));
1418 /* The possible values for type are GL_UNSIGNED_BYTE (0x1401),
1419 * GL_UNSIGNED_SHORT (0x1403), and GL_UNSIGNED_INT (0x1405) which we want
1420 * to map to scale factors of 0, 1, and 2, respectively. These scale
1421 * factors are then left-shfited by 8 to be in the correct position in the
1422 * CMD_INDEX_BUFFER packet.
1424 * Subtracting 0x1401 gives 0, 2, and 4. Shifting left by 7 afterwards
1425 * gives 0x00000000, 0x00000100, and 0x00000200. These just happen to be
1426 * the values the need to be written in the CMD_INDEX_BUFFER packet.
1428 return (type
- 0x1401) << 7;
1431 void brw_prepare_vertices(struct brw_context
*brw
);
1433 /* brw_wm_surface_state.c */
1434 void brw_init_surface_formats(struct brw_context
*brw
);
1435 void brw_create_constant_surface(struct brw_context
*brw
,
1439 uint32_t *out_offset
,
1441 void brw_create_buffer_surface(struct brw_context
*brw
,
1445 uint32_t *out_offset
,
1447 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1449 uint32_t *surf_offset
);
1451 brw_update_sol_surface(struct brw_context
*brw
,
1452 struct gl_buffer_object
*buffer_obj
,
1453 uint32_t *out_offset
, unsigned num_vector_components
,
1454 unsigned stride_dwords
, unsigned offset_dwords
);
1455 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1456 struct gl_shader
*shader
,
1457 struct brw_stage_state
*stage_state
,
1458 struct brw_stage_prog_data
*prog_data
,
1460 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1461 struct gl_shader
*shader
,
1462 struct brw_stage_state
*stage_state
,
1463 struct brw_stage_prog_data
*prog_data
);
1464 void brw_upload_image_surfaces(struct brw_context
*brw
,
1465 struct gl_shader
*shader
,
1466 struct brw_stage_state
*stage_state
,
1467 struct brw_stage_prog_data
*prog_data
);
1469 /* brw_surface_formats.c */
1470 bool brw_render_target_supported(struct brw_context
*brw
,
1471 struct gl_renderbuffer
*rb
);
1472 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1473 mesa_format
brw_lower_mesa_image_format(const struct brw_device_info
*devinfo
,
1474 mesa_format format
);
1476 /* brw_performance_monitor.c */
1477 void brw_init_performance_monitors(struct brw_context
*brw
);
1478 void brw_dump_perf_monitors(struct brw_context
*brw
);
1479 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1480 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1482 /* intel_buffer_objects.c */
1483 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1484 const char *bo_name
);
1485 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1486 const char *bo_name
);
1488 /* intel_extensions.c */
1489 extern void intelInitExtensions(struct gl_context
*ctx
);
1492 extern int intel_translate_shadow_compare_func(GLenum func
);
1493 extern int intel_translate_compare_func(GLenum func
);
1494 extern int intel_translate_stencil_op(GLenum op
);
1495 extern int intel_translate_logic_op(GLenum opcode
);
1497 /* intel_syncobj.c */
1498 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1501 struct gl_transform_feedback_object
*
1502 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1504 brw_delete_transform_feedback(struct gl_context
*ctx
,
1505 struct gl_transform_feedback_object
*obj
);
1507 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1508 struct gl_transform_feedback_object
*obj
);
1510 brw_end_transform_feedback(struct gl_context
*ctx
,
1511 struct gl_transform_feedback_object
*obj
);
1513 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1514 struct gl_transform_feedback_object
*obj
,
1517 /* gen7_sol_state.c */
1519 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1520 struct gl_transform_feedback_object
*obj
);
1522 gen7_end_transform_feedback(struct gl_context
*ctx
,
1523 struct gl_transform_feedback_object
*obj
);
1525 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1526 struct gl_transform_feedback_object
*obj
);
1528 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1529 struct gl_transform_feedback_object
*obj
);
1531 /* brw_blorp_blit.cpp */
1533 brw_blorp_framebuffer(struct brw_context
*brw
,
1534 struct gl_framebuffer
*readFb
,
1535 struct gl_framebuffer
*drawFb
,
1536 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1537 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1538 GLbitfield mask
, GLenum filter
);
1541 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1542 struct gl_renderbuffer
*src_rb
,
1543 struct gl_texture_image
*dst_image
,
1545 int srcX0
, int srcY0
,
1546 int dstX0
, int dstY0
,
1547 int width
, int height
);
1549 /* gen6_multisample_state.c */
1551 gen6_determine_sample_mask(struct brw_context
*brw
);
1554 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1555 unsigned num_samples
);
1557 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1559 gen6_get_sample_position(struct gl_context
*ctx
,
1560 struct gl_framebuffer
*fb
,
1564 gen6_set_sample_maps(struct gl_context
*ctx
);
1566 /* gen8_multisample_state.c */
1567 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1568 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1572 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1573 unsigned gs_size
, unsigned fs_size
);
1576 gen7_emit_urb_state(struct brw_context
*brw
,
1577 unsigned nr_vs_entries
, unsigned vs_size
,
1578 unsigned vs_start
, unsigned nr_gs_entries
,
1579 unsigned gs_size
, unsigned gs_start
);
1584 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1588 brw_init_compute_functions(struct dd_function_table
*functions
);
1590 /*======================================================================
1591 * Inline conversion functions. These are better-typed than the
1592 * macros used previously:
1594 static inline struct brw_context
*
1595 brw_context( struct gl_context
*ctx
)
1597 return (struct brw_context
*)ctx
;
1600 static inline struct brw_vertex_program
*
1601 brw_vertex_program(struct gl_vertex_program
*p
)
1603 return (struct brw_vertex_program
*) p
;
1606 static inline const struct brw_vertex_program
*
1607 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1609 return (const struct brw_vertex_program
*) p
;
1612 static inline struct brw_geometry_program
*
1613 brw_geometry_program(struct gl_geometry_program
*p
)
1615 return (struct brw_geometry_program
*) p
;
1618 static inline struct brw_fragment_program
*
1619 brw_fragment_program(struct gl_fragment_program
*p
)
1621 return (struct brw_fragment_program
*) p
;
1624 static inline const struct brw_fragment_program
*
1625 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1627 return (const struct brw_fragment_program
*) p
;
1630 static inline struct brw_compute_program
*
1631 brw_compute_program(struct gl_compute_program
*p
)
1633 return (struct brw_compute_program
*) p
;
1637 * Pre-gen6, the register file of the EUs was shared between threads,
1638 * and each thread used some subset allocated on a 16-register block
1639 * granularity. The unit states wanted these block counts.
1642 brw_register_blocks(int reg_count
)
1644 return ALIGN(reg_count
, 16) / 16 - 1;
1647 static inline uint32_t
1648 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1649 uint32_t prog_offset
)
1651 if (brw
->gen
>= 5) {
1652 /* Using state base address. */
1656 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1660 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1662 return brw
->cache
.bo
->offset64
+ prog_offset
;
1665 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1666 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1667 struct exec_list
*instructions
);
1668 bool brw_do_lower_unnormalized_offset(struct exec_list
*instructions
);
1670 struct opcode_desc
{
1676 extern const struct opcode_desc opcode_descs
[128];
1677 extern const char * const conditional_modifier
[16];
1678 extern const char *const pred_ctrl_align16
[16];
1681 brw_emit_depthbuffer(struct brw_context
*brw
);
1684 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1685 struct intel_mipmap_tree
*depth_mt
,
1686 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1687 uint32_t depth_surface_type
,
1688 struct intel_mipmap_tree
*stencil_mt
,
1689 bool hiz
, bool separate_stencil
,
1690 uint32_t width
, uint32_t height
,
1691 uint32_t tile_x
, uint32_t tile_y
);
1694 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1695 struct intel_mipmap_tree
*depth_mt
,
1696 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1697 uint32_t depth_surface_type
,
1698 struct intel_mipmap_tree
*stencil_mt
,
1699 bool hiz
, bool separate_stencil
,
1700 uint32_t width
, uint32_t height
,
1701 uint32_t tile_x
, uint32_t tile_y
);
1704 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1705 struct intel_mipmap_tree
*depth_mt
,
1706 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1707 uint32_t depth_surface_type
,
1708 struct intel_mipmap_tree
*stencil_mt
,
1709 bool hiz
, bool separate_stencil
,
1710 uint32_t width
, uint32_t height
,
1711 uint32_t tile_x
, uint32_t tile_y
);
1713 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1714 struct intel_mipmap_tree
*depth_mt
,
1715 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1716 uint32_t depth_surface_type
,
1717 struct intel_mipmap_tree
*stencil_mt
,
1718 bool hiz
, bool separate_stencil
,
1719 uint32_t width
, uint32_t height
,
1720 uint32_t tile_x
, uint32_t tile_y
);
1722 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1723 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);
1725 uint32_t get_hw_prim_for_gl_prim(int mode
);
1728 gen6_upload_push_constants(struct brw_context
*brw
,
1729 const struct gl_program
*prog
,
1730 const struct brw_stage_prog_data
*prog_data
,
1731 struct brw_stage_state
*stage_state
,
1732 enum aub_state_struct_type type
);
1735 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
1736 const struct intel_mipmap_tree
*mt
);
1738 /* brw_pipe_control.c */
1739 int brw_init_pipe_control(struct brw_context
*brw
,
1740 const struct brw_device_info
*info
);
1741 void brw_fini_pipe_control(struct brw_context
*brw
);
1743 void brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
);
1744 void brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
1745 drm_intel_bo
*bo
, uint32_t offset
,
1746 uint32_t imm_lower
, uint32_t imm_upper
);
1747 void brw_emit_mi_flush(struct brw_context
*brw
);
1748 void brw_emit_post_sync_nonzero_flush(struct brw_context
*brw
);
1749 void brw_emit_depth_stall_flushes(struct brw_context
*brw
);
1750 void gen7_emit_vs_workaround_flush(struct brw_context
*brw
);
1751 void gen7_emit_cs_stall_flush(struct brw_context
*brw
);