2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
38 #include "main/imports.h"
39 #include "main/macros.h"
41 #include "main/mtypes.h"
42 #include "brw_structs.h"
43 #include "intel_aub.h"
44 #include "program/prog_parameter.h"
48 /* Evil hack for using libdrm in a c++ compiler. */
53 #include <intel_bufmgr.h>
63 #include "intel_debug.h"
64 #include "intel_screen.h"
65 #include "intel_tex_obj.h"
66 #include "intel_resolve_map.h"
70 * URB - uniform resource buffer. A mid-sized buffer which is
71 * partitioned between the fixed function units and used for passing
72 * values (vertices, primitives, constants) between them.
74 * CURBE - constant URB entry. An urb region (entry) used to hold
75 * constant values which the fixed function units can be instructed to
76 * preload into the GRF when spawning a thread.
78 * VUE - vertex URB entry. An urb entry holding a vertex and usually
79 * a vertex header. The header contains control information and
80 * things like primitive type, Begin/end flags and clip codes.
82 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
83 * unit holding rasterization and interpolation parameters.
85 * GRF - general register file. One of several register files
86 * addressable by programmed threads. The inputs (r0, payload, curbe,
87 * urb) of the thread are preloaded to this area before the thread is
88 * spawned. The registers are individually 8 dwords wide and suitable
89 * for general usage. Registers holding thread input values are not
90 * special and may be overwritten.
92 * MRF - message register file. Threads communicate (and terminate)
93 * by sending messages. Message parameters are placed in contiguous
94 * MRF registers. All program output is via these messages. URB
95 * entries are populated by sending a message to the shared URB
96 * function containing the new data, together with a control word,
97 * often an unmodified copy of R0.
99 * R0 - GRF register 0. Typically holds control information used when
100 * sending messages to other threads.
102 * EU or GEN4 EU: The name of the programmable subsystem of the
103 * i965 hardware. Threads are executed by the EU, the registers
104 * described above are part of the EU architecture.
106 * Fixed function units:
108 * CS - Command streamer. Notional first unit, little software
109 * interaction. Holds the URB entries used for constant data, ie the
112 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
113 * this unit is responsible for pulling vertices out of vertex buffers
114 * in vram and injecting them into the processing pipe as VUEs. If
115 * enabled, it first passes them to a VS thread which is a good place
116 * for the driver to implement any active vertex shader.
118 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
119 * enabled, incoming strips etc are passed to GS threads in individual
120 * line/triangle/point units. The GS thread may perform arbitary
121 * computation and emit whatever primtives with whatever vertices it
122 * chooses. This makes GS an excellent place to implement GL's
123 * unfilled polygon modes, though of course it is capable of much
124 * more. Additionally, GS is used to translate away primitives not
125 * handled by latter units, including Quads and Lineloops.
127 * CS - Clipper. Mesa's clipping algorithms are imported to run on
128 * this unit. The fixed function part performs cliptesting against
129 * the 6 fixed clipplanes and makes descisions on whether or not the
130 * incoming primitive needs to be passed to a thread for clipping.
131 * User clip planes are handled via cooperation with the VS thread.
133 * SF - Strips Fans or Setup: Triangles are prepared for
134 * rasterization. Interpolation coefficients are calculated.
135 * Flatshading and two-side lighting usually performed here.
137 * WM - Windower. Interpolation of vertex attributes performed here.
138 * Fragment shader implemented here. SIMD aspects of EU taken full
139 * advantage of, as pixels are processed in blocks of 16.
141 * CC - Color Calculator. No EU threads associated with this unit.
142 * Handles blending and (presumably) depth and stencil testing.
147 struct brw_vs_prog_key
;
148 struct brw_vec4_prog_key
;
149 struct brw_wm_prog_key
;
150 struct brw_wm_prog_data
;
154 BRW_STATE_FRAGMENT_PROGRAM
,
155 BRW_STATE_GEOMETRY_PROGRAM
,
156 BRW_STATE_VERTEX_PROGRAM
,
157 BRW_STATE_CURBE_OFFSETS
,
158 BRW_STATE_REDUCED_PRIMITIVE
,
163 BRW_STATE_VS_BINDING_TABLE
,
164 BRW_STATE_GS_BINDING_TABLE
,
165 BRW_STATE_PS_BINDING_TABLE
,
169 BRW_STATE_INDEX_BUFFER
,
170 BRW_STATE_VS_CONSTBUF
,
171 BRW_STATE_GS_CONSTBUF
,
172 BRW_STATE_PROGRAM_CACHE
,
173 BRW_STATE_STATE_BASE_ADDRESS
,
174 BRW_STATE_VUE_MAP_VS
,
175 BRW_STATE_VUE_MAP_GEOM_OUT
,
176 BRW_STATE_TRANSFORM_FEEDBACK
,
177 BRW_STATE_RASTERIZER_DISCARD
,
179 BRW_STATE_UNIFORM_BUFFER
,
180 BRW_STATE_ATOMIC_BUFFER
,
181 BRW_STATE_META_IN_PROGRESS
,
182 BRW_STATE_INTERPOLATION_MAP
,
183 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
184 BRW_STATE_NUM_SAMPLES
,
185 BRW_STATE_TEXTURE_BUFFER
,
186 BRW_STATE_GEN4_UNIT_STATE
,
193 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
194 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
195 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
196 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
197 #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
198 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
199 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
200 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
201 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
202 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
203 #define BRW_NEW_VS_BINDING_TABLE (1ull << BRW_STATE_VS_BINDING_TABLE)
204 #define BRW_NEW_GS_BINDING_TABLE (1ull << BRW_STATE_GS_BINDING_TABLE)
205 #define BRW_NEW_PS_BINDING_TABLE (1ull << BRW_STATE_PS_BINDING_TABLE)
206 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
207 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
209 * Used for any batch entry with a relocated pointer that will be used
210 * by any 3D rendering.
212 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
213 /** \see brw.state.depth_region */
214 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
215 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
216 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
217 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
218 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
219 #define BRW_NEW_VUE_MAP_VS (1ull << BRW_STATE_VUE_MAP_VS)
220 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
221 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
222 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
223 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
224 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
225 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
226 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
227 #define BRW_NEW_INTERPOLATION_MAP (1ull << BRW_STATE_INTERPOLATION_MAP)
228 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
229 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
230 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
231 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
232 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
233 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
234 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
236 struct brw_state_flags
{
237 /** State update flags signalled by mesa internals */
240 * State update flags signalled as the result of brw_tracked_state updates
244 * State update flags that used to be signalled by brw_state_cache.c
247 * Now almost all of that state is just streamed out on demand, but the
248 * flags for those state blobs updating have stayed in the same bitfield.
249 * brw_state_cache.c still flags CACHE_NEW_*_PROG.
254 /** Subclass of Mesa vertex program */
255 struct brw_vertex_program
{
256 struct gl_vertex_program program
;
261 /** Subclass of Mesa geometry program */
262 struct brw_geometry_program
{
263 struct gl_geometry_program program
;
264 unsigned id
; /**< serial no. to identify geom progs, never re-used */
268 /** Subclass of Mesa fragment program */
269 struct brw_fragment_program
{
270 struct gl_fragment_program program
;
271 GLuint id
; /**< serial no. to identify frag progs, never re-used */
275 /** Subclass of Mesa compute program */
276 struct brw_compute_program
{
277 struct gl_compute_program program
;
278 unsigned id
; /**< serial no. to identify compute progs, never re-used */
283 struct gl_shader base
;
288 /* Note: If adding fields that need anything besides a normal memcmp() for
289 * comparing them, be sure to go fix brw_stage_prog_data_compare().
291 struct brw_stage_prog_data
{
293 /** size of our binding table. */
297 * surface indices for the various groups of surfaces
299 uint32_t pull_constants_start
;
300 uint32_t texture_start
;
301 uint32_t gather_texture_start
;
304 uint32_t shader_time_start
;
308 GLuint nr_params
; /**< number of float params/constants */
309 GLuint nr_pull_params
;
311 unsigned curb_read_length
;
312 unsigned total_scratch
;
315 * Register where the thread expects to find input data from the URB
316 * (typically uniforms, followed by vertex or fragment attributes).
318 unsigned dispatch_grf_start_reg
;
320 /* Pointers to tracked values (only valid once
321 * _mesa_load_state_parameters has been called at runtime).
323 * These must be the last fields of the struct (see
324 * brw_stage_prog_data_compare()).
326 const gl_constant_value
**param
;
327 const gl_constant_value
**pull_param
;
330 /* Data about a particular attempt to compile a program. Note that
331 * there can be many of these, each in a different GL state
332 * corresponding to a different brw_wm_prog_key struct, with different
335 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
338 struct brw_wm_prog_data
{
339 struct brw_stage_prog_data base
;
341 GLuint num_varying_inputs
;
343 GLuint dispatch_grf_start_reg_16
;
345 GLuint reg_blocks_16
;
349 * surface indices the WM-specific surfaces
351 uint32_t render_target_start
;
357 bool uses_pos_offset
;
360 uint32_t prog_offset_16
;
363 * Mask of which interpolation modes are required by the fragment shader.
364 * Used in hardware setup on gen6+.
366 uint32_t barycentric_interp_modes
;
369 * Map from gl_varying_slot to the position within the FS setup data
370 * payload where the varying's attribute vertex deltas should be delivered.
371 * For varying slots that are not used by the FS, the value is -1.
373 int urb_setup
[VARYING_SLOT_MAX
];
377 * Enum representing the i965-specific vertex results that don't correspond
378 * exactly to any element of gl_varying_slot. The values of this enum are
379 * assigned such that they don't conflict with gl_varying_slot.
383 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
384 BRW_VARYING_SLOT_PAD
,
386 * Technically this is not a varying but just a placeholder that
387 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
388 * builtin variable to be compiled correctly. see compile_sf_prog() for
391 BRW_VARYING_SLOT_PNTC
,
392 BRW_VARYING_SLOT_COUNT
397 * Data structure recording the relationship between the gl_varying_slot enum
398 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
399 * single octaword within the VUE (128 bits).
401 * Note that each BRW register contains 256 bits (2 octawords), so when
402 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
403 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
404 * in a vertex shader), each register corresponds to a single VUE slot, since
405 * it contains data for two separate vertices.
409 * Bitfield representing all varying slots that are (a) stored in this VUE
410 * map, and (b) actually written by the shader. Does not include any of
411 * the additional varying slots defined in brw_varying_slot.
413 GLbitfield64 slots_valid
;
416 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
417 * not stored in a slot (because they are not written, or because
418 * additional processing is applied before storing them in the VUE), the
421 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
424 * Map from VUE slot to gl_varying_slot value. For slots that do not
425 * directly correspond to a gl_varying_slot, the value comes from
428 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
429 * simplifies code that uses the value stored in slot_to_varying to
430 * create a bit mask).
432 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
435 * Total number of VUE slots in use
441 * Convert a VUE slot number into a byte offset within the VUE.
443 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
449 * Convert a vertex output (brw_varying_slot) into a byte offset within the
452 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
455 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
458 void brw_compute_vue_map(struct brw_context
*brw
, struct brw_vue_map
*vue_map
,
459 GLbitfield64 slots_valid
);
463 * Bitmask indicating which fragment shader inputs represent varyings (and
464 * hence have to be delivered to the fragment shader by the SF/SBE stage).
466 #define BRW_FS_VARYING_INPUT_MASK \
467 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
468 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
472 * Mapping of VUE map slots to interpolation modes.
474 struct interpolation_mode_map
{
475 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
478 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
480 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
481 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
487 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
489 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
490 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
497 struct brw_sf_prog_data
{
498 GLuint urb_read_length
;
501 /* Each vertex may have upto 12 attributes, 4 components each,
502 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
505 * Actually we use 4 for each, so call it 12 rows.
507 GLuint urb_entry_size
;
512 * We always program SF to start reading at an offset of 1 (2 varying slots)
513 * from the start of the vertex URB entry. This causes it to skip:
514 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
515 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
517 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
520 struct brw_clip_prog_data
{
521 GLuint curb_read_length
; /* user planes? */
523 GLuint urb_read_length
;
527 struct brw_ff_gs_prog_data
{
528 GLuint urb_read_length
;
532 * Gen6 transform feedback: Amount by which the streaming vertex buffer
533 * indices should be incremented each time the GS is invoked.
535 unsigned svbi_postincrement_value
;
539 /* Note: brw_vec4_prog_data_compare() must be updated when adding fields to
542 struct brw_vec4_prog_data
{
543 struct brw_stage_prog_data base
;
544 struct brw_vue_map vue_map
;
546 GLuint urb_read_length
;
549 /* Used for calculating urb partitions. In the VS, this is the size of the
550 * URB entry used for both input and output to the thread. In the GS, this
551 * is the size of the URB entry used for output.
553 GLuint urb_entry_size
;
557 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
560 struct brw_vs_prog_data
{
561 struct brw_vec4_prog_data base
;
563 GLbitfield64 inputs_read
;
566 bool uses_instanceid
;
569 /** Number of texture sampler units */
570 #define BRW_MAX_TEX_UNIT 32
572 /** Max number of render targets in a shader */
573 #define BRW_MAX_DRAW_BUFFERS 8
575 /** Max number of atomic counter buffer objects in a shader */
576 #define BRW_MAX_ABO 16
579 * Max number of binding table entries used for stream output.
581 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
582 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
584 * On Gen6, the size of transform feedback data is limited not by the number
585 * of components but by the number of binding table entries we set aside. We
586 * use one binding table entry for a float, one entry for a vector, and one
587 * entry per matrix column. Since the only way we can communicate our
588 * transform feedback capabilities to the client is via
589 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
590 * worst case, in which all the varyings are floats, so we use up one binding
591 * table entry per component. Therefore we need to set aside at least 64
592 * binding table entries for use by transform feedback.
594 * Note: since we don't currently pack varyings, it is currently impossible
595 * for the client to actually use up all of these binding table entries--if
596 * all of their varyings were floats, they would run out of varying slots and
597 * fail to link. But that's a bug, so it seems prudent to go ahead and
598 * allocate the number of binding table entries we will need once the bug is
601 #define BRW_MAX_SOL_BINDINGS 64
603 /** Maximum number of actual buffers used for stream output */
604 #define BRW_MAX_SOL_BUFFERS 4
606 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
607 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
610 2 /* shader time, pull constants */)
612 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
614 /* Note: brw_gs_prog_data_compare() must be updated when adding fields to
617 struct brw_gs_prog_data
619 struct brw_vec4_prog_data base
;
622 * Size of an output vertex, measured in HWORDS (32 bytes).
624 unsigned output_vertex_size_hwords
;
626 unsigned output_topology
;
629 * Size of the control data (cut bits or StreamID bits), in hwords (32
630 * bytes). 0 if there is no control data.
632 unsigned control_data_header_size_hwords
;
635 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
636 * if the control data is StreamID bits, or
637 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
638 * Ignored if control_data_header_size is 0.
640 unsigned control_data_format
;
642 bool include_primitive_id
;
647 * Dispatch mode, can be any of:
648 * GEN7_GS_DISPATCH_MODE_DUAL_OBJECT
649 * GEN7_GS_DISPATCH_MODE_DUAL_INSTANCE
650 * GEN7_GS_DISPATCH_MODE_SINGLE
655 * Gen6 transform feedback enabled flag.
657 bool gen6_xfb_enabled
;
660 * Gen6: Provoking vertex convention for odd-numbered triangles
666 * Gen6: Number of varyings that are output to transform feedback.
668 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
671 * Gen6: Map from the index of a transform feedback binding table entry to the
672 * gl_varying_slot that should be streamed out through that binding table
675 unsigned char transform_feedback_bindings
[BRW_MAX_SOL_BINDINGS
];
678 * Gen6: Map from the index of a transform feedback binding table entry to the
679 * swizzles that should be used when streaming out data through that
680 * binding table entry.
682 unsigned char transform_feedback_swizzles
[BRW_MAX_SOL_BINDINGS
];
686 * Stride in bytes between shader_time entries.
688 * We separate entries by a cacheline to reduce traffic between EUs writing to
691 #define SHADER_TIME_STRIDE 64
706 struct brw_cache_item
{
708 * Effectively part of the key, cache_id identifies what kind of state
709 * buffer is involved, and also which brw->state.dirty.cache flag should
710 * be set when this cache item is chosen.
712 enum brw_cache_id cache_id
;
713 /** 32-bit hash of the key data */
715 GLuint key_size
; /* for variable-sized keys */
722 struct brw_cache_item
*next
;
726 typedef bool (*cache_aux_compare_func
)(const void *a
, const void *b
);
727 typedef void (*cache_aux_free_func
)(const void *aux
);
730 struct brw_context
*brw
;
732 struct brw_cache_item
**items
;
734 GLuint size
, n_items
;
736 uint32_t next_offset
;
740 * Optional functions used in determining whether the prog_data for a new
741 * cache item matches an existing cache item (in case there's relevant data
742 * outside of the prog_data). If NULL, a plain memcmp is done.
744 cache_aux_compare_func aux_compare
[BRW_MAX_CACHE
];
745 /** Optional functions for freeing other pointers attached to a prog_data. */
746 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
750 /* Considered adding a member to this struct to document which flags
751 * an update might raise so that ordering of the state atoms can be
752 * checked or derived at runtime. Dropped the idea in favor of having
753 * a debug mode where the state is monitored for flags which are
754 * raised that have already been tested against.
756 struct brw_tracked_state
{
757 struct brw_state_flags dirty
;
758 void (*emit
)( struct brw_context
*brw
);
761 enum shader_time_shader_type
{
777 /* Flags for brw->state.cache.
779 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
780 #define CACHE_NEW_BLORP_BLIT_PROG (1<<BRW_BLORP_BLIT_PROG)
781 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
782 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
783 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
784 #define CACHE_NEW_FF_GS_PROG (1<<BRW_FF_GS_PROG)
785 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
786 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
788 struct brw_vertex_buffer
{
789 /** Buffer object containing the uploaded vertex data */
792 /** Byte stride between elements in the uploaded array */
796 struct brw_vertex_element
{
797 const struct gl_client_array
*glarray
;
801 /** Offset of the first element within the buffer object */
805 struct brw_query_object
{
806 struct gl_query_object Base
;
808 /** Last query BO associated with this query. */
811 /** Last index in bo with query data for this object. */
815 struct intel_sync_object
{
816 struct gl_sync_object Base
;
818 /** Batch associated with this sync object */
828 struct intel_batchbuffer
{
829 /** Current batchbuffer being queued up. */
831 /** Last BO submitted to the hardware. Used for glFinish(). */
832 drm_intel_bo
*last_bo
;
833 /** BO for post-sync nonzero writes for gen6 workaround. */
834 drm_intel_bo
*workaround_bo
;
835 bool need_workaround_flush
;
837 uint16_t emit
, total
;
838 uint16_t used
, reserved_space
;
841 #define BATCH_SZ (8192*sizeof(uint32_t))
843 uint32_t state_batch_offset
;
844 enum brw_gpu_ring ring
;
845 bool needs_sol_reset
;
853 #define BRW_MAX_XFB_STREAMS 4
855 struct brw_transform_feedback_object
{
856 struct gl_transform_feedback_object base
;
858 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
859 drm_intel_bo
*offset_bo
;
861 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
864 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
865 GLenum primitive_mode
;
868 * Count of primitives generated during this transform feedback operation.
871 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
872 drm_intel_bo
*prim_count_bo
;
873 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
877 * Number of vertices written between last Begin/EndTransformFeedback().
879 * Used to implement DrawTransformFeedback().
881 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
882 bool vertices_written_valid
;
886 * Data shared between each programmable stage in the pipeline (vs, gs, and
889 struct brw_stage_state
891 gl_shader_stage stage
;
892 struct brw_stage_prog_data
*prog_data
;
895 * Optional scratch buffer used to store spilled register values and
896 * variably-indexed GRF arrays.
898 drm_intel_bo
*scratch_bo
;
900 /** Offset in the program cache to the program */
901 uint32_t prog_offset
;
903 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
904 uint32_t state_offset
;
906 uint32_t push_const_offset
; /* Offset in the batchbuffer */
907 int push_const_size
; /* in 256-bit register increments */
909 /* Binding table: pointers to SURFACE_STATE entries. */
910 uint32_t bind_bo_offset
;
911 uint32_t surf_offset
[BRW_MAX_SURFACES
];
913 /** SAMPLER_STATE count and table offset */
914 uint32_t sampler_count
;
915 uint32_t sampler_offset
;
920 * brw_context is derived from gl_context.
924 struct gl_context ctx
; /**< base class, must be first field */
928 void (*update_texture_surface
)(struct gl_context
*ctx
,
930 uint32_t *surf_offset
,
932 void (*update_renderbuffer_surface
)(struct brw_context
*brw
,
933 struct gl_renderbuffer
*rb
,
936 void (*update_null_renderbuffer_surface
)(struct brw_context
*brw
,
939 void (*create_raw_surface
)(struct brw_context
*brw
,
943 uint32_t *out_offset
,
945 void (*emit_buffer_surface_state
)(struct brw_context
*brw
,
946 uint32_t *out_offset
,
948 unsigned buffer_offset
,
949 unsigned surface_format
,
950 unsigned buffer_size
,
956 * Send the appropriate state packets to configure depth, stencil, and
957 * HiZ buffers (i965+ only)
959 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
960 struct intel_mipmap_tree
*depth_mt
,
961 uint32_t depth_offset
,
962 uint32_t depthbuffer_format
,
963 uint32_t depth_surface_type
,
964 struct intel_mipmap_tree
*stencil_mt
,
965 bool hiz
, bool separate_stencil
,
966 uint32_t width
, uint32_t height
,
967 uint32_t tile_x
, uint32_t tile_y
);
973 drm_intel_context
*hw_ctx
;
976 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
977 * and would need flushing before being used from another cache domain that
978 * isn't coherent with it (i.e. the sampler).
980 struct set
*render_cache
;
983 * Number of resets observed in the system at context creation.
985 * This is tracked in the context so that we can determine that another
988 uint32_t reset_count
;
990 struct intel_batchbuffer batch
;
995 uint32_t next_offset
;
999 * Set if rendering has occured to the drawable's front buffer.
1001 * This is used in the DRI2 case to detect that glFlush should also copy
1002 * the contents of the fake front buffer to the real front buffer.
1004 bool front_buffer_dirty
;
1006 /** Framerate throttling: @{ */
1007 drm_intel_bo
*first_post_swapbuffers_batch
;
1018 bool always_flush_batch
;
1019 bool always_flush_cache
;
1020 bool disable_throttling
;
1022 bool disable_derivative_optimization
;
1024 driOptionCache optionCache
;
1027 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
1029 GLenum reduced_primitive
;
1032 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
1033 * variable is set, this is the flag indicating to do expensive work that
1034 * might lead to a perf_debug() call.
1038 uint32_t max_gtt_map_object_size
;
1049 bool has_separate_stencil
;
1050 bool must_use_separate_stencil
;
1053 bool has_surface_tile_offset
;
1055 bool has_negative_rhw_bug
;
1061 * Some versions of Gen hardware don't do centroid interpolation correctly
1062 * on unlit pixels, causing incorrect values for derivatives near triangle
1063 * edges. Enabling this flag causes the fragment shader to use
1064 * non-centroid interpolation for unlit pixels, at the expense of two extra
1065 * fragment shader instructions.
1067 bool needs_unlit_centroid_workaround
;
1071 struct brw_state_flags dirty
;
1074 struct brw_cache cache
;
1076 /** IDs for meta stencil blit shader programs. */
1077 unsigned meta_stencil_blit_programs
[2];
1079 /* Whether a meta-operation is in progress. */
1080 bool meta_in_progress
;
1082 /* Whether the last depth/stencil packets were both NULL. */
1083 bool no_depth_or_stencil
;
1085 /* The last PMA stall bits programmed. */
1086 uint32_t pma_stall_bits
;
1089 /** Does the current draw use the index buffer? */
1092 int start_vertex_location
;
1093 int base_vertex_location
;
1096 * Buffer and offset used for GL_ARB_shader_draw_parameters
1097 * (for now, only gl_BaseVertex).
1099 drm_intel_bo
*draw_params_bo
;
1100 uint32_t draw_params_offset
;
1104 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
1105 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
1107 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
1111 /* Summary of size and varying of active arrays, so we can check
1112 * for changes to this state:
1114 unsigned int min_index
, max_index
;
1116 /* Offset from start of vertex buffer so we can avoid redefining
1117 * the same VB packed over and over again.
1119 unsigned int start_vertex_bias
;
1124 * Index buffer for this draw_prims call.
1126 * Updates are signaled by BRW_NEW_INDICES.
1128 const struct _mesa_index_buffer
*ib
;
1130 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
1134 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
1135 * avoid re-uploading the IB packet over and over if we're actually
1136 * referencing the same index buffer.
1138 unsigned int start_vertex_offset
;
1141 /* Active vertex program:
1143 const struct gl_vertex_program
*vertex_program
;
1144 const struct gl_geometry_program
*geometry_program
;
1145 const struct gl_fragment_program
*fragment_program
;
1148 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
1149 * that we don't have to reemit that state every time we change FBOs.
1154 * Platform specific constants containing the maximum number of threads
1155 * for each pipeline stage.
1161 /* BRW_NEW_URB_ALLOCATIONS:
1164 GLuint vsize
; /* vertex size plus header in urb registers */
1165 GLuint gsize
; /* GS output size in urb registers */
1166 GLuint csize
; /* constant buffer size in urb registers */
1167 GLuint sfsize
; /* setup data size in urb registers */
1171 GLuint min_vs_entries
; /* Minimum number of VS entries */
1172 GLuint max_vs_entries
; /* Maximum number of VS entries */
1173 GLuint max_gs_entries
; /* Maximum number of GS entries */
1175 GLuint nr_vs_entries
;
1176 GLuint nr_gs_entries
;
1177 GLuint nr_clip_entries
;
1178 GLuint nr_sf_entries
;
1179 GLuint nr_cs_entries
;
1186 GLuint size
; /* Hardware URB size, in KB. */
1188 /* True if the most recently sent _3DSTATE_URB message allocated
1189 * URB space for the GS.
1195 /* BRW_NEW_CURBE_OFFSETS:
1198 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1199 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1207 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1208 * for upload to the CURBE.
1210 drm_intel_bo
*curbe_bo
;
1211 /** Offset within curbe_bo of space for current curbe entry */
1212 GLuint curbe_offset
;
1216 * Layout of vertex data exiting the vertex shader.
1218 * BRW_NEW_VUE_MAP_VS is flagged when this VUE map changes.
1220 struct brw_vue_map vue_map_vs
;
1223 * Layout of vertex data exiting the geometry portion of the pipleine.
1224 * This comes from the geometry shader if one exists, otherwise from the
1227 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1229 struct brw_vue_map vue_map_geom_out
;
1232 struct brw_stage_state base
;
1233 struct brw_vs_prog_data
*prog_data
;
1237 struct brw_stage_state base
;
1238 struct brw_gs_prog_data
*prog_data
;
1241 * True if the 3DSTATE_GS command most recently emitted to the 3D
1242 * pipeline enabled the GS; false otherwise.
1248 struct brw_ff_gs_prog_data
*prog_data
;
1251 /** Offset in the program cache to the CLIP program pre-gen6 */
1252 uint32_t prog_offset
;
1253 uint32_t state_offset
;
1255 uint32_t bind_bo_offset
;
1257 * Surface offsets for the binding table. We only need surfaces to
1258 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1259 * need in this case.
1261 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1265 struct brw_clip_prog_data
*prog_data
;
1267 /** Offset in the program cache to the CLIP program pre-gen6 */
1268 uint32_t prog_offset
;
1270 /* Offset in the batch to the CLIP state on pre-gen6. */
1271 uint32_t state_offset
;
1273 /* As of gen6, this is the offset in the batch to the CLIP VP,
1281 struct brw_sf_prog_data
*prog_data
;
1283 /** Offset in the program cache to the CLIP program pre-gen6 */
1284 uint32_t prog_offset
;
1285 uint32_t state_offset
;
1287 bool viewport_transform_enable
;
1291 struct brw_stage_state base
;
1292 struct brw_wm_prog_data
*prog_data
;
1297 * Buffer object used in place of multisampled null render targets on
1298 * Gen6. See brw_update_null_renderbuffer_surface().
1300 drm_intel_bo
*multisampled_null_render_target_bo
;
1301 uint32_t fast_clear_op
;
1306 uint32_t state_offset
;
1307 uint32_t blend_state_offset
;
1308 uint32_t depth_stencil_state_offset
;
1313 struct brw_query_object
*obj
;
1318 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1319 const int *statistics_registers
;
1321 /** The number of active monitors using OA counters. */
1325 * A buffer object storing OA counter snapshots taken at the start and
1326 * end of each batch (creating "bookends" around the batch).
1328 drm_intel_bo
*bookend_bo
;
1330 /** The number of snapshots written to bookend_bo. */
1331 int bookend_snapshots
;
1334 * An array of monitors whose results haven't yet been assembled based on
1335 * the data in buffer objects.
1337 * These may be active, or have already ended. However, the results
1338 * have not been requested.
1340 struct brw_perf_monitor_object
**unresolved
;
1341 int unresolved_elements
;
1342 int unresolved_array_size
;
1345 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1346 * the counter which MI_REPORT_PERF_COUNT stores there.
1348 const int *oa_snapshot_layout
;
1350 /** Number of 32-bit entries in a hardware counter snapshot. */
1351 int entries_per_oa_snapshot
;
1355 const struct brw_tracked_state
**atoms
;
1357 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1361 enum aub_state_struct_type type
;
1362 } *state_batch_list
;
1363 int state_batch_count
;
1365 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1366 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1368 /* Interpolation modes, one byte per vue slot.
1369 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1371 struct interpolation_mode_map interpolation_mode
;
1373 /* PrimitiveRestart */
1376 bool enable_cut_index
;
1379 /** Computed depth/stencil/hiz state from the current attached
1380 * renderbuffers, valid only during the drawing state upload loop after
1381 * brw_workaround_depthstencil_alignment().
1384 struct intel_mipmap_tree
*depth_mt
;
1385 struct intel_mipmap_tree
*stencil_mt
;
1387 /* Inter-tile (page-aligned) byte offsets. */
1388 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1389 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1390 uint32_t tile_x
, tile_y
;
1393 uint32_t num_instances
;
1398 struct gl_shader_program
**shader_programs
;
1399 struct gl_program
**programs
;
1400 enum shader_time_shader_type
*types
;
1401 uint64_t *cumulative
;
1407 struct brw_fast_clear_state
*fast_clear_state
;
1409 __DRIcontext
*driContext
;
1410 struct intel_screen
*intelScreen
;
1413 /*======================================================================
1416 void brwInitVtbl( struct brw_context
*brw
);
1419 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1421 /*======================================================================
1424 extern const char *const brw_vendor_string
;
1426 extern const char *brw_get_renderer_string(unsigned deviceID
);
1429 DRI_CONF_BO_REUSE_DISABLED
,
1430 DRI_CONF_BO_REUSE_ALL
1433 void intel_update_renderbuffers(__DRIcontext
*context
,
1434 __DRIdrawable
*drawable
);
1435 void intel_prepare_render(struct brw_context
*brw
);
1437 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1438 __DRIdrawable
*drawable
);
1440 GLboolean
brwCreateContext(gl_api api
,
1441 const struct gl_config
*mesaVis
,
1442 __DRIcontext
*driContextPriv
,
1443 unsigned major_version
,
1444 unsigned minor_version
,
1448 void *sharedContextPrivate
);
1450 /*======================================================================
1453 GLuint
brw_get_rb_for_slice(struct brw_context
*brw
,
1454 struct intel_mipmap_tree
*mt
,
1455 unsigned level
, unsigned layer
, bool flat
);
1457 void brw_meta_updownsample(struct brw_context
*brw
,
1458 struct intel_mipmap_tree
*src
,
1459 struct intel_mipmap_tree
*dst
);
1461 void brw_meta_fbo_stencil_blit(struct brw_context
*brw
,
1462 GLfloat srcX0
, GLfloat srcY0
,
1463 GLfloat srcX1
, GLfloat srcY1
,
1464 GLfloat dstX0
, GLfloat dstY0
,
1465 GLfloat dstX1
, GLfloat dstY1
);
1467 void brw_meta_stencil_updownsample(struct brw_context
*brw
,
1468 struct intel_mipmap_tree
*src
,
1469 struct intel_mipmap_tree
*dst
);
1471 bool brw_meta_fast_clear(struct brw_context
*brw
,
1472 struct gl_framebuffer
*fb
,
1474 bool partial_clear
);
1477 brw_meta_resolve_color(struct brw_context
*brw
,
1478 struct intel_mipmap_tree
*mt
);
1480 brw_meta_fast_clear_free(struct brw_context
*brw
);
1483 /*======================================================================
1486 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1487 uint32_t depth_level
,
1488 uint32_t depth_layer
,
1489 struct intel_mipmap_tree
*stencil_mt
,
1490 uint32_t *out_tile_mask_x
,
1491 uint32_t *out_tile_mask_y
);
1492 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1493 GLbitfield clear_mask
);
1495 /* brw_object_purgeable.c */
1496 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1498 /*======================================================================
1501 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1502 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1503 void brw_emit_query_begin(struct brw_context
*brw
);
1504 void brw_emit_query_end(struct brw_context
*brw
);
1506 /** gen6_queryobj.c */
1507 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1508 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1509 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1510 void brw_store_register_mem64(struct brw_context
*brw
,
1511 drm_intel_bo
*bo
, uint32_t reg
, int idx
);
1513 /** intel_batchbuffer.c */
1514 void brw_load_register_mem(struct brw_context
*brw
,
1517 uint32_t read_domains
, uint32_t write_domain
,
1520 /*======================================================================
1523 void brw_debug_batch(struct brw_context
*brw
);
1524 void brw_annotate_aub(struct brw_context
*brw
);
1526 /*======================================================================
1529 void brw_validate_textures( struct brw_context
*brw
);
1532 /*======================================================================
1535 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1537 int brw_get_scratch_size(int size
);
1538 void brw_get_scratch_bo(struct brw_context
*brw
,
1539 drm_intel_bo
**scratch_bo
, int size
);
1540 void brw_init_shader_time(struct brw_context
*brw
);
1541 int brw_get_shader_time_index(struct brw_context
*brw
,
1542 struct gl_shader_program
*shader_prog
,
1543 struct gl_program
*prog
,
1544 enum shader_time_shader_type type
);
1545 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1546 void brw_destroy_shader_time(struct brw_context
*brw
);
1550 void brw_upload_urb_fence(struct brw_context
*brw
);
1554 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1556 /* brw_fs_reg_allocate.cpp
1558 void brw_fs_alloc_reg_sets(struct intel_screen
*screen
);
1560 /* brw_vec4_reg_allocate.cpp */
1561 void brw_vec4_alloc_reg_set(struct intel_screen
*screen
);
1564 int brw_disassemble_inst(FILE *file
, struct brw_context
*brw
,
1565 struct brw_inst
*inst
, bool is_compacted
);
1568 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1570 /* brw_draw_upload.c */
1571 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1572 const struct gl_client_array
*glarray
);
1573 unsigned brw_get_index_type(GLenum type
);
1574 void brw_prepare_vertices(struct brw_context
*brw
);
1576 /* brw_wm_surface_state.c */
1577 void brw_init_surface_formats(struct brw_context
*brw
);
1578 void brw_create_constant_surface(struct brw_context
*brw
,
1582 uint32_t *out_offset
,
1584 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1586 uint32_t *surf_offset
);
1588 brw_update_sol_surface(struct brw_context
*brw
,
1589 struct gl_buffer_object
*buffer_obj
,
1590 uint32_t *out_offset
, unsigned num_vector_components
,
1591 unsigned stride_dwords
, unsigned offset_dwords
);
1592 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1593 struct gl_shader
*shader
,
1594 struct brw_stage_state
*stage_state
,
1595 struct brw_stage_prog_data
*prog_data
);
1596 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1597 struct gl_shader_program
*prog
,
1598 struct brw_stage_state
*stage_state
,
1599 struct brw_stage_prog_data
*prog_data
);
1601 /* brw_surface_formats.c */
1602 bool brw_is_hiz_depth_format(struct brw_context
*ctx
, mesa_format format
);
1603 bool brw_render_target_supported(struct brw_context
*brw
,
1604 struct gl_renderbuffer
*rb
);
1605 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1607 /* brw_performance_monitor.c */
1608 void brw_init_performance_monitors(struct brw_context
*brw
);
1609 void brw_dump_perf_monitors(struct brw_context
*brw
);
1610 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1611 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1613 /* intel_buffer_objects.c */
1614 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1615 const char *bo_name
);
1616 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1617 const char *bo_name
);
1619 /* intel_extensions.c */
1620 extern void intelInitExtensions(struct gl_context
*ctx
);
1623 extern int intel_translate_shadow_compare_func(GLenum func
);
1624 extern int intel_translate_compare_func(GLenum func
);
1625 extern int intel_translate_stencil_op(GLenum op
);
1626 extern int intel_translate_logic_op(GLenum opcode
);
1628 /* intel_syncobj.c */
1629 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1632 struct gl_transform_feedback_object
*
1633 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1635 brw_delete_transform_feedback(struct gl_context
*ctx
,
1636 struct gl_transform_feedback_object
*obj
);
1638 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1639 struct gl_transform_feedback_object
*obj
);
1641 brw_end_transform_feedback(struct gl_context
*ctx
,
1642 struct gl_transform_feedback_object
*obj
);
1644 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1645 struct gl_transform_feedback_object
*obj
,
1648 /* gen7_sol_state.c */
1650 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1651 struct gl_transform_feedback_object
*obj
);
1653 gen7_end_transform_feedback(struct gl_context
*ctx
,
1654 struct gl_transform_feedback_object
*obj
);
1656 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1657 struct gl_transform_feedback_object
*obj
);
1659 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1660 struct gl_transform_feedback_object
*obj
);
1662 /* brw_blorp_blit.cpp */
1664 brw_blorp_framebuffer(struct brw_context
*brw
,
1665 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1666 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1667 GLbitfield mask
, GLenum filter
);
1670 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1671 struct gl_renderbuffer
*src_rb
,
1672 struct gl_texture_image
*dst_image
,
1674 int srcX0
, int srcY0
,
1675 int dstX0
, int dstY0
,
1676 int width
, int height
);
1678 /* gen6_multisample_state.c */
1680 gen6_determine_sample_mask(struct brw_context
*brw
);
1683 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1684 unsigned num_samples
);
1686 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1688 gen6_get_sample_position(struct gl_context
*ctx
,
1689 struct gl_framebuffer
*fb
,
1693 gen6_set_sample_maps(struct gl_context
*ctx
);
1695 /* gen8_multisample_state.c */
1696 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1697 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1701 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1702 unsigned gs_size
, unsigned fs_size
);
1705 gen7_emit_urb_state(struct brw_context
*brw
,
1706 unsigned nr_vs_entries
, unsigned vs_size
,
1707 unsigned vs_start
, unsigned nr_gs_entries
,
1708 unsigned gs_size
, unsigned gs_start
);
1713 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1715 /*======================================================================
1716 * Inline conversion functions. These are better-typed than the
1717 * macros used previously:
1719 static inline struct brw_context
*
1720 brw_context( struct gl_context
*ctx
)
1722 return (struct brw_context
*)ctx
;
1725 static inline struct brw_vertex_program
*
1726 brw_vertex_program(struct gl_vertex_program
*p
)
1728 return (struct brw_vertex_program
*) p
;
1731 static inline const struct brw_vertex_program
*
1732 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1734 return (const struct brw_vertex_program
*) p
;
1737 static inline struct brw_geometry_program
*
1738 brw_geometry_program(struct gl_geometry_program
*p
)
1740 return (struct brw_geometry_program
*) p
;
1743 static inline struct brw_fragment_program
*
1744 brw_fragment_program(struct gl_fragment_program
*p
)
1746 return (struct brw_fragment_program
*) p
;
1749 static inline const struct brw_fragment_program
*
1750 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1752 return (const struct brw_fragment_program
*) p
;
1756 * Pre-gen6, the register file of the EUs was shared between threads,
1757 * and each thread used some subset allocated on a 16-register block
1758 * granularity. The unit states wanted these block counts.
1761 brw_register_blocks(int reg_count
)
1763 return ALIGN(reg_count
, 16) / 16 - 1;
1766 static inline uint32_t
1767 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1768 uint32_t prog_offset
)
1770 if (brw
->gen
>= 5) {
1771 /* Using state base address. */
1775 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1779 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1781 return brw
->cache
.bo
->offset64
+ prog_offset
;
1784 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1785 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1786 struct exec_list
*instructions
);
1787 bool brw_do_lower_unnormalized_offset(struct exec_list
*instructions
);
1789 struct opcode_desc
{
1795 extern const struct opcode_desc opcode_descs
[128];
1796 extern const char * const conditional_modifier
[16];
1799 brw_emit_depthbuffer(struct brw_context
*brw
);
1802 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1803 struct intel_mipmap_tree
*depth_mt
,
1804 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1805 uint32_t depth_surface_type
,
1806 struct intel_mipmap_tree
*stencil_mt
,
1807 bool hiz
, bool separate_stencil
,
1808 uint32_t width
, uint32_t height
,
1809 uint32_t tile_x
, uint32_t tile_y
);
1812 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1813 struct intel_mipmap_tree
*depth_mt
,
1814 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1815 uint32_t depth_surface_type
,
1816 struct intel_mipmap_tree
*stencil_mt
,
1817 bool hiz
, bool separate_stencil
,
1818 uint32_t width
, uint32_t height
,
1819 uint32_t tile_x
, uint32_t tile_y
);
1822 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1823 struct intel_mipmap_tree
*depth_mt
,
1824 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1825 uint32_t depth_surface_type
,
1826 struct intel_mipmap_tree
*stencil_mt
,
1827 bool hiz
, bool separate_stencil
,
1828 uint32_t width
, uint32_t height
,
1829 uint32_t tile_x
, uint32_t tile_y
);
1831 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1832 struct intel_mipmap_tree
*depth_mt
,
1833 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1834 uint32_t depth_surface_type
,
1835 struct intel_mipmap_tree
*stencil_mt
,
1836 bool hiz
, bool separate_stencil
,
1837 uint32_t width
, uint32_t height
,
1838 uint32_t tile_x
, uint32_t tile_y
);
1840 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1841 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);
1843 uint32_t get_hw_prim_for_gl_prim(int mode
);
1846 brw_setup_vec4_key_clip_info(struct brw_context
*brw
,
1847 struct brw_vec4_prog_key
*key
,
1848 bool program_uses_clip_distance
);
1851 gen6_upload_push_constants(struct brw_context
*brw
,
1852 const struct gl_program
*prog
,
1853 const struct brw_stage_prog_data
*prog_data
,
1854 struct brw_stage_state
*stage_state
,
1855 enum aub_state_struct_type type
);
1857 /* ================================================================
1858 * From linux kernel i386 header files, copes with odd sizes better
1859 * than COPY_DWORDS would:
1860 * XXX Put this in src/mesa/main/imports.h ???
1862 #if defined(i386) || defined(__i386__)
1863 static inline void * __memcpy(void * to
, const void * from
, size_t n
)
1866 __asm__
__volatile__(
1871 "1:\ttestb $1,%b4\n\t"
1875 : "=&c" (d0
), "=&D" (d1
), "=&S" (d2
)
1876 :"0" (n
/4), "q" (n
),"1" ((long) to
),"2" ((long) from
)
1881 #define __memcpy(a,b,c) memcpy(a,b,c)