2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
38 #include "main/imports.h"
39 #include "main/macros.h"
41 #include "main/mtypes.h"
42 #include "brw_structs.h"
43 #include "intel_aub.h"
44 #include "program/prog_parameter.h"
48 /* Evil hack for using libdrm in a c++ compiler. */
53 #include <intel_bufmgr.h>
63 #include "intel_debug.h"
64 #include "intel_screen.h"
65 #include "intel_tex_obj.h"
66 #include "intel_resolve_map.h"
70 * URB - uniform resource buffer. A mid-sized buffer which is
71 * partitioned between the fixed function units and used for passing
72 * values (vertices, primitives, constants) between them.
74 * CURBE - constant URB entry. An urb region (entry) used to hold
75 * constant values which the fixed function units can be instructed to
76 * preload into the GRF when spawning a thread.
78 * VUE - vertex URB entry. An urb entry holding a vertex and usually
79 * a vertex header. The header contains control information and
80 * things like primitive type, Begin/end flags and clip codes.
82 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
83 * unit holding rasterization and interpolation parameters.
85 * GRF - general register file. One of several register files
86 * addressable by programmed threads. The inputs (r0, payload, curbe,
87 * urb) of the thread are preloaded to this area before the thread is
88 * spawned. The registers are individually 8 dwords wide and suitable
89 * for general usage. Registers holding thread input values are not
90 * special and may be overwritten.
92 * MRF - message register file. Threads communicate (and terminate)
93 * by sending messages. Message parameters are placed in contiguous
94 * MRF registers. All program output is via these messages. URB
95 * entries are populated by sending a message to the shared URB
96 * function containing the new data, together with a control word,
97 * often an unmodified copy of R0.
99 * R0 - GRF register 0. Typically holds control information used when
100 * sending messages to other threads.
102 * EU or GEN4 EU: The name of the programmable subsystem of the
103 * i965 hardware. Threads are executed by the EU, the registers
104 * described above are part of the EU architecture.
106 * Fixed function units:
108 * CS - Command streamer. Notional first unit, little software
109 * interaction. Holds the URB entries used for constant data, ie the
112 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
113 * this unit is responsible for pulling vertices out of vertex buffers
114 * in vram and injecting them into the processing pipe as VUEs. If
115 * enabled, it first passes them to a VS thread which is a good place
116 * for the driver to implement any active vertex shader.
118 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
119 * enabled, incoming strips etc are passed to GS threads in individual
120 * line/triangle/point units. The GS thread may perform arbitary
121 * computation and emit whatever primtives with whatever vertices it
122 * chooses. This makes GS an excellent place to implement GL's
123 * unfilled polygon modes, though of course it is capable of much
124 * more. Additionally, GS is used to translate away primitives not
125 * handled by latter units, including Quads and Lineloops.
127 * CS - Clipper. Mesa's clipping algorithms are imported to run on
128 * this unit. The fixed function part performs cliptesting against
129 * the 6 fixed clipplanes and makes descisions on whether or not the
130 * incoming primitive needs to be passed to a thread for clipping.
131 * User clip planes are handled via cooperation with the VS thread.
133 * SF - Strips Fans or Setup: Triangles are prepared for
134 * rasterization. Interpolation coefficients are calculated.
135 * Flatshading and two-side lighting usually performed here.
137 * WM - Windower. Interpolation of vertex attributes performed here.
138 * Fragment shader implemented here. SIMD aspects of EU taken full
139 * advantage of, as pixels are processed in blocks of 16.
141 * CC - Color Calculator. No EU threads associated with this unit.
142 * Handles blending and (presumably) depth and stencil testing.
147 struct brw_vs_prog_key
;
148 struct brw_vec4_prog_key
;
149 struct brw_wm_prog_key
;
150 struct brw_wm_prog_data
;
154 BRW_STATE_FRAGMENT_PROGRAM
,
155 BRW_STATE_GEOMETRY_PROGRAM
,
156 BRW_STATE_VERTEX_PROGRAM
,
157 BRW_STATE_CURBE_OFFSETS
,
158 BRW_STATE_REDUCED_PRIMITIVE
,
163 BRW_STATE_VS_BINDING_TABLE
,
164 BRW_STATE_GS_BINDING_TABLE
,
165 BRW_STATE_PS_BINDING_TABLE
,
169 BRW_STATE_INDEX_BUFFER
,
170 BRW_STATE_VS_CONSTBUF
,
171 BRW_STATE_GS_CONSTBUF
,
172 BRW_STATE_PROGRAM_CACHE
,
173 BRW_STATE_STATE_BASE_ADDRESS
,
174 BRW_STATE_VUE_MAP_VS
,
175 BRW_STATE_VUE_MAP_GEOM_OUT
,
176 BRW_STATE_TRANSFORM_FEEDBACK
,
177 BRW_STATE_RASTERIZER_DISCARD
,
179 BRW_STATE_UNIFORM_BUFFER
,
180 BRW_STATE_ATOMIC_BUFFER
,
181 BRW_STATE_META_IN_PROGRESS
,
182 BRW_STATE_INTERPOLATION_MAP
,
183 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
184 BRW_STATE_NUM_SAMPLES
,
188 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
189 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
190 #define BRW_NEW_GEOMETRY_PROGRAM (1 << BRW_STATE_GEOMETRY_PROGRAM)
191 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
192 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
193 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
194 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
195 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
196 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
197 #define BRW_NEW_SURFACES (1 << BRW_STATE_SURFACES)
198 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
199 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
200 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
201 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
202 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
204 * Used for any batch entry with a relocated pointer that will be used
205 * by any 3D rendering.
207 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
208 /** \see brw.state.depth_region */
209 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
210 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
211 #define BRW_NEW_GS_CONSTBUF (1 << BRW_STATE_GS_CONSTBUF)
212 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
213 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
214 #define BRW_NEW_VUE_MAP_VS (1 << BRW_STATE_VUE_MAP_VS)
215 #define BRW_NEW_VUE_MAP_GEOM_OUT (1 << BRW_STATE_VUE_MAP_GEOM_OUT)
216 #define BRW_NEW_TRANSFORM_FEEDBACK (1 << BRW_STATE_TRANSFORM_FEEDBACK)
217 #define BRW_NEW_RASTERIZER_DISCARD (1 << BRW_STATE_RASTERIZER_DISCARD)
218 #define BRW_NEW_STATS_WM (1 << BRW_STATE_STATS_WM)
219 #define BRW_NEW_UNIFORM_BUFFER (1 << BRW_STATE_UNIFORM_BUFFER)
220 #define BRW_NEW_ATOMIC_BUFFER (1 << BRW_STATE_ATOMIC_BUFFER)
221 #define BRW_NEW_META_IN_PROGRESS (1 << BRW_STATE_META_IN_PROGRESS)
222 #define BRW_NEW_INTERPOLATION_MAP (1 << BRW_STATE_INTERPOLATION_MAP)
223 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1 << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
224 #define BRW_NEW_NUM_SAMPLES (1 << BRW_STATE_NUM_SAMPLES)
226 struct brw_state_flags
{
227 /** State update flags signalled by mesa internals */
230 * State update flags signalled as the result of brw_tracked_state updates
234 * State update flags that used to be signalled by brw_state_cache.c
237 * Now almost all of that state is just streamed out on demand, but the
238 * flags for those state blobs updating have stayed in the same bitfield.
239 * brw_state_cache.c still flags CACHE_NEW_*_PROG.
246 * Enum representing the different pipelines.
250 * 3D rendering pipeline (vertex through fragment shader).
255 * Compute shader pipeline.
257 BRW_PIPELINE_COMPUTE
,
264 * Set one of the bits in a field of brw_state_flags.
266 #define SET_DIRTY_BIT(FIELD, FLAG) \
268 for (int pipeline = 0; pipeline < BRW_NUM_PIPELINES; pipeline++) \
269 brw->state.pipeline_dirty[pipeline].FIELD |= (FLAG); \
274 * Set all of the bits in a field of brw_state_flags.
276 #define SET_DIRTY_ALL(FIELD) \
278 /* ~0 == 0xffffffff, so make sure field is <= 32 bits */ \
279 STATIC_ASSERT(sizeof(brw->state.pipeline_dirty[0].FIELD) == 4); \
280 for (int pipeline = 0; pipeline < BRW_NUM_PIPELINES; pipeline++) \
281 brw->state.pipeline_dirty[pipeline].FIELD = ~0; \
286 * Set all of the bits in a field of brw_state_flags.
288 #define SET_DIRTY64_ALL(FIELD) \
290 /* ~0ULL == 0xffffffffffffffff, so make sure field is <= 64 bits */ \
291 STATIC_ASSERT(sizeof(brw->state.pipeline_dirty[0].FIELD) == 8); \
292 for (int pipeline = 0; pipeline < BRW_NUM_PIPELINES; pipeline++) \
293 brw->state.pipeline_dirty[pipeline].FIELD = ~(0ULL); \
298 * Check one of the bits in a field of brw_state_flags.
300 #define CHECK_DIRTY_BIT(FIELD, FLAG) \
301 ((brw->state.pipeline_dirty[brw->state.current_pipeline].FIELD & (FLAG)) \
305 /** Subclass of Mesa vertex program */
306 struct brw_vertex_program
{
307 struct gl_vertex_program program
;
312 /** Subclass of Mesa geometry program */
313 struct brw_geometry_program
{
314 struct gl_geometry_program program
;
315 unsigned id
; /**< serial no. to identify geom progs, never re-used */
319 /** Subclass of Mesa fragment program */
320 struct brw_fragment_program
{
321 struct gl_fragment_program program
;
322 GLuint id
; /**< serial no. to identify frag progs, never re-used */
326 /** Subclass of Mesa compute program */
327 struct brw_compute_program
{
328 struct gl_compute_program program
;
329 unsigned id
; /**< serial no. to identify compute progs, never re-used */
334 struct gl_shader base
;
339 /* Note: If adding fields that need anything besides a normal memcmp() for
340 * comparing them, be sure to go fix brw_stage_prog_data_compare().
342 struct brw_stage_prog_data
{
344 /** size of our binding table. */
348 * surface indices for the various groups of surfaces
350 uint32_t pull_constants_start
;
351 uint32_t texture_start
;
352 uint32_t gather_texture_start
;
355 uint32_t shader_time_start
;
359 GLuint nr_params
; /**< number of float params/constants */
360 GLuint nr_pull_params
;
362 unsigned curb_read_length
;
363 unsigned total_scratch
;
366 * Register where the thread expects to find input data from the URB
367 * (typically uniforms, followed by vertex or fragment attributes).
369 unsigned dispatch_grf_start_reg
;
371 /* Pointers to tracked values (only valid once
372 * _mesa_load_state_parameters has been called at runtime).
374 * These must be the last fields of the struct (see
375 * brw_stage_prog_data_compare()).
377 const gl_constant_value
**param
;
378 const gl_constant_value
**pull_param
;
381 /* Data about a particular attempt to compile a program. Note that
382 * there can be many of these, each in a different GL state
383 * corresponding to a different brw_wm_prog_key struct, with different
386 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
389 struct brw_wm_prog_data
{
390 struct brw_stage_prog_data base
;
392 GLuint num_varying_inputs
;
394 GLuint dispatch_grf_start_reg_16
;
396 GLuint reg_blocks_16
;
400 * surface indices the WM-specific surfaces
402 uint32_t render_target_start
;
408 bool uses_pos_offset
;
410 uint32_t prog_offset_16
;
413 * Mask of which interpolation modes are required by the fragment shader.
414 * Used in hardware setup on gen6+.
416 uint32_t barycentric_interp_modes
;
419 * Map from gl_varying_slot to the position within the FS setup data
420 * payload where the varying's attribute vertex deltas should be delivered.
421 * For varying slots that are not used by the FS, the value is -1.
423 int urb_setup
[VARYING_SLOT_MAX
];
427 * Enum representing the i965-specific vertex results that don't correspond
428 * exactly to any element of gl_varying_slot. The values of this enum are
429 * assigned such that they don't conflict with gl_varying_slot.
433 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
434 BRW_VARYING_SLOT_PAD
,
436 * Technically this is not a varying but just a placeholder that
437 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
438 * builtin variable to be compiled correctly. see compile_sf_prog() for
441 BRW_VARYING_SLOT_PNTC
,
442 BRW_VARYING_SLOT_COUNT
447 * Data structure recording the relationship between the gl_varying_slot enum
448 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
449 * single octaword within the VUE (128 bits).
451 * Note that each BRW register contains 256 bits (2 octawords), so when
452 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
453 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
454 * in a vertex shader), each register corresponds to a single VUE slot, since
455 * it contains data for two separate vertices.
459 * Bitfield representing all varying slots that are (a) stored in this VUE
460 * map, and (b) actually written by the shader. Does not include any of
461 * the additional varying slots defined in brw_varying_slot.
463 GLbitfield64 slots_valid
;
466 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
467 * not stored in a slot (because they are not written, or because
468 * additional processing is applied before storing them in the VUE), the
471 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
474 * Map from VUE slot to gl_varying_slot value. For slots that do not
475 * directly correspond to a gl_varying_slot, the value comes from
478 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
479 * simplifies code that uses the value stored in slot_to_varying to
480 * create a bit mask).
482 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
485 * Total number of VUE slots in use
491 * Convert a VUE slot number into a byte offset within the VUE.
493 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
499 * Convert a vertex output (brw_varying_slot) into a byte offset within the
502 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
505 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
508 void brw_compute_vue_map(struct brw_context
*brw
, struct brw_vue_map
*vue_map
,
509 GLbitfield64 slots_valid
);
513 * Bitmask indicating which fragment shader inputs represent varyings (and
514 * hence have to be delivered to the fragment shader by the SF/SBE stage).
516 #define BRW_FS_VARYING_INPUT_MASK \
517 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
518 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
522 * Mapping of VUE map slots to interpolation modes.
524 struct interpolation_mode_map
{
525 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
528 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
530 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
531 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
537 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
539 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
540 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
547 struct brw_sf_prog_data
{
548 GLuint urb_read_length
;
551 /* Each vertex may have upto 12 attributes, 4 components each,
552 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
555 * Actually we use 4 for each, so call it 12 rows.
557 GLuint urb_entry_size
;
562 * We always program SF to start reading at an offset of 1 (2 varying slots)
563 * from the start of the vertex URB entry. This causes it to skip:
564 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
565 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
567 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
570 struct brw_clip_prog_data
{
571 GLuint curb_read_length
; /* user planes? */
573 GLuint urb_read_length
;
577 struct brw_ff_gs_prog_data
{
578 GLuint urb_read_length
;
582 * Gen6 transform feedback: Amount by which the streaming vertex buffer
583 * indices should be incremented each time the GS is invoked.
585 unsigned svbi_postincrement_value
;
589 /* Note: brw_vec4_prog_data_compare() must be updated when adding fields to
592 struct brw_vec4_prog_data
{
593 struct brw_stage_prog_data base
;
594 struct brw_vue_map vue_map
;
596 GLuint urb_read_length
;
599 /* Used for calculating urb partitions. In the VS, this is the size of the
600 * URB entry used for both input and output to the thread. In the GS, this
601 * is the size of the URB entry used for output.
603 GLuint urb_entry_size
;
607 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
610 struct brw_vs_prog_data
{
611 struct brw_vec4_prog_data base
;
613 GLbitfield64 inputs_read
;
619 /* Note: brw_gs_prog_data_compare() must be updated when adding fields to
622 struct brw_gs_prog_data
624 struct brw_vec4_prog_data base
;
627 * Size of an output vertex, measured in HWORDS (32 bytes).
629 unsigned output_vertex_size_hwords
;
631 unsigned output_topology
;
634 * Size of the control data (cut bits or StreamID bits), in hwords (32
635 * bytes). 0 if there is no control data.
637 unsigned control_data_header_size_hwords
;
640 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
641 * if the control data is StreamID bits, or
642 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
643 * Ignored if control_data_header_size is 0.
645 unsigned control_data_format
;
647 bool include_primitive_id
;
652 * True if the thread should be dispatched in DUAL_INSTANCE mode, false if
653 * it should be dispatched in DUAL_OBJECT mode.
655 bool dual_instanced_dispatch
;
658 /** Number of texture sampler units */
659 #define BRW_MAX_TEX_UNIT 32
661 /** Max number of render targets in a shader */
662 #define BRW_MAX_DRAW_BUFFERS 8
664 /** Max number of atomic counter buffer objects in a shader */
665 #define BRW_MAX_ABO 16
668 * Max number of binding table entries used for stream output.
670 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
671 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
673 * On Gen6, the size of transform feedback data is limited not by the number
674 * of components but by the number of binding table entries we set aside. We
675 * use one binding table entry for a float, one entry for a vector, and one
676 * entry per matrix column. Since the only way we can communicate our
677 * transform feedback capabilities to the client is via
678 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
679 * worst case, in which all the varyings are floats, so we use up one binding
680 * table entry per component. Therefore we need to set aside at least 64
681 * binding table entries for use by transform feedback.
683 * Note: since we don't currently pack varyings, it is currently impossible
684 * for the client to actually use up all of these binding table entries--if
685 * all of their varyings were floats, they would run out of varying slots and
686 * fail to link. But that's a bug, so it seems prudent to go ahead and
687 * allocate the number of binding table entries we will need once the bug is
690 #define BRW_MAX_SOL_BINDINGS 64
692 /** Maximum number of actual buffers used for stream output */
693 #define BRW_MAX_SOL_BUFFERS 4
695 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
696 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
699 2 /* shader time, pull constants */)
701 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
702 #define BRW_MAX_GEN6_GS_SURFACES SURF_INDEX_GEN6_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
705 * Stride in bytes between shader_time entries.
707 * We separate entries by a cacheline to reduce traffic between EUs writing to
710 #define SHADER_TIME_STRIDE 64
717 BRW_BLORP_CONST_COLOR_PROG
,
722 BRW_SF_UNIT
, /* scissor state on gen6 */
735 struct brw_cache_item
{
737 * Effectively part of the key, cache_id identifies what kind of state
738 * buffer is involved, and also which brw->state.dirty.cache flag should
739 * be set when this cache item is chosen.
741 enum brw_cache_id cache_id
;
742 /** 32-bit hash of the key data */
744 GLuint key_size
; /* for variable-sized keys */
751 struct brw_cache_item
*next
;
755 typedef bool (*cache_aux_compare_func
)(const void *a
, const void *b
);
756 typedef void (*cache_aux_free_func
)(const void *aux
);
759 struct brw_context
*brw
;
761 struct brw_cache_item
**items
;
763 GLuint size
, n_items
;
765 uint32_t next_offset
;
769 * Optional functions used in determining whether the prog_data for a new
770 * cache item matches an existing cache item (in case there's relevant data
771 * outside of the prog_data). If NULL, a plain memcmp is done.
773 cache_aux_compare_func aux_compare
[BRW_MAX_CACHE
];
774 /** Optional functions for freeing other pointers attached to a prog_data. */
775 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
779 /* Considered adding a member to this struct to document which flags
780 * an update might raise so that ordering of the state atoms can be
781 * checked or derived at runtime. Dropped the idea in favor of having
782 * a debug mode where the state is monitored for flags which are
783 * raised that have already been tested against.
785 struct brw_tracked_state
{
786 struct brw_state_flags dirty
;
787 void (*emit
)( struct brw_context
*brw
);
790 enum shader_time_shader_type
{
806 /* Flags for brw->state.cache.
808 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
809 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
810 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
811 #define CACHE_NEW_BLORP_BLIT_PROG (1<<BRW_BLORP_BLIT_PROG)
812 #define CACHE_NEW_BLORP_CONST_COLOR_PROG (1<<BRW_BLORP_CONST_COLOR_PROG)
813 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
814 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
815 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
816 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
817 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
818 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
819 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
820 #define CACHE_NEW_FF_GS_UNIT (1<<BRW_FF_GS_UNIT)
821 #define CACHE_NEW_FF_GS_PROG (1<<BRW_FF_GS_PROG)
822 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
823 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
824 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
825 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
827 struct brw_vertex_buffer
{
828 /** Buffer object containing the uploaded vertex data */
831 /** Byte stride between elements in the uploaded array */
835 struct brw_vertex_element
{
836 const struct gl_client_array
*glarray
;
840 /** Offset of the first element within the buffer object */
844 struct brw_query_object
{
845 struct gl_query_object Base
;
847 /** Last query BO associated with this query. */
850 /** Last index in bo with query data for this object. */
854 struct intel_sync_object
{
855 struct gl_sync_object Base
;
857 /** Batch associated with this sync object */
867 struct intel_batchbuffer
{
868 /** Current batchbuffer being queued up. */
870 /** Last BO submitted to the hardware. Used for glFinish(). */
871 drm_intel_bo
*last_bo
;
872 /** BO for post-sync nonzero writes for gen6 workaround. */
873 drm_intel_bo
*workaround_bo
;
874 bool need_workaround_flush
;
876 uint16_t emit
, total
;
877 uint16_t used
, reserved_space
;
880 #define BATCH_SZ (8192*sizeof(uint32_t))
882 uint32_t state_batch_offset
;
883 enum brw_gpu_ring ring
;
884 bool needs_sol_reset
;
892 #define BRW_MAX_XFB_STREAMS 4
894 struct brw_transform_feedback_object
{
895 struct gl_transform_feedback_object base
;
897 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
898 drm_intel_bo
*offset_bo
;
900 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
903 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
904 GLenum primitive_mode
;
907 * Count of primitives generated during this transform feedback operation.
910 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
911 drm_intel_bo
*prim_count_bo
;
912 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
916 * Number of vertices written between last Begin/EndTransformFeedback().
918 * Used to implement DrawTransformFeedback().
920 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
921 bool vertices_written_valid
;
925 * Data shared between each programmable stage in the pipeline (vs, gs, and
928 struct brw_stage_state
930 gl_shader_stage stage
;
931 struct brw_stage_prog_data
*prog_data
;
934 * Optional scratch buffer used to store spilled register values and
935 * variably-indexed GRF arrays.
937 drm_intel_bo
*scratch_bo
;
939 /** Offset in the program cache to the program */
940 uint32_t prog_offset
;
942 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
943 uint32_t state_offset
;
945 uint32_t push_const_offset
; /* Offset in the batchbuffer */
946 int push_const_size
; /* in 256-bit register increments */
948 /* Binding table: pointers to SURFACE_STATE entries. */
949 uint32_t bind_bo_offset
;
950 uint32_t surf_offset
[BRW_MAX_SURFACES
];
952 /** SAMPLER_STATE count and table offset */
953 uint32_t sampler_count
;
954 uint32_t sampler_offset
;
959 * brw_context is derived from gl_context.
963 struct gl_context ctx
; /**< base class, must be first field */
967 void (*update_texture_surface
)(struct gl_context
*ctx
,
969 uint32_t *surf_offset
,
971 void (*update_renderbuffer_surface
)(struct brw_context
*brw
,
972 struct gl_renderbuffer
*rb
,
975 void (*update_null_renderbuffer_surface
)(struct brw_context
*brw
,
978 void (*create_raw_surface
)(struct brw_context
*brw
,
982 uint32_t *out_offset
,
984 void (*emit_buffer_surface_state
)(struct brw_context
*brw
,
985 uint32_t *out_offset
,
987 unsigned buffer_offset
,
988 unsigned surface_format
,
989 unsigned buffer_size
,
995 * Send the appropriate state packets to configure depth, stencil, and
996 * HiZ buffers (i965+ only)
998 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
999 struct intel_mipmap_tree
*depth_mt
,
1000 uint32_t depth_offset
,
1001 uint32_t depthbuffer_format
,
1002 uint32_t depth_surface_type
,
1003 struct intel_mipmap_tree
*stencil_mt
,
1004 bool hiz
, bool separate_stencil
,
1005 uint32_t width
, uint32_t height
,
1006 uint32_t tile_x
, uint32_t tile_y
);
1012 drm_intel_context
*hw_ctx
;
1015 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
1016 * and would need flushing before being used from another cache domain that
1017 * isn't coherent with it (i.e. the sampler).
1019 struct set
*render_cache
;
1022 * Number of resets observed in the system at context creation.
1024 * This is tracked in the context so that we can determine that another
1025 * reset has occured.
1027 uint32_t reset_count
;
1029 struct intel_batchbuffer batch
;
1034 uint32_t next_offset
;
1038 * Set if rendering has occured to the drawable's front buffer.
1040 * This is used in the DRI2 case to detect that glFlush should also copy
1041 * the contents of the fake front buffer to the real front buffer.
1043 bool front_buffer_dirty
;
1045 /** Framerate throttling: @{ */
1046 drm_intel_bo
*first_post_swapbuffers_batch
;
1057 bool always_flush_batch
;
1058 bool always_flush_cache
;
1059 bool disable_throttling
;
1061 bool disable_derivative_optimization
;
1063 driOptionCache optionCache
;
1066 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
1068 GLenum reduced_primitive
;
1071 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
1072 * variable is set, this is the flag indicating to do expensive work that
1073 * might lead to a perf_debug() call.
1077 uint32_t max_gtt_map_object_size
;
1088 bool has_separate_stencil
;
1089 bool must_use_separate_stencil
;
1092 bool has_surface_tile_offset
;
1094 bool has_negative_rhw_bug
;
1100 * Some versions of Gen hardware don't do centroid interpolation correctly
1101 * on unlit pixels, causing incorrect values for derivatives near triangle
1102 * edges. Enabling this flag causes the fragment shader to use
1103 * non-centroid interpolation for unlit pixels, at the expense of two extra
1104 * fragment shader instructions.
1106 bool needs_unlit_centroid_workaround
;
1110 struct brw_state_flags pipeline_dirty
[BRW_NUM_PIPELINES
];
1111 brw_pipeline current_pipeline
;
1114 struct brw_cache cache
;
1116 /** IDs for meta stencil blit shader programs. */
1117 unsigned meta_stencil_blit_programs
[2];
1119 /* Whether a meta-operation is in progress. */
1120 bool meta_in_progress
;
1122 /* Whether the last depth/stencil packets were both NULL. */
1123 bool no_depth_or_stencil
;
1126 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
1127 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
1129 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
1133 /* Summary of size and varying of active arrays, so we can check
1134 * for changes to this state:
1136 unsigned int min_index
, max_index
;
1138 /* Offset from start of vertex buffer so we can avoid redefining
1139 * the same VB packed over and over again.
1141 unsigned int start_vertex_bias
;
1146 * Index buffer for this draw_prims call.
1148 * Updates are signaled by BRW_NEW_INDICES.
1150 const struct _mesa_index_buffer
*ib
;
1152 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
1156 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
1157 * avoid re-uploading the IB packet over and over if we're actually
1158 * referencing the same index buffer.
1160 unsigned int start_vertex_offset
;
1163 /* Active vertex program:
1165 const struct gl_vertex_program
*vertex_program
;
1166 const struct gl_geometry_program
*geometry_program
;
1167 const struct gl_fragment_program
*fragment_program
;
1170 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
1171 * that we don't have to reemit that state every time we change FBOs.
1176 * Platform specific constants containing the maximum number of threads
1177 * for each pipeline stage.
1183 /* BRW_NEW_URB_ALLOCATIONS:
1186 GLuint vsize
; /* vertex size plus header in urb registers */
1187 GLuint csize
; /* constant buffer size in urb registers */
1188 GLuint sfsize
; /* setup data size in urb registers */
1192 GLuint min_vs_entries
; /* Minimum number of VS entries */
1193 GLuint max_vs_entries
; /* Maximum number of VS entries */
1194 GLuint max_gs_entries
; /* Maximum number of GS entries */
1196 GLuint nr_vs_entries
;
1197 GLuint nr_gs_entries
;
1198 GLuint nr_clip_entries
;
1199 GLuint nr_sf_entries
;
1200 GLuint nr_cs_entries
;
1207 GLuint size
; /* Hardware URB size, in KB. */
1209 /* gen6: True if the most recently sent _3DSTATE_URB message allocated
1210 * URB space for the GS.
1212 bool gen6_gs_previously_active
;
1216 /* BRW_NEW_CURBE_OFFSETS:
1219 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1220 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1228 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1229 * for upload to the CURBE.
1231 drm_intel_bo
*curbe_bo
;
1232 /** Offset within curbe_bo of space for current curbe entry */
1233 GLuint curbe_offset
;
1237 * Layout of vertex data exiting the vertex shader.
1239 * BRW_NEW_VUE_MAP_VS is flagged when this VUE map changes.
1241 struct brw_vue_map vue_map_vs
;
1244 * Layout of vertex data exiting the geometry portion of the pipleine.
1245 * This comes from the geometry shader if one exists, otherwise from the
1248 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1250 struct brw_vue_map vue_map_geom_out
;
1253 struct brw_stage_state base
;
1254 struct brw_vs_prog_data
*prog_data
;
1258 struct brw_stage_state base
;
1259 struct brw_gs_prog_data
*prog_data
;
1262 * True if the 3DSTATE_GS command most recently emitted to the 3D
1263 * pipeline enabled the GS; false otherwise.
1269 struct brw_ff_gs_prog_data
*prog_data
;
1272 /** Offset in the program cache to the CLIP program pre-gen6 */
1273 uint32_t prog_offset
;
1274 uint32_t state_offset
;
1276 uint32_t bind_bo_offset
;
1277 uint32_t surf_offset
[BRW_MAX_GEN6_GS_SURFACES
];
1281 struct brw_clip_prog_data
*prog_data
;
1283 /** Offset in the program cache to the CLIP program pre-gen6 */
1284 uint32_t prog_offset
;
1286 /* Offset in the batch to the CLIP state on pre-gen6. */
1287 uint32_t state_offset
;
1289 /* As of gen6, this is the offset in the batch to the CLIP VP,
1297 struct brw_sf_prog_data
*prog_data
;
1299 /** Offset in the program cache to the CLIP program pre-gen6 */
1300 uint32_t prog_offset
;
1301 uint32_t state_offset
;
1303 bool viewport_transform_enable
;
1307 struct brw_stage_state base
;
1308 struct brw_wm_prog_data
*prog_data
;
1313 * Buffer object used in place of multisampled null render targets on
1314 * Gen6. See brw_update_null_renderbuffer_surface().
1316 drm_intel_bo
*multisampled_null_render_target_bo
;
1317 uint32_t fast_clear_op
;
1322 uint32_t state_offset
;
1323 uint32_t blend_state_offset
;
1324 uint32_t depth_stencil_state_offset
;
1329 struct brw_query_object
*obj
;
1334 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1335 const int *statistics_registers
;
1337 /** The number of active monitors using OA counters. */
1341 * A buffer object storing OA counter snapshots taken at the start and
1342 * end of each batch (creating "bookends" around the batch).
1344 drm_intel_bo
*bookend_bo
;
1346 /** The number of snapshots written to bookend_bo. */
1347 int bookend_snapshots
;
1350 * An array of monitors whose results haven't yet been assembled based on
1351 * the data in buffer objects.
1353 * These may be active, or have already ended. However, the results
1354 * have not been requested.
1356 struct brw_perf_monitor_object
**unresolved
;
1357 int unresolved_elements
;
1358 int unresolved_array_size
;
1361 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1362 * the counter which MI_REPORT_PERF_COUNT stores there.
1364 const int *oa_snapshot_layout
;
1366 /** Number of 32-bit entries in a hardware counter snapshot. */
1367 int entries_per_oa_snapshot
;
1370 int num_atoms
[BRW_NUM_PIPELINES
];
1371 const struct brw_tracked_state
**atoms
[BRW_NUM_PIPELINES
];
1373 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1377 enum aub_state_struct_type type
;
1378 } *state_batch_list
;
1379 int state_batch_count
;
1381 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1382 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1384 /* Interpolation modes, one byte per vue slot.
1385 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1387 struct interpolation_mode_map interpolation_mode
;
1389 /* PrimitiveRestart */
1392 bool enable_cut_index
;
1395 /** Computed depth/stencil/hiz state from the current attached
1396 * renderbuffers, valid only during the drawing state upload loop after
1397 * brw_workaround_depthstencil_alignment().
1400 struct intel_mipmap_tree
*depth_mt
;
1401 struct intel_mipmap_tree
*stencil_mt
;
1403 /* Inter-tile (page-aligned) byte offsets. */
1404 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1405 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1406 uint32_t tile_x
, tile_y
;
1409 uint32_t num_instances
;
1414 struct gl_shader_program
**shader_programs
;
1415 struct gl_program
**programs
;
1416 enum shader_time_shader_type
*types
;
1417 uint64_t *cumulative
;
1423 struct brw_fast_clear_state
*fast_clear_state
;
1425 __DRIcontext
*driContext
;
1426 struct intel_screen
*intelScreen
;
1429 /*======================================================================
1432 void brwInitVtbl( struct brw_context
*brw
);
1435 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1437 /*======================================================================
1440 extern const char *const brw_vendor_string
;
1442 extern const char *brw_get_renderer_string(unsigned deviceID
);
1445 DRI_CONF_BO_REUSE_DISABLED
,
1446 DRI_CONF_BO_REUSE_ALL
1449 void intel_update_renderbuffers(__DRIcontext
*context
,
1450 __DRIdrawable
*drawable
);
1451 void intel_prepare_render(struct brw_context
*brw
);
1453 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1454 __DRIdrawable
*drawable
);
1456 GLboolean
brwCreateContext(gl_api api
,
1457 const struct gl_config
*mesaVis
,
1458 __DRIcontext
*driContextPriv
,
1459 unsigned major_version
,
1460 unsigned minor_version
,
1464 void *sharedContextPrivate
);
1466 /*======================================================================
1469 GLuint
brw_get_rb_for_slice(struct brw_context
*brw
,
1470 struct intel_mipmap_tree
*mt
,
1471 unsigned level
, unsigned layer
, bool flat
);
1473 void brw_meta_updownsample(struct brw_context
*brw
,
1474 struct intel_mipmap_tree
*src
,
1475 struct intel_mipmap_tree
*dst
);
1477 void brw_meta_fbo_stencil_blit(struct brw_context
*brw
,
1478 GLfloat srcX0
, GLfloat srcY0
,
1479 GLfloat srcX1
, GLfloat srcY1
,
1480 GLfloat dstX0
, GLfloat dstY0
,
1481 GLfloat dstX1
, GLfloat dstY1
);
1483 void brw_meta_stencil_updownsample(struct brw_context
*brw
,
1484 struct intel_mipmap_tree
*src
,
1485 struct intel_mipmap_tree
*dst
);
1487 bool brw_meta_fast_clear(struct brw_context
*brw
,
1488 struct gl_framebuffer
*fb
,
1490 bool partial_clear
);
1493 brw_meta_resolve_color(struct brw_context
*brw
,
1494 struct intel_mipmap_tree
*mt
);
1496 brw_meta_fast_clear_free(struct brw_context
*brw
);
1499 /*======================================================================
1502 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1503 uint32_t depth_level
,
1504 uint32_t depth_layer
,
1505 struct intel_mipmap_tree
*stencil_mt
,
1506 uint32_t *out_tile_mask_x
,
1507 uint32_t *out_tile_mask_y
);
1508 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1509 GLbitfield clear_mask
);
1511 /* brw_object_purgeable.c */
1512 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1514 /*======================================================================
1517 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1518 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1519 void brw_emit_query_begin(struct brw_context
*brw
);
1520 void brw_emit_query_end(struct brw_context
*brw
);
1522 /** gen6_queryobj.c */
1523 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1524 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1525 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1526 void brw_store_register_mem64(struct brw_context
*brw
,
1527 drm_intel_bo
*bo
, uint32_t reg
, int idx
);
1529 /** intel_batchbuffer.c */
1530 void brw_load_register_mem(struct brw_context
*brw
,
1533 uint32_t read_domains
, uint32_t write_domain
,
1536 /*======================================================================
1539 void brw_debug_batch(struct brw_context
*brw
);
1540 void brw_annotate_aub(struct brw_context
*brw
);
1542 /*======================================================================
1545 void brw_validate_textures( struct brw_context
*brw
);
1548 /*======================================================================
1551 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1553 int brw_get_scratch_size(int size
);
1554 void brw_get_scratch_bo(struct brw_context
*brw
,
1555 drm_intel_bo
**scratch_bo
, int size
);
1556 void brw_init_shader_time(struct brw_context
*brw
);
1557 int brw_get_shader_time_index(struct brw_context
*brw
,
1558 struct gl_shader_program
*shader_prog
,
1559 struct gl_program
*prog
,
1560 enum shader_time_shader_type type
);
1561 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1562 void brw_destroy_shader_time(struct brw_context
*brw
);
1566 void brw_upload_urb_fence(struct brw_context
*brw
);
1570 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1572 /* brw_fs_reg_allocate.cpp
1574 void brw_fs_alloc_reg_sets(struct intel_screen
*screen
);
1576 /* brw_vec4_reg_allocate.cpp */
1577 void brw_vec4_alloc_reg_set(struct intel_screen
*screen
);
1580 int brw_disassemble_inst(FILE *file
, struct brw_context
*brw
,
1581 struct brw_inst
*inst
, bool is_compacted
);
1584 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1586 /* brw_draw_upload.c */
1587 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1588 const struct gl_client_array
*glarray
);
1589 unsigned brw_get_index_type(GLenum type
);
1590 void brw_prepare_vertices(struct brw_context
*brw
);
1592 /* brw_wm_surface_state.c */
1593 void brw_init_surface_formats(struct brw_context
*brw
);
1594 void brw_create_constant_surface(struct brw_context
*brw
,
1598 uint32_t *out_offset
,
1600 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1602 uint32_t *surf_offset
);
1604 brw_update_sol_surface(struct brw_context
*brw
,
1605 struct gl_buffer_object
*buffer_obj
,
1606 uint32_t *out_offset
, unsigned num_vector_components
,
1607 unsigned stride_dwords
, unsigned offset_dwords
);
1608 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1609 struct gl_shader
*shader
,
1610 struct brw_stage_state
*stage_state
,
1611 struct brw_stage_prog_data
*prog_data
);
1612 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1613 struct gl_shader_program
*prog
,
1614 struct brw_stage_state
*stage_state
,
1615 struct brw_stage_prog_data
*prog_data
);
1617 /* brw_surface_formats.c */
1618 bool brw_is_hiz_depth_format(struct brw_context
*ctx
, mesa_format format
);
1619 bool brw_render_target_supported(struct brw_context
*brw
,
1620 struct gl_renderbuffer
*rb
);
1621 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1623 /* brw_performance_monitor.c */
1624 void brw_init_performance_monitors(struct brw_context
*brw
);
1625 void brw_dump_perf_monitors(struct brw_context
*brw
);
1626 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1627 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1629 /* intel_buffer_objects.c */
1630 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1631 const char *bo_name
);
1632 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1633 const char *bo_name
);
1635 /* intel_extensions.c */
1636 extern void intelInitExtensions(struct gl_context
*ctx
);
1639 extern int intel_translate_shadow_compare_func(GLenum func
);
1640 extern int intel_translate_compare_func(GLenum func
);
1641 extern int intel_translate_stencil_op(GLenum op
);
1642 extern int intel_translate_logic_op(GLenum opcode
);
1644 /* intel_syncobj.c */
1645 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1648 struct gl_transform_feedback_object
*
1649 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1651 brw_delete_transform_feedback(struct gl_context
*ctx
,
1652 struct gl_transform_feedback_object
*obj
);
1654 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1655 struct gl_transform_feedback_object
*obj
);
1657 brw_end_transform_feedback(struct gl_context
*ctx
,
1658 struct gl_transform_feedback_object
*obj
);
1660 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1661 struct gl_transform_feedback_object
*obj
,
1664 /* gen7_sol_state.c */
1666 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1667 struct gl_transform_feedback_object
*obj
);
1669 gen7_end_transform_feedback(struct gl_context
*ctx
,
1670 struct gl_transform_feedback_object
*obj
);
1672 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1673 struct gl_transform_feedback_object
*obj
);
1675 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1676 struct gl_transform_feedback_object
*obj
);
1678 /* brw_blorp_blit.cpp */
1680 brw_blorp_framebuffer(struct brw_context
*brw
,
1681 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1682 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1683 GLbitfield mask
, GLenum filter
);
1686 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1687 struct gl_renderbuffer
*src_rb
,
1688 struct gl_texture_image
*dst_image
,
1690 int srcX0
, int srcY0
,
1691 int dstX0
, int dstY0
,
1692 int width
, int height
);
1694 /* gen6_multisample_state.c */
1696 gen6_determine_sample_mask(struct brw_context
*brw
);
1699 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1700 unsigned num_samples
);
1702 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1704 gen6_get_sample_position(struct gl_context
*ctx
,
1705 struct gl_framebuffer
*fb
,
1709 /* gen8_multisample_state.c */
1710 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1711 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1715 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1716 unsigned gs_size
, unsigned fs_size
);
1719 gen7_emit_urb_state(struct brw_context
*brw
,
1720 unsigned nr_vs_entries
, unsigned vs_size
,
1721 unsigned vs_start
, unsigned nr_gs_entries
,
1722 unsigned gs_size
, unsigned gs_start
);
1727 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1729 /*======================================================================
1730 * Inline conversion functions. These are better-typed than the
1731 * macros used previously:
1733 static inline struct brw_context
*
1734 brw_context( struct gl_context
*ctx
)
1736 return (struct brw_context
*)ctx
;
1739 static inline struct brw_vertex_program
*
1740 brw_vertex_program(struct gl_vertex_program
*p
)
1742 return (struct brw_vertex_program
*) p
;
1745 static inline const struct brw_vertex_program
*
1746 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1748 return (const struct brw_vertex_program
*) p
;
1751 static inline struct brw_geometry_program
*
1752 brw_geometry_program(struct gl_geometry_program
*p
)
1754 return (struct brw_geometry_program
*) p
;
1757 static inline struct brw_fragment_program
*
1758 brw_fragment_program(struct gl_fragment_program
*p
)
1760 return (struct brw_fragment_program
*) p
;
1763 static inline const struct brw_fragment_program
*
1764 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1766 return (const struct brw_fragment_program
*) p
;
1770 * Pre-gen6, the register file of the EUs was shared between threads,
1771 * and each thread used some subset allocated on a 16-register block
1772 * granularity. The unit states wanted these block counts.
1775 brw_register_blocks(int reg_count
)
1777 return ALIGN(reg_count
, 16) / 16 - 1;
1780 static inline uint32_t
1781 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1782 uint32_t prog_offset
)
1784 if (brw
->gen
>= 5) {
1785 /* Using state base address. */
1789 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1793 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1795 return brw
->cache
.bo
->offset64
+ prog_offset
;
1798 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1799 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1800 struct exec_list
*instructions
);
1801 bool brw_do_lower_unnormalized_offset(struct exec_list
*instructions
);
1803 struct opcode_desc
{
1809 extern const struct opcode_desc opcode_descs
[128];
1810 extern const char * const conditional_modifier
[16];
1813 brw_emit_depthbuffer(struct brw_context
*brw
);
1816 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1817 struct intel_mipmap_tree
*depth_mt
,
1818 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1819 uint32_t depth_surface_type
,
1820 struct intel_mipmap_tree
*stencil_mt
,
1821 bool hiz
, bool separate_stencil
,
1822 uint32_t width
, uint32_t height
,
1823 uint32_t tile_x
, uint32_t tile_y
);
1826 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1827 struct intel_mipmap_tree
*depth_mt
,
1828 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1829 uint32_t depth_surface_type
,
1830 struct intel_mipmap_tree
*stencil_mt
,
1831 bool hiz
, bool separate_stencil
,
1832 uint32_t width
, uint32_t height
,
1833 uint32_t tile_x
, uint32_t tile_y
);
1836 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1837 struct intel_mipmap_tree
*depth_mt
,
1838 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1839 uint32_t depth_surface_type
,
1840 struct intel_mipmap_tree
*stencil_mt
,
1841 bool hiz
, bool separate_stencil
,
1842 uint32_t width
, uint32_t height
,
1843 uint32_t tile_x
, uint32_t tile_y
);
1845 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1846 struct intel_mipmap_tree
*depth_mt
,
1847 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1848 uint32_t depth_surface_type
,
1849 struct intel_mipmap_tree
*stencil_mt
,
1850 bool hiz
, bool separate_stencil
,
1851 uint32_t width
, uint32_t height
,
1852 uint32_t tile_x
, uint32_t tile_y
);
1854 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1855 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);
1857 uint32_t get_hw_prim_for_gl_prim(int mode
);
1860 brw_setup_vec4_key_clip_info(struct brw_context
*brw
,
1861 struct brw_vec4_prog_key
*key
,
1862 bool program_uses_clip_distance
);
1865 gen6_upload_push_constants(struct brw_context
*brw
,
1866 const struct gl_program
*prog
,
1867 const struct brw_stage_prog_data
*prog_data
,
1868 struct brw_stage_state
*stage_state
,
1869 enum aub_state_struct_type type
);
1871 /* ================================================================
1872 * From linux kernel i386 header files, copes with odd sizes better
1873 * than COPY_DWORDS would:
1874 * XXX Put this in src/mesa/main/imports.h ???
1876 #if defined(i386) || defined(__i386__)
1877 static inline void * __memcpy(void * to
, const void * from
, size_t n
)
1880 __asm__
__volatile__(
1885 "1:\ttestb $1,%b4\n\t"
1889 : "=&c" (d0
), "=&D" (d1
), "=&S" (d2
)
1890 :"0" (n
/4), "q" (n
),"1" ((long) to
),"2" ((long) from
)
1895 #define __memcpy(a,b,c) memcpy(a,b,c)