2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
38 #include "main/imports.h"
39 #include "main/macros.h"
41 #include "main/mtypes.h"
42 #include "brw_structs.h"
43 #include "intel_aub.h"
44 #include "program/prog_parameter.h"
48 /* Evil hack for using libdrm in a c++ compiler. */
53 #include <intel_bufmgr.h>
63 #include "intel_debug.h"
64 #include "intel_screen.h"
65 #include "intel_tex_obj.h"
66 #include "intel_resolve_map.h"
70 * URB - uniform resource buffer. A mid-sized buffer which is
71 * partitioned between the fixed function units and used for passing
72 * values (vertices, primitives, constants) between them.
74 * CURBE - constant URB entry. An urb region (entry) used to hold
75 * constant values which the fixed function units can be instructed to
76 * preload into the GRF when spawning a thread.
78 * VUE - vertex URB entry. An urb entry holding a vertex and usually
79 * a vertex header. The header contains control information and
80 * things like primitive type, Begin/end flags and clip codes.
82 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
83 * unit holding rasterization and interpolation parameters.
85 * GRF - general register file. One of several register files
86 * addressable by programmed threads. The inputs (r0, payload, curbe,
87 * urb) of the thread are preloaded to this area before the thread is
88 * spawned. The registers are individually 8 dwords wide and suitable
89 * for general usage. Registers holding thread input values are not
90 * special and may be overwritten.
92 * MRF - message register file. Threads communicate (and terminate)
93 * by sending messages. Message parameters are placed in contiguous
94 * MRF registers. All program output is via these messages. URB
95 * entries are populated by sending a message to the shared URB
96 * function containing the new data, together with a control word,
97 * often an unmodified copy of R0.
99 * R0 - GRF register 0. Typically holds control information used when
100 * sending messages to other threads.
102 * EU or GEN4 EU: The name of the programmable subsystem of the
103 * i965 hardware. Threads are executed by the EU, the registers
104 * described above are part of the EU architecture.
106 * Fixed function units:
108 * CS - Command streamer. Notional first unit, little software
109 * interaction. Holds the URB entries used for constant data, ie the
112 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
113 * this unit is responsible for pulling vertices out of vertex buffers
114 * in vram and injecting them into the processing pipe as VUEs. If
115 * enabled, it first passes them to a VS thread which is a good place
116 * for the driver to implement any active vertex shader.
118 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
119 * enabled, incoming strips etc are passed to GS threads in individual
120 * line/triangle/point units. The GS thread may perform arbitary
121 * computation and emit whatever primtives with whatever vertices it
122 * chooses. This makes GS an excellent place to implement GL's
123 * unfilled polygon modes, though of course it is capable of much
124 * more. Additionally, GS is used to translate away primitives not
125 * handled by latter units, including Quads and Lineloops.
127 * CS - Clipper. Mesa's clipping algorithms are imported to run on
128 * this unit. The fixed function part performs cliptesting against
129 * the 6 fixed clipplanes and makes descisions on whether or not the
130 * incoming primitive needs to be passed to a thread for clipping.
131 * User clip planes are handled via cooperation with the VS thread.
133 * SF - Strips Fans or Setup: Triangles are prepared for
134 * rasterization. Interpolation coefficients are calculated.
135 * Flatshading and two-side lighting usually performed here.
137 * WM - Windower. Interpolation of vertex attributes performed here.
138 * Fragment shader implemented here. SIMD aspects of EU taken full
139 * advantage of, as pixels are processed in blocks of 16.
141 * CC - Color Calculator. No EU threads associated with this unit.
142 * Handles blending and (presumably) depth and stencil testing.
147 struct brw_vs_prog_key
;
148 struct brw_vue_prog_key
;
149 struct brw_wm_prog_key
;
150 struct brw_wm_prog_data
;
154 BRW_CACHE_BLORP_BLIT_PROG
,
157 BRW_CACHE_FF_GS_PROG
,
165 /* brw_cache_ids must come first - see brw_state_cache.c */
166 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
167 BRW_STATE_FRAGMENT_PROGRAM
,
168 BRW_STATE_GEOMETRY_PROGRAM
,
169 BRW_STATE_VERTEX_PROGRAM
,
170 BRW_STATE_CURBE_OFFSETS
,
171 BRW_STATE_REDUCED_PRIMITIVE
,
176 BRW_STATE_VS_BINDING_TABLE
,
177 BRW_STATE_GS_BINDING_TABLE
,
178 BRW_STATE_PS_BINDING_TABLE
,
182 BRW_STATE_INDEX_BUFFER
,
183 BRW_STATE_VS_CONSTBUF
,
184 BRW_STATE_GS_CONSTBUF
,
185 BRW_STATE_PROGRAM_CACHE
,
186 BRW_STATE_STATE_BASE_ADDRESS
,
187 BRW_STATE_VUE_MAP_VS
,
188 BRW_STATE_VUE_MAP_GEOM_OUT
,
189 BRW_STATE_TRANSFORM_FEEDBACK
,
190 BRW_STATE_RASTERIZER_DISCARD
,
192 BRW_STATE_UNIFORM_BUFFER
,
193 BRW_STATE_ATOMIC_BUFFER
,
194 BRW_STATE_META_IN_PROGRESS
,
195 BRW_STATE_INTERPOLATION_MAP
,
196 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
197 BRW_STATE_NUM_SAMPLES
,
198 BRW_STATE_TEXTURE_BUFFER
,
199 BRW_STATE_GEN4_UNIT_STATE
,
203 BRW_STATE_SAMPLER_STATE_TABLE
,
204 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
209 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
211 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
212 * When the currently bound shader program differs from the previous draw
213 * call, these will be flagged. They cover brw->{stage}_program and
214 * ctx->{Stage}Program->_Current.
216 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
217 * driver perspective. Even if the same shader is bound at the API level,
218 * we may need to switch between multiple versions of that shader to handle
219 * changes in non-orthagonal state.
221 * Additionally, multiple shader programs may have identical vertex shaders
222 * (for example), or compile down to the same code in the backend. We combine
223 * those into a single program cache entry.
225 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
226 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
228 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
229 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
230 * use the normal state upload paths), but the cache is still used. To avoid
231 * polluting the brw_state_cache code with special cases, we retain the dirty
232 * bit for now. It should eventually be removed.
234 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_BLIT_PROG)
235 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
236 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
237 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
238 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
239 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
240 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
241 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
242 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
243 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
244 #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
245 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
246 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
247 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
248 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
249 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
250 #define BRW_NEW_VS_BINDING_TABLE (1ull << BRW_STATE_VS_BINDING_TABLE)
251 #define BRW_NEW_GS_BINDING_TABLE (1ull << BRW_STATE_GS_BINDING_TABLE)
252 #define BRW_NEW_PS_BINDING_TABLE (1ull << BRW_STATE_PS_BINDING_TABLE)
253 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
254 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
256 * Used for any batch entry with a relocated pointer that will be used
257 * by any 3D rendering.
259 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
260 /** \see brw.state.depth_region */
261 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
262 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
263 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
264 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
265 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
266 #define BRW_NEW_VUE_MAP_VS (1ull << BRW_STATE_VUE_MAP_VS)
267 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
268 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
269 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
270 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
271 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
272 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
273 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
274 #define BRW_NEW_INTERPOLATION_MAP (1ull << BRW_STATE_INTERPOLATION_MAP)
275 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
276 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
277 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
278 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
279 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
280 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
281 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
282 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
283 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
285 struct brw_state_flags
{
286 /** State update flags signalled by mesa internals */
289 * State update flags signalled as the result of brw_tracked_state updates
294 /** Subclass of Mesa vertex program */
295 struct brw_vertex_program
{
296 struct gl_vertex_program program
;
301 /** Subclass of Mesa geometry program */
302 struct brw_geometry_program
{
303 struct gl_geometry_program program
;
304 unsigned id
; /**< serial no. to identify geom progs, never re-used */
308 /** Subclass of Mesa fragment program */
309 struct brw_fragment_program
{
310 struct gl_fragment_program program
;
311 GLuint id
; /**< serial no. to identify frag progs, never re-used */
315 /** Subclass of Mesa compute program */
316 struct brw_compute_program
{
317 struct gl_compute_program program
;
318 unsigned id
; /**< serial no. to identify compute progs, never re-used */
323 struct gl_shader base
;
328 /* Note: If adding fields that need anything besides a normal memcmp() for
329 * comparing them, be sure to go fix brw_stage_prog_data_compare().
331 struct brw_stage_prog_data
{
333 /** size of our binding table. */
337 * surface indices for the various groups of surfaces
339 uint32_t pull_constants_start
;
340 uint32_t texture_start
;
341 uint32_t gather_texture_start
;
344 uint32_t image_start
;
345 uint32_t shader_time_start
;
349 GLuint nr_params
; /**< number of float params/constants */
350 GLuint nr_pull_params
;
352 unsigned curb_read_length
;
353 unsigned total_scratch
;
356 * Register where the thread expects to find input data from the URB
357 * (typically uniforms, followed by vertex or fragment attributes).
359 unsigned dispatch_grf_start_reg
;
361 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
363 /* Pointers to tracked values (only valid once
364 * _mesa_load_state_parameters has been called at runtime).
366 * These must be the last fields of the struct (see
367 * brw_stage_prog_data_compare()).
369 const gl_constant_value
**param
;
370 const gl_constant_value
**pull_param
;
373 /* Data about a particular attempt to compile a program. Note that
374 * there can be many of these, each in a different GL state
375 * corresponding to a different brw_wm_prog_key struct, with different
378 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
381 struct brw_wm_prog_data
{
382 struct brw_stage_prog_data base
;
384 GLuint num_varying_inputs
;
386 GLuint dispatch_grf_start_reg_16
;
388 GLuint reg_blocks_16
;
392 * surface indices the WM-specific surfaces
394 uint32_t render_target_start
;
398 uint8_t computed_depth_mode
;
402 bool uses_pos_offset
;
405 uint32_t prog_offset_16
;
408 * Mask of which interpolation modes are required by the fragment shader.
409 * Used in hardware setup on gen6+.
411 uint32_t barycentric_interp_modes
;
414 * Map from gl_varying_slot to the position within the FS setup data
415 * payload where the varying's attribute vertex deltas should be delivered.
416 * For varying slots that are not used by the FS, the value is -1.
418 int urb_setup
[VARYING_SLOT_MAX
];
422 * Enum representing the i965-specific vertex results that don't correspond
423 * exactly to any element of gl_varying_slot. The values of this enum are
424 * assigned such that they don't conflict with gl_varying_slot.
428 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
429 BRW_VARYING_SLOT_PAD
,
431 * Technically this is not a varying but just a placeholder that
432 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
433 * builtin variable to be compiled correctly. see compile_sf_prog() for
436 BRW_VARYING_SLOT_PNTC
,
437 BRW_VARYING_SLOT_COUNT
442 * Data structure recording the relationship between the gl_varying_slot enum
443 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
444 * single octaword within the VUE (128 bits).
446 * Note that each BRW register contains 256 bits (2 octawords), so when
447 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
448 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
449 * in a vertex shader), each register corresponds to a single VUE slot, since
450 * it contains data for two separate vertices.
454 * Bitfield representing all varying slots that are (a) stored in this VUE
455 * map, and (b) actually written by the shader. Does not include any of
456 * the additional varying slots defined in brw_varying_slot.
458 GLbitfield64 slots_valid
;
461 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
462 * not stored in a slot (because they are not written, or because
463 * additional processing is applied before storing them in the VUE), the
466 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
469 * Map from VUE slot to gl_varying_slot value. For slots that do not
470 * directly correspond to a gl_varying_slot, the value comes from
473 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
474 * simplifies code that uses the value stored in slot_to_varying to
475 * create a bit mask).
477 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
480 * Total number of VUE slots in use
486 * Convert a VUE slot number into a byte offset within the VUE.
488 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
494 * Convert a vertex output (brw_varying_slot) into a byte offset within the
497 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
500 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
503 void brw_compute_vue_map(struct brw_context
*brw
, struct brw_vue_map
*vue_map
,
504 GLbitfield64 slots_valid
);
508 * Bitmask indicating which fragment shader inputs represent varyings (and
509 * hence have to be delivered to the fragment shader by the SF/SBE stage).
511 #define BRW_FS_VARYING_INPUT_MASK \
512 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
513 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
517 * Mapping of VUE map slots to interpolation modes.
519 struct interpolation_mode_map
{
520 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
523 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
525 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
526 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
532 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
534 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
535 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
542 struct brw_sf_prog_data
{
543 GLuint urb_read_length
;
546 /* Each vertex may have upto 12 attributes, 4 components each,
547 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
550 * Actually we use 4 for each, so call it 12 rows.
552 GLuint urb_entry_size
;
557 * We always program SF to start reading at an offset of 1 (2 varying slots)
558 * from the start of the vertex URB entry. This causes it to skip:
559 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
560 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
562 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
565 struct brw_clip_prog_data
{
566 GLuint curb_read_length
; /* user planes? */
568 GLuint urb_read_length
;
572 struct brw_ff_gs_prog_data
{
573 GLuint urb_read_length
;
577 * Gen6 transform feedback: Amount by which the streaming vertex buffer
578 * indices should be incremented each time the GS is invoked.
580 unsigned svbi_postincrement_value
;
584 /* Note: brw_vue_prog_data_compare() must be updated when adding fields to
587 struct brw_vue_prog_data
{
588 struct brw_stage_prog_data base
;
589 struct brw_vue_map vue_map
;
591 GLuint urb_read_length
;
594 /* Used for calculating urb partitions. In the VS, this is the size of the
595 * URB entry used for both input and output to the thread. In the GS, this
596 * is the size of the URB entry used for output.
598 GLuint urb_entry_size
;
604 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
607 struct brw_vs_prog_data
{
608 struct brw_vue_prog_data base
;
610 GLbitfield64 inputs_read
;
613 bool uses_instanceid
;
616 /** Number of texture sampler units */
617 #define BRW_MAX_TEX_UNIT 32
619 /** Max number of render targets in a shader */
620 #define BRW_MAX_DRAW_BUFFERS 8
622 /** Max number of atomic counter buffer objects in a shader */
623 #define BRW_MAX_ABO 16
625 /** Max number of image uniforms in a shader */
626 #define BRW_MAX_IMAGES 32
629 * Max number of binding table entries used for stream output.
631 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
632 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
634 * On Gen6, the size of transform feedback data is limited not by the number
635 * of components but by the number of binding table entries we set aside. We
636 * use one binding table entry for a float, one entry for a vector, and one
637 * entry per matrix column. Since the only way we can communicate our
638 * transform feedback capabilities to the client is via
639 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
640 * worst case, in which all the varyings are floats, so we use up one binding
641 * table entry per component. Therefore we need to set aside at least 64
642 * binding table entries for use by transform feedback.
644 * Note: since we don't currently pack varyings, it is currently impossible
645 * for the client to actually use up all of these binding table entries--if
646 * all of their varyings were floats, they would run out of varying slots and
647 * fail to link. But that's a bug, so it seems prudent to go ahead and
648 * allocate the number of binding table entries we will need once the bug is
651 #define BRW_MAX_SOL_BINDINGS 64
653 /** Maximum number of actual buffers used for stream output */
654 #define BRW_MAX_SOL_BUFFERS 4
656 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
657 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
661 2 /* shader time, pull constants */)
663 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
665 /* Note: brw_gs_prog_data_compare() must be updated when adding fields to
668 struct brw_gs_prog_data
670 struct brw_vue_prog_data base
;
673 * Size of an output vertex, measured in HWORDS (32 bytes).
675 unsigned output_vertex_size_hwords
;
677 unsigned output_topology
;
680 * Size of the control data (cut bits or StreamID bits), in hwords (32
681 * bytes). 0 if there is no control data.
683 unsigned control_data_header_size_hwords
;
686 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
687 * if the control data is StreamID bits, or
688 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
689 * Ignored if control_data_header_size is 0.
691 unsigned control_data_format
;
693 bool include_primitive_id
;
698 * Dispatch mode, can be any of:
699 * GEN7_GS_DISPATCH_MODE_DUAL_OBJECT
700 * GEN7_GS_DISPATCH_MODE_DUAL_INSTANCE
701 * GEN7_GS_DISPATCH_MODE_SINGLE
706 * Gen6 transform feedback enabled flag.
708 bool gen6_xfb_enabled
;
711 * Gen6: Provoking vertex convention for odd-numbered triangles
717 * Gen6: Number of varyings that are output to transform feedback.
719 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
722 * Gen6: Map from the index of a transform feedback binding table entry to the
723 * gl_varying_slot that should be streamed out through that binding table
726 unsigned char transform_feedback_bindings
[BRW_MAX_SOL_BINDINGS
];
729 * Gen6: Map from the index of a transform feedback binding table entry to the
730 * swizzles that should be used when streaming out data through that
731 * binding table entry.
733 unsigned char transform_feedback_swizzles
[BRW_MAX_SOL_BINDINGS
];
737 * Stride in bytes between shader_time entries.
739 * We separate entries by a cacheline to reduce traffic between EUs writing to
742 #define SHADER_TIME_STRIDE 64
744 struct brw_cache_item
{
746 * Effectively part of the key, cache_id identifies what kind of state
747 * buffer is involved, and also which dirty flag should set.
749 enum brw_cache_id cache_id
;
750 /** 32-bit hash of the key data */
752 GLuint key_size
; /* for variable-sized keys */
759 struct brw_cache_item
*next
;
763 typedef bool (*cache_aux_compare_func
)(const void *a
, const void *b
);
764 typedef void (*cache_aux_free_func
)(const void *aux
);
767 struct brw_context
*brw
;
769 struct brw_cache_item
**items
;
771 GLuint size
, n_items
;
773 uint32_t next_offset
;
777 * Optional functions used in determining whether the prog_data for a new
778 * cache item matches an existing cache item (in case there's relevant data
779 * outside of the prog_data). If NULL, a plain memcmp is done.
781 cache_aux_compare_func aux_compare
[BRW_MAX_CACHE
];
782 /** Optional functions for freeing other pointers attached to a prog_data. */
783 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
787 /* Considered adding a member to this struct to document which flags
788 * an update might raise so that ordering of the state atoms can be
789 * checked or derived at runtime. Dropped the idea in favor of having
790 * a debug mode where the state is monitored for flags which are
791 * raised that have already been tested against.
793 struct brw_tracked_state
{
794 struct brw_state_flags dirty
;
795 void (*emit
)( struct brw_context
*brw
);
798 enum shader_time_shader_type
{
814 struct brw_vertex_buffer
{
815 /** Buffer object containing the uploaded vertex data */
818 /** Byte stride between elements in the uploaded array */
822 struct brw_vertex_element
{
823 const struct gl_client_array
*glarray
;
827 /** Offset of the first element within the buffer object */
831 struct brw_query_object
{
832 struct gl_query_object Base
;
834 /** Last query BO associated with this query. */
837 /** Last index in bo with query data for this object. */
840 /** True if we know the batch has been flushed since we ended the query. */
844 struct intel_sync_object
{
845 struct gl_sync_object Base
;
847 /** Batch associated with this sync object */
857 struct intel_batchbuffer
{
858 /** Current batchbuffer being queued up. */
860 /** Last BO submitted to the hardware. Used for glFinish(). */
861 drm_intel_bo
*last_bo
;
862 /** BO for post-sync nonzero writes for gen6 workaround. */
863 drm_intel_bo
*workaround_bo
;
865 uint16_t emit
, total
;
866 uint16_t used
, reserved_space
;
869 #define BATCH_SZ (8192*sizeof(uint32_t))
871 uint32_t state_batch_offset
;
872 enum brw_gpu_ring ring
;
873 bool needs_sol_reset
;
875 uint8_t pipe_controls_since_last_cs_stall
;
883 #define BRW_MAX_XFB_STREAMS 4
885 struct brw_transform_feedback_object
{
886 struct gl_transform_feedback_object base
;
888 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
889 drm_intel_bo
*offset_bo
;
891 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
894 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
895 GLenum primitive_mode
;
898 * Count of primitives generated during this transform feedback operation.
901 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
902 drm_intel_bo
*prim_count_bo
;
903 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
907 * Number of vertices written between last Begin/EndTransformFeedback().
909 * Used to implement DrawTransformFeedback().
911 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
912 bool vertices_written_valid
;
916 * Data shared between each programmable stage in the pipeline (vs, gs, and
919 struct brw_stage_state
921 gl_shader_stage stage
;
922 struct brw_stage_prog_data
*prog_data
;
925 * Optional scratch buffer used to store spilled register values and
926 * variably-indexed GRF arrays.
928 drm_intel_bo
*scratch_bo
;
930 /** Offset in the program cache to the program */
931 uint32_t prog_offset
;
933 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
934 uint32_t state_offset
;
936 uint32_t push_const_offset
; /* Offset in the batchbuffer */
937 int push_const_size
; /* in 256-bit register increments */
939 /* Binding table: pointers to SURFACE_STATE entries. */
940 uint32_t bind_bo_offset
;
941 uint32_t surf_offset
[BRW_MAX_SURFACES
];
943 /** SAMPLER_STATE count and table offset */
944 uint32_t sampler_count
;
945 uint32_t sampler_offset
;
950 * brw_context is derived from gl_context.
954 struct gl_context ctx
; /**< base class, must be first field */
958 void (*update_texture_surface
)(struct gl_context
*ctx
,
960 uint32_t *surf_offset
,
962 void (*update_renderbuffer_surface
)(struct brw_context
*brw
,
963 struct gl_renderbuffer
*rb
,
967 void (*emit_buffer_surface_state
)(struct brw_context
*brw
,
968 uint32_t *out_offset
,
970 unsigned buffer_offset
,
971 unsigned surface_format
,
972 unsigned buffer_size
,
975 void (*emit_null_surface_state
)(struct brw_context
*brw
,
979 uint32_t *out_offset
);
982 * Send the appropriate state packets to configure depth, stencil, and
983 * HiZ buffers (i965+ only)
985 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
986 struct intel_mipmap_tree
*depth_mt
,
987 uint32_t depth_offset
,
988 uint32_t depthbuffer_format
,
989 uint32_t depth_surface_type
,
990 struct intel_mipmap_tree
*stencil_mt
,
991 bool hiz
, bool separate_stencil
,
992 uint32_t width
, uint32_t height
,
993 uint32_t tile_x
, uint32_t tile_y
);
999 drm_intel_context
*hw_ctx
;
1002 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
1003 * and would need flushing before being used from another cache domain that
1004 * isn't coherent with it (i.e. the sampler).
1006 struct set
*render_cache
;
1009 * Number of resets observed in the system at context creation.
1011 * This is tracked in the context so that we can determine that another
1012 * reset has occured.
1014 uint32_t reset_count
;
1016 struct intel_batchbuffer batch
;
1021 uint32_t next_offset
;
1025 * Set if rendering has occured to the drawable's front buffer.
1027 * This is used in the DRI2 case to detect that glFlush should also copy
1028 * the contents of the fake front buffer to the real front buffer.
1030 bool front_buffer_dirty
;
1032 /** Framerate throttling: @{ */
1033 drm_intel_bo
*throttle_batch
[2];
1035 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
1036 * frame of rendering to complete. This gives a very precise cap to the
1037 * latency between input and output such that rendering never gets more
1038 * than a frame behind the user. (With the caveat that we technically are
1039 * not using the SwapBuffers itself as a barrier but the first batch
1040 * submitted afterwards, which may be immediately prior to the next
1043 bool need_swap_throttle
;
1045 /** General throttling, not caught by throttling between SwapBuffers */
1046 bool need_flush_throttle
;
1056 bool always_flush_batch
;
1057 bool always_flush_cache
;
1058 bool disable_throttling
;
1061 driOptionCache optionCache
;
1064 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
1066 GLenum reduced_primitive
;
1069 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
1070 * variable is set, this is the flag indicating to do expensive work that
1071 * might lead to a perf_debug() call.
1075 uint32_t max_gtt_map_object_size
;
1079 /* GT revision. This will be -1 if the revision couldn't be determined (eg,
1080 * if the kernel doesn't support the query).
1090 bool has_separate_stencil
;
1091 bool must_use_separate_stencil
;
1094 bool has_surface_tile_offset
;
1096 bool has_negative_rhw_bug
;
1103 * Some versions of Gen hardware don't do centroid interpolation correctly
1104 * on unlit pixels, causing incorrect values for derivatives near triangle
1105 * edges. Enabling this flag causes the fragment shader to use
1106 * non-centroid interpolation for unlit pixels, at the expense of two extra
1107 * fragment shader instructions.
1109 bool needs_unlit_centroid_workaround
;
1113 struct brw_state_flags dirty
;
1116 struct brw_cache cache
;
1118 /** IDs for meta stencil blit shader programs. */
1119 unsigned meta_stencil_blit_programs
[2];
1121 /* Whether a meta-operation is in progress. */
1122 bool meta_in_progress
;
1124 /* Whether the last depth/stencil packets were both NULL. */
1125 bool no_depth_or_stencil
;
1127 /* The last PMA stall bits programmed. */
1128 uint32_t pma_stall_bits
;
1131 /** The value of gl_BaseVertex for the current _mesa_prim. */
1135 * Buffer and offset used for GL_ARB_shader_draw_parameters
1136 * (for now, only gl_BaseVertex).
1138 drm_intel_bo
*draw_params_bo
;
1139 uint32_t draw_params_offset
;
1143 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
1144 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
1146 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
1150 /* Summary of size and varying of active arrays, so we can check
1151 * for changes to this state:
1153 unsigned int min_index
, max_index
;
1155 /* Offset from start of vertex buffer so we can avoid redefining
1156 * the same VB packed over and over again.
1158 unsigned int start_vertex_bias
;
1161 * Certain vertex attribute formats aren't natively handled by the
1162 * hardware and require special VS code to fix up their values.
1164 * These bitfields indicate which workarounds are needed.
1166 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
1171 * Index buffer for this draw_prims call.
1173 * Updates are signaled by BRW_NEW_INDICES.
1175 const struct _mesa_index_buffer
*ib
;
1177 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
1181 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
1182 * avoid re-uploading the IB packet over and over if we're actually
1183 * referencing the same index buffer.
1185 unsigned int start_vertex_offset
;
1188 /* Active vertex program:
1190 const struct gl_vertex_program
*vertex_program
;
1191 const struct gl_geometry_program
*geometry_program
;
1192 const struct gl_fragment_program
*fragment_program
;
1195 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
1196 * that we don't have to reemit that state every time we change FBOs.
1201 * Platform specific constants containing the maximum number of threads
1202 * for each pipeline stage.
1210 /* BRW_NEW_URB_ALLOCATIONS:
1213 GLuint vsize
; /* vertex size plus header in urb registers */
1214 GLuint gsize
; /* GS output size in urb registers */
1215 GLuint csize
; /* constant buffer size in urb registers */
1216 GLuint sfsize
; /* setup data size in urb registers */
1220 GLuint min_vs_entries
; /* Minimum number of VS entries */
1221 GLuint max_vs_entries
; /* Maximum number of VS entries */
1222 GLuint max_hs_entries
; /* Maximum number of HS entries */
1223 GLuint max_ds_entries
; /* Maximum number of DS entries */
1224 GLuint max_gs_entries
; /* Maximum number of GS entries */
1226 GLuint nr_vs_entries
;
1227 GLuint nr_gs_entries
;
1228 GLuint nr_clip_entries
;
1229 GLuint nr_sf_entries
;
1230 GLuint nr_cs_entries
;
1237 GLuint size
; /* Hardware URB size, in KB. */
1239 /* True if the most recently sent _3DSTATE_URB message allocated
1240 * URB space for the GS.
1246 /* BRW_NEW_CURBE_OFFSETS:
1249 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1250 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1258 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1259 * for upload to the CURBE.
1261 drm_intel_bo
*curbe_bo
;
1262 /** Offset within curbe_bo of space for current curbe entry */
1263 GLuint curbe_offset
;
1267 * Layout of vertex data exiting the vertex shader.
1269 * BRW_NEW_VUE_MAP_VS is flagged when this VUE map changes.
1271 struct brw_vue_map vue_map_vs
;
1274 * Layout of vertex data exiting the geometry portion of the pipleine.
1275 * This comes from the geometry shader if one exists, otherwise from the
1278 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1280 struct brw_vue_map vue_map_geom_out
;
1283 struct brw_stage_state base
;
1284 struct brw_vs_prog_data
*prog_data
;
1288 struct brw_stage_state base
;
1289 struct brw_gs_prog_data
*prog_data
;
1292 * True if the 3DSTATE_GS command most recently emitted to the 3D
1293 * pipeline enabled the GS; false otherwise.
1299 struct brw_ff_gs_prog_data
*prog_data
;
1302 /** Offset in the program cache to the CLIP program pre-gen6 */
1303 uint32_t prog_offset
;
1304 uint32_t state_offset
;
1306 uint32_t bind_bo_offset
;
1308 * Surface offsets for the binding table. We only need surfaces to
1309 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1310 * need in this case.
1312 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1316 struct brw_clip_prog_data
*prog_data
;
1318 /** Offset in the program cache to the CLIP program pre-gen6 */
1319 uint32_t prog_offset
;
1321 /* Offset in the batch to the CLIP state on pre-gen6. */
1322 uint32_t state_offset
;
1324 /* As of gen6, this is the offset in the batch to the CLIP VP,
1332 struct brw_sf_prog_data
*prog_data
;
1334 /** Offset in the program cache to the CLIP program pre-gen6 */
1335 uint32_t prog_offset
;
1336 uint32_t state_offset
;
1338 bool viewport_transform_enable
;
1342 struct brw_stage_state base
;
1343 struct brw_wm_prog_data
*prog_data
;
1348 * Buffer object used in place of multisampled null render targets on
1349 * Gen6. See brw_emit_null_surface_state().
1351 drm_intel_bo
*multisampled_null_render_target_bo
;
1352 uint32_t fast_clear_op
;
1357 uint32_t state_offset
;
1358 uint32_t blend_state_offset
;
1359 uint32_t depth_stencil_state_offset
;
1364 struct brw_query_object
*obj
;
1369 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1370 const int *statistics_registers
;
1372 /** The number of active monitors using OA counters. */
1376 * A buffer object storing OA counter snapshots taken at the start and
1377 * end of each batch (creating "bookends" around the batch).
1379 drm_intel_bo
*bookend_bo
;
1381 /** The number of snapshots written to bookend_bo. */
1382 int bookend_snapshots
;
1385 * An array of monitors whose results haven't yet been assembled based on
1386 * the data in buffer objects.
1388 * These may be active, or have already ended. However, the results
1389 * have not been requested.
1391 struct brw_perf_monitor_object
**unresolved
;
1392 int unresolved_elements
;
1393 int unresolved_array_size
;
1396 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1397 * the counter which MI_REPORT_PERF_COUNT stores there.
1399 const int *oa_snapshot_layout
;
1401 /** Number of 32-bit entries in a hardware counter snapshot. */
1402 int entries_per_oa_snapshot
;
1406 const struct brw_tracked_state atoms
[57];
1408 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1412 enum aub_state_struct_type type
;
1413 } *state_batch_list
;
1414 int state_batch_count
;
1416 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1417 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1419 /* Interpolation modes, one byte per vue slot.
1420 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1422 struct interpolation_mode_map interpolation_mode
;
1424 /* PrimitiveRestart */
1427 bool enable_cut_index
;
1430 /** Computed depth/stencil/hiz state from the current attached
1431 * renderbuffers, valid only during the drawing state upload loop after
1432 * brw_workaround_depthstencil_alignment().
1435 struct intel_mipmap_tree
*depth_mt
;
1436 struct intel_mipmap_tree
*stencil_mt
;
1438 /* Inter-tile (page-aligned) byte offsets. */
1439 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1440 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1441 uint32_t tile_x
, tile_y
;
1444 uint32_t num_instances
;
1449 struct gl_shader_program
**shader_programs
;
1450 struct gl_program
**programs
;
1451 enum shader_time_shader_type
*types
;
1452 uint64_t *cumulative
;
1458 struct brw_fast_clear_state
*fast_clear_state
;
1460 __DRIcontext
*driContext
;
1461 struct intel_screen
*intelScreen
;
1464 /*======================================================================
1467 void brwInitVtbl( struct brw_context
*brw
);
1470 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1472 /*======================================================================
1475 extern const char *const brw_vendor_string
;
1477 extern const char *brw_get_renderer_string(unsigned deviceID
);
1480 DRI_CONF_BO_REUSE_DISABLED
,
1481 DRI_CONF_BO_REUSE_ALL
1484 void intel_update_renderbuffers(__DRIcontext
*context
,
1485 __DRIdrawable
*drawable
);
1486 void intel_prepare_render(struct brw_context
*brw
);
1488 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1489 __DRIdrawable
*drawable
);
1491 GLboolean
brwCreateContext(gl_api api
,
1492 const struct gl_config
*mesaVis
,
1493 __DRIcontext
*driContextPriv
,
1494 unsigned major_version
,
1495 unsigned minor_version
,
1499 void *sharedContextPrivate
);
1501 /*======================================================================
1504 GLuint
brw_get_rb_for_slice(struct brw_context
*brw
,
1505 struct intel_mipmap_tree
*mt
,
1506 unsigned level
, unsigned layer
, bool flat
);
1508 void brw_meta_updownsample(struct brw_context
*brw
,
1509 struct intel_mipmap_tree
*src
,
1510 struct intel_mipmap_tree
*dst
);
1512 void brw_meta_fbo_stencil_blit(struct brw_context
*brw
,
1513 struct gl_framebuffer
*read_fb
,
1514 struct gl_framebuffer
*draw_fb
,
1515 GLfloat srcX0
, GLfloat srcY0
,
1516 GLfloat srcX1
, GLfloat srcY1
,
1517 GLfloat dstX0
, GLfloat dstY0
,
1518 GLfloat dstX1
, GLfloat dstY1
);
1520 void brw_meta_stencil_updownsample(struct brw_context
*brw
,
1521 struct intel_mipmap_tree
*src
,
1522 struct intel_mipmap_tree
*dst
);
1524 bool brw_meta_fast_clear(struct brw_context
*brw
,
1525 struct gl_framebuffer
*fb
,
1527 bool partial_clear
);
1530 brw_meta_resolve_color(struct brw_context
*brw
,
1531 struct intel_mipmap_tree
*mt
);
1533 brw_meta_fast_clear_free(struct brw_context
*brw
);
1536 /*======================================================================
1539 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1540 uint32_t depth_level
,
1541 uint32_t depth_layer
,
1542 struct intel_mipmap_tree
*stencil_mt
,
1543 uint32_t *out_tile_mask_x
,
1544 uint32_t *out_tile_mask_y
);
1545 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1546 GLbitfield clear_mask
);
1548 /* brw_object_purgeable.c */
1549 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1551 /*======================================================================
1554 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1555 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1556 void brw_emit_query_begin(struct brw_context
*brw
);
1557 void brw_emit_query_end(struct brw_context
*brw
);
1559 /** gen6_queryobj.c */
1560 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1561 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1562 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1563 void brw_store_register_mem64(struct brw_context
*brw
,
1564 drm_intel_bo
*bo
, uint32_t reg
, int idx
);
1566 /** intel_batchbuffer.c */
1567 void brw_load_register_mem(struct brw_context
*brw
,
1570 uint32_t read_domains
, uint32_t write_domain
,
1573 /*======================================================================
1576 void brw_debug_batch(struct brw_context
*brw
);
1577 void brw_annotate_aub(struct brw_context
*brw
);
1579 /*======================================================================
1582 void brw_validate_textures( struct brw_context
*brw
);
1585 /*======================================================================
1588 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1590 int brw_get_scratch_size(int size
);
1591 void brw_get_scratch_bo(struct brw_context
*brw
,
1592 drm_intel_bo
**scratch_bo
, int size
);
1593 void brw_init_shader_time(struct brw_context
*brw
);
1594 int brw_get_shader_time_index(struct brw_context
*brw
,
1595 struct gl_shader_program
*shader_prog
,
1596 struct gl_program
*prog
,
1597 enum shader_time_shader_type type
);
1598 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1599 void brw_destroy_shader_time(struct brw_context
*brw
);
1603 void brw_upload_urb_fence(struct brw_context
*brw
);
1607 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1609 /* brw_fs_reg_allocate.cpp
1611 void brw_fs_alloc_reg_sets(struct intel_screen
*screen
);
1613 /* brw_vec4_reg_allocate.cpp */
1614 void brw_vec4_alloc_reg_set(struct intel_screen
*screen
);
1617 int brw_disassemble_inst(FILE *file
, struct brw_context
*brw
,
1618 struct brw_inst
*inst
, bool is_compacted
);
1621 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1623 /* brw_draw_upload.c */
1624 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1625 const struct gl_client_array
*glarray
);
1627 static inline unsigned
1628 brw_get_index_type(GLenum type
)
1630 assert((type
== GL_UNSIGNED_BYTE
)
1631 || (type
== GL_UNSIGNED_SHORT
)
1632 || (type
== GL_UNSIGNED_INT
));
1634 /* The possible values for type are GL_UNSIGNED_BYTE (0x1401),
1635 * GL_UNSIGNED_SHORT (0x1403), and GL_UNSIGNED_INT (0x1405) which we want
1636 * to map to scale factors of 0, 1, and 2, respectively. These scale
1637 * factors are then left-shfited by 8 to be in the correct position in the
1638 * CMD_INDEX_BUFFER packet.
1640 * Subtracting 0x1401 gives 0, 2, and 4. Shifting left by 7 afterwards
1641 * gives 0x00000000, 0x00000100, and 0x00000200. These just happen to be
1642 * the values the need to be written in the CMD_INDEX_BUFFER packet.
1644 return (type
- 0x1401) << 7;
1647 void brw_prepare_vertices(struct brw_context
*brw
);
1649 /* brw_wm_surface_state.c */
1650 void brw_init_surface_formats(struct brw_context
*brw
);
1651 void brw_create_constant_surface(struct brw_context
*brw
,
1655 uint32_t *out_offset
,
1657 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1659 uint32_t *surf_offset
);
1661 brw_update_sol_surface(struct brw_context
*brw
,
1662 struct gl_buffer_object
*buffer_obj
,
1663 uint32_t *out_offset
, unsigned num_vector_components
,
1664 unsigned stride_dwords
, unsigned offset_dwords
);
1665 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1666 struct gl_shader
*shader
,
1667 struct brw_stage_state
*stage_state
,
1668 struct brw_stage_prog_data
*prog_data
,
1670 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1671 struct gl_shader_program
*prog
,
1672 struct brw_stage_state
*stage_state
,
1673 struct brw_stage_prog_data
*prog_data
);
1675 /* brw_surface_formats.c */
1676 bool brw_is_hiz_depth_format(struct brw_context
*ctx
, mesa_format format
);
1677 bool brw_render_target_supported(struct brw_context
*brw
,
1678 struct gl_renderbuffer
*rb
);
1679 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1681 /* brw_performance_monitor.c */
1682 void brw_init_performance_monitors(struct brw_context
*brw
);
1683 void brw_dump_perf_monitors(struct brw_context
*brw
);
1684 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1685 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1687 /* intel_buffer_objects.c */
1688 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1689 const char *bo_name
);
1690 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1691 const char *bo_name
);
1693 /* intel_extensions.c */
1694 extern void intelInitExtensions(struct gl_context
*ctx
);
1697 extern int intel_translate_shadow_compare_func(GLenum func
);
1698 extern int intel_translate_compare_func(GLenum func
);
1699 extern int intel_translate_stencil_op(GLenum op
);
1700 extern int intel_translate_logic_op(GLenum opcode
);
1702 /* intel_syncobj.c */
1703 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1706 struct gl_transform_feedback_object
*
1707 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1709 brw_delete_transform_feedback(struct gl_context
*ctx
,
1710 struct gl_transform_feedback_object
*obj
);
1712 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1713 struct gl_transform_feedback_object
*obj
);
1715 brw_end_transform_feedback(struct gl_context
*ctx
,
1716 struct gl_transform_feedback_object
*obj
);
1718 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1719 struct gl_transform_feedback_object
*obj
,
1722 /* gen7_sol_state.c */
1724 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1725 struct gl_transform_feedback_object
*obj
);
1727 gen7_end_transform_feedback(struct gl_context
*ctx
,
1728 struct gl_transform_feedback_object
*obj
);
1730 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1731 struct gl_transform_feedback_object
*obj
);
1733 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1734 struct gl_transform_feedback_object
*obj
);
1736 /* brw_blorp_blit.cpp */
1738 brw_blorp_framebuffer(struct brw_context
*brw
,
1739 struct gl_framebuffer
*readFb
,
1740 struct gl_framebuffer
*drawFb
,
1741 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1742 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1743 GLbitfield mask
, GLenum filter
);
1746 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1747 struct gl_renderbuffer
*src_rb
,
1748 struct gl_texture_image
*dst_image
,
1750 int srcX0
, int srcY0
,
1751 int dstX0
, int dstY0
,
1752 int width
, int height
);
1754 /* gen6_multisample_state.c */
1756 gen6_determine_sample_mask(struct brw_context
*brw
);
1759 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1760 unsigned num_samples
);
1762 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1764 gen6_get_sample_position(struct gl_context
*ctx
,
1765 struct gl_framebuffer
*fb
,
1769 gen6_set_sample_maps(struct gl_context
*ctx
);
1771 /* gen8_multisample_state.c */
1772 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1773 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1777 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1778 unsigned gs_size
, unsigned fs_size
);
1781 gen7_emit_urb_state(struct brw_context
*brw
,
1782 unsigned nr_vs_entries
, unsigned vs_size
,
1783 unsigned vs_start
, unsigned nr_gs_entries
,
1784 unsigned gs_size
, unsigned gs_start
);
1789 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1791 /*======================================================================
1792 * Inline conversion functions. These are better-typed than the
1793 * macros used previously:
1795 static inline struct brw_context
*
1796 brw_context( struct gl_context
*ctx
)
1798 return (struct brw_context
*)ctx
;
1801 static inline struct brw_vertex_program
*
1802 brw_vertex_program(struct gl_vertex_program
*p
)
1804 return (struct brw_vertex_program
*) p
;
1807 static inline const struct brw_vertex_program
*
1808 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1810 return (const struct brw_vertex_program
*) p
;
1813 static inline struct brw_geometry_program
*
1814 brw_geometry_program(struct gl_geometry_program
*p
)
1816 return (struct brw_geometry_program
*) p
;
1819 static inline struct brw_fragment_program
*
1820 brw_fragment_program(struct gl_fragment_program
*p
)
1822 return (struct brw_fragment_program
*) p
;
1825 static inline const struct brw_fragment_program
*
1826 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1828 return (const struct brw_fragment_program
*) p
;
1832 * Pre-gen6, the register file of the EUs was shared between threads,
1833 * and each thread used some subset allocated on a 16-register block
1834 * granularity. The unit states wanted these block counts.
1837 brw_register_blocks(int reg_count
)
1839 return ALIGN(reg_count
, 16) / 16 - 1;
1842 static inline uint32_t
1843 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1844 uint32_t prog_offset
)
1846 if (brw
->gen
>= 5) {
1847 /* Using state base address. */
1851 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1855 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1857 return brw
->cache
.bo
->offset64
+ prog_offset
;
1860 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1861 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1862 struct exec_list
*instructions
);
1863 bool brw_do_lower_unnormalized_offset(struct exec_list
*instructions
);
1865 struct opcode_desc
{
1871 extern const struct opcode_desc opcode_descs
[128];
1872 extern const char * const conditional_modifier
[16];
1875 brw_emit_depthbuffer(struct brw_context
*brw
);
1878 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1879 struct intel_mipmap_tree
*depth_mt
,
1880 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1881 uint32_t depth_surface_type
,
1882 struct intel_mipmap_tree
*stencil_mt
,
1883 bool hiz
, bool separate_stencil
,
1884 uint32_t width
, uint32_t height
,
1885 uint32_t tile_x
, uint32_t tile_y
);
1888 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1889 struct intel_mipmap_tree
*depth_mt
,
1890 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1891 uint32_t depth_surface_type
,
1892 struct intel_mipmap_tree
*stencil_mt
,
1893 bool hiz
, bool separate_stencil
,
1894 uint32_t width
, uint32_t height
,
1895 uint32_t tile_x
, uint32_t tile_y
);
1898 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1899 struct intel_mipmap_tree
*depth_mt
,
1900 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1901 uint32_t depth_surface_type
,
1902 struct intel_mipmap_tree
*stencil_mt
,
1903 bool hiz
, bool separate_stencil
,
1904 uint32_t width
, uint32_t height
,
1905 uint32_t tile_x
, uint32_t tile_y
);
1907 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1908 struct intel_mipmap_tree
*depth_mt
,
1909 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1910 uint32_t depth_surface_type
,
1911 struct intel_mipmap_tree
*stencil_mt
,
1912 bool hiz
, bool separate_stencil
,
1913 uint32_t width
, uint32_t height
,
1914 uint32_t tile_x
, uint32_t tile_y
);
1916 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1917 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);
1919 uint32_t get_hw_prim_for_gl_prim(int mode
);
1922 brw_setup_vue_key_clip_info(struct brw_context
*brw
,
1923 struct brw_vue_prog_key
*key
,
1924 bool program_uses_clip_distance
);
1927 gen6_upload_push_constants(struct brw_context
*brw
,
1928 const struct gl_program
*prog
,
1929 const struct brw_stage_prog_data
*prog_data
,
1930 struct brw_stage_state
*stage_state
,
1931 enum aub_state_struct_type type
);