2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
37 #include "main/macros.h"
38 #include "main/mtypes.h"
39 #include "brw_structs.h"
40 #include "brw_compiler.h"
41 #include "intel_aub.h"
45 /* Evil hack for using libdrm in a c++ compiler. */
49 #include <intel_bufmgr.h>
58 #include "intel_debug.h"
59 #include "intel_screen.h"
60 #include "intel_tex_obj.h"
61 #include "intel_resolve_map.h"
65 * URB - uniform resource buffer. A mid-sized buffer which is
66 * partitioned between the fixed function units and used for passing
67 * values (vertices, primitives, constants) between them.
69 * CURBE - constant URB entry. An urb region (entry) used to hold
70 * constant values which the fixed function units can be instructed to
71 * preload into the GRF when spawning a thread.
73 * VUE - vertex URB entry. An urb entry holding a vertex and usually
74 * a vertex header. The header contains control information and
75 * things like primitive type, Begin/end flags and clip codes.
77 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
78 * unit holding rasterization and interpolation parameters.
80 * GRF - general register file. One of several register files
81 * addressable by programmed threads. The inputs (r0, payload, curbe,
82 * urb) of the thread are preloaded to this area before the thread is
83 * spawned. The registers are individually 8 dwords wide and suitable
84 * for general usage. Registers holding thread input values are not
85 * special and may be overwritten.
87 * MRF - message register file. Threads communicate (and terminate)
88 * by sending messages. Message parameters are placed in contiguous
89 * MRF registers. All program output is via these messages. URB
90 * entries are populated by sending a message to the shared URB
91 * function containing the new data, together with a control word,
92 * often an unmodified copy of R0.
94 * R0 - GRF register 0. Typically holds control information used when
95 * sending messages to other threads.
97 * EU or GEN4 EU: The name of the programmable subsystem of the
98 * i965 hardware. Threads are executed by the EU, the registers
99 * described above are part of the EU architecture.
101 * Fixed function units:
103 * CS - Command streamer. Notional first unit, little software
104 * interaction. Holds the URB entries used for constant data, ie the
107 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
108 * this unit is responsible for pulling vertices out of vertex buffers
109 * in vram and injecting them into the processing pipe as VUEs. If
110 * enabled, it first passes them to a VS thread which is a good place
111 * for the driver to implement any active vertex shader.
113 * HS - Hull Shader (Tessellation Control Shader)
115 * TE - Tessellation Engine (Tessellation Primitive Generation)
117 * DS - Domain Shader (Tessellation Evaluation Shader)
119 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
120 * enabled, incoming strips etc are passed to GS threads in individual
121 * line/triangle/point units. The GS thread may perform arbitary
122 * computation and emit whatever primtives with whatever vertices it
123 * chooses. This makes GS an excellent place to implement GL's
124 * unfilled polygon modes, though of course it is capable of much
125 * more. Additionally, GS is used to translate away primitives not
126 * handled by latter units, including Quads and Lineloops.
128 * CS - Clipper. Mesa's clipping algorithms are imported to run on
129 * this unit. The fixed function part performs cliptesting against
130 * the 6 fixed clipplanes and makes descisions on whether or not the
131 * incoming primitive needs to be passed to a thread for clipping.
132 * User clip planes are handled via cooperation with the VS thread.
134 * SF - Strips Fans or Setup: Triangles are prepared for
135 * rasterization. Interpolation coefficients are calculated.
136 * Flatshading and two-side lighting usually performed here.
138 * WM - Windower. Interpolation of vertex attributes performed here.
139 * Fragment shader implemented here. SIMD aspects of EU taken full
140 * advantage of, as pixels are processed in blocks of 16.
142 * CC - Color Calculator. No EU threads associated with this unit.
143 * Handles blending and (presumably) depth and stencil testing.
148 struct brw_vs_prog_key
;
149 struct brw_vue_prog_key
;
150 struct brw_wm_prog_key
;
151 struct brw_wm_prog_data
;
152 struct brw_cs_prog_key
;
153 struct brw_cs_prog_data
;
157 BRW_COMPUTE_PIPELINE
,
164 BRW_CACHE_BLORP_BLIT_PROG
,
167 BRW_CACHE_FF_GS_PROG
,
178 /* brw_cache_ids must come first - see brw_state_cache.c */
179 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
180 BRW_STATE_FRAGMENT_PROGRAM
,
181 BRW_STATE_GEOMETRY_PROGRAM
,
182 BRW_STATE_TESS_CTRL_PROGRAM
,
183 BRW_STATE_TESS_EVAL_PROGRAM
,
184 BRW_STATE_VERTEX_PROGRAM
,
185 BRW_STATE_CURBE_OFFSETS
,
186 BRW_STATE_REDUCED_PRIMITIVE
,
187 BRW_STATE_PATCH_PRIMITIVE
,
192 BRW_STATE_BINDING_TABLE_POINTERS
,
196 BRW_STATE_INDEX_BUFFER
,
197 BRW_STATE_VS_CONSTBUF
,
198 BRW_STATE_GS_CONSTBUF
,
199 BRW_STATE_PROGRAM_CACHE
,
200 BRW_STATE_STATE_BASE_ADDRESS
,
201 BRW_STATE_VUE_MAP_GEOM_OUT
,
202 BRW_STATE_TRANSFORM_FEEDBACK
,
203 BRW_STATE_RASTERIZER_DISCARD
,
205 BRW_STATE_UNIFORM_BUFFER
,
206 BRW_STATE_ATOMIC_BUFFER
,
207 BRW_STATE_IMAGE_UNITS
,
208 BRW_STATE_META_IN_PROGRESS
,
209 BRW_STATE_INTERPOLATION_MAP
,
210 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
211 BRW_STATE_NUM_SAMPLES
,
212 BRW_STATE_TEXTURE_BUFFER
,
213 BRW_STATE_GEN4_UNIT_STATE
,
217 BRW_STATE_SAMPLER_STATE_TABLE
,
218 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
219 BRW_STATE_COMPUTE_PROGRAM
,
220 BRW_STATE_CS_WORK_GROUPS
,
225 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
227 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
228 * When the currently bound shader program differs from the previous draw
229 * call, these will be flagged. They cover brw->{stage}_program and
230 * ctx->{Stage}Program->_Current.
232 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
233 * driver perspective. Even if the same shader is bound at the API level,
234 * we may need to switch between multiple versions of that shader to handle
235 * changes in non-orthagonal state.
237 * Additionally, multiple shader programs may have identical vertex shaders
238 * (for example), or compile down to the same code in the backend. We combine
239 * those into a single program cache entry.
241 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
242 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
244 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
245 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
246 * use the normal state upload paths), but the cache is still used. To avoid
247 * polluting the brw_state_cache code with special cases, we retain the dirty
248 * bit for now. It should eventually be removed.
250 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_BLIT_PROG)
251 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
252 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
253 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
254 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
255 #define BRW_NEW_TCS_PROG_DATA (1ull << BRW_CACHE_TCS_PROG)
256 #define BRW_NEW_TES_PROG_DATA (1ull << BRW_CACHE_TES_PROG)
257 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
258 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
259 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
260 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
261 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
262 #define BRW_NEW_TESS_EVAL_PROGRAM (1ull << BRW_STATE_TESS_EVAL_PROGRAM)
263 #define BRW_NEW_TESS_CTRL_PROGRAM (1ull << BRW_STATE_TESS_CTRL_PROGRAM)
264 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
265 #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
266 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
267 #define BRW_NEW_PATCH_PRIMITIVE (1ull << BRW_STATE_PATCH_PRIMITIVE)
268 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
269 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
270 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
271 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
272 #define BRW_NEW_BINDING_TABLE_POINTERS (1ull << BRW_STATE_BINDING_TABLE_POINTERS)
273 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
274 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
276 * Used for any batch entry with a relocated pointer that will be used
277 * by any 3D rendering.
279 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
280 /** \see brw.state.depth_region */
281 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
282 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
283 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
284 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
285 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
286 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
287 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
288 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
289 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
290 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
291 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
292 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
293 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
294 #define BRW_NEW_INTERPOLATION_MAP (1ull << BRW_STATE_INTERPOLATION_MAP)
295 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
296 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
297 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
298 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
299 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
300 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
301 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
302 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
303 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
304 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
305 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
307 struct brw_state_flags
{
308 /** State update flags signalled by mesa internals */
311 * State update flags signalled as the result of brw_tracked_state updates
316 /** Subclass of Mesa vertex program */
317 struct brw_vertex_program
{
318 struct gl_vertex_program program
;
323 /** Subclass of Mesa tessellation control program */
324 struct brw_tess_ctrl_program
{
325 struct gl_tess_ctrl_program program
;
326 unsigned id
; /**< serial no. to identify tess ctrl progs, never re-used */
330 /** Subclass of Mesa tessellation evaluation program */
331 struct brw_tess_eval_program
{
332 struct gl_tess_eval_program program
;
333 unsigned id
; /**< serial no. to identify tess eval progs, never re-used */
337 /** Subclass of Mesa geometry program */
338 struct brw_geometry_program
{
339 struct gl_geometry_program program
;
340 unsigned id
; /**< serial no. to identify geom progs, never re-used */
344 /** Subclass of Mesa fragment program */
345 struct brw_fragment_program
{
346 struct gl_fragment_program program
;
347 GLuint id
; /**< serial no. to identify frag progs, never re-used */
351 /** Subclass of Mesa compute program */
352 struct brw_compute_program
{
353 struct gl_compute_program program
;
354 unsigned id
; /**< serial no. to identify compute progs, never re-used */
359 struct gl_shader base
;
365 * Bitmask indicating which fragment shader inputs represent varyings (and
366 * hence have to be delivered to the fragment shader by the SF/SBE stage).
368 #define BRW_FS_VARYING_INPUT_MASK \
369 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
370 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
374 * Mapping of VUE map slots to interpolation modes.
376 struct interpolation_mode_map
{
377 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
380 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
382 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
383 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
389 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
391 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
392 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
399 struct brw_sf_prog_data
{
400 GLuint urb_read_length
;
403 /* Each vertex may have upto 12 attributes, 4 components each,
404 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
407 * Actually we use 4 for each, so call it 12 rows.
409 GLuint urb_entry_size
;
414 * We always program SF to start reading at an offset of 1 (2 varying slots)
415 * from the start of the vertex URB entry. This causes it to skip:
416 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
417 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
419 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
422 struct brw_clip_prog_data
{
423 GLuint curb_read_length
; /* user planes? */
425 GLuint urb_read_length
;
429 struct brw_ff_gs_prog_data
{
430 GLuint urb_read_length
;
434 * Gen6 transform feedback: Amount by which the streaming vertex buffer
435 * indices should be incremented each time the GS is invoked.
437 unsigned svbi_postincrement_value
;
440 /** Number of texture sampler units */
441 #define BRW_MAX_TEX_UNIT 32
443 /** Max number of render targets in a shader */
444 #define BRW_MAX_DRAW_BUFFERS 8
446 /** Max number of UBOs in a shader */
447 #define BRW_MAX_UBO 14
449 /** Max number of SSBOs in a shader */
450 #define BRW_MAX_SSBO 12
452 /** Max number of atomic counter buffer objects in a shader */
453 #define BRW_MAX_ABO 16
455 /** Max number of image uniforms in a shader */
456 #define BRW_MAX_IMAGES 32
459 * Max number of binding table entries used for stream output.
461 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
462 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
464 * On Gen6, the size of transform feedback data is limited not by the number
465 * of components but by the number of binding table entries we set aside. We
466 * use one binding table entry for a float, one entry for a vector, and one
467 * entry per matrix column. Since the only way we can communicate our
468 * transform feedback capabilities to the client is via
469 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
470 * worst case, in which all the varyings are floats, so we use up one binding
471 * table entry per component. Therefore we need to set aside at least 64
472 * binding table entries for use by transform feedback.
474 * Note: since we don't currently pack varyings, it is currently impossible
475 * for the client to actually use up all of these binding table entries--if
476 * all of their varyings were floats, they would run out of varying slots and
477 * fail to link. But that's a bug, so it seems prudent to go ahead and
478 * allocate the number of binding table entries we will need once the bug is
481 #define BRW_MAX_SOL_BINDINGS 64
483 /** Maximum number of actual buffers used for stream output */
484 #define BRW_MAX_SOL_BUFFERS 4
486 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
487 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
492 2 + /* shader time, pull constants */ \
493 1 /* cs num work groups */)
495 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
498 * Stride in bytes between shader_time entries.
500 * We separate entries by a cacheline to reduce traffic between EUs writing to
503 #define SHADER_TIME_STRIDE 64
505 struct brw_cache_item
{
507 * Effectively part of the key, cache_id identifies what kind of state
508 * buffer is involved, and also which dirty flag should set.
510 enum brw_cache_id cache_id
;
511 /** 32-bit hash of the key data */
513 GLuint key_size
; /* for variable-sized keys */
520 struct brw_cache_item
*next
;
525 struct brw_context
*brw
;
527 struct brw_cache_item
**items
;
529 GLuint size
, n_items
;
531 uint32_t next_offset
;
536 /* Considered adding a member to this struct to document which flags
537 * an update might raise so that ordering of the state atoms can be
538 * checked or derived at runtime. Dropped the idea in favor of having
539 * a debug mode where the state is monitored for flags which are
540 * raised that have already been tested against.
542 struct brw_tracked_state
{
543 struct brw_state_flags dirty
;
544 void (*emit
)( struct brw_context
*brw
);
547 enum shader_time_shader_type
{
558 struct brw_vertex_buffer
{
559 /** Buffer object containing the uploaded vertex data */
562 /** Byte stride between elements in the uploaded array */
566 struct brw_vertex_element
{
567 const struct gl_client_array
*glarray
;
571 /** Offset of the first element within the buffer object */
575 struct brw_query_object
{
576 struct gl_query_object Base
;
578 /** Last query BO associated with this query. */
581 /** Last index in bo with query data for this object. */
584 /** True if we know the batch has been flushed since we ended the query. */
594 struct intel_batchbuffer
{
595 /** Current batchbuffer being queued up. */
597 /** Last BO submitted to the hardware. Used for glFinish(). */
598 drm_intel_bo
*last_bo
;
601 uint16_t emit
, total
;
603 uint16_t reserved_space
;
607 #define BATCH_SZ (8192*sizeof(uint32_t))
609 uint32_t state_batch_offset
;
610 enum brw_gpu_ring ring
;
611 bool needs_sol_reset
;
619 #define MAX_GS_INPUT_VERTICES 6
621 #define BRW_MAX_XFB_STREAMS 4
623 struct brw_transform_feedback_object
{
624 struct gl_transform_feedback_object base
;
626 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
627 drm_intel_bo
*offset_bo
;
629 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
632 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
633 GLenum primitive_mode
;
636 * Count of primitives generated during this transform feedback operation.
639 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
640 drm_intel_bo
*prim_count_bo
;
641 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
645 * Number of vertices written between last Begin/EndTransformFeedback().
647 * Used to implement DrawTransformFeedback().
649 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
650 bool vertices_written_valid
;
654 * Data shared between each programmable stage in the pipeline (vs, gs, and
657 struct brw_stage_state
659 gl_shader_stage stage
;
660 struct brw_stage_prog_data
*prog_data
;
663 * Optional scratch buffer used to store spilled register values and
664 * variably-indexed GRF arrays.
666 drm_intel_bo
*scratch_bo
;
668 /** Offset in the program cache to the program */
669 uint32_t prog_offset
;
671 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
672 uint32_t state_offset
;
674 uint32_t push_const_offset
; /* Offset in the batchbuffer */
675 int push_const_size
; /* in 256-bit register increments */
677 /* Binding table: pointers to SURFACE_STATE entries. */
678 uint32_t bind_bo_offset
;
679 uint32_t surf_offset
[BRW_MAX_SURFACES
];
681 /** SAMPLER_STATE count and table offset */
682 uint32_t sampler_count
;
683 uint32_t sampler_offset
;
686 enum brw_predicate_state
{
687 /* The first two states are used if we can determine whether to draw
688 * without having to look at the values in the query object buffer. This
689 * will happen if there is no conditional render in progress, if the query
690 * object is already completed or if something else has already added
691 * samples to the preliminary result such as via a BLT command.
693 BRW_PREDICATE_STATE_RENDER
,
694 BRW_PREDICATE_STATE_DONT_RENDER
,
695 /* In this case whether to draw or not depends on the result of an
696 * MI_PREDICATE command so the predicate enable bit needs to be checked.
698 BRW_PREDICATE_STATE_USE_BIT
704 * brw_context is derived from gl_context.
708 struct gl_context ctx
; /**< base class, must be first field */
712 void (*update_texture_surface
)(struct gl_context
*ctx
,
714 uint32_t *surf_offset
,
716 uint32_t (*update_renderbuffer_surface
)(struct brw_context
*brw
,
717 struct gl_renderbuffer
*rb
,
718 bool layered
, unsigned unit
,
719 uint32_t surf_index
);
721 void (*emit_texture_surface_state
)(struct brw_context
*brw
,
722 struct intel_mipmap_tree
*mt
,
730 uint32_t *surf_offset
,
731 bool rw
, bool for_gather
);
732 void (*emit_buffer_surface_state
)(struct brw_context
*brw
,
733 uint32_t *out_offset
,
735 unsigned buffer_offset
,
736 unsigned surface_format
,
737 unsigned buffer_size
,
740 void (*emit_null_surface_state
)(struct brw_context
*brw
,
744 uint32_t *out_offset
);
747 * Send the appropriate state packets to configure depth, stencil, and
748 * HiZ buffers (i965+ only)
750 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
751 struct intel_mipmap_tree
*depth_mt
,
752 uint32_t depth_offset
,
753 uint32_t depthbuffer_format
,
754 uint32_t depth_surface_type
,
755 struct intel_mipmap_tree
*stencil_mt
,
756 bool hiz
, bool separate_stencil
,
757 uint32_t width
, uint32_t height
,
758 uint32_t tile_x
, uint32_t tile_y
);
764 drm_intel_context
*hw_ctx
;
766 /** BO for post-sync nonzero writes for gen6 workaround. */
767 drm_intel_bo
*workaround_bo
;
768 uint8_t pipe_controls_since_last_cs_stall
;
771 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
772 * and would need flushing before being used from another cache domain that
773 * isn't coherent with it (i.e. the sampler).
775 struct set
*render_cache
;
778 * Number of resets observed in the system at context creation.
780 * This is tracked in the context so that we can determine that another
781 * reset has occurred.
783 uint32_t reset_count
;
785 struct intel_batchbuffer batch
;
790 uint32_t next_offset
;
794 * Set if rendering has occurred to the drawable's front buffer.
796 * This is used in the DRI2 case to detect that glFlush should also copy
797 * the contents of the fake front buffer to the real front buffer.
799 bool front_buffer_dirty
;
801 /** Framerate throttling: @{ */
802 drm_intel_bo
*throttle_batch
[2];
804 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
805 * frame of rendering to complete. This gives a very precise cap to the
806 * latency between input and output such that rendering never gets more
807 * than a frame behind the user. (With the caveat that we technically are
808 * not using the SwapBuffers itself as a barrier but the first batch
809 * submitted afterwards, which may be immediately prior to the next
812 bool need_swap_throttle
;
814 /** General throttling, not caught by throttling between SwapBuffers */
815 bool need_flush_throttle
;
825 bool always_flush_batch
;
826 bool always_flush_cache
;
827 bool disable_throttling
;
830 driOptionCache optionCache
;
833 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
835 GLenum reduced_primitive
;
838 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
839 * variable is set, this is the flag indicating to do expensive work that
840 * might lead to a perf_debug() call.
844 uint32_t max_gtt_map_object_size
;
856 bool has_separate_stencil
;
857 bool must_use_separate_stencil
;
860 bool has_surface_tile_offset
;
862 bool has_negative_rhw_bug
;
866 bool use_resource_streamer
;
869 * Some versions of Gen hardware don't do centroid interpolation correctly
870 * on unlit pixels, causing incorrect values for derivatives near triangle
871 * edges. Enabling this flag causes the fragment shader to use
872 * non-centroid interpolation for unlit pixels, at the expense of two extra
873 * fragment shader instructions.
875 bool needs_unlit_centroid_workaround
;
879 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
882 enum brw_pipeline last_pipeline
;
884 struct brw_cache cache
;
886 /** IDs for meta stencil blit shader programs. */
887 unsigned meta_stencil_blit_programs
[2];
889 /* Whether a meta-operation is in progress. */
890 bool meta_in_progress
;
892 /* Whether the last depth/stencil packets were both NULL. */
893 bool no_depth_or_stencil
;
895 /* The last PMA stall bits programmed. */
896 uint32_t pma_stall_bits
;
899 /** The value of gl_BaseVertex for the current _mesa_prim. */
903 * Buffer and offset used for GL_ARB_shader_draw_parameters
904 * (for now, only gl_BaseVertex).
906 drm_intel_bo
*draw_params_bo
;
907 uint32_t draw_params_offset
;
912 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
913 * an indirect call, and num_work_groups_offset is valid. Otherwise,
914 * num_work_groups is set based on glDispatchCompute.
916 drm_intel_bo
*num_work_groups_bo
;
917 GLintptr num_work_groups_offset
;
918 const GLuint
*num_work_groups
;
922 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
923 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
925 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
929 /* Summary of size and varying of active arrays, so we can check
930 * for changes to this state:
932 unsigned int min_index
, max_index
;
934 /* Offset from start of vertex buffer so we can avoid redefining
935 * the same VB packed over and over again.
937 unsigned int start_vertex_bias
;
940 * Certain vertex attribute formats aren't natively handled by the
941 * hardware and require special VS code to fix up their values.
943 * These bitfields indicate which workarounds are needed.
945 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
950 * Index buffer for this draw_prims call.
952 * Updates are signaled by BRW_NEW_INDICES.
954 const struct _mesa_index_buffer
*ib
;
956 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
960 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
961 * avoid re-uploading the IB packet over and over if we're actually
962 * referencing the same index buffer.
964 unsigned int start_vertex_offset
;
967 /* Active vertex program:
969 const struct gl_vertex_program
*vertex_program
;
970 const struct gl_geometry_program
*geometry_program
;
971 const struct gl_tess_ctrl_program
*tess_ctrl_program
;
972 const struct gl_tess_eval_program
*tess_eval_program
;
973 const struct gl_fragment_program
*fragment_program
;
974 const struct gl_compute_program
*compute_program
;
977 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
978 * that we don't have to reemit that state every time we change FBOs.
983 * Platform specific constants containing the maximum number of threads
984 * for each pipeline stage.
986 unsigned max_vs_threads
;
987 unsigned max_hs_threads
;
988 unsigned max_ds_threads
;
989 unsigned max_gs_threads
;
990 unsigned max_wm_threads
;
991 unsigned max_cs_threads
;
993 /* BRW_NEW_URB_ALLOCATIONS:
996 GLuint vsize
; /* vertex size plus header in urb registers */
997 GLuint gsize
; /* GS output size in urb registers */
998 GLuint csize
; /* constant buffer size in urb registers */
999 GLuint sfsize
; /* setup data size in urb registers */
1003 GLuint min_vs_entries
; /* Minimum number of VS entries */
1004 GLuint max_vs_entries
; /* Maximum number of VS entries */
1005 GLuint max_hs_entries
; /* Maximum number of HS entries */
1006 GLuint max_ds_entries
; /* Maximum number of DS entries */
1007 GLuint max_gs_entries
; /* Maximum number of GS entries */
1009 GLuint nr_vs_entries
;
1010 GLuint nr_gs_entries
;
1011 GLuint nr_clip_entries
;
1012 GLuint nr_sf_entries
;
1013 GLuint nr_cs_entries
;
1020 GLuint size
; /* Hardware URB size, in KB. */
1022 /* True if the most recently sent _3DSTATE_URB message allocated
1023 * URB space for the GS.
1029 /* BRW_NEW_CURBE_OFFSETS:
1032 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1033 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1041 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1042 * for upload to the CURBE.
1044 drm_intel_bo
*curbe_bo
;
1045 /** Offset within curbe_bo of space for current curbe entry */
1046 GLuint curbe_offset
;
1050 * Layout of vertex data exiting the geometry portion of the pipleine.
1051 * This comes from the last enabled shader stage (GS, DS, or VS).
1053 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1055 struct brw_vue_map vue_map_geom_out
;
1058 struct brw_stage_state base
;
1059 struct brw_vs_prog_data
*prog_data
;
1063 struct brw_stage_state base
;
1064 struct brw_tcs_prog_data
*prog_data
;
1067 * True if the 3DSTATE_HS command most recently emitted to the 3D
1068 * pipeline enabled the HS; false otherwise.
1074 struct brw_stage_state base
;
1075 struct brw_tes_prog_data
*prog_data
;
1078 * True if the 3DSTATE_DS command most recently emitted to the 3D
1079 * pipeline enabled the DS; false otherwise.
1085 struct brw_stage_state base
;
1086 struct brw_gs_prog_data
*prog_data
;
1089 * True if the 3DSTATE_GS command most recently emitted to the 3D
1090 * pipeline enabled the GS; false otherwise.
1096 struct brw_ff_gs_prog_data
*prog_data
;
1099 /** Offset in the program cache to the CLIP program pre-gen6 */
1100 uint32_t prog_offset
;
1101 uint32_t state_offset
;
1103 uint32_t bind_bo_offset
;
1105 * Surface offsets for the binding table. We only need surfaces to
1106 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1107 * need in this case.
1109 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1113 struct brw_clip_prog_data
*prog_data
;
1115 /** Offset in the program cache to the CLIP program pre-gen6 */
1116 uint32_t prog_offset
;
1118 /* Offset in the batch to the CLIP state on pre-gen6. */
1119 uint32_t state_offset
;
1121 /* As of gen6, this is the offset in the batch to the CLIP VP,
1129 struct brw_sf_prog_data
*prog_data
;
1131 /** Offset in the program cache to the CLIP program pre-gen6 */
1132 uint32_t prog_offset
;
1133 uint32_t state_offset
;
1135 bool viewport_transform_enable
;
1139 struct brw_stage_state base
;
1140 struct brw_wm_prog_data
*prog_data
;
1145 * Buffer object used in place of multisampled null render targets on
1146 * Gen6. See brw_emit_null_surface_state().
1148 drm_intel_bo
*multisampled_null_render_target_bo
;
1149 uint32_t fast_clear_op
;
1155 struct brw_stage_state base
;
1156 struct brw_cs_prog_data
*prog_data
;
1159 /* RS hardware binding table */
1162 uint32_t next_offset
;
1166 uint32_t state_offset
;
1167 uint32_t blend_state_offset
;
1168 uint32_t depth_stencil_state_offset
;
1173 struct brw_query_object
*obj
;
1178 enum brw_predicate_state state
;
1183 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1184 const int *statistics_registers
;
1186 /** The number of active monitors using OA counters. */
1190 * A buffer object storing OA counter snapshots taken at the start and
1191 * end of each batch (creating "bookends" around the batch).
1193 drm_intel_bo
*bookend_bo
;
1195 /** The number of snapshots written to bookend_bo. */
1196 int bookend_snapshots
;
1199 * An array of monitors whose results haven't yet been assembled based on
1200 * the data in buffer objects.
1202 * These may be active, or have already ended. However, the results
1203 * have not been requested.
1205 struct brw_perf_monitor_object
**unresolved
;
1206 int unresolved_elements
;
1207 int unresolved_array_size
;
1210 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1211 * the counter which MI_REPORT_PERF_COUNT stores there.
1213 const int *oa_snapshot_layout
;
1215 /** Number of 32-bit entries in a hardware counter snapshot. */
1216 int entries_per_oa_snapshot
;
1219 int num_atoms
[BRW_NUM_PIPELINES
];
1220 const struct brw_tracked_state render_atoms
[61];
1221 const struct brw_tracked_state compute_atoms
[9];
1223 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1227 enum aub_state_struct_type type
;
1229 } *state_batch_list
;
1230 int state_batch_count
;
1232 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1233 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1235 /* Interpolation modes, one byte per vue slot.
1236 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1238 struct interpolation_mode_map interpolation_mode
;
1240 /* PrimitiveRestart */
1243 bool enable_cut_index
;
1246 /** Computed depth/stencil/hiz state from the current attached
1247 * renderbuffers, valid only during the drawing state upload loop after
1248 * brw_workaround_depthstencil_alignment().
1251 struct intel_mipmap_tree
*depth_mt
;
1252 struct intel_mipmap_tree
*stencil_mt
;
1254 /* Inter-tile (page-aligned) byte offsets. */
1255 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1256 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1257 uint32_t tile_x
, tile_y
;
1260 uint32_t num_instances
;
1267 enum shader_time_shader_type
*types
;
1268 struct shader_times
*cumulative
;
1274 struct brw_fast_clear_state
*fast_clear_state
;
1276 __DRIcontext
*driContext
;
1277 struct intel_screen
*intelScreen
;
1280 /*======================================================================
1283 void brwInitVtbl( struct brw_context
*brw
);
1286 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1288 /*======================================================================
1291 extern const char *const brw_vendor_string
;
1293 extern const char *brw_get_renderer_string(unsigned deviceID
);
1296 DRI_CONF_BO_REUSE_DISABLED
,
1297 DRI_CONF_BO_REUSE_ALL
1300 void intel_update_renderbuffers(__DRIcontext
*context
,
1301 __DRIdrawable
*drawable
);
1302 void intel_prepare_render(struct brw_context
*brw
);
1304 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1305 __DRIdrawable
*drawable
);
1307 GLboolean
brwCreateContext(gl_api api
,
1308 const struct gl_config
*mesaVis
,
1309 __DRIcontext
*driContextPriv
,
1310 unsigned major_version
,
1311 unsigned minor_version
,
1315 void *sharedContextPrivate
);
1317 /*======================================================================
1320 GLuint
brw_get_rb_for_slice(struct brw_context
*brw
,
1321 struct intel_mipmap_tree
*mt
,
1322 unsigned level
, unsigned layer
, bool flat
);
1324 void brw_meta_updownsample(struct brw_context
*brw
,
1325 struct intel_mipmap_tree
*src
,
1326 struct intel_mipmap_tree
*dst
);
1328 void brw_meta_fbo_stencil_blit(struct brw_context
*brw
,
1329 struct gl_framebuffer
*read_fb
,
1330 struct gl_framebuffer
*draw_fb
,
1331 GLfloat srcX0
, GLfloat srcY0
,
1332 GLfloat srcX1
, GLfloat srcY1
,
1333 GLfloat dstX0
, GLfloat dstY0
,
1334 GLfloat dstX1
, GLfloat dstY1
);
1336 void brw_meta_stencil_updownsample(struct brw_context
*brw
,
1337 struct intel_mipmap_tree
*src
,
1338 struct intel_mipmap_tree
*dst
);
1340 bool brw_meta_fast_clear(struct brw_context
*brw
,
1341 struct gl_framebuffer
*fb
,
1343 bool partial_clear
);
1346 brw_meta_resolve_color(struct brw_context
*brw
,
1347 struct intel_mipmap_tree
*mt
);
1349 brw_meta_fast_clear_free(struct brw_context
*brw
);
1352 /*======================================================================
1355 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1356 uint32_t depth_level
,
1357 uint32_t depth_layer
,
1358 struct intel_mipmap_tree
*stencil_mt
,
1359 uint32_t *out_tile_mask_x
,
1360 uint32_t *out_tile_mask_y
);
1361 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1362 GLbitfield clear_mask
);
1364 /* brw_object_purgeable.c */
1365 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1367 /*======================================================================
1370 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1371 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1372 void brw_emit_query_begin(struct brw_context
*brw
);
1373 void brw_emit_query_end(struct brw_context
*brw
);
1375 /** gen6_queryobj.c */
1376 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1377 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1378 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1379 void brw_store_register_mem64(struct brw_context
*brw
,
1380 drm_intel_bo
*bo
, uint32_t reg
, int idx
);
1382 /** brw_conditional_render.c */
1383 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1384 bool brw_check_conditional_render(struct brw_context
*brw
);
1386 /** intel_batchbuffer.c */
1387 void brw_load_register_mem(struct brw_context
*brw
,
1390 uint32_t read_domains
, uint32_t write_domain
,
1392 void brw_load_register_mem64(struct brw_context
*brw
,
1395 uint32_t read_domains
, uint32_t write_domain
,
1398 /*======================================================================
1401 void brw_debug_batch(struct brw_context
*brw
);
1402 void brw_annotate_aub(struct brw_context
*brw
);
1404 /*======================================================================
1407 void brw_validate_textures( struct brw_context
*brw
);
1410 /*======================================================================
1414 key_debug(struct brw_context
*brw
, const char *name
, int a
, int b
)
1417 perf_debug(" %s %d->%d\n", name
, a
, b
);
1423 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1425 /* Per-thread scratch space is a power-of-two multiple of 1KB. */
1427 brw_get_scratch_size(int size
)
1429 return util_next_power_of_two(size
| 1023);
1431 void brw_get_scratch_bo(struct brw_context
*brw
,
1432 drm_intel_bo
**scratch_bo
, int size
);
1433 void brw_init_shader_time(struct brw_context
*brw
);
1434 int brw_get_shader_time_index(struct brw_context
*brw
,
1435 struct gl_shader_program
*shader_prog
,
1436 struct gl_program
*prog
,
1437 enum shader_time_shader_type type
);
1438 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1439 void brw_destroy_shader_time(struct brw_context
*brw
);
1443 void brw_upload_urb_fence(struct brw_context
*brw
);
1447 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1449 /* brw_fs_reg_allocate.cpp
1451 void brw_fs_alloc_reg_sets(struct brw_compiler
*compiler
);
1453 /* brw_vec4_reg_allocate.cpp */
1454 void brw_vec4_alloc_reg_set(struct brw_compiler
*compiler
);
1457 int brw_disassemble_inst(FILE *file
, const struct brw_device_info
*devinfo
,
1458 struct brw_inst
*inst
, bool is_compacted
);
1461 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1463 /* brw_draw_upload.c */
1464 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1465 const struct gl_client_array
*glarray
);
1467 static inline unsigned
1468 brw_get_index_type(GLenum type
)
1470 assert((type
== GL_UNSIGNED_BYTE
)
1471 || (type
== GL_UNSIGNED_SHORT
)
1472 || (type
== GL_UNSIGNED_INT
));
1474 /* The possible values for type are GL_UNSIGNED_BYTE (0x1401),
1475 * GL_UNSIGNED_SHORT (0x1403), and GL_UNSIGNED_INT (0x1405) which we want
1476 * to map to scale factors of 0, 1, and 2, respectively. These scale
1477 * factors are then left-shfited by 8 to be in the correct position in the
1478 * CMD_INDEX_BUFFER packet.
1480 * Subtracting 0x1401 gives 0, 2, and 4. Shifting left by 7 afterwards
1481 * gives 0x00000000, 0x00000100, and 0x00000200. These just happen to be
1482 * the values the need to be written in the CMD_INDEX_BUFFER packet.
1484 return (type
- 0x1401) << 7;
1487 void brw_prepare_vertices(struct brw_context
*brw
);
1489 /* brw_wm_surface_state.c */
1490 void brw_init_surface_formats(struct brw_context
*brw
);
1491 void brw_create_constant_surface(struct brw_context
*brw
,
1495 uint32_t *out_offset
,
1497 void brw_create_buffer_surface(struct brw_context
*brw
,
1501 uint32_t *out_offset
,
1503 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1505 uint32_t *surf_offset
);
1507 brw_update_sol_surface(struct brw_context
*brw
,
1508 struct gl_buffer_object
*buffer_obj
,
1509 uint32_t *out_offset
, unsigned num_vector_components
,
1510 unsigned stride_dwords
, unsigned offset_dwords
);
1511 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1512 struct gl_shader
*shader
,
1513 struct brw_stage_state
*stage_state
,
1514 struct brw_stage_prog_data
*prog_data
,
1516 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1517 struct gl_shader
*shader
,
1518 struct brw_stage_state
*stage_state
,
1519 struct brw_stage_prog_data
*prog_data
);
1520 void brw_upload_image_surfaces(struct brw_context
*brw
,
1521 struct gl_shader
*shader
,
1522 struct brw_stage_state
*stage_state
,
1523 struct brw_stage_prog_data
*prog_data
);
1525 /* brw_surface_formats.c */
1526 bool brw_render_target_supported(struct brw_context
*brw
,
1527 struct gl_renderbuffer
*rb
);
1528 bool brw_losslessly_compressible_format(struct brw_context
*brw
,
1529 uint32_t brw_format
);
1530 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1531 mesa_format
brw_lower_mesa_image_format(const struct brw_device_info
*devinfo
,
1532 mesa_format format
);
1534 /* brw_performance_monitor.c */
1535 void brw_init_performance_monitors(struct brw_context
*brw
);
1536 void brw_dump_perf_monitors(struct brw_context
*brw
);
1537 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1538 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1540 /* intel_buffer_objects.c */
1541 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1542 const char *bo_name
);
1543 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1544 const char *bo_name
);
1546 /* intel_extensions.c */
1547 extern void intelInitExtensions(struct gl_context
*ctx
);
1550 extern int intel_translate_shadow_compare_func(GLenum func
);
1551 extern int intel_translate_compare_func(GLenum func
);
1552 extern int intel_translate_stencil_op(GLenum op
);
1553 extern int intel_translate_logic_op(GLenum opcode
);
1555 /* intel_syncobj.c */
1556 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1559 struct gl_transform_feedback_object
*
1560 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1562 brw_delete_transform_feedback(struct gl_context
*ctx
,
1563 struct gl_transform_feedback_object
*obj
);
1565 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1566 struct gl_transform_feedback_object
*obj
);
1568 brw_end_transform_feedback(struct gl_context
*ctx
,
1569 struct gl_transform_feedback_object
*obj
);
1571 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1572 struct gl_transform_feedback_object
*obj
,
1575 /* gen7_sol_state.c */
1577 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1578 struct gl_transform_feedback_object
*obj
);
1580 gen7_end_transform_feedback(struct gl_context
*ctx
,
1581 struct gl_transform_feedback_object
*obj
);
1583 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1584 struct gl_transform_feedback_object
*obj
);
1586 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1587 struct gl_transform_feedback_object
*obj
);
1589 /* brw_blorp_blit.cpp */
1591 brw_blorp_framebuffer(struct brw_context
*brw
,
1592 struct gl_framebuffer
*readFb
,
1593 struct gl_framebuffer
*drawFb
,
1594 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1595 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1596 GLbitfield mask
, GLenum filter
);
1599 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1600 struct gl_renderbuffer
*src_rb
,
1601 struct gl_texture_image
*dst_image
,
1603 int srcX0
, int srcY0
,
1604 int dstX0
, int dstY0
,
1605 int width
, int height
);
1607 /* gen6_multisample_state.c */
1609 gen6_determine_sample_mask(struct brw_context
*brw
);
1612 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1613 unsigned num_samples
);
1615 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1617 gen6_get_sample_position(struct gl_context
*ctx
,
1618 struct gl_framebuffer
*fb
,
1622 gen6_set_sample_maps(struct gl_context
*ctx
);
1624 /* gen8_multisample_state.c */
1625 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1626 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1630 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1631 unsigned gs_size
, unsigned fs_size
);
1634 gen7_emit_urb_state(struct brw_context
*brw
,
1635 unsigned nr_vs_entries
, unsigned vs_size
,
1636 unsigned vs_start
, unsigned nr_gs_entries
,
1637 unsigned gs_size
, unsigned gs_start
);
1642 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1646 brw_init_compute_functions(struct dd_function_table
*functions
);
1648 /*======================================================================
1649 * Inline conversion functions. These are better-typed than the
1650 * macros used previously:
1652 static inline struct brw_context
*
1653 brw_context( struct gl_context
*ctx
)
1655 return (struct brw_context
*)ctx
;
1658 static inline struct brw_vertex_program
*
1659 brw_vertex_program(struct gl_vertex_program
*p
)
1661 return (struct brw_vertex_program
*) p
;
1664 static inline const struct brw_vertex_program
*
1665 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1667 return (const struct brw_vertex_program
*) p
;
1670 static inline struct brw_geometry_program
*
1671 brw_geometry_program(struct gl_geometry_program
*p
)
1673 return (struct brw_geometry_program
*) p
;
1676 static inline struct brw_fragment_program
*
1677 brw_fragment_program(struct gl_fragment_program
*p
)
1679 return (struct brw_fragment_program
*) p
;
1682 static inline const struct brw_fragment_program
*
1683 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1685 return (const struct brw_fragment_program
*) p
;
1688 static inline struct brw_compute_program
*
1689 brw_compute_program(struct gl_compute_program
*p
)
1691 return (struct brw_compute_program
*) p
;
1695 * Pre-gen6, the register file of the EUs was shared between threads,
1696 * and each thread used some subset allocated on a 16-register block
1697 * granularity. The unit states wanted these block counts.
1700 brw_register_blocks(int reg_count
)
1702 return ALIGN(reg_count
, 16) / 16 - 1;
1705 static inline uint32_t
1706 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1707 uint32_t prog_offset
)
1709 if (brw
->gen
>= 5) {
1710 /* Using state base address. */
1714 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1718 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1720 return brw
->cache
.bo
->offset64
+ prog_offset
;
1723 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1724 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1725 struct exec_list
*instructions
);
1726 bool brw_do_lower_unnormalized_offset(struct exec_list
*instructions
);
1728 struct opcode_desc
{
1734 extern const struct opcode_desc opcode_descs
[128];
1735 extern const char * const conditional_modifier
[16];
1736 extern const char *const pred_ctrl_align16
[16];
1739 brw_emit_depthbuffer(struct brw_context
*brw
);
1742 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1743 struct intel_mipmap_tree
*depth_mt
,
1744 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1745 uint32_t depth_surface_type
,
1746 struct intel_mipmap_tree
*stencil_mt
,
1747 bool hiz
, bool separate_stencil
,
1748 uint32_t width
, uint32_t height
,
1749 uint32_t tile_x
, uint32_t tile_y
);
1752 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1753 struct intel_mipmap_tree
*depth_mt
,
1754 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1755 uint32_t depth_surface_type
,
1756 struct intel_mipmap_tree
*stencil_mt
,
1757 bool hiz
, bool separate_stencil
,
1758 uint32_t width
, uint32_t height
,
1759 uint32_t tile_x
, uint32_t tile_y
);
1762 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1763 struct intel_mipmap_tree
*depth_mt
,
1764 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1765 uint32_t depth_surface_type
,
1766 struct intel_mipmap_tree
*stencil_mt
,
1767 bool hiz
, bool separate_stencil
,
1768 uint32_t width
, uint32_t height
,
1769 uint32_t tile_x
, uint32_t tile_y
);
1771 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1772 struct intel_mipmap_tree
*depth_mt
,
1773 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1774 uint32_t depth_surface_type
,
1775 struct intel_mipmap_tree
*stencil_mt
,
1776 bool hiz
, bool separate_stencil
,
1777 uint32_t width
, uint32_t height
,
1778 uint32_t tile_x
, uint32_t tile_y
);
1780 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1781 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);
1783 uint32_t get_hw_prim_for_gl_prim(int mode
);
1786 gen6_upload_push_constants(struct brw_context
*brw
,
1787 const struct gl_program
*prog
,
1788 const struct brw_stage_prog_data
*prog_data
,
1789 struct brw_stage_state
*stage_state
,
1790 enum aub_state_struct_type type
);
1793 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
1794 const struct intel_mipmap_tree
*mt
);
1796 /* brw_pipe_control.c */
1797 int brw_init_pipe_control(struct brw_context
*brw
,
1798 const struct brw_device_info
*info
);
1799 void brw_fini_pipe_control(struct brw_context
*brw
);
1801 void brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
);
1802 void brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
1803 drm_intel_bo
*bo
, uint32_t offset
,
1804 uint32_t imm_lower
, uint32_t imm_upper
);
1805 void brw_emit_mi_flush(struct brw_context
*brw
);
1806 void brw_emit_post_sync_nonzero_flush(struct brw_context
*brw
);
1807 void brw_emit_depth_stall_flushes(struct brw_context
*brw
);
1808 void gen7_emit_vs_workaround_flush(struct brw_context
*brw
);
1809 void gen7_emit_cs_stall_flush(struct brw_context
*brw
);