2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
38 #include "main/imports.h"
39 #include "main/macros.h"
41 #include "main/mtypes.h"
42 #include "brw_structs.h"
43 #include "intel_aub.h"
44 #include "program/prog_parameter.h"
48 /* Evil hack for using libdrm in a c++ compiler. */
53 #include <intel_bufmgr.h>
63 #include "intel_debug.h"
64 #include "intel_screen.h"
65 #include "intel_tex_obj.h"
66 #include "intel_resolve_map.h"
70 * URB - uniform resource buffer. A mid-sized buffer which is
71 * partitioned between the fixed function units and used for passing
72 * values (vertices, primitives, constants) between them.
74 * CURBE - constant URB entry. An urb region (entry) used to hold
75 * constant values which the fixed function units can be instructed to
76 * preload into the GRF when spawning a thread.
78 * VUE - vertex URB entry. An urb entry holding a vertex and usually
79 * a vertex header. The header contains control information and
80 * things like primitive type, Begin/end flags and clip codes.
82 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
83 * unit holding rasterization and interpolation parameters.
85 * GRF - general register file. One of several register files
86 * addressable by programmed threads. The inputs (r0, payload, curbe,
87 * urb) of the thread are preloaded to this area before the thread is
88 * spawned. The registers are individually 8 dwords wide and suitable
89 * for general usage. Registers holding thread input values are not
90 * special and may be overwritten.
92 * MRF - message register file. Threads communicate (and terminate)
93 * by sending messages. Message parameters are placed in contiguous
94 * MRF registers. All program output is via these messages. URB
95 * entries are populated by sending a message to the shared URB
96 * function containing the new data, together with a control word,
97 * often an unmodified copy of R0.
99 * R0 - GRF register 0. Typically holds control information used when
100 * sending messages to other threads.
102 * EU or GEN4 EU: The name of the programmable subsystem of the
103 * i965 hardware. Threads are executed by the EU, the registers
104 * described above are part of the EU architecture.
106 * Fixed function units:
108 * CS - Command streamer. Notional first unit, little software
109 * interaction. Holds the URB entries used for constant data, ie the
112 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
113 * this unit is responsible for pulling vertices out of vertex buffers
114 * in vram and injecting them into the processing pipe as VUEs. If
115 * enabled, it first passes them to a VS thread which is a good place
116 * for the driver to implement any active vertex shader.
118 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
119 * enabled, incoming strips etc are passed to GS threads in individual
120 * line/triangle/point units. The GS thread may perform arbitary
121 * computation and emit whatever primtives with whatever vertices it
122 * chooses. This makes GS an excellent place to implement GL's
123 * unfilled polygon modes, though of course it is capable of much
124 * more. Additionally, GS is used to translate away primitives not
125 * handled by latter units, including Quads and Lineloops.
127 * CS - Clipper. Mesa's clipping algorithms are imported to run on
128 * this unit. The fixed function part performs cliptesting against
129 * the 6 fixed clipplanes and makes descisions on whether or not the
130 * incoming primitive needs to be passed to a thread for clipping.
131 * User clip planes are handled via cooperation with the VS thread.
133 * SF - Strips Fans or Setup: Triangles are prepared for
134 * rasterization. Interpolation coefficients are calculated.
135 * Flatshading and two-side lighting usually performed here.
137 * WM - Windower. Interpolation of vertex attributes performed here.
138 * Fragment shader implemented here. SIMD aspects of EU taken full
139 * advantage of, as pixels are processed in blocks of 16.
141 * CC - Color Calculator. No EU threads associated with this unit.
142 * Handles blending and (presumably) depth and stencil testing.
147 struct brw_vs_prog_key
;
148 struct brw_vue_prog_key
;
149 struct brw_wm_prog_key
;
150 struct brw_wm_prog_data
;
151 struct brw_cs_prog_key
;
152 struct brw_cs_prog_data
;
156 BRW_COMPUTE_PIPELINE
,
163 BRW_CACHE_BLORP_BLIT_PROG
,
166 BRW_CACHE_FF_GS_PROG
,
175 /* brw_cache_ids must come first - see brw_state_cache.c */
176 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
177 BRW_STATE_FRAGMENT_PROGRAM
,
178 BRW_STATE_GEOMETRY_PROGRAM
,
179 BRW_STATE_VERTEX_PROGRAM
,
180 BRW_STATE_CURBE_OFFSETS
,
181 BRW_STATE_REDUCED_PRIMITIVE
,
186 BRW_STATE_VS_BINDING_TABLE
,
187 BRW_STATE_GS_BINDING_TABLE
,
188 BRW_STATE_PS_BINDING_TABLE
,
192 BRW_STATE_INDEX_BUFFER
,
193 BRW_STATE_VS_CONSTBUF
,
194 BRW_STATE_GS_CONSTBUF
,
195 BRW_STATE_PROGRAM_CACHE
,
196 BRW_STATE_STATE_BASE_ADDRESS
,
197 BRW_STATE_VUE_MAP_GEOM_OUT
,
198 BRW_STATE_TRANSFORM_FEEDBACK
,
199 BRW_STATE_RASTERIZER_DISCARD
,
201 BRW_STATE_UNIFORM_BUFFER
,
202 BRW_STATE_ATOMIC_BUFFER
,
203 BRW_STATE_IMAGE_UNITS
,
204 BRW_STATE_META_IN_PROGRESS
,
205 BRW_STATE_INTERPOLATION_MAP
,
206 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
207 BRW_STATE_NUM_SAMPLES
,
208 BRW_STATE_TEXTURE_BUFFER
,
209 BRW_STATE_GEN4_UNIT_STATE
,
213 BRW_STATE_SAMPLER_STATE_TABLE
,
214 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
215 BRW_STATE_COMPUTE_PROGRAM
,
220 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
222 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
223 * When the currently bound shader program differs from the previous draw
224 * call, these will be flagged. They cover brw->{stage}_program and
225 * ctx->{Stage}Program->_Current.
227 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
228 * driver perspective. Even if the same shader is bound at the API level,
229 * we may need to switch between multiple versions of that shader to handle
230 * changes in non-orthagonal state.
232 * Additionally, multiple shader programs may have identical vertex shaders
233 * (for example), or compile down to the same code in the backend. We combine
234 * those into a single program cache entry.
236 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
237 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
239 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
240 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
241 * use the normal state upload paths), but the cache is still used. To avoid
242 * polluting the brw_state_cache code with special cases, we retain the dirty
243 * bit for now. It should eventually be removed.
245 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_BLIT_PROG)
246 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
247 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
248 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
249 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
250 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
251 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
252 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
253 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
254 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
255 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
256 #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
257 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
258 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
259 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
260 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
261 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
262 #define BRW_NEW_VS_BINDING_TABLE (1ull << BRW_STATE_VS_BINDING_TABLE)
263 #define BRW_NEW_GS_BINDING_TABLE (1ull << BRW_STATE_GS_BINDING_TABLE)
264 #define BRW_NEW_PS_BINDING_TABLE (1ull << BRW_STATE_PS_BINDING_TABLE)
265 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
266 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
268 * Used for any batch entry with a relocated pointer that will be used
269 * by any 3D rendering.
271 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
272 /** \see brw.state.depth_region */
273 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
274 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
275 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
276 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
277 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
278 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
279 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
280 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
281 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
282 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
283 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
284 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
285 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
286 #define BRW_NEW_INTERPOLATION_MAP (1ull << BRW_STATE_INTERPOLATION_MAP)
287 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
288 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
289 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
290 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
291 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
292 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
293 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
294 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
295 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
296 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
298 struct brw_state_flags
{
299 /** State update flags signalled by mesa internals */
302 * State update flags signalled as the result of brw_tracked_state updates
307 /** Subclass of Mesa vertex program */
308 struct brw_vertex_program
{
309 struct gl_vertex_program program
;
314 /** Subclass of Mesa geometry program */
315 struct brw_geometry_program
{
316 struct gl_geometry_program program
;
317 unsigned id
; /**< serial no. to identify geom progs, never re-used */
321 /** Subclass of Mesa fragment program */
322 struct brw_fragment_program
{
323 struct gl_fragment_program program
;
324 GLuint id
; /**< serial no. to identify frag progs, never re-used */
328 /** Subclass of Mesa compute program */
329 struct brw_compute_program
{
330 struct gl_compute_program program
;
331 unsigned id
; /**< serial no. to identify compute progs, never re-used */
336 struct gl_shader base
;
341 /* Note: If adding fields that need anything besides a normal memcmp() for
342 * comparing them, be sure to go fix brw_stage_prog_data_compare().
344 struct brw_stage_prog_data
{
346 /** size of our binding table. */
350 * surface indices for the various groups of surfaces
352 uint32_t pull_constants_start
;
353 uint32_t texture_start
;
354 uint32_t gather_texture_start
;
357 uint32_t image_start
;
358 uint32_t shader_time_start
;
362 GLuint nr_params
; /**< number of float params/constants */
363 GLuint nr_pull_params
;
364 unsigned nr_image_params
;
366 unsigned curb_read_length
;
367 unsigned total_scratch
;
370 * Register where the thread expects to find input data from the URB
371 * (typically uniforms, followed by vertex or fragment attributes).
373 unsigned dispatch_grf_start_reg
;
375 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
377 /* Pointers to tracked values (only valid once
378 * _mesa_load_state_parameters has been called at runtime).
380 * These must be the last fields of the struct (see
381 * brw_stage_prog_data_compare()).
383 const gl_constant_value
**param
;
384 const gl_constant_value
**pull_param
;
387 * Image metadata passed to the shader as uniforms. This is deliberately
388 * ignored by brw_stage_prog_data_compare() because its contents don't have
389 * any influence on program compilation.
391 struct brw_image_param
*image_param
;
395 * Image metadata structure as laid out in the shader parameter
396 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
397 * able to use them. That's okay because the padding and any unused
398 * entries [most of them except when we're doing untyped surface
399 * access] will be removed by the uniform packing pass.
401 #define BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET 0
402 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 4
403 #define BRW_IMAGE_PARAM_SIZE_OFFSET 8
404 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 12
405 #define BRW_IMAGE_PARAM_TILING_OFFSET 16
406 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 20
407 #define BRW_IMAGE_PARAM_SIZE 24
409 struct brw_image_param
{
410 /** Surface binding table index. */
411 uint32_t surface_idx
;
413 /** Offset applied to the X and Y surface coordinates. */
416 /** Surface X, Y and Z dimensions. */
419 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
420 * pixels, vertical slice stride in pixels.
424 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
428 * Right shift to apply for bit 6 address swizzling. Two different
429 * swizzles can be specified and will be applied one after the other. The
430 * resulting address will be:
432 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
433 * (addr >> swizzling[1])))
435 * Use \c 0xff if any of the swizzles is not required.
437 uint32_t swizzling
[2];
440 /* Data about a particular attempt to compile a program. Note that
441 * there can be many of these, each in a different GL state
442 * corresponding to a different brw_wm_prog_key struct, with different
445 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
448 struct brw_wm_prog_data
{
449 struct brw_stage_prog_data base
;
451 GLuint num_varying_inputs
;
453 GLuint dispatch_grf_start_reg_16
;
455 GLuint reg_blocks_16
;
459 * surface indices the WM-specific surfaces
461 uint32_t render_target_start
;
465 uint8_t computed_depth_mode
;
467 bool early_fragment_tests
;
470 bool uses_pos_offset
;
474 uint32_t prog_offset_16
;
477 * Mask of which interpolation modes are required by the fragment shader.
478 * Used in hardware setup on gen6+.
480 uint32_t barycentric_interp_modes
;
483 * Map from gl_varying_slot to the position within the FS setup data
484 * payload where the varying's attribute vertex deltas should be delivered.
485 * For varying slots that are not used by the FS, the value is -1.
487 int urb_setup
[VARYING_SLOT_MAX
];
490 /* Note: brw_cs_prog_data_compare() must be updated when adding fields to this
493 struct brw_cs_prog_data
{
494 struct brw_stage_prog_data base
;
496 GLuint dispatch_grf_start_reg_16
;
497 unsigned local_size
[3];
503 * surface indices the CS-specific surfaces
505 uint32_t work_groups_start
;
511 * Enum representing the i965-specific vertex results that don't correspond
512 * exactly to any element of gl_varying_slot. The values of this enum are
513 * assigned such that they don't conflict with gl_varying_slot.
517 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
518 BRW_VARYING_SLOT_PAD
,
520 * Technically this is not a varying but just a placeholder that
521 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
522 * builtin variable to be compiled correctly. see compile_sf_prog() for
525 BRW_VARYING_SLOT_PNTC
,
526 BRW_VARYING_SLOT_COUNT
531 * Data structure recording the relationship between the gl_varying_slot enum
532 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
533 * single octaword within the VUE (128 bits).
535 * Note that each BRW register contains 256 bits (2 octawords), so when
536 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
537 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
538 * in a vertex shader), each register corresponds to a single VUE slot, since
539 * it contains data for two separate vertices.
543 * Bitfield representing all varying slots that are (a) stored in this VUE
544 * map, and (b) actually written by the shader. Does not include any of
545 * the additional varying slots defined in brw_varying_slot.
547 GLbitfield64 slots_valid
;
550 * Is this VUE map for a separate shader pipeline?
552 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
553 * without the linker having a chance to dead code eliminate unused varyings.
555 * This means that we have to use a fixed slot layout, based on the output's
556 * location field, rather than assigning slots in a compact contiguous block.
561 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
562 * not stored in a slot (because they are not written, or because
563 * additional processing is applied before storing them in the VUE), the
566 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
569 * Map from VUE slot to gl_varying_slot value. For slots that do not
570 * directly correspond to a gl_varying_slot, the value comes from
573 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
574 * simplifies code that uses the value stored in slot_to_varying to
575 * create a bit mask).
577 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
580 * Total number of VUE slots in use
586 * Convert a VUE slot number into a byte offset within the VUE.
588 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
594 * Convert a vertex output (brw_varying_slot) into a byte offset within the
597 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
600 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
603 void brw_compute_vue_map(const struct brw_device_info
*devinfo
,
604 struct brw_vue_map
*vue_map
,
605 GLbitfield64 slots_valid
,
606 bool separate_shader
);
610 * Bitmask indicating which fragment shader inputs represent varyings (and
611 * hence have to be delivered to the fragment shader by the SF/SBE stage).
613 #define BRW_FS_VARYING_INPUT_MASK \
614 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
615 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
619 * Mapping of VUE map slots to interpolation modes.
621 struct interpolation_mode_map
{
622 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
625 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
627 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
628 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
634 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
636 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
637 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
644 struct brw_sf_prog_data
{
645 GLuint urb_read_length
;
648 /* Each vertex may have upto 12 attributes, 4 components each,
649 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
652 * Actually we use 4 for each, so call it 12 rows.
654 GLuint urb_entry_size
;
659 * We always program SF to start reading at an offset of 1 (2 varying slots)
660 * from the start of the vertex URB entry. This causes it to skip:
661 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
662 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
664 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
667 struct brw_clip_prog_data
{
668 GLuint curb_read_length
; /* user planes? */
670 GLuint urb_read_length
;
674 struct brw_ff_gs_prog_data
{
675 GLuint urb_read_length
;
679 * Gen6 transform feedback: Amount by which the streaming vertex buffer
680 * indices should be incremented each time the GS is invoked.
682 unsigned svbi_postincrement_value
;
685 enum shader_dispatch_mode
{
686 DISPATCH_MODE_4X1_SINGLE
= 0,
687 DISPATCH_MODE_4X2_DUAL_INSTANCE
= 1,
688 DISPATCH_MODE_4X2_DUAL_OBJECT
= 2,
689 DISPATCH_MODE_SIMD8
= 3,
692 /* Note: brw_vue_prog_data_compare() must be updated when adding fields to
695 struct brw_vue_prog_data
{
696 struct brw_stage_prog_data base
;
697 struct brw_vue_map vue_map
;
699 GLuint urb_read_length
;
702 /* Used for calculating urb partitions. In the VS, this is the size of the
703 * URB entry used for both input and output to the thread. In the GS, this
704 * is the size of the URB entry used for output.
706 GLuint urb_entry_size
;
708 enum shader_dispatch_mode dispatch_mode
;
712 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
715 struct brw_vs_prog_data
{
716 struct brw_vue_prog_data base
;
718 GLbitfield64 inputs_read
;
721 bool uses_instanceid
;
724 /** Number of texture sampler units */
725 #define BRW_MAX_TEX_UNIT 32
727 /** Max number of render targets in a shader */
728 #define BRW_MAX_DRAW_BUFFERS 8
730 /** Max number of atomic counter buffer objects in a shader */
731 #define BRW_MAX_ABO 16
733 /** Max number of image uniforms in a shader */
734 #define BRW_MAX_IMAGES 32
737 * Max number of binding table entries used for stream output.
739 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
740 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
742 * On Gen6, the size of transform feedback data is limited not by the number
743 * of components but by the number of binding table entries we set aside. We
744 * use one binding table entry for a float, one entry for a vector, and one
745 * entry per matrix column. Since the only way we can communicate our
746 * transform feedback capabilities to the client is via
747 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
748 * worst case, in which all the varyings are floats, so we use up one binding
749 * table entry per component. Therefore we need to set aside at least 64
750 * binding table entries for use by transform feedback.
752 * Note: since we don't currently pack varyings, it is currently impossible
753 * for the client to actually use up all of these binding table entries--if
754 * all of their varyings were floats, they would run out of varying slots and
755 * fail to link. But that's a bug, so it seems prudent to go ahead and
756 * allocate the number of binding table entries we will need once the bug is
759 #define BRW_MAX_SOL_BINDINGS 64
761 /** Maximum number of actual buffers used for stream output */
762 #define BRW_MAX_SOL_BUFFERS 4
764 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
765 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
769 2 + /* shader time, pull constants */ \
770 1 /* cs num work groups */)
772 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
774 /* Note: brw_gs_prog_data_compare() must be updated when adding fields to
777 struct brw_gs_prog_data
779 struct brw_vue_prog_data base
;
782 * Size of an output vertex, measured in HWORDS (32 bytes).
784 unsigned output_vertex_size_hwords
;
786 unsigned output_topology
;
789 * Size of the control data (cut bits or StreamID bits), in hwords (32
790 * bytes). 0 if there is no control data.
792 unsigned control_data_header_size_hwords
;
795 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
796 * if the control data is StreamID bits, or
797 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
798 * Ignored if control_data_header_size is 0.
800 unsigned control_data_format
;
802 bool include_primitive_id
;
805 * The number of vertices emitted, if constant - otherwise -1.
807 int static_vertex_count
;
812 * Gen6 transform feedback enabled flag.
814 bool gen6_xfb_enabled
;
817 * Gen6: Provoking vertex convention for odd-numbered triangles
823 * Gen6: Number of varyings that are output to transform feedback.
825 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
828 * Gen6: Map from the index of a transform feedback binding table entry to the
829 * gl_varying_slot that should be streamed out through that binding table
832 unsigned char transform_feedback_bindings
[BRW_MAX_SOL_BINDINGS
];
835 * Gen6: Map from the index of a transform feedback binding table entry to the
836 * swizzles that should be used when streaming out data through that
837 * binding table entry.
839 unsigned char transform_feedback_swizzles
[BRW_MAX_SOL_BINDINGS
];
843 * Stride in bytes between shader_time entries.
845 * We separate entries by a cacheline to reduce traffic between EUs writing to
848 #define SHADER_TIME_STRIDE 64
850 struct brw_cache_item
{
852 * Effectively part of the key, cache_id identifies what kind of state
853 * buffer is involved, and also which dirty flag should set.
855 enum brw_cache_id cache_id
;
856 /** 32-bit hash of the key data */
858 GLuint key_size
; /* for variable-sized keys */
865 struct brw_cache_item
*next
;
869 typedef bool (*cache_aux_compare_func
)(const void *a
, const void *b
);
870 typedef void (*cache_aux_free_func
)(const void *aux
);
873 struct brw_context
*brw
;
875 struct brw_cache_item
**items
;
877 GLuint size
, n_items
;
879 uint32_t next_offset
;
883 * Optional functions used in determining whether the prog_data for a new
884 * cache item matches an existing cache item (in case there's relevant data
885 * outside of the prog_data). If NULL, a plain memcmp is done.
887 cache_aux_compare_func aux_compare
[BRW_MAX_CACHE
];
888 /** Optional functions for freeing other pointers attached to a prog_data. */
889 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
893 /* Considered adding a member to this struct to document which flags
894 * an update might raise so that ordering of the state atoms can be
895 * checked or derived at runtime. Dropped the idea in favor of having
896 * a debug mode where the state is monitored for flags which are
897 * raised that have already been tested against.
899 struct brw_tracked_state
{
900 struct brw_state_flags dirty
;
901 void (*emit
)( struct brw_context
*brw
);
904 enum shader_time_shader_type
{
913 struct brw_vertex_buffer
{
914 /** Buffer object containing the uploaded vertex data */
917 /** Byte stride between elements in the uploaded array */
921 struct brw_vertex_element
{
922 const struct gl_client_array
*glarray
;
926 /** Offset of the first element within the buffer object */
930 struct brw_query_object
{
931 struct gl_query_object Base
;
933 /** Last query BO associated with this query. */
936 /** Last index in bo with query data for this object. */
939 /** True if we know the batch has been flushed since we ended the query. */
949 struct intel_batchbuffer
{
950 /** Current batchbuffer being queued up. */
952 /** Last BO submitted to the hardware. Used for glFinish(). */
953 drm_intel_bo
*last_bo
;
956 uint16_t emit
, total
;
958 uint16_t reserved_space
;
962 #define BATCH_SZ (8192*sizeof(uint32_t))
964 uint32_t state_batch_offset
;
965 enum brw_gpu_ring ring
;
966 bool needs_sol_reset
;
974 #define BRW_MAX_XFB_STREAMS 4
976 struct brw_transform_feedback_object
{
977 struct gl_transform_feedback_object base
;
979 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
980 drm_intel_bo
*offset_bo
;
982 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
985 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
986 GLenum primitive_mode
;
989 * Count of primitives generated during this transform feedback operation.
992 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
993 drm_intel_bo
*prim_count_bo
;
994 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
998 * Number of vertices written between last Begin/EndTransformFeedback().
1000 * Used to implement DrawTransformFeedback().
1002 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
1003 bool vertices_written_valid
;
1007 * Data shared between each programmable stage in the pipeline (vs, gs, and
1010 struct brw_stage_state
1012 gl_shader_stage stage
;
1013 struct brw_stage_prog_data
*prog_data
;
1016 * Optional scratch buffer used to store spilled register values and
1017 * variably-indexed GRF arrays.
1019 drm_intel_bo
*scratch_bo
;
1021 /** Offset in the program cache to the program */
1022 uint32_t prog_offset
;
1024 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
1025 uint32_t state_offset
;
1027 uint32_t push_const_offset
; /* Offset in the batchbuffer */
1028 int push_const_size
; /* in 256-bit register increments */
1030 /* Binding table: pointers to SURFACE_STATE entries. */
1031 uint32_t bind_bo_offset
;
1032 uint32_t surf_offset
[BRW_MAX_SURFACES
];
1034 /** SAMPLER_STATE count and table offset */
1035 uint32_t sampler_count
;
1036 uint32_t sampler_offset
;
1039 enum brw_predicate_state
{
1040 /* The first two states are used if we can determine whether to draw
1041 * without having to look at the values in the query object buffer. This
1042 * will happen if there is no conditional render in progress, if the query
1043 * object is already completed or if something else has already added
1044 * samples to the preliminary result such as via a BLT command.
1046 BRW_PREDICATE_STATE_RENDER
,
1047 BRW_PREDICATE_STATE_DONT_RENDER
,
1048 /* In this case whether to draw or not depends on the result of an
1049 * MI_PREDICATE command so the predicate enable bit needs to be checked.
1051 BRW_PREDICATE_STATE_USE_BIT
1054 struct shader_times
;
1057 * brw_context is derived from gl_context.
1061 struct gl_context ctx
; /**< base class, must be first field */
1065 void (*update_texture_surface
)(struct gl_context
*ctx
,
1067 uint32_t *surf_offset
,
1069 uint32_t (*update_renderbuffer_surface
)(struct brw_context
*brw
,
1070 struct gl_renderbuffer
*rb
,
1071 bool layered
, unsigned unit
,
1072 uint32_t surf_index
);
1074 void (*emit_texture_surface_state
)(struct brw_context
*brw
,
1075 struct intel_mipmap_tree
*mt
,
1083 uint32_t *surf_offset
,
1084 bool rw
, bool for_gather
);
1085 void (*emit_buffer_surface_state
)(struct brw_context
*brw
,
1086 uint32_t *out_offset
,
1088 unsigned buffer_offset
,
1089 unsigned surface_format
,
1090 unsigned buffer_size
,
1093 void (*emit_null_surface_state
)(struct brw_context
*brw
,
1097 uint32_t *out_offset
);
1100 * Send the appropriate state packets to configure depth, stencil, and
1101 * HiZ buffers (i965+ only)
1103 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
1104 struct intel_mipmap_tree
*depth_mt
,
1105 uint32_t depth_offset
,
1106 uint32_t depthbuffer_format
,
1107 uint32_t depth_surface_type
,
1108 struct intel_mipmap_tree
*stencil_mt
,
1109 bool hiz
, bool separate_stencil
,
1110 uint32_t width
, uint32_t height
,
1111 uint32_t tile_x
, uint32_t tile_y
);
1117 drm_intel_context
*hw_ctx
;
1119 /** BO for post-sync nonzero writes for gen6 workaround. */
1120 drm_intel_bo
*workaround_bo
;
1121 uint8_t pipe_controls_since_last_cs_stall
;
1124 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
1125 * and would need flushing before being used from another cache domain that
1126 * isn't coherent with it (i.e. the sampler).
1128 struct set
*render_cache
;
1131 * Number of resets observed in the system at context creation.
1133 * This is tracked in the context so that we can determine that another
1134 * reset has occurred.
1136 uint32_t reset_count
;
1138 struct intel_batchbuffer batch
;
1143 uint32_t next_offset
;
1147 * Set if rendering has occurred to the drawable's front buffer.
1149 * This is used in the DRI2 case to detect that glFlush should also copy
1150 * the contents of the fake front buffer to the real front buffer.
1152 bool front_buffer_dirty
;
1154 /** Framerate throttling: @{ */
1155 drm_intel_bo
*throttle_batch
[2];
1157 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
1158 * frame of rendering to complete. This gives a very precise cap to the
1159 * latency between input and output such that rendering never gets more
1160 * than a frame behind the user. (With the caveat that we technically are
1161 * not using the SwapBuffers itself as a barrier but the first batch
1162 * submitted afterwards, which may be immediately prior to the next
1165 bool need_swap_throttle
;
1167 /** General throttling, not caught by throttling between SwapBuffers */
1168 bool need_flush_throttle
;
1178 bool always_flush_batch
;
1179 bool always_flush_cache
;
1180 bool disable_throttling
;
1183 driOptionCache optionCache
;
1186 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
1188 GLenum reduced_primitive
;
1191 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
1192 * variable is set, this is the flag indicating to do expensive work that
1193 * might lead to a perf_debug() call.
1197 uint32_t max_gtt_map_object_size
;
1209 bool has_separate_stencil
;
1210 bool must_use_separate_stencil
;
1213 bool has_surface_tile_offset
;
1215 bool has_negative_rhw_bug
;
1219 bool use_resource_streamer
;
1222 * Some versions of Gen hardware don't do centroid interpolation correctly
1223 * on unlit pixels, causing incorrect values for derivatives near triangle
1224 * edges. Enabling this flag causes the fragment shader to use
1225 * non-centroid interpolation for unlit pixels, at the expense of two extra
1226 * fragment shader instructions.
1228 bool needs_unlit_centroid_workaround
;
1232 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
1235 enum brw_pipeline last_pipeline
;
1237 struct brw_cache cache
;
1239 /** IDs for meta stencil blit shader programs. */
1240 unsigned meta_stencil_blit_programs
[2];
1242 /* Whether a meta-operation is in progress. */
1243 bool meta_in_progress
;
1245 /* Whether the last depth/stencil packets were both NULL. */
1246 bool no_depth_or_stencil
;
1248 /* The last PMA stall bits programmed. */
1249 uint32_t pma_stall_bits
;
1252 /** The value of gl_BaseVertex for the current _mesa_prim. */
1256 * Buffer and offset used for GL_ARB_shader_draw_parameters
1257 * (for now, only gl_BaseVertex).
1259 drm_intel_bo
*draw_params_bo
;
1260 uint32_t draw_params_offset
;
1265 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
1266 * an indirect call, and num_work_groups_offset is valid. Otherwise,
1267 * num_work_groups is set based on glDispatchCompute.
1269 drm_intel_bo
*num_work_groups_bo
;
1270 GLintptr num_work_groups_offset
;
1271 const GLuint
*num_work_groups
;
1275 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
1276 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
1278 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
1282 /* Summary of size and varying of active arrays, so we can check
1283 * for changes to this state:
1285 unsigned int min_index
, max_index
;
1287 /* Offset from start of vertex buffer so we can avoid redefining
1288 * the same VB packed over and over again.
1290 unsigned int start_vertex_bias
;
1293 * Certain vertex attribute formats aren't natively handled by the
1294 * hardware and require special VS code to fix up their values.
1296 * These bitfields indicate which workarounds are needed.
1298 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
1303 * Index buffer for this draw_prims call.
1305 * Updates are signaled by BRW_NEW_INDICES.
1307 const struct _mesa_index_buffer
*ib
;
1309 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
1313 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
1314 * avoid re-uploading the IB packet over and over if we're actually
1315 * referencing the same index buffer.
1317 unsigned int start_vertex_offset
;
1320 /* Active vertex program:
1322 const struct gl_vertex_program
*vertex_program
;
1323 const struct gl_geometry_program
*geometry_program
;
1324 const struct gl_fragment_program
*fragment_program
;
1325 const struct gl_compute_program
*compute_program
;
1328 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
1329 * that we don't have to reemit that state every time we change FBOs.
1334 * Platform specific constants containing the maximum number of threads
1335 * for each pipeline stage.
1337 unsigned max_vs_threads
;
1338 unsigned max_hs_threads
;
1339 unsigned max_ds_threads
;
1340 unsigned max_gs_threads
;
1341 unsigned max_wm_threads
;
1342 unsigned max_cs_threads
;
1344 /* BRW_NEW_URB_ALLOCATIONS:
1347 GLuint vsize
; /* vertex size plus header in urb registers */
1348 GLuint gsize
; /* GS output size in urb registers */
1349 GLuint csize
; /* constant buffer size in urb registers */
1350 GLuint sfsize
; /* setup data size in urb registers */
1354 GLuint min_vs_entries
; /* Minimum number of VS entries */
1355 GLuint max_vs_entries
; /* Maximum number of VS entries */
1356 GLuint max_hs_entries
; /* Maximum number of HS entries */
1357 GLuint max_ds_entries
; /* Maximum number of DS entries */
1358 GLuint max_gs_entries
; /* Maximum number of GS entries */
1360 GLuint nr_vs_entries
;
1361 GLuint nr_gs_entries
;
1362 GLuint nr_clip_entries
;
1363 GLuint nr_sf_entries
;
1364 GLuint nr_cs_entries
;
1371 GLuint size
; /* Hardware URB size, in KB. */
1373 /* True if the most recently sent _3DSTATE_URB message allocated
1374 * URB space for the GS.
1380 /* BRW_NEW_CURBE_OFFSETS:
1383 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1384 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1392 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1393 * for upload to the CURBE.
1395 drm_intel_bo
*curbe_bo
;
1396 /** Offset within curbe_bo of space for current curbe entry */
1397 GLuint curbe_offset
;
1401 * Layout of vertex data exiting the geometry portion of the pipleine.
1402 * This comes from the last enabled shader stage (GS, DS, or VS).
1404 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1406 struct brw_vue_map vue_map_geom_out
;
1409 struct brw_stage_state base
;
1410 struct brw_vs_prog_data
*prog_data
;
1414 struct brw_stage_state base
;
1415 struct brw_gs_prog_data
*prog_data
;
1418 * True if the 3DSTATE_GS command most recently emitted to the 3D
1419 * pipeline enabled the GS; false otherwise.
1425 struct brw_ff_gs_prog_data
*prog_data
;
1428 /** Offset in the program cache to the CLIP program pre-gen6 */
1429 uint32_t prog_offset
;
1430 uint32_t state_offset
;
1432 uint32_t bind_bo_offset
;
1434 * Surface offsets for the binding table. We only need surfaces to
1435 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1436 * need in this case.
1438 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1442 struct brw_clip_prog_data
*prog_data
;
1444 /** Offset in the program cache to the CLIP program pre-gen6 */
1445 uint32_t prog_offset
;
1447 /* Offset in the batch to the CLIP state on pre-gen6. */
1448 uint32_t state_offset
;
1450 /* As of gen6, this is the offset in the batch to the CLIP VP,
1458 struct brw_sf_prog_data
*prog_data
;
1460 /** Offset in the program cache to the CLIP program pre-gen6 */
1461 uint32_t prog_offset
;
1462 uint32_t state_offset
;
1464 bool viewport_transform_enable
;
1468 struct brw_stage_state base
;
1469 struct brw_wm_prog_data
*prog_data
;
1474 * Buffer object used in place of multisampled null render targets on
1475 * Gen6. See brw_emit_null_surface_state().
1477 drm_intel_bo
*multisampled_null_render_target_bo
;
1478 uint32_t fast_clear_op
;
1482 struct brw_stage_state base
;
1483 struct brw_cs_prog_data
*prog_data
;
1486 /* RS hardware binding table */
1489 uint32_t next_offset
;
1493 uint32_t state_offset
;
1494 uint32_t blend_state_offset
;
1495 uint32_t depth_stencil_state_offset
;
1500 struct brw_query_object
*obj
;
1505 enum brw_predicate_state state
;
1510 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1511 const int *statistics_registers
;
1513 /** The number of active monitors using OA counters. */
1517 * A buffer object storing OA counter snapshots taken at the start and
1518 * end of each batch (creating "bookends" around the batch).
1520 drm_intel_bo
*bookend_bo
;
1522 /** The number of snapshots written to bookend_bo. */
1523 int bookend_snapshots
;
1526 * An array of monitors whose results haven't yet been assembled based on
1527 * the data in buffer objects.
1529 * These may be active, or have already ended. However, the results
1530 * have not been requested.
1532 struct brw_perf_monitor_object
**unresolved
;
1533 int unresolved_elements
;
1534 int unresolved_array_size
;
1537 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1538 * the counter which MI_REPORT_PERF_COUNT stores there.
1540 const int *oa_snapshot_layout
;
1542 /** Number of 32-bit entries in a hardware counter snapshot. */
1543 int entries_per_oa_snapshot
;
1546 int num_atoms
[BRW_NUM_PIPELINES
];
1547 const struct brw_tracked_state render_atoms
[60];
1548 const struct brw_tracked_state compute_atoms
[6];
1550 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1554 enum aub_state_struct_type type
;
1556 } *state_batch_list
;
1557 int state_batch_count
;
1559 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1560 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1562 /* Interpolation modes, one byte per vue slot.
1563 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1565 struct interpolation_mode_map interpolation_mode
;
1567 /* PrimitiveRestart */
1570 bool enable_cut_index
;
1573 /** Computed depth/stencil/hiz state from the current attached
1574 * renderbuffers, valid only during the drawing state upload loop after
1575 * brw_workaround_depthstencil_alignment().
1578 struct intel_mipmap_tree
*depth_mt
;
1579 struct intel_mipmap_tree
*stencil_mt
;
1581 /* Inter-tile (page-aligned) byte offsets. */
1582 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1583 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1584 uint32_t tile_x
, tile_y
;
1587 uint32_t num_instances
;
1594 enum shader_time_shader_type
*types
;
1595 struct shader_times
*cumulative
;
1601 struct brw_fast_clear_state
*fast_clear_state
;
1603 __DRIcontext
*driContext
;
1604 struct intel_screen
*intelScreen
;
1607 /*======================================================================
1610 void brwInitVtbl( struct brw_context
*brw
);
1613 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1615 /*======================================================================
1618 extern const char *const brw_vendor_string
;
1620 extern const char *brw_get_renderer_string(unsigned deviceID
);
1623 DRI_CONF_BO_REUSE_DISABLED
,
1624 DRI_CONF_BO_REUSE_ALL
1627 void intel_update_renderbuffers(__DRIcontext
*context
,
1628 __DRIdrawable
*drawable
);
1629 void intel_prepare_render(struct brw_context
*brw
);
1631 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1632 __DRIdrawable
*drawable
);
1634 GLboolean
brwCreateContext(gl_api api
,
1635 const struct gl_config
*mesaVis
,
1636 __DRIcontext
*driContextPriv
,
1637 unsigned major_version
,
1638 unsigned minor_version
,
1642 void *sharedContextPrivate
);
1644 /*======================================================================
1647 GLuint
brw_get_rb_for_slice(struct brw_context
*brw
,
1648 struct intel_mipmap_tree
*mt
,
1649 unsigned level
, unsigned layer
, bool flat
);
1651 void brw_meta_updownsample(struct brw_context
*brw
,
1652 struct intel_mipmap_tree
*src
,
1653 struct intel_mipmap_tree
*dst
);
1655 void brw_meta_fbo_stencil_blit(struct brw_context
*brw
,
1656 struct gl_framebuffer
*read_fb
,
1657 struct gl_framebuffer
*draw_fb
,
1658 GLfloat srcX0
, GLfloat srcY0
,
1659 GLfloat srcX1
, GLfloat srcY1
,
1660 GLfloat dstX0
, GLfloat dstY0
,
1661 GLfloat dstX1
, GLfloat dstY1
);
1663 void brw_meta_stencil_updownsample(struct brw_context
*brw
,
1664 struct intel_mipmap_tree
*src
,
1665 struct intel_mipmap_tree
*dst
);
1667 bool brw_meta_fast_clear(struct brw_context
*brw
,
1668 struct gl_framebuffer
*fb
,
1670 bool partial_clear
);
1673 brw_meta_resolve_color(struct brw_context
*brw
,
1674 struct intel_mipmap_tree
*mt
);
1676 brw_meta_fast_clear_free(struct brw_context
*brw
);
1679 /*======================================================================
1682 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1683 uint32_t depth_level
,
1684 uint32_t depth_layer
,
1685 struct intel_mipmap_tree
*stencil_mt
,
1686 uint32_t *out_tile_mask_x
,
1687 uint32_t *out_tile_mask_y
);
1688 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1689 GLbitfield clear_mask
);
1691 /* brw_object_purgeable.c */
1692 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1694 /*======================================================================
1697 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1698 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1699 void brw_emit_query_begin(struct brw_context
*brw
);
1700 void brw_emit_query_end(struct brw_context
*brw
);
1702 /** gen6_queryobj.c */
1703 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1704 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1705 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1706 void brw_store_register_mem64(struct brw_context
*brw
,
1707 drm_intel_bo
*bo
, uint32_t reg
, int idx
);
1709 /** brw_conditional_render.c */
1710 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1711 bool brw_check_conditional_render(struct brw_context
*brw
);
1713 /** intel_batchbuffer.c */
1714 void brw_load_register_mem(struct brw_context
*brw
,
1717 uint32_t read_domains
, uint32_t write_domain
,
1719 void brw_load_register_mem64(struct brw_context
*brw
,
1722 uint32_t read_domains
, uint32_t write_domain
,
1725 /*======================================================================
1728 void brw_debug_batch(struct brw_context
*brw
);
1729 void brw_annotate_aub(struct brw_context
*brw
);
1731 /*======================================================================
1734 void brw_validate_textures( struct brw_context
*brw
);
1737 /*======================================================================
1740 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1742 int brw_get_scratch_size(int size
);
1743 void brw_get_scratch_bo(struct brw_context
*brw
,
1744 drm_intel_bo
**scratch_bo
, int size
);
1745 void brw_init_shader_time(struct brw_context
*brw
);
1746 int brw_get_shader_time_index(struct brw_context
*brw
,
1747 struct gl_shader_program
*shader_prog
,
1748 struct gl_program
*prog
,
1749 enum shader_time_shader_type type
);
1750 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1751 void brw_destroy_shader_time(struct brw_context
*brw
);
1755 void brw_upload_urb_fence(struct brw_context
*brw
);
1759 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1761 /* brw_fs_reg_allocate.cpp
1763 void brw_fs_alloc_reg_sets(struct brw_compiler
*compiler
);
1765 /* brw_vec4_reg_allocate.cpp */
1766 void brw_vec4_alloc_reg_set(struct brw_compiler
*compiler
);
1769 int brw_disassemble_inst(FILE *file
, const struct brw_device_info
*devinfo
,
1770 struct brw_inst
*inst
, bool is_compacted
);
1773 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1775 /* brw_draw_upload.c */
1776 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1777 const struct gl_client_array
*glarray
);
1779 static inline unsigned
1780 brw_get_index_type(GLenum type
)
1782 assert((type
== GL_UNSIGNED_BYTE
)
1783 || (type
== GL_UNSIGNED_SHORT
)
1784 || (type
== GL_UNSIGNED_INT
));
1786 /* The possible values for type are GL_UNSIGNED_BYTE (0x1401),
1787 * GL_UNSIGNED_SHORT (0x1403), and GL_UNSIGNED_INT (0x1405) which we want
1788 * to map to scale factors of 0, 1, and 2, respectively. These scale
1789 * factors are then left-shfited by 8 to be in the correct position in the
1790 * CMD_INDEX_BUFFER packet.
1792 * Subtracting 0x1401 gives 0, 2, and 4. Shifting left by 7 afterwards
1793 * gives 0x00000000, 0x00000100, and 0x00000200. These just happen to be
1794 * the values the need to be written in the CMD_INDEX_BUFFER packet.
1796 return (type
- 0x1401) << 7;
1799 void brw_prepare_vertices(struct brw_context
*brw
);
1801 /* brw_wm_surface_state.c */
1802 void brw_init_surface_formats(struct brw_context
*brw
);
1803 void brw_create_constant_surface(struct brw_context
*brw
,
1807 uint32_t *out_offset
,
1809 void brw_create_buffer_surface(struct brw_context
*brw
,
1813 uint32_t *out_offset
,
1815 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1817 uint32_t *surf_offset
);
1819 brw_update_sol_surface(struct brw_context
*brw
,
1820 struct gl_buffer_object
*buffer_obj
,
1821 uint32_t *out_offset
, unsigned num_vector_components
,
1822 unsigned stride_dwords
, unsigned offset_dwords
);
1823 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1824 struct gl_shader
*shader
,
1825 struct brw_stage_state
*stage_state
,
1826 struct brw_stage_prog_data
*prog_data
,
1828 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1829 struct gl_shader_program
*prog
,
1830 struct brw_stage_state
*stage_state
,
1831 struct brw_stage_prog_data
*prog_data
);
1832 void brw_upload_image_surfaces(struct brw_context
*brw
,
1833 struct gl_shader
*shader
,
1834 struct brw_stage_state
*stage_state
,
1835 struct brw_stage_prog_data
*prog_data
);
1837 /* brw_surface_formats.c */
1838 bool brw_render_target_supported(struct brw_context
*brw
,
1839 struct gl_renderbuffer
*rb
);
1840 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1841 mesa_format
brw_lower_mesa_image_format(const struct brw_device_info
*devinfo
,
1842 mesa_format format
);
1844 /* brw_performance_monitor.c */
1845 void brw_init_performance_monitors(struct brw_context
*brw
);
1846 void brw_dump_perf_monitors(struct brw_context
*brw
);
1847 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1848 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1850 /* intel_buffer_objects.c */
1851 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1852 const char *bo_name
);
1853 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1854 const char *bo_name
);
1856 /* intel_extensions.c */
1857 extern void intelInitExtensions(struct gl_context
*ctx
);
1860 extern int intel_translate_shadow_compare_func(GLenum func
);
1861 extern int intel_translate_compare_func(GLenum func
);
1862 extern int intel_translate_stencil_op(GLenum op
);
1863 extern int intel_translate_logic_op(GLenum opcode
);
1865 /* intel_syncobj.c */
1866 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1869 struct gl_transform_feedback_object
*
1870 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1872 brw_delete_transform_feedback(struct gl_context
*ctx
,
1873 struct gl_transform_feedback_object
*obj
);
1875 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1876 struct gl_transform_feedback_object
*obj
);
1878 brw_end_transform_feedback(struct gl_context
*ctx
,
1879 struct gl_transform_feedback_object
*obj
);
1881 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1882 struct gl_transform_feedback_object
*obj
,
1885 /* gen7_sol_state.c */
1887 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1888 struct gl_transform_feedback_object
*obj
);
1890 gen7_end_transform_feedback(struct gl_context
*ctx
,
1891 struct gl_transform_feedback_object
*obj
);
1893 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1894 struct gl_transform_feedback_object
*obj
);
1896 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1897 struct gl_transform_feedback_object
*obj
);
1899 /* brw_blorp_blit.cpp */
1901 brw_blorp_framebuffer(struct brw_context
*brw
,
1902 struct gl_framebuffer
*readFb
,
1903 struct gl_framebuffer
*drawFb
,
1904 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1905 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1906 GLbitfield mask
, GLenum filter
);
1909 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1910 struct gl_renderbuffer
*src_rb
,
1911 struct gl_texture_image
*dst_image
,
1913 int srcX0
, int srcY0
,
1914 int dstX0
, int dstY0
,
1915 int width
, int height
);
1917 /* gen6_multisample_state.c */
1919 gen6_determine_sample_mask(struct brw_context
*brw
);
1922 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1923 unsigned num_samples
);
1925 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1927 gen6_get_sample_position(struct gl_context
*ctx
,
1928 struct gl_framebuffer
*fb
,
1932 gen6_set_sample_maps(struct gl_context
*ctx
);
1934 /* gen8_multisample_state.c */
1935 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1936 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1940 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1941 unsigned gs_size
, unsigned fs_size
);
1944 gen7_emit_urb_state(struct brw_context
*brw
,
1945 unsigned nr_vs_entries
, unsigned vs_size
,
1946 unsigned vs_start
, unsigned nr_gs_entries
,
1947 unsigned gs_size
, unsigned gs_start
);
1952 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1956 brw_init_compute_functions(struct dd_function_table
*functions
);
1958 /*======================================================================
1959 * Inline conversion functions. These are better-typed than the
1960 * macros used previously:
1962 static inline struct brw_context
*
1963 brw_context( struct gl_context
*ctx
)
1965 return (struct brw_context
*)ctx
;
1968 static inline struct brw_vertex_program
*
1969 brw_vertex_program(struct gl_vertex_program
*p
)
1971 return (struct brw_vertex_program
*) p
;
1974 static inline const struct brw_vertex_program
*
1975 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1977 return (const struct brw_vertex_program
*) p
;
1980 static inline struct brw_geometry_program
*
1981 brw_geometry_program(struct gl_geometry_program
*p
)
1983 return (struct brw_geometry_program
*) p
;
1986 static inline struct brw_fragment_program
*
1987 brw_fragment_program(struct gl_fragment_program
*p
)
1989 return (struct brw_fragment_program
*) p
;
1992 static inline const struct brw_fragment_program
*
1993 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1995 return (const struct brw_fragment_program
*) p
;
1998 static inline struct brw_compute_program
*
1999 brw_compute_program(struct gl_compute_program
*p
)
2001 return (struct brw_compute_program
*) p
;
2005 * Pre-gen6, the register file of the EUs was shared between threads,
2006 * and each thread used some subset allocated on a 16-register block
2007 * granularity. The unit states wanted these block counts.
2010 brw_register_blocks(int reg_count
)
2012 return ALIGN(reg_count
, 16) / 16 - 1;
2015 static inline uint32_t
2016 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
2017 uint32_t prog_offset
)
2019 if (brw
->gen
>= 5) {
2020 /* Using state base address. */
2024 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
2028 I915_GEM_DOMAIN_INSTRUCTION
, 0);
2030 return brw
->cache
.bo
->offset64
+ prog_offset
;
2033 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
2034 bool brw_lower_texture_gradients(struct brw_context
*brw
,
2035 struct exec_list
*instructions
);
2036 bool brw_do_lower_unnormalized_offset(struct exec_list
*instructions
);
2038 struct opcode_desc
{
2044 extern const struct opcode_desc opcode_descs
[128];
2045 extern const char * const conditional_modifier
[16];
2048 brw_emit_depthbuffer(struct brw_context
*brw
);
2051 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
2052 struct intel_mipmap_tree
*depth_mt
,
2053 uint32_t depth_offset
, uint32_t depthbuffer_format
,
2054 uint32_t depth_surface_type
,
2055 struct intel_mipmap_tree
*stencil_mt
,
2056 bool hiz
, bool separate_stencil
,
2057 uint32_t width
, uint32_t height
,
2058 uint32_t tile_x
, uint32_t tile_y
);
2061 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
2062 struct intel_mipmap_tree
*depth_mt
,
2063 uint32_t depth_offset
, uint32_t depthbuffer_format
,
2064 uint32_t depth_surface_type
,
2065 struct intel_mipmap_tree
*stencil_mt
,
2066 bool hiz
, bool separate_stencil
,
2067 uint32_t width
, uint32_t height
,
2068 uint32_t tile_x
, uint32_t tile_y
);
2071 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
2072 struct intel_mipmap_tree
*depth_mt
,
2073 uint32_t depth_offset
, uint32_t depthbuffer_format
,
2074 uint32_t depth_surface_type
,
2075 struct intel_mipmap_tree
*stencil_mt
,
2076 bool hiz
, bool separate_stencil
,
2077 uint32_t width
, uint32_t height
,
2078 uint32_t tile_x
, uint32_t tile_y
);
2080 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
2081 struct intel_mipmap_tree
*depth_mt
,
2082 uint32_t depth_offset
, uint32_t depthbuffer_format
,
2083 uint32_t depth_surface_type
,
2084 struct intel_mipmap_tree
*stencil_mt
,
2085 bool hiz
, bool separate_stencil
,
2086 uint32_t width
, uint32_t height
,
2087 uint32_t tile_x
, uint32_t tile_y
);
2089 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
2090 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);
2092 uint32_t get_hw_prim_for_gl_prim(int mode
);
2095 gen6_upload_push_constants(struct brw_context
*brw
,
2096 const struct gl_program
*prog
,
2097 const struct brw_stage_prog_data
*prog_data
,
2098 struct brw_stage_state
*stage_state
,
2099 enum aub_state_struct_type type
);
2102 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
2103 const struct intel_mipmap_tree
*mt
);
2105 /* brw_pipe_control.c */
2106 int brw_init_pipe_control(struct brw_context
*brw
,
2107 const struct brw_device_info
*info
);
2108 void brw_fini_pipe_control(struct brw_context
*brw
);
2110 void brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
);
2111 void brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
2112 drm_intel_bo
*bo
, uint32_t offset
,
2113 uint32_t imm_lower
, uint32_t imm_upper
);
2114 void brw_emit_mi_flush(struct brw_context
*brw
);
2115 void brw_emit_post_sync_nonzero_flush(struct brw_context
*brw
);
2116 void brw_emit_depth_stall_flushes(struct brw_context
*brw
);
2117 void gen7_emit_vs_workaround_flush(struct brw_context
*brw
);
2118 void gen7_emit_cs_stall_flush(struct brw_context
*brw
);