2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
38 #include "main/imports.h"
39 #include "main/macros.h"
41 #include "main/mtypes.h"
42 #include "brw_structs.h"
43 #include "intel_aub.h"
44 #include "program/prog_parameter.h"
48 /* Evil hack for using libdrm in a c++ compiler. */
53 #include <intel_bufmgr.h>
63 #include "intel_debug.h"
64 #include "intel_screen.h"
65 #include "intel_tex_obj.h"
66 #include "intel_resolve_map.h"
70 * URB - uniform resource buffer. A mid-sized buffer which is
71 * partitioned between the fixed function units and used for passing
72 * values (vertices, primitives, constants) between them.
74 * CURBE - constant URB entry. An urb region (entry) used to hold
75 * constant values which the fixed function units can be instructed to
76 * preload into the GRF when spawning a thread.
78 * VUE - vertex URB entry. An urb entry holding a vertex and usually
79 * a vertex header. The header contains control information and
80 * things like primitive type, Begin/end flags and clip codes.
82 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
83 * unit holding rasterization and interpolation parameters.
85 * GRF - general register file. One of several register files
86 * addressable by programmed threads. The inputs (r0, payload, curbe,
87 * urb) of the thread are preloaded to this area before the thread is
88 * spawned. The registers are individually 8 dwords wide and suitable
89 * for general usage. Registers holding thread input values are not
90 * special and may be overwritten.
92 * MRF - message register file. Threads communicate (and terminate)
93 * by sending messages. Message parameters are placed in contiguous
94 * MRF registers. All program output is via these messages. URB
95 * entries are populated by sending a message to the shared URB
96 * function containing the new data, together with a control word,
97 * often an unmodified copy of R0.
99 * R0 - GRF register 0. Typically holds control information used when
100 * sending messages to other threads.
102 * EU or GEN4 EU: The name of the programmable subsystem of the
103 * i965 hardware. Threads are executed by the EU, the registers
104 * described above are part of the EU architecture.
106 * Fixed function units:
108 * CS - Command streamer. Notional first unit, little software
109 * interaction. Holds the URB entries used for constant data, ie the
112 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
113 * this unit is responsible for pulling vertices out of vertex buffers
114 * in vram and injecting them into the processing pipe as VUEs. If
115 * enabled, it first passes them to a VS thread which is a good place
116 * for the driver to implement any active vertex shader.
118 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
119 * enabled, incoming strips etc are passed to GS threads in individual
120 * line/triangle/point units. The GS thread may perform arbitary
121 * computation and emit whatever primtives with whatever vertices it
122 * chooses. This makes GS an excellent place to implement GL's
123 * unfilled polygon modes, though of course it is capable of much
124 * more. Additionally, GS is used to translate away primitives not
125 * handled by latter units, including Quads and Lineloops.
127 * CS - Clipper. Mesa's clipping algorithms are imported to run on
128 * this unit. The fixed function part performs cliptesting against
129 * the 6 fixed clipplanes and makes descisions on whether or not the
130 * incoming primitive needs to be passed to a thread for clipping.
131 * User clip planes are handled via cooperation with the VS thread.
133 * SF - Strips Fans or Setup: Triangles are prepared for
134 * rasterization. Interpolation coefficients are calculated.
135 * Flatshading and two-side lighting usually performed here.
137 * WM - Windower. Interpolation of vertex attributes performed here.
138 * Fragment shader implemented here. SIMD aspects of EU taken full
139 * advantage of, as pixels are processed in blocks of 16.
141 * CC - Color Calculator. No EU threads associated with this unit.
142 * Handles blending and (presumably) depth and stencil testing.
147 struct brw_vs_prog_key
;
148 struct brw_vec4_prog_key
;
149 struct brw_wm_prog_key
;
150 struct brw_wm_prog_data
;
154 BRW_CACHE_BLORP_BLIT_PROG
,
157 BRW_CACHE_FF_GS_PROG
,
165 /* brw_cache_ids must come first - see brw_state_cache.c */
166 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
167 BRW_STATE_FRAGMENT_PROGRAM
,
168 BRW_STATE_GEOMETRY_PROGRAM
,
169 BRW_STATE_VERTEX_PROGRAM
,
170 BRW_STATE_CURBE_OFFSETS
,
171 BRW_STATE_REDUCED_PRIMITIVE
,
176 BRW_STATE_VS_BINDING_TABLE
,
177 BRW_STATE_GS_BINDING_TABLE
,
178 BRW_STATE_PS_BINDING_TABLE
,
182 BRW_STATE_INDEX_BUFFER
,
183 BRW_STATE_VS_CONSTBUF
,
184 BRW_STATE_GS_CONSTBUF
,
185 BRW_STATE_PROGRAM_CACHE
,
186 BRW_STATE_STATE_BASE_ADDRESS
,
187 BRW_STATE_VUE_MAP_VS
,
188 BRW_STATE_VUE_MAP_GEOM_OUT
,
189 BRW_STATE_TRANSFORM_FEEDBACK
,
190 BRW_STATE_RASTERIZER_DISCARD
,
192 BRW_STATE_UNIFORM_BUFFER
,
193 BRW_STATE_ATOMIC_BUFFER
,
194 BRW_STATE_META_IN_PROGRESS
,
195 BRW_STATE_INTERPOLATION_MAP
,
196 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
197 BRW_STATE_NUM_SAMPLES
,
198 BRW_STATE_TEXTURE_BUFFER
,
199 BRW_STATE_GEN4_UNIT_STATE
,
203 BRW_STATE_SAMPLER_STATE_TABLE
,
208 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
210 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
211 * When the currently bound shader program differs from the previous draw
212 * call, these will be flagged. They cover brw->{stage}_program and
213 * ctx->{Stage}Program->_Current.
215 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
216 * driver perspective. Even if the same shader is bound at the API level,
217 * we may need to switch between multiple versions of that shader to handle
218 * changes in non-orthagonal state.
220 * Additionally, multiple shader programs may have identical vertex shaders
221 * (for example), or compile down to the same code in the backend. We combine
222 * those into a single program cache entry.
224 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
225 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
227 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
228 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
229 * use the normal state upload paths), but the cache is still used. To avoid
230 * polluting the brw_state_cache code with special cases, we retain the dirty
231 * bit for now. It should eventually be removed.
233 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_BLIT_PROG)
234 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
235 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
236 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
237 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
238 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
239 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
240 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
241 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
242 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
243 #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
244 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
245 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
246 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
247 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
248 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
249 #define BRW_NEW_VS_BINDING_TABLE (1ull << BRW_STATE_VS_BINDING_TABLE)
250 #define BRW_NEW_GS_BINDING_TABLE (1ull << BRW_STATE_GS_BINDING_TABLE)
251 #define BRW_NEW_PS_BINDING_TABLE (1ull << BRW_STATE_PS_BINDING_TABLE)
252 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
253 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
255 * Used for any batch entry with a relocated pointer that will be used
256 * by any 3D rendering.
258 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
259 /** \see brw.state.depth_region */
260 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
261 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
262 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
263 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
264 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
265 #define BRW_NEW_VUE_MAP_VS (1ull << BRW_STATE_VUE_MAP_VS)
266 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
267 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
268 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
269 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
270 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
271 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
272 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
273 #define BRW_NEW_INTERPOLATION_MAP (1ull << BRW_STATE_INTERPOLATION_MAP)
274 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
275 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
276 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
277 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
278 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
279 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
280 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
281 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
283 struct brw_state_flags
{
284 /** State update flags signalled by mesa internals */
287 * State update flags signalled as the result of brw_tracked_state updates
291 * State update flags that used to be signalled by brw_state_cache.c
294 * Now almost all of that state is just streamed out on demand, but the
295 * flags for those state blobs updating have stayed in the same bitfield.
296 * brw_state_cache.c still flags BRW_NEW_*_PROG_DATA.
301 /** Subclass of Mesa vertex program */
302 struct brw_vertex_program
{
303 struct gl_vertex_program program
;
308 /** Subclass of Mesa geometry program */
309 struct brw_geometry_program
{
310 struct gl_geometry_program program
;
311 unsigned id
; /**< serial no. to identify geom progs, never re-used */
315 /** Subclass of Mesa fragment program */
316 struct brw_fragment_program
{
317 struct gl_fragment_program program
;
318 GLuint id
; /**< serial no. to identify frag progs, never re-used */
322 /** Subclass of Mesa compute program */
323 struct brw_compute_program
{
324 struct gl_compute_program program
;
325 unsigned id
; /**< serial no. to identify compute progs, never re-used */
330 struct gl_shader base
;
335 /* Note: If adding fields that need anything besides a normal memcmp() for
336 * comparing them, be sure to go fix brw_stage_prog_data_compare().
338 struct brw_stage_prog_data
{
340 /** size of our binding table. */
344 * surface indices for the various groups of surfaces
346 uint32_t pull_constants_start
;
347 uint32_t texture_start
;
348 uint32_t gather_texture_start
;
351 uint32_t shader_time_start
;
355 GLuint nr_params
; /**< number of float params/constants */
356 GLuint nr_pull_params
;
358 unsigned curb_read_length
;
359 unsigned total_scratch
;
362 * Register where the thread expects to find input data from the URB
363 * (typically uniforms, followed by vertex or fragment attributes).
365 unsigned dispatch_grf_start_reg
;
367 /* Pointers to tracked values (only valid once
368 * _mesa_load_state_parameters has been called at runtime).
370 * These must be the last fields of the struct (see
371 * brw_stage_prog_data_compare()).
373 const gl_constant_value
**param
;
374 const gl_constant_value
**pull_param
;
377 /* Data about a particular attempt to compile a program. Note that
378 * there can be many of these, each in a different GL state
379 * corresponding to a different brw_wm_prog_key struct, with different
382 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
385 struct brw_wm_prog_data
{
386 struct brw_stage_prog_data base
;
388 GLuint num_varying_inputs
;
390 GLuint dispatch_grf_start_reg_16
;
392 GLuint reg_blocks_16
;
396 * surface indices the WM-specific surfaces
398 uint32_t render_target_start
;
404 bool uses_pos_offset
;
407 uint32_t prog_offset_16
;
410 * Mask of which interpolation modes are required by the fragment shader.
411 * Used in hardware setup on gen6+.
413 uint32_t barycentric_interp_modes
;
416 * Map from gl_varying_slot to the position within the FS setup data
417 * payload where the varying's attribute vertex deltas should be delivered.
418 * For varying slots that are not used by the FS, the value is -1.
420 int urb_setup
[VARYING_SLOT_MAX
];
424 * Enum representing the i965-specific vertex results that don't correspond
425 * exactly to any element of gl_varying_slot. The values of this enum are
426 * assigned such that they don't conflict with gl_varying_slot.
430 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
431 BRW_VARYING_SLOT_PAD
,
433 * Technically this is not a varying but just a placeholder that
434 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
435 * builtin variable to be compiled correctly. see compile_sf_prog() for
438 BRW_VARYING_SLOT_PNTC
,
439 BRW_VARYING_SLOT_COUNT
444 * Data structure recording the relationship between the gl_varying_slot enum
445 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
446 * single octaword within the VUE (128 bits).
448 * Note that each BRW register contains 256 bits (2 octawords), so when
449 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
450 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
451 * in a vertex shader), each register corresponds to a single VUE slot, since
452 * it contains data for two separate vertices.
456 * Bitfield representing all varying slots that are (a) stored in this VUE
457 * map, and (b) actually written by the shader. Does not include any of
458 * the additional varying slots defined in brw_varying_slot.
460 GLbitfield64 slots_valid
;
463 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
464 * not stored in a slot (because they are not written, or because
465 * additional processing is applied before storing them in the VUE), the
468 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
471 * Map from VUE slot to gl_varying_slot value. For slots that do not
472 * directly correspond to a gl_varying_slot, the value comes from
475 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
476 * simplifies code that uses the value stored in slot_to_varying to
477 * create a bit mask).
479 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
482 * Total number of VUE slots in use
488 * Convert a VUE slot number into a byte offset within the VUE.
490 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
496 * Convert a vertex output (brw_varying_slot) into a byte offset within the
499 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
502 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
505 void brw_compute_vue_map(struct brw_context
*brw
, struct brw_vue_map
*vue_map
,
506 GLbitfield64 slots_valid
);
510 * Bitmask indicating which fragment shader inputs represent varyings (and
511 * hence have to be delivered to the fragment shader by the SF/SBE stage).
513 #define BRW_FS_VARYING_INPUT_MASK \
514 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
515 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
519 * Mapping of VUE map slots to interpolation modes.
521 struct interpolation_mode_map
{
522 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
525 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
527 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
528 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
534 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
536 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
537 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
544 struct brw_sf_prog_data
{
545 GLuint urb_read_length
;
548 /* Each vertex may have upto 12 attributes, 4 components each,
549 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
552 * Actually we use 4 for each, so call it 12 rows.
554 GLuint urb_entry_size
;
559 * We always program SF to start reading at an offset of 1 (2 varying slots)
560 * from the start of the vertex URB entry. This causes it to skip:
561 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
562 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
564 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
567 struct brw_clip_prog_data
{
568 GLuint curb_read_length
; /* user planes? */
570 GLuint urb_read_length
;
574 struct brw_ff_gs_prog_data
{
575 GLuint urb_read_length
;
579 * Gen6 transform feedback: Amount by which the streaming vertex buffer
580 * indices should be incremented each time the GS is invoked.
582 unsigned svbi_postincrement_value
;
586 /* Note: brw_vec4_prog_data_compare() must be updated when adding fields to
589 struct brw_vec4_prog_data
{
590 struct brw_stage_prog_data base
;
591 struct brw_vue_map vue_map
;
593 GLuint urb_read_length
;
596 /* Used for calculating urb partitions. In the VS, this is the size of the
597 * URB entry used for both input and output to the thread. In the GS, this
598 * is the size of the URB entry used for output.
600 GLuint urb_entry_size
;
604 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
607 struct brw_vs_prog_data
{
608 struct brw_vec4_prog_data base
;
610 GLbitfield64 inputs_read
;
613 bool uses_instanceid
;
616 /** Number of texture sampler units */
617 #define BRW_MAX_TEX_UNIT 32
619 /** Max number of render targets in a shader */
620 #define BRW_MAX_DRAW_BUFFERS 8
622 /** Max number of atomic counter buffer objects in a shader */
623 #define BRW_MAX_ABO 16
626 * Max number of binding table entries used for stream output.
628 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
629 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
631 * On Gen6, the size of transform feedback data is limited not by the number
632 * of components but by the number of binding table entries we set aside. We
633 * use one binding table entry for a float, one entry for a vector, and one
634 * entry per matrix column. Since the only way we can communicate our
635 * transform feedback capabilities to the client is via
636 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
637 * worst case, in which all the varyings are floats, so we use up one binding
638 * table entry per component. Therefore we need to set aside at least 64
639 * binding table entries for use by transform feedback.
641 * Note: since we don't currently pack varyings, it is currently impossible
642 * for the client to actually use up all of these binding table entries--if
643 * all of their varyings were floats, they would run out of varying slots and
644 * fail to link. But that's a bug, so it seems prudent to go ahead and
645 * allocate the number of binding table entries we will need once the bug is
648 #define BRW_MAX_SOL_BINDINGS 64
650 /** Maximum number of actual buffers used for stream output */
651 #define BRW_MAX_SOL_BUFFERS 4
653 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
654 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
657 2 /* shader time, pull constants */)
659 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
661 /* Note: brw_gs_prog_data_compare() must be updated when adding fields to
664 struct brw_gs_prog_data
666 struct brw_vec4_prog_data base
;
669 * Size of an output vertex, measured in HWORDS (32 bytes).
671 unsigned output_vertex_size_hwords
;
673 unsigned output_topology
;
676 * Size of the control data (cut bits or StreamID bits), in hwords (32
677 * bytes). 0 if there is no control data.
679 unsigned control_data_header_size_hwords
;
682 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
683 * if the control data is StreamID bits, or
684 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
685 * Ignored if control_data_header_size is 0.
687 unsigned control_data_format
;
689 bool include_primitive_id
;
694 * Dispatch mode, can be any of:
695 * GEN7_GS_DISPATCH_MODE_DUAL_OBJECT
696 * GEN7_GS_DISPATCH_MODE_DUAL_INSTANCE
697 * GEN7_GS_DISPATCH_MODE_SINGLE
702 * Gen6 transform feedback enabled flag.
704 bool gen6_xfb_enabled
;
707 * Gen6: Provoking vertex convention for odd-numbered triangles
713 * Gen6: Number of varyings that are output to transform feedback.
715 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
718 * Gen6: Map from the index of a transform feedback binding table entry to the
719 * gl_varying_slot that should be streamed out through that binding table
722 unsigned char transform_feedback_bindings
[BRW_MAX_SOL_BINDINGS
];
725 * Gen6: Map from the index of a transform feedback binding table entry to the
726 * swizzles that should be used when streaming out data through that
727 * binding table entry.
729 unsigned char transform_feedback_swizzles
[BRW_MAX_SOL_BINDINGS
];
733 * Stride in bytes between shader_time entries.
735 * We separate entries by a cacheline to reduce traffic between EUs writing to
738 #define SHADER_TIME_STRIDE 64
740 struct brw_cache_item
{
742 * Effectively part of the key, cache_id identifies what kind of state
743 * buffer is involved, and also which brw->state.dirty.cache flag should
744 * be set when this cache item is chosen.
746 enum brw_cache_id cache_id
;
747 /** 32-bit hash of the key data */
749 GLuint key_size
; /* for variable-sized keys */
756 struct brw_cache_item
*next
;
760 typedef bool (*cache_aux_compare_func
)(const void *a
, const void *b
);
761 typedef void (*cache_aux_free_func
)(const void *aux
);
764 struct brw_context
*brw
;
766 struct brw_cache_item
**items
;
768 GLuint size
, n_items
;
770 uint32_t next_offset
;
774 * Optional functions used in determining whether the prog_data for a new
775 * cache item matches an existing cache item (in case there's relevant data
776 * outside of the prog_data). If NULL, a plain memcmp is done.
778 cache_aux_compare_func aux_compare
[BRW_MAX_CACHE
];
779 /** Optional functions for freeing other pointers attached to a prog_data. */
780 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
784 /* Considered adding a member to this struct to document which flags
785 * an update might raise so that ordering of the state atoms can be
786 * checked or derived at runtime. Dropped the idea in favor of having
787 * a debug mode where the state is monitored for flags which are
788 * raised that have already been tested against.
790 struct brw_tracked_state
{
791 struct brw_state_flags dirty
;
792 void (*emit
)( struct brw_context
*brw
);
795 enum shader_time_shader_type
{
811 struct brw_vertex_buffer
{
812 /** Buffer object containing the uploaded vertex data */
815 /** Byte stride between elements in the uploaded array */
819 struct brw_vertex_element
{
820 const struct gl_client_array
*glarray
;
824 /** Offset of the first element within the buffer object */
828 struct brw_query_object
{
829 struct gl_query_object Base
;
831 /** Last query BO associated with this query. */
834 /** Last index in bo with query data for this object. */
838 struct intel_sync_object
{
839 struct gl_sync_object Base
;
841 /** Batch associated with this sync object */
851 struct intel_batchbuffer
{
852 /** Current batchbuffer being queued up. */
854 /** Last BO submitted to the hardware. Used for glFinish(). */
855 drm_intel_bo
*last_bo
;
856 /** BO for post-sync nonzero writes for gen6 workaround. */
857 drm_intel_bo
*workaround_bo
;
858 bool need_workaround_flush
;
860 uint16_t emit
, total
;
861 uint16_t used
, reserved_space
;
864 #define BATCH_SZ (8192*sizeof(uint32_t))
866 uint32_t state_batch_offset
;
867 enum brw_gpu_ring ring
;
868 bool needs_sol_reset
;
876 #define BRW_MAX_XFB_STREAMS 4
878 struct brw_transform_feedback_object
{
879 struct gl_transform_feedback_object base
;
881 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
882 drm_intel_bo
*offset_bo
;
884 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
887 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
888 GLenum primitive_mode
;
891 * Count of primitives generated during this transform feedback operation.
894 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
895 drm_intel_bo
*prim_count_bo
;
896 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
900 * Number of vertices written between last Begin/EndTransformFeedback().
902 * Used to implement DrawTransformFeedback().
904 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
905 bool vertices_written_valid
;
909 * Data shared between each programmable stage in the pipeline (vs, gs, and
912 struct brw_stage_state
914 gl_shader_stage stage
;
915 struct brw_stage_prog_data
*prog_data
;
918 * Optional scratch buffer used to store spilled register values and
919 * variably-indexed GRF arrays.
921 drm_intel_bo
*scratch_bo
;
923 /** Offset in the program cache to the program */
924 uint32_t prog_offset
;
926 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
927 uint32_t state_offset
;
929 uint32_t push_const_offset
; /* Offset in the batchbuffer */
930 int push_const_size
; /* in 256-bit register increments */
932 /* Binding table: pointers to SURFACE_STATE entries. */
933 uint32_t bind_bo_offset
;
934 uint32_t surf_offset
[BRW_MAX_SURFACES
];
936 /** SAMPLER_STATE count and table offset */
937 uint32_t sampler_count
;
938 uint32_t sampler_offset
;
943 * brw_context is derived from gl_context.
947 struct gl_context ctx
; /**< base class, must be first field */
951 void (*update_texture_surface
)(struct gl_context
*ctx
,
953 uint32_t *surf_offset
,
955 void (*update_renderbuffer_surface
)(struct brw_context
*brw
,
956 struct gl_renderbuffer
*rb
,
959 void (*update_null_renderbuffer_surface
)(struct brw_context
*brw
,
962 void (*create_raw_surface
)(struct brw_context
*brw
,
966 uint32_t *out_offset
,
968 void (*emit_buffer_surface_state
)(struct brw_context
*brw
,
969 uint32_t *out_offset
,
971 unsigned buffer_offset
,
972 unsigned surface_format
,
973 unsigned buffer_size
,
979 * Send the appropriate state packets to configure depth, stencil, and
980 * HiZ buffers (i965+ only)
982 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
983 struct intel_mipmap_tree
*depth_mt
,
984 uint32_t depth_offset
,
985 uint32_t depthbuffer_format
,
986 uint32_t depth_surface_type
,
987 struct intel_mipmap_tree
*stencil_mt
,
988 bool hiz
, bool separate_stencil
,
989 uint32_t width
, uint32_t height
,
990 uint32_t tile_x
, uint32_t tile_y
);
996 drm_intel_context
*hw_ctx
;
999 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
1000 * and would need flushing before being used from another cache domain that
1001 * isn't coherent with it (i.e. the sampler).
1003 struct set
*render_cache
;
1006 * Number of resets observed in the system at context creation.
1008 * This is tracked in the context so that we can determine that another
1009 * reset has occured.
1011 uint32_t reset_count
;
1013 struct intel_batchbuffer batch
;
1018 uint32_t next_offset
;
1022 * Set if rendering has occured to the drawable's front buffer.
1024 * This is used in the DRI2 case to detect that glFlush should also copy
1025 * the contents of the fake front buffer to the real front buffer.
1027 bool front_buffer_dirty
;
1029 /** Framerate throttling: @{ */
1030 drm_intel_bo
*first_post_swapbuffers_batch
;
1041 bool always_flush_batch
;
1042 bool always_flush_cache
;
1043 bool disable_throttling
;
1046 driOptionCache optionCache
;
1049 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
1051 GLenum reduced_primitive
;
1054 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
1055 * variable is set, this is the flag indicating to do expensive work that
1056 * might lead to a perf_debug() call.
1060 uint32_t max_gtt_map_object_size
;
1071 bool has_separate_stencil
;
1072 bool must_use_separate_stencil
;
1075 bool has_surface_tile_offset
;
1077 bool has_negative_rhw_bug
;
1083 * Some versions of Gen hardware don't do centroid interpolation correctly
1084 * on unlit pixels, causing incorrect values for derivatives near triangle
1085 * edges. Enabling this flag causes the fragment shader to use
1086 * non-centroid interpolation for unlit pixels, at the expense of two extra
1087 * fragment shader instructions.
1089 bool needs_unlit_centroid_workaround
;
1093 struct brw_state_flags dirty
;
1096 struct brw_cache cache
;
1098 /** IDs for meta stencil blit shader programs. */
1099 unsigned meta_stencil_blit_programs
[2];
1101 /* Whether a meta-operation is in progress. */
1102 bool meta_in_progress
;
1104 /* Whether the last depth/stencil packets were both NULL. */
1105 bool no_depth_or_stencil
;
1107 /* The last PMA stall bits programmed. */
1108 uint32_t pma_stall_bits
;
1111 /** Does the current draw use the index buffer? */
1114 int start_vertex_location
;
1115 int base_vertex_location
;
1118 * Buffer and offset used for GL_ARB_shader_draw_parameters
1119 * (for now, only gl_BaseVertex).
1121 drm_intel_bo
*draw_params_bo
;
1122 uint32_t draw_params_offset
;
1126 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
1127 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
1129 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
1133 /* Summary of size and varying of active arrays, so we can check
1134 * for changes to this state:
1136 unsigned int min_index
, max_index
;
1138 /* Offset from start of vertex buffer so we can avoid redefining
1139 * the same VB packed over and over again.
1141 unsigned int start_vertex_bias
;
1146 * Index buffer for this draw_prims call.
1148 * Updates are signaled by BRW_NEW_INDICES.
1150 const struct _mesa_index_buffer
*ib
;
1152 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
1156 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
1157 * avoid re-uploading the IB packet over and over if we're actually
1158 * referencing the same index buffer.
1160 unsigned int start_vertex_offset
;
1163 /* Active vertex program:
1165 const struct gl_vertex_program
*vertex_program
;
1166 const struct gl_geometry_program
*geometry_program
;
1167 const struct gl_fragment_program
*fragment_program
;
1170 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
1171 * that we don't have to reemit that state every time we change FBOs.
1176 * Platform specific constants containing the maximum number of threads
1177 * for each pipeline stage.
1183 /* BRW_NEW_URB_ALLOCATIONS:
1186 GLuint vsize
; /* vertex size plus header in urb registers */
1187 GLuint gsize
; /* GS output size in urb registers */
1188 GLuint csize
; /* constant buffer size in urb registers */
1189 GLuint sfsize
; /* setup data size in urb registers */
1193 GLuint min_vs_entries
; /* Minimum number of VS entries */
1194 GLuint max_vs_entries
; /* Maximum number of VS entries */
1195 GLuint max_gs_entries
; /* Maximum number of GS entries */
1197 GLuint nr_vs_entries
;
1198 GLuint nr_gs_entries
;
1199 GLuint nr_clip_entries
;
1200 GLuint nr_sf_entries
;
1201 GLuint nr_cs_entries
;
1208 GLuint size
; /* Hardware URB size, in KB. */
1210 /* True if the most recently sent _3DSTATE_URB message allocated
1211 * URB space for the GS.
1217 /* BRW_NEW_CURBE_OFFSETS:
1220 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1221 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1229 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1230 * for upload to the CURBE.
1232 drm_intel_bo
*curbe_bo
;
1233 /** Offset within curbe_bo of space for current curbe entry */
1234 GLuint curbe_offset
;
1238 * Layout of vertex data exiting the vertex shader.
1240 * BRW_NEW_VUE_MAP_VS is flagged when this VUE map changes.
1242 struct brw_vue_map vue_map_vs
;
1245 * Layout of vertex data exiting the geometry portion of the pipleine.
1246 * This comes from the geometry shader if one exists, otherwise from the
1249 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1251 struct brw_vue_map vue_map_geom_out
;
1254 struct brw_stage_state base
;
1255 struct brw_vs_prog_data
*prog_data
;
1259 struct brw_stage_state base
;
1260 struct brw_gs_prog_data
*prog_data
;
1263 * True if the 3DSTATE_GS command most recently emitted to the 3D
1264 * pipeline enabled the GS; false otherwise.
1270 struct brw_ff_gs_prog_data
*prog_data
;
1273 /** Offset in the program cache to the CLIP program pre-gen6 */
1274 uint32_t prog_offset
;
1275 uint32_t state_offset
;
1277 uint32_t bind_bo_offset
;
1279 * Surface offsets for the binding table. We only need surfaces to
1280 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1281 * need in this case.
1283 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1287 struct brw_clip_prog_data
*prog_data
;
1289 /** Offset in the program cache to the CLIP program pre-gen6 */
1290 uint32_t prog_offset
;
1292 /* Offset in the batch to the CLIP state on pre-gen6. */
1293 uint32_t state_offset
;
1295 /* As of gen6, this is the offset in the batch to the CLIP VP,
1303 struct brw_sf_prog_data
*prog_data
;
1305 /** Offset in the program cache to the CLIP program pre-gen6 */
1306 uint32_t prog_offset
;
1307 uint32_t state_offset
;
1309 bool viewport_transform_enable
;
1313 struct brw_stage_state base
;
1314 struct brw_wm_prog_data
*prog_data
;
1319 * Buffer object used in place of multisampled null render targets on
1320 * Gen6. See brw_update_null_renderbuffer_surface().
1322 drm_intel_bo
*multisampled_null_render_target_bo
;
1323 uint32_t fast_clear_op
;
1328 uint32_t state_offset
;
1329 uint32_t blend_state_offset
;
1330 uint32_t depth_stencil_state_offset
;
1335 struct brw_query_object
*obj
;
1340 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1341 const int *statistics_registers
;
1343 /** The number of active monitors using OA counters. */
1347 * A buffer object storing OA counter snapshots taken at the start and
1348 * end of each batch (creating "bookends" around the batch).
1350 drm_intel_bo
*bookend_bo
;
1352 /** The number of snapshots written to bookend_bo. */
1353 int bookend_snapshots
;
1356 * An array of monitors whose results haven't yet been assembled based on
1357 * the data in buffer objects.
1359 * These may be active, or have already ended. However, the results
1360 * have not been requested.
1362 struct brw_perf_monitor_object
**unresolved
;
1363 int unresolved_elements
;
1364 int unresolved_array_size
;
1367 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1368 * the counter which MI_REPORT_PERF_COUNT stores there.
1370 const int *oa_snapshot_layout
;
1372 /** Number of 32-bit entries in a hardware counter snapshot. */
1373 int entries_per_oa_snapshot
;
1377 const struct brw_tracked_state
**atoms
;
1379 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1383 enum aub_state_struct_type type
;
1384 } *state_batch_list
;
1385 int state_batch_count
;
1387 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1388 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1390 /* Interpolation modes, one byte per vue slot.
1391 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1393 struct interpolation_mode_map interpolation_mode
;
1395 /* PrimitiveRestart */
1398 bool enable_cut_index
;
1401 /** Computed depth/stencil/hiz state from the current attached
1402 * renderbuffers, valid only during the drawing state upload loop after
1403 * brw_workaround_depthstencil_alignment().
1406 struct intel_mipmap_tree
*depth_mt
;
1407 struct intel_mipmap_tree
*stencil_mt
;
1409 /* Inter-tile (page-aligned) byte offsets. */
1410 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1411 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1412 uint32_t tile_x
, tile_y
;
1415 uint32_t num_instances
;
1420 struct gl_shader_program
**shader_programs
;
1421 struct gl_program
**programs
;
1422 enum shader_time_shader_type
*types
;
1423 uint64_t *cumulative
;
1429 struct brw_fast_clear_state
*fast_clear_state
;
1431 __DRIcontext
*driContext
;
1432 struct intel_screen
*intelScreen
;
1435 /*======================================================================
1438 void brwInitVtbl( struct brw_context
*brw
);
1441 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1443 /*======================================================================
1446 extern const char *const brw_vendor_string
;
1448 extern const char *brw_get_renderer_string(unsigned deviceID
);
1451 DRI_CONF_BO_REUSE_DISABLED
,
1452 DRI_CONF_BO_REUSE_ALL
1455 void intel_update_renderbuffers(__DRIcontext
*context
,
1456 __DRIdrawable
*drawable
);
1457 void intel_prepare_render(struct brw_context
*brw
);
1459 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1460 __DRIdrawable
*drawable
);
1462 GLboolean
brwCreateContext(gl_api api
,
1463 const struct gl_config
*mesaVis
,
1464 __DRIcontext
*driContextPriv
,
1465 unsigned major_version
,
1466 unsigned minor_version
,
1470 void *sharedContextPrivate
);
1472 /*======================================================================
1475 GLuint
brw_get_rb_for_slice(struct brw_context
*brw
,
1476 struct intel_mipmap_tree
*mt
,
1477 unsigned level
, unsigned layer
, bool flat
);
1479 void brw_meta_updownsample(struct brw_context
*brw
,
1480 struct intel_mipmap_tree
*src
,
1481 struct intel_mipmap_tree
*dst
);
1483 void brw_meta_fbo_stencil_blit(struct brw_context
*brw
,
1484 GLfloat srcX0
, GLfloat srcY0
,
1485 GLfloat srcX1
, GLfloat srcY1
,
1486 GLfloat dstX0
, GLfloat dstY0
,
1487 GLfloat dstX1
, GLfloat dstY1
);
1489 void brw_meta_stencil_updownsample(struct brw_context
*brw
,
1490 struct intel_mipmap_tree
*src
,
1491 struct intel_mipmap_tree
*dst
);
1493 bool brw_meta_fast_clear(struct brw_context
*brw
,
1494 struct gl_framebuffer
*fb
,
1496 bool partial_clear
);
1499 brw_meta_resolve_color(struct brw_context
*brw
,
1500 struct intel_mipmap_tree
*mt
);
1502 brw_meta_fast_clear_free(struct brw_context
*brw
);
1505 /*======================================================================
1508 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1509 uint32_t depth_level
,
1510 uint32_t depth_layer
,
1511 struct intel_mipmap_tree
*stencil_mt
,
1512 uint32_t *out_tile_mask_x
,
1513 uint32_t *out_tile_mask_y
);
1514 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1515 GLbitfield clear_mask
);
1517 /* brw_object_purgeable.c */
1518 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1520 /*======================================================================
1523 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1524 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1525 void brw_emit_query_begin(struct brw_context
*brw
);
1526 void brw_emit_query_end(struct brw_context
*brw
);
1528 /** gen6_queryobj.c */
1529 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1530 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1531 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1532 void brw_store_register_mem64(struct brw_context
*brw
,
1533 drm_intel_bo
*bo
, uint32_t reg
, int idx
);
1535 /** intel_batchbuffer.c */
1536 void brw_load_register_mem(struct brw_context
*brw
,
1539 uint32_t read_domains
, uint32_t write_domain
,
1542 /*======================================================================
1545 void brw_debug_batch(struct brw_context
*brw
);
1546 void brw_annotate_aub(struct brw_context
*brw
);
1548 /*======================================================================
1551 void brw_validate_textures( struct brw_context
*brw
);
1554 /*======================================================================
1557 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1559 int brw_get_scratch_size(int size
);
1560 void brw_get_scratch_bo(struct brw_context
*brw
,
1561 drm_intel_bo
**scratch_bo
, int size
);
1562 void brw_init_shader_time(struct brw_context
*brw
);
1563 int brw_get_shader_time_index(struct brw_context
*brw
,
1564 struct gl_shader_program
*shader_prog
,
1565 struct gl_program
*prog
,
1566 enum shader_time_shader_type type
);
1567 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1568 void brw_destroy_shader_time(struct brw_context
*brw
);
1572 void brw_upload_urb_fence(struct brw_context
*brw
);
1576 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1578 /* brw_fs_reg_allocate.cpp
1580 void brw_fs_alloc_reg_sets(struct intel_screen
*screen
);
1582 /* brw_vec4_reg_allocate.cpp */
1583 void brw_vec4_alloc_reg_set(struct intel_screen
*screen
);
1586 int brw_disassemble_inst(FILE *file
, struct brw_context
*brw
,
1587 struct brw_inst
*inst
, bool is_compacted
);
1590 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1592 /* brw_draw_upload.c */
1593 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1594 const struct gl_client_array
*glarray
);
1595 unsigned brw_get_index_type(GLenum type
);
1596 void brw_prepare_vertices(struct brw_context
*brw
);
1598 /* brw_wm_surface_state.c */
1599 void brw_init_surface_formats(struct brw_context
*brw
);
1600 void brw_create_constant_surface(struct brw_context
*brw
,
1604 uint32_t *out_offset
,
1606 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1608 uint32_t *surf_offset
);
1610 brw_update_sol_surface(struct brw_context
*brw
,
1611 struct gl_buffer_object
*buffer_obj
,
1612 uint32_t *out_offset
, unsigned num_vector_components
,
1613 unsigned stride_dwords
, unsigned offset_dwords
);
1614 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1615 struct gl_shader
*shader
,
1616 struct brw_stage_state
*stage_state
,
1617 struct brw_stage_prog_data
*prog_data
);
1618 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1619 struct gl_shader_program
*prog
,
1620 struct brw_stage_state
*stage_state
,
1621 struct brw_stage_prog_data
*prog_data
);
1623 /* brw_surface_formats.c */
1624 bool brw_is_hiz_depth_format(struct brw_context
*ctx
, mesa_format format
);
1625 bool brw_render_target_supported(struct brw_context
*brw
,
1626 struct gl_renderbuffer
*rb
);
1627 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1629 /* brw_performance_monitor.c */
1630 void brw_init_performance_monitors(struct brw_context
*brw
);
1631 void brw_dump_perf_monitors(struct brw_context
*brw
);
1632 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1633 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1635 /* intel_buffer_objects.c */
1636 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1637 const char *bo_name
);
1638 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1639 const char *bo_name
);
1641 /* intel_extensions.c */
1642 extern void intelInitExtensions(struct gl_context
*ctx
);
1645 extern int intel_translate_shadow_compare_func(GLenum func
);
1646 extern int intel_translate_compare_func(GLenum func
);
1647 extern int intel_translate_stencil_op(GLenum op
);
1648 extern int intel_translate_logic_op(GLenum opcode
);
1650 /* intel_syncobj.c */
1651 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1654 struct gl_transform_feedback_object
*
1655 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1657 brw_delete_transform_feedback(struct gl_context
*ctx
,
1658 struct gl_transform_feedback_object
*obj
);
1660 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1661 struct gl_transform_feedback_object
*obj
);
1663 brw_end_transform_feedback(struct gl_context
*ctx
,
1664 struct gl_transform_feedback_object
*obj
);
1666 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1667 struct gl_transform_feedback_object
*obj
,
1670 /* gen7_sol_state.c */
1672 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1673 struct gl_transform_feedback_object
*obj
);
1675 gen7_end_transform_feedback(struct gl_context
*ctx
,
1676 struct gl_transform_feedback_object
*obj
);
1678 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1679 struct gl_transform_feedback_object
*obj
);
1681 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1682 struct gl_transform_feedback_object
*obj
);
1684 /* brw_blorp_blit.cpp */
1686 brw_blorp_framebuffer(struct brw_context
*brw
,
1687 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1688 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1689 GLbitfield mask
, GLenum filter
);
1692 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1693 struct gl_renderbuffer
*src_rb
,
1694 struct gl_texture_image
*dst_image
,
1696 int srcX0
, int srcY0
,
1697 int dstX0
, int dstY0
,
1698 int width
, int height
);
1700 /* gen6_multisample_state.c */
1702 gen6_determine_sample_mask(struct brw_context
*brw
);
1705 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1706 unsigned num_samples
);
1708 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1710 gen6_get_sample_position(struct gl_context
*ctx
,
1711 struct gl_framebuffer
*fb
,
1715 gen6_set_sample_maps(struct gl_context
*ctx
);
1717 /* gen8_multisample_state.c */
1718 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1719 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1723 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1724 unsigned gs_size
, unsigned fs_size
);
1727 gen7_emit_urb_state(struct brw_context
*brw
,
1728 unsigned nr_vs_entries
, unsigned vs_size
,
1729 unsigned vs_start
, unsigned nr_gs_entries
,
1730 unsigned gs_size
, unsigned gs_start
);
1735 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1737 /*======================================================================
1738 * Inline conversion functions. These are better-typed than the
1739 * macros used previously:
1741 static inline struct brw_context
*
1742 brw_context( struct gl_context
*ctx
)
1744 return (struct brw_context
*)ctx
;
1747 static inline struct brw_vertex_program
*
1748 brw_vertex_program(struct gl_vertex_program
*p
)
1750 return (struct brw_vertex_program
*) p
;
1753 static inline const struct brw_vertex_program
*
1754 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1756 return (const struct brw_vertex_program
*) p
;
1759 static inline struct brw_geometry_program
*
1760 brw_geometry_program(struct gl_geometry_program
*p
)
1762 return (struct brw_geometry_program
*) p
;
1765 static inline struct brw_fragment_program
*
1766 brw_fragment_program(struct gl_fragment_program
*p
)
1768 return (struct brw_fragment_program
*) p
;
1771 static inline const struct brw_fragment_program
*
1772 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1774 return (const struct brw_fragment_program
*) p
;
1778 * Pre-gen6, the register file of the EUs was shared between threads,
1779 * and each thread used some subset allocated on a 16-register block
1780 * granularity. The unit states wanted these block counts.
1783 brw_register_blocks(int reg_count
)
1785 return ALIGN(reg_count
, 16) / 16 - 1;
1788 static inline uint32_t
1789 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1790 uint32_t prog_offset
)
1792 if (brw
->gen
>= 5) {
1793 /* Using state base address. */
1797 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1801 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1803 return brw
->cache
.bo
->offset64
+ prog_offset
;
1806 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1807 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1808 struct exec_list
*instructions
);
1809 bool brw_do_lower_unnormalized_offset(struct exec_list
*instructions
);
1811 struct opcode_desc
{
1817 extern const struct opcode_desc opcode_descs
[128];
1818 extern const char * const conditional_modifier
[16];
1821 brw_emit_depthbuffer(struct brw_context
*brw
);
1824 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1825 struct intel_mipmap_tree
*depth_mt
,
1826 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1827 uint32_t depth_surface_type
,
1828 struct intel_mipmap_tree
*stencil_mt
,
1829 bool hiz
, bool separate_stencil
,
1830 uint32_t width
, uint32_t height
,
1831 uint32_t tile_x
, uint32_t tile_y
);
1834 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1835 struct intel_mipmap_tree
*depth_mt
,
1836 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1837 uint32_t depth_surface_type
,
1838 struct intel_mipmap_tree
*stencil_mt
,
1839 bool hiz
, bool separate_stencil
,
1840 uint32_t width
, uint32_t height
,
1841 uint32_t tile_x
, uint32_t tile_y
);
1844 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1845 struct intel_mipmap_tree
*depth_mt
,
1846 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1847 uint32_t depth_surface_type
,
1848 struct intel_mipmap_tree
*stencil_mt
,
1849 bool hiz
, bool separate_stencil
,
1850 uint32_t width
, uint32_t height
,
1851 uint32_t tile_x
, uint32_t tile_y
);
1853 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1854 struct intel_mipmap_tree
*depth_mt
,
1855 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1856 uint32_t depth_surface_type
,
1857 struct intel_mipmap_tree
*stencil_mt
,
1858 bool hiz
, bool separate_stencil
,
1859 uint32_t width
, uint32_t height
,
1860 uint32_t tile_x
, uint32_t tile_y
);
1862 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1863 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);
1865 uint32_t get_hw_prim_for_gl_prim(int mode
);
1868 brw_setup_vec4_key_clip_info(struct brw_context
*brw
,
1869 struct brw_vec4_prog_key
*key
,
1870 bool program_uses_clip_distance
);
1873 gen6_upload_push_constants(struct brw_context
*brw
,
1874 const struct gl_program
*prog
,
1875 const struct brw_stage_prog_data
*prog_data
,
1876 struct brw_stage_state
*stage_state
,
1877 enum aub_state_struct_type type
);
1879 /* ================================================================
1880 * From linux kernel i386 header files, copes with odd sizes better
1881 * than COPY_DWORDS would:
1882 * XXX Put this in src/mesa/main/imports.h ???
1884 #if defined(i386) || defined(__i386__)
1885 static inline void * __memcpy(void * to
, const void * from
, size_t n
)
1888 __asm__
__volatile__(
1893 "1:\ttestb $1,%b4\n\t"
1897 : "=&c" (d0
), "=&D" (d1
), "=&S" (d2
)
1898 :"0" (n
/4), "q" (n
),"1" ((long) to
),"2" ((long) from
)
1903 #define __memcpy(a,b,c) memcpy(a,b,c)