2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
38 #include "main/imports.h"
39 #include "main/macros.h"
41 #include "main/mtypes.h"
42 #include "brw_structs.h"
43 #include "intel_aub.h"
44 #include "program/prog_parameter.h"
48 /* Evil hack for using libdrm in a c++ compiler. */
53 #include <intel_bufmgr.h>
63 #include "intel_debug.h"
64 #include "intel_screen.h"
65 #include "intel_tex_obj.h"
66 #include "intel_resolve_map.h"
70 * URB - uniform resource buffer. A mid-sized buffer which is
71 * partitioned between the fixed function units and used for passing
72 * values (vertices, primitives, constants) between them.
74 * CURBE - constant URB entry. An urb region (entry) used to hold
75 * constant values which the fixed function units can be instructed to
76 * preload into the GRF when spawning a thread.
78 * VUE - vertex URB entry. An urb entry holding a vertex and usually
79 * a vertex header. The header contains control information and
80 * things like primitive type, Begin/end flags and clip codes.
82 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
83 * unit holding rasterization and interpolation parameters.
85 * GRF - general register file. One of several register files
86 * addressable by programmed threads. The inputs (r0, payload, curbe,
87 * urb) of the thread are preloaded to this area before the thread is
88 * spawned. The registers are individually 8 dwords wide and suitable
89 * for general usage. Registers holding thread input values are not
90 * special and may be overwritten.
92 * MRF - message register file. Threads communicate (and terminate)
93 * by sending messages. Message parameters are placed in contiguous
94 * MRF registers. All program output is via these messages. URB
95 * entries are populated by sending a message to the shared URB
96 * function containing the new data, together with a control word,
97 * often an unmodified copy of R0.
99 * R0 - GRF register 0. Typically holds control information used when
100 * sending messages to other threads.
102 * EU or GEN4 EU: The name of the programmable subsystem of the
103 * i965 hardware. Threads are executed by the EU, the registers
104 * described above are part of the EU architecture.
106 * Fixed function units:
108 * CS - Command streamer. Notional first unit, little software
109 * interaction. Holds the URB entries used for constant data, ie the
112 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
113 * this unit is responsible for pulling vertices out of vertex buffers
114 * in vram and injecting them into the processing pipe as VUEs. If
115 * enabled, it first passes them to a VS thread which is a good place
116 * for the driver to implement any active vertex shader.
118 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
119 * enabled, incoming strips etc are passed to GS threads in individual
120 * line/triangle/point units. The GS thread may perform arbitary
121 * computation and emit whatever primtives with whatever vertices it
122 * chooses. This makes GS an excellent place to implement GL's
123 * unfilled polygon modes, though of course it is capable of much
124 * more. Additionally, GS is used to translate away primitives not
125 * handled by latter units, including Quads and Lineloops.
127 * CS - Clipper. Mesa's clipping algorithms are imported to run on
128 * this unit. The fixed function part performs cliptesting against
129 * the 6 fixed clipplanes and makes descisions on whether or not the
130 * incoming primitive needs to be passed to a thread for clipping.
131 * User clip planes are handled via cooperation with the VS thread.
133 * SF - Strips Fans or Setup: Triangles are prepared for
134 * rasterization. Interpolation coefficients are calculated.
135 * Flatshading and two-side lighting usually performed here.
137 * WM - Windower. Interpolation of vertex attributes performed here.
138 * Fragment shader implemented here. SIMD aspects of EU taken full
139 * advantage of, as pixels are processed in blocks of 16.
141 * CC - Color Calculator. No EU threads associated with this unit.
142 * Handles blending and (presumably) depth and stencil testing.
147 struct brw_vs_prog_key
;
148 struct brw_vue_prog_key
;
149 struct brw_wm_prog_key
;
150 struct brw_wm_prog_data
;
154 BRW_COMPUTE_PIPELINE
,
161 BRW_CACHE_BLORP_BLIT_PROG
,
164 BRW_CACHE_FF_GS_PROG
,
172 /* brw_cache_ids must come first - see brw_state_cache.c */
173 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
174 BRW_STATE_FRAGMENT_PROGRAM
,
175 BRW_STATE_GEOMETRY_PROGRAM
,
176 BRW_STATE_VERTEX_PROGRAM
,
177 BRW_STATE_CURBE_OFFSETS
,
178 BRW_STATE_REDUCED_PRIMITIVE
,
183 BRW_STATE_VS_BINDING_TABLE
,
184 BRW_STATE_GS_BINDING_TABLE
,
185 BRW_STATE_PS_BINDING_TABLE
,
189 BRW_STATE_INDEX_BUFFER
,
190 BRW_STATE_VS_CONSTBUF
,
191 BRW_STATE_GS_CONSTBUF
,
192 BRW_STATE_PROGRAM_CACHE
,
193 BRW_STATE_STATE_BASE_ADDRESS
,
194 BRW_STATE_VUE_MAP_VS
,
195 BRW_STATE_VUE_MAP_GEOM_OUT
,
196 BRW_STATE_TRANSFORM_FEEDBACK
,
197 BRW_STATE_RASTERIZER_DISCARD
,
199 BRW_STATE_UNIFORM_BUFFER
,
200 BRW_STATE_ATOMIC_BUFFER
,
201 BRW_STATE_META_IN_PROGRESS
,
202 BRW_STATE_INTERPOLATION_MAP
,
203 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
204 BRW_STATE_NUM_SAMPLES
,
205 BRW_STATE_TEXTURE_BUFFER
,
206 BRW_STATE_GEN4_UNIT_STATE
,
210 BRW_STATE_SAMPLER_STATE_TABLE
,
211 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
216 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
218 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
219 * When the currently bound shader program differs from the previous draw
220 * call, these will be flagged. They cover brw->{stage}_program and
221 * ctx->{Stage}Program->_Current.
223 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
224 * driver perspective. Even if the same shader is bound at the API level,
225 * we may need to switch between multiple versions of that shader to handle
226 * changes in non-orthagonal state.
228 * Additionally, multiple shader programs may have identical vertex shaders
229 * (for example), or compile down to the same code in the backend. We combine
230 * those into a single program cache entry.
232 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
233 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
235 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
236 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
237 * use the normal state upload paths), but the cache is still used. To avoid
238 * polluting the brw_state_cache code with special cases, we retain the dirty
239 * bit for now. It should eventually be removed.
241 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_BLIT_PROG)
242 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
243 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
244 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
245 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
246 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
247 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
248 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
249 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
250 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
251 #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
252 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
253 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
254 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
255 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
256 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
257 #define BRW_NEW_VS_BINDING_TABLE (1ull << BRW_STATE_VS_BINDING_TABLE)
258 #define BRW_NEW_GS_BINDING_TABLE (1ull << BRW_STATE_GS_BINDING_TABLE)
259 #define BRW_NEW_PS_BINDING_TABLE (1ull << BRW_STATE_PS_BINDING_TABLE)
260 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
261 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
263 * Used for any batch entry with a relocated pointer that will be used
264 * by any 3D rendering.
266 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
267 /** \see brw.state.depth_region */
268 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
269 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
270 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
271 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
272 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
273 #define BRW_NEW_VUE_MAP_VS (1ull << BRW_STATE_VUE_MAP_VS)
274 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
275 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
276 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
277 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
278 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
279 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
280 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
281 #define BRW_NEW_INTERPOLATION_MAP (1ull << BRW_STATE_INTERPOLATION_MAP)
282 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
283 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
284 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
285 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
286 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
287 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
288 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
289 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
290 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
292 struct brw_state_flags
{
293 /** State update flags signalled by mesa internals */
296 * State update flags signalled as the result of brw_tracked_state updates
301 /** Subclass of Mesa vertex program */
302 struct brw_vertex_program
{
303 struct gl_vertex_program program
;
308 /** Subclass of Mesa geometry program */
309 struct brw_geometry_program
{
310 struct gl_geometry_program program
;
311 unsigned id
; /**< serial no. to identify geom progs, never re-used */
315 /** Subclass of Mesa fragment program */
316 struct brw_fragment_program
{
317 struct gl_fragment_program program
;
318 GLuint id
; /**< serial no. to identify frag progs, never re-used */
322 /** Subclass of Mesa compute program */
323 struct brw_compute_program
{
324 struct gl_compute_program program
;
325 unsigned id
; /**< serial no. to identify compute progs, never re-used */
330 struct gl_shader base
;
335 /* Note: If adding fields that need anything besides a normal memcmp() for
336 * comparing them, be sure to go fix brw_stage_prog_data_compare().
338 struct brw_stage_prog_data
{
340 /** size of our binding table. */
344 * surface indices for the various groups of surfaces
346 uint32_t pull_constants_start
;
347 uint32_t texture_start
;
348 uint32_t gather_texture_start
;
351 uint32_t image_start
;
352 uint32_t shader_time_start
;
356 GLuint nr_params
; /**< number of float params/constants */
357 GLuint nr_pull_params
;
359 unsigned curb_read_length
;
360 unsigned total_scratch
;
363 * Register where the thread expects to find input data from the URB
364 * (typically uniforms, followed by vertex or fragment attributes).
366 unsigned dispatch_grf_start_reg
;
368 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
370 /* Pointers to tracked values (only valid once
371 * _mesa_load_state_parameters has been called at runtime).
373 * These must be the last fields of the struct (see
374 * brw_stage_prog_data_compare()).
376 const gl_constant_value
**param
;
377 const gl_constant_value
**pull_param
;
380 /* Data about a particular attempt to compile a program. Note that
381 * there can be many of these, each in a different GL state
382 * corresponding to a different brw_wm_prog_key struct, with different
385 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
388 struct brw_wm_prog_data
{
389 struct brw_stage_prog_data base
;
391 GLuint num_varying_inputs
;
393 GLuint dispatch_grf_start_reg_16
;
395 GLuint reg_blocks_16
;
399 * surface indices the WM-specific surfaces
401 uint32_t render_target_start
;
405 uint8_t computed_depth_mode
;
409 bool uses_pos_offset
;
412 uint32_t prog_offset_16
;
415 * Mask of which interpolation modes are required by the fragment shader.
416 * Used in hardware setup on gen6+.
418 uint32_t barycentric_interp_modes
;
421 * Map from gl_varying_slot to the position within the FS setup data
422 * payload where the varying's attribute vertex deltas should be delivered.
423 * For varying slots that are not used by the FS, the value is -1.
425 int urb_setup
[VARYING_SLOT_MAX
];
429 * Enum representing the i965-specific vertex results that don't correspond
430 * exactly to any element of gl_varying_slot. The values of this enum are
431 * assigned such that they don't conflict with gl_varying_slot.
435 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
436 BRW_VARYING_SLOT_PAD
,
438 * Technically this is not a varying but just a placeholder that
439 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
440 * builtin variable to be compiled correctly. see compile_sf_prog() for
443 BRW_VARYING_SLOT_PNTC
,
444 BRW_VARYING_SLOT_COUNT
449 * Data structure recording the relationship between the gl_varying_slot enum
450 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
451 * single octaword within the VUE (128 bits).
453 * Note that each BRW register contains 256 bits (2 octawords), so when
454 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
455 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
456 * in a vertex shader), each register corresponds to a single VUE slot, since
457 * it contains data for two separate vertices.
461 * Bitfield representing all varying slots that are (a) stored in this VUE
462 * map, and (b) actually written by the shader. Does not include any of
463 * the additional varying slots defined in brw_varying_slot.
465 GLbitfield64 slots_valid
;
468 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
469 * not stored in a slot (because they are not written, or because
470 * additional processing is applied before storing them in the VUE), the
473 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
476 * Map from VUE slot to gl_varying_slot value. For slots that do not
477 * directly correspond to a gl_varying_slot, the value comes from
480 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
481 * simplifies code that uses the value stored in slot_to_varying to
482 * create a bit mask).
484 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
487 * Total number of VUE slots in use
493 * Convert a VUE slot number into a byte offset within the VUE.
495 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
501 * Convert a vertex output (brw_varying_slot) into a byte offset within the
504 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
507 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
510 void brw_compute_vue_map(struct brw_context
*brw
, struct brw_vue_map
*vue_map
,
511 GLbitfield64 slots_valid
);
515 * Bitmask indicating which fragment shader inputs represent varyings (and
516 * hence have to be delivered to the fragment shader by the SF/SBE stage).
518 #define BRW_FS_VARYING_INPUT_MASK \
519 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
520 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
524 * Mapping of VUE map slots to interpolation modes.
526 struct interpolation_mode_map
{
527 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
530 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
532 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
533 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
539 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
541 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
542 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
549 struct brw_sf_prog_data
{
550 GLuint urb_read_length
;
553 /* Each vertex may have upto 12 attributes, 4 components each,
554 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
557 * Actually we use 4 for each, so call it 12 rows.
559 GLuint urb_entry_size
;
564 * We always program SF to start reading at an offset of 1 (2 varying slots)
565 * from the start of the vertex URB entry. This causes it to skip:
566 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
567 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
569 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
572 struct brw_clip_prog_data
{
573 GLuint curb_read_length
; /* user planes? */
575 GLuint urb_read_length
;
579 struct brw_ff_gs_prog_data
{
580 GLuint urb_read_length
;
584 * Gen6 transform feedback: Amount by which the streaming vertex buffer
585 * indices should be incremented each time the GS is invoked.
587 unsigned svbi_postincrement_value
;
591 /* Note: brw_vue_prog_data_compare() must be updated when adding fields to
594 struct brw_vue_prog_data
{
595 struct brw_stage_prog_data base
;
596 struct brw_vue_map vue_map
;
598 GLuint urb_read_length
;
601 /* Used for calculating urb partitions. In the VS, this is the size of the
602 * URB entry used for both input and output to the thread. In the GS, this
603 * is the size of the URB entry used for output.
605 GLuint urb_entry_size
;
611 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
614 struct brw_vs_prog_data
{
615 struct brw_vue_prog_data base
;
617 GLbitfield64 inputs_read
;
620 bool uses_instanceid
;
623 /** Number of texture sampler units */
624 #define BRW_MAX_TEX_UNIT 32
626 /** Max number of render targets in a shader */
627 #define BRW_MAX_DRAW_BUFFERS 8
629 /** Max number of atomic counter buffer objects in a shader */
630 #define BRW_MAX_ABO 16
632 /** Max number of image uniforms in a shader */
633 #define BRW_MAX_IMAGES 32
636 * Max number of binding table entries used for stream output.
638 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
639 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
641 * On Gen6, the size of transform feedback data is limited not by the number
642 * of components but by the number of binding table entries we set aside. We
643 * use one binding table entry for a float, one entry for a vector, and one
644 * entry per matrix column. Since the only way we can communicate our
645 * transform feedback capabilities to the client is via
646 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
647 * worst case, in which all the varyings are floats, so we use up one binding
648 * table entry per component. Therefore we need to set aside at least 64
649 * binding table entries for use by transform feedback.
651 * Note: since we don't currently pack varyings, it is currently impossible
652 * for the client to actually use up all of these binding table entries--if
653 * all of their varyings were floats, they would run out of varying slots and
654 * fail to link. But that's a bug, so it seems prudent to go ahead and
655 * allocate the number of binding table entries we will need once the bug is
658 #define BRW_MAX_SOL_BINDINGS 64
660 /** Maximum number of actual buffers used for stream output */
661 #define BRW_MAX_SOL_BUFFERS 4
663 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
664 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
668 2 /* shader time, pull constants */)
670 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
672 /* Note: brw_gs_prog_data_compare() must be updated when adding fields to
675 struct brw_gs_prog_data
677 struct brw_vue_prog_data base
;
680 * Size of an output vertex, measured in HWORDS (32 bytes).
682 unsigned output_vertex_size_hwords
;
684 unsigned output_topology
;
687 * Size of the control data (cut bits or StreamID bits), in hwords (32
688 * bytes). 0 if there is no control data.
690 unsigned control_data_header_size_hwords
;
693 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
694 * if the control data is StreamID bits, or
695 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
696 * Ignored if control_data_header_size is 0.
698 unsigned control_data_format
;
700 bool include_primitive_id
;
705 * Dispatch mode, can be any of:
706 * GEN7_GS_DISPATCH_MODE_DUAL_OBJECT
707 * GEN7_GS_DISPATCH_MODE_DUAL_INSTANCE
708 * GEN7_GS_DISPATCH_MODE_SINGLE
713 * Gen6 transform feedback enabled flag.
715 bool gen6_xfb_enabled
;
718 * Gen6: Provoking vertex convention for odd-numbered triangles
724 * Gen6: Number of varyings that are output to transform feedback.
726 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
729 * Gen6: Map from the index of a transform feedback binding table entry to the
730 * gl_varying_slot that should be streamed out through that binding table
733 unsigned char transform_feedback_bindings
[BRW_MAX_SOL_BINDINGS
];
736 * Gen6: Map from the index of a transform feedback binding table entry to the
737 * swizzles that should be used when streaming out data through that
738 * binding table entry.
740 unsigned char transform_feedback_swizzles
[BRW_MAX_SOL_BINDINGS
];
744 * Stride in bytes between shader_time entries.
746 * We separate entries by a cacheline to reduce traffic between EUs writing to
749 #define SHADER_TIME_STRIDE 64
751 struct brw_cache_item
{
753 * Effectively part of the key, cache_id identifies what kind of state
754 * buffer is involved, and also which dirty flag should set.
756 enum brw_cache_id cache_id
;
757 /** 32-bit hash of the key data */
759 GLuint key_size
; /* for variable-sized keys */
766 struct brw_cache_item
*next
;
770 typedef bool (*cache_aux_compare_func
)(const void *a
, const void *b
);
771 typedef void (*cache_aux_free_func
)(const void *aux
);
774 struct brw_context
*brw
;
776 struct brw_cache_item
**items
;
778 GLuint size
, n_items
;
780 uint32_t next_offset
;
784 * Optional functions used in determining whether the prog_data for a new
785 * cache item matches an existing cache item (in case there's relevant data
786 * outside of the prog_data). If NULL, a plain memcmp is done.
788 cache_aux_compare_func aux_compare
[BRW_MAX_CACHE
];
789 /** Optional functions for freeing other pointers attached to a prog_data. */
790 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
794 /* Considered adding a member to this struct to document which flags
795 * an update might raise so that ordering of the state atoms can be
796 * checked or derived at runtime. Dropped the idea in favor of having
797 * a debug mode where the state is monitored for flags which are
798 * raised that have already been tested against.
800 struct brw_tracked_state
{
801 struct brw_state_flags dirty
;
802 void (*emit
)( struct brw_context
*brw
);
805 enum shader_time_shader_type
{
821 struct brw_vertex_buffer
{
822 /** Buffer object containing the uploaded vertex data */
825 /** Byte stride between elements in the uploaded array */
829 struct brw_vertex_element
{
830 const struct gl_client_array
*glarray
;
834 /** Offset of the first element within the buffer object */
838 struct brw_query_object
{
839 struct gl_query_object Base
;
841 /** Last query BO associated with this query. */
844 /** Last index in bo with query data for this object. */
847 /** True if we know the batch has been flushed since we ended the query. */
851 struct intel_sync_object
{
852 struct gl_sync_object Base
;
854 /** Batch associated with this sync object */
864 struct intel_batchbuffer
{
865 /** Current batchbuffer being queued up. */
867 /** Last BO submitted to the hardware. Used for glFinish(). */
868 drm_intel_bo
*last_bo
;
869 /** BO for post-sync nonzero writes for gen6 workaround. */
870 drm_intel_bo
*workaround_bo
;
872 uint16_t emit
, total
;
873 uint16_t used
, reserved_space
;
876 #define BATCH_SZ (8192*sizeof(uint32_t))
878 uint32_t state_batch_offset
;
879 enum brw_gpu_ring ring
;
880 bool needs_sol_reset
;
882 uint8_t pipe_controls_since_last_cs_stall
;
890 #define BRW_MAX_XFB_STREAMS 4
892 struct brw_transform_feedback_object
{
893 struct gl_transform_feedback_object base
;
895 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
896 drm_intel_bo
*offset_bo
;
898 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
901 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
902 GLenum primitive_mode
;
905 * Count of primitives generated during this transform feedback operation.
908 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
909 drm_intel_bo
*prim_count_bo
;
910 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
914 * Number of vertices written between last Begin/EndTransformFeedback().
916 * Used to implement DrawTransformFeedback().
918 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
919 bool vertices_written_valid
;
923 * Data shared between each programmable stage in the pipeline (vs, gs, and
926 struct brw_stage_state
928 gl_shader_stage stage
;
929 struct brw_stage_prog_data
*prog_data
;
932 * Optional scratch buffer used to store spilled register values and
933 * variably-indexed GRF arrays.
935 drm_intel_bo
*scratch_bo
;
937 /** Offset in the program cache to the program */
938 uint32_t prog_offset
;
940 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
941 uint32_t state_offset
;
943 uint32_t push_const_offset
; /* Offset in the batchbuffer */
944 int push_const_size
; /* in 256-bit register increments */
946 /* Binding table: pointers to SURFACE_STATE entries. */
947 uint32_t bind_bo_offset
;
948 uint32_t surf_offset
[BRW_MAX_SURFACES
];
950 /** SAMPLER_STATE count and table offset */
951 uint32_t sampler_count
;
952 uint32_t sampler_offset
;
957 * brw_context is derived from gl_context.
961 struct gl_context ctx
; /**< base class, must be first field */
965 void (*update_texture_surface
)(struct gl_context
*ctx
,
967 uint32_t *surf_offset
,
969 void (*update_renderbuffer_surface
)(struct brw_context
*brw
,
970 struct gl_renderbuffer
*rb
,
974 void (*emit_buffer_surface_state
)(struct brw_context
*brw
,
975 uint32_t *out_offset
,
977 unsigned buffer_offset
,
978 unsigned surface_format
,
979 unsigned buffer_size
,
982 void (*emit_null_surface_state
)(struct brw_context
*brw
,
986 uint32_t *out_offset
);
989 * Send the appropriate state packets to configure depth, stencil, and
990 * HiZ buffers (i965+ only)
992 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
993 struct intel_mipmap_tree
*depth_mt
,
994 uint32_t depth_offset
,
995 uint32_t depthbuffer_format
,
996 uint32_t depth_surface_type
,
997 struct intel_mipmap_tree
*stencil_mt
,
998 bool hiz
, bool separate_stencil
,
999 uint32_t width
, uint32_t height
,
1000 uint32_t tile_x
, uint32_t tile_y
);
1006 drm_intel_context
*hw_ctx
;
1009 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
1010 * and would need flushing before being used from another cache domain that
1011 * isn't coherent with it (i.e. the sampler).
1013 struct set
*render_cache
;
1016 * Number of resets observed in the system at context creation.
1018 * This is tracked in the context so that we can determine that another
1019 * reset has occured.
1021 uint32_t reset_count
;
1023 struct intel_batchbuffer batch
;
1028 uint32_t next_offset
;
1032 * Set if rendering has occured to the drawable's front buffer.
1034 * This is used in the DRI2 case to detect that glFlush should also copy
1035 * the contents of the fake front buffer to the real front buffer.
1037 bool front_buffer_dirty
;
1039 /** Framerate throttling: @{ */
1040 drm_intel_bo
*throttle_batch
[2];
1042 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
1043 * frame of rendering to complete. This gives a very precise cap to the
1044 * latency between input and output such that rendering never gets more
1045 * than a frame behind the user. (With the caveat that we technically are
1046 * not using the SwapBuffers itself as a barrier but the first batch
1047 * submitted afterwards, which may be immediately prior to the next
1050 bool need_swap_throttle
;
1052 /** General throttling, not caught by throttling between SwapBuffers */
1053 bool need_flush_throttle
;
1063 bool always_flush_batch
;
1064 bool always_flush_cache
;
1065 bool disable_throttling
;
1068 driOptionCache optionCache
;
1071 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
1073 GLenum reduced_primitive
;
1076 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
1077 * variable is set, this is the flag indicating to do expensive work that
1078 * might lead to a perf_debug() call.
1082 uint32_t max_gtt_map_object_size
;
1086 /* GT revision. This will be -1 if the revision couldn't be determined (eg,
1087 * if the kernel doesn't support the query).
1097 bool has_separate_stencil
;
1098 bool must_use_separate_stencil
;
1101 bool has_surface_tile_offset
;
1103 bool has_negative_rhw_bug
;
1110 * Some versions of Gen hardware don't do centroid interpolation correctly
1111 * on unlit pixels, causing incorrect values for derivatives near triangle
1112 * edges. Enabling this flag causes the fragment shader to use
1113 * non-centroid interpolation for unlit pixels, at the expense of two extra
1114 * fragment shader instructions.
1116 bool needs_unlit_centroid_workaround
;
1120 struct brw_state_flags dirty
;
1121 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
1124 struct brw_cache cache
;
1126 /** IDs for meta stencil blit shader programs. */
1127 unsigned meta_stencil_blit_programs
[2];
1129 /* Whether a meta-operation is in progress. */
1130 bool meta_in_progress
;
1132 /* Whether the last depth/stencil packets were both NULL. */
1133 bool no_depth_or_stencil
;
1135 /* The last PMA stall bits programmed. */
1136 uint32_t pma_stall_bits
;
1139 /** The value of gl_BaseVertex for the current _mesa_prim. */
1143 * Buffer and offset used for GL_ARB_shader_draw_parameters
1144 * (for now, only gl_BaseVertex).
1146 drm_intel_bo
*draw_params_bo
;
1147 uint32_t draw_params_offset
;
1151 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
1152 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
1154 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
1158 /* Summary of size and varying of active arrays, so we can check
1159 * for changes to this state:
1161 unsigned int min_index
, max_index
;
1163 /* Offset from start of vertex buffer so we can avoid redefining
1164 * the same VB packed over and over again.
1166 unsigned int start_vertex_bias
;
1169 * Certain vertex attribute formats aren't natively handled by the
1170 * hardware and require special VS code to fix up their values.
1172 * These bitfields indicate which workarounds are needed.
1174 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
1179 * Index buffer for this draw_prims call.
1181 * Updates are signaled by BRW_NEW_INDICES.
1183 const struct _mesa_index_buffer
*ib
;
1185 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
1189 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
1190 * avoid re-uploading the IB packet over and over if we're actually
1191 * referencing the same index buffer.
1193 unsigned int start_vertex_offset
;
1196 /* Active vertex program:
1198 const struct gl_vertex_program
*vertex_program
;
1199 const struct gl_geometry_program
*geometry_program
;
1200 const struct gl_fragment_program
*fragment_program
;
1203 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
1204 * that we don't have to reemit that state every time we change FBOs.
1209 * Platform specific constants containing the maximum number of threads
1210 * for each pipeline stage.
1218 /* BRW_NEW_URB_ALLOCATIONS:
1221 GLuint vsize
; /* vertex size plus header in urb registers */
1222 GLuint gsize
; /* GS output size in urb registers */
1223 GLuint csize
; /* constant buffer size in urb registers */
1224 GLuint sfsize
; /* setup data size in urb registers */
1228 GLuint min_vs_entries
; /* Minimum number of VS entries */
1229 GLuint max_vs_entries
; /* Maximum number of VS entries */
1230 GLuint max_hs_entries
; /* Maximum number of HS entries */
1231 GLuint max_ds_entries
; /* Maximum number of DS entries */
1232 GLuint max_gs_entries
; /* Maximum number of GS entries */
1234 GLuint nr_vs_entries
;
1235 GLuint nr_gs_entries
;
1236 GLuint nr_clip_entries
;
1237 GLuint nr_sf_entries
;
1238 GLuint nr_cs_entries
;
1245 GLuint size
; /* Hardware URB size, in KB. */
1247 /* True if the most recently sent _3DSTATE_URB message allocated
1248 * URB space for the GS.
1254 /* BRW_NEW_CURBE_OFFSETS:
1257 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1258 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1266 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1267 * for upload to the CURBE.
1269 drm_intel_bo
*curbe_bo
;
1270 /** Offset within curbe_bo of space for current curbe entry */
1271 GLuint curbe_offset
;
1275 * Layout of vertex data exiting the vertex shader.
1277 * BRW_NEW_VUE_MAP_VS is flagged when this VUE map changes.
1279 struct brw_vue_map vue_map_vs
;
1282 * Layout of vertex data exiting the geometry portion of the pipleine.
1283 * This comes from the geometry shader if one exists, otherwise from the
1286 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1288 struct brw_vue_map vue_map_geom_out
;
1291 struct brw_stage_state base
;
1292 struct brw_vs_prog_data
*prog_data
;
1296 struct brw_stage_state base
;
1297 struct brw_gs_prog_data
*prog_data
;
1300 * True if the 3DSTATE_GS command most recently emitted to the 3D
1301 * pipeline enabled the GS; false otherwise.
1307 struct brw_ff_gs_prog_data
*prog_data
;
1310 /** Offset in the program cache to the CLIP program pre-gen6 */
1311 uint32_t prog_offset
;
1312 uint32_t state_offset
;
1314 uint32_t bind_bo_offset
;
1316 * Surface offsets for the binding table. We only need surfaces to
1317 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1318 * need in this case.
1320 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1324 struct brw_clip_prog_data
*prog_data
;
1326 /** Offset in the program cache to the CLIP program pre-gen6 */
1327 uint32_t prog_offset
;
1329 /* Offset in the batch to the CLIP state on pre-gen6. */
1330 uint32_t state_offset
;
1332 /* As of gen6, this is the offset in the batch to the CLIP VP,
1340 struct brw_sf_prog_data
*prog_data
;
1342 /** Offset in the program cache to the CLIP program pre-gen6 */
1343 uint32_t prog_offset
;
1344 uint32_t state_offset
;
1346 bool viewport_transform_enable
;
1350 struct brw_stage_state base
;
1351 struct brw_wm_prog_data
*prog_data
;
1356 * Buffer object used in place of multisampled null render targets on
1357 * Gen6. See brw_emit_null_surface_state().
1359 drm_intel_bo
*multisampled_null_render_target_bo
;
1360 uint32_t fast_clear_op
;
1365 uint32_t state_offset
;
1366 uint32_t blend_state_offset
;
1367 uint32_t depth_stencil_state_offset
;
1372 struct brw_query_object
*obj
;
1377 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1378 const int *statistics_registers
;
1380 /** The number of active monitors using OA counters. */
1384 * A buffer object storing OA counter snapshots taken at the start and
1385 * end of each batch (creating "bookends" around the batch).
1387 drm_intel_bo
*bookend_bo
;
1389 /** The number of snapshots written to bookend_bo. */
1390 int bookend_snapshots
;
1393 * An array of monitors whose results haven't yet been assembled based on
1394 * the data in buffer objects.
1396 * These may be active, or have already ended. However, the results
1397 * have not been requested.
1399 struct brw_perf_monitor_object
**unresolved
;
1400 int unresolved_elements
;
1401 int unresolved_array_size
;
1404 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1405 * the counter which MI_REPORT_PERF_COUNT stores there.
1407 const int *oa_snapshot_layout
;
1409 /** Number of 32-bit entries in a hardware counter snapshot. */
1410 int entries_per_oa_snapshot
;
1413 int num_atoms
[BRW_NUM_PIPELINES
];
1414 const struct brw_tracked_state render_atoms
[57];
1415 const struct brw_tracked_state compute_atoms
[1];
1417 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1421 enum aub_state_struct_type type
;
1422 } *state_batch_list
;
1423 int state_batch_count
;
1425 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1426 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1428 /* Interpolation modes, one byte per vue slot.
1429 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1431 struct interpolation_mode_map interpolation_mode
;
1433 /* PrimitiveRestart */
1436 bool enable_cut_index
;
1439 /** Computed depth/stencil/hiz state from the current attached
1440 * renderbuffers, valid only during the drawing state upload loop after
1441 * brw_workaround_depthstencil_alignment().
1444 struct intel_mipmap_tree
*depth_mt
;
1445 struct intel_mipmap_tree
*stencil_mt
;
1447 /* Inter-tile (page-aligned) byte offsets. */
1448 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1449 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1450 uint32_t tile_x
, tile_y
;
1453 uint32_t num_instances
;
1458 struct gl_shader_program
**shader_programs
;
1459 struct gl_program
**programs
;
1460 enum shader_time_shader_type
*types
;
1461 uint64_t *cumulative
;
1467 struct brw_fast_clear_state
*fast_clear_state
;
1469 __DRIcontext
*driContext
;
1470 struct intel_screen
*intelScreen
;
1473 /*======================================================================
1476 void brwInitVtbl( struct brw_context
*brw
);
1479 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1481 /*======================================================================
1484 extern const char *const brw_vendor_string
;
1486 extern const char *brw_get_renderer_string(unsigned deviceID
);
1489 DRI_CONF_BO_REUSE_DISABLED
,
1490 DRI_CONF_BO_REUSE_ALL
1493 void intel_update_renderbuffers(__DRIcontext
*context
,
1494 __DRIdrawable
*drawable
);
1495 void intel_prepare_render(struct brw_context
*brw
);
1497 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1498 __DRIdrawable
*drawable
);
1500 GLboolean
brwCreateContext(gl_api api
,
1501 const struct gl_config
*mesaVis
,
1502 __DRIcontext
*driContextPriv
,
1503 unsigned major_version
,
1504 unsigned minor_version
,
1508 void *sharedContextPrivate
);
1510 /*======================================================================
1513 GLuint
brw_get_rb_for_slice(struct brw_context
*brw
,
1514 struct intel_mipmap_tree
*mt
,
1515 unsigned level
, unsigned layer
, bool flat
);
1517 void brw_meta_updownsample(struct brw_context
*brw
,
1518 struct intel_mipmap_tree
*src
,
1519 struct intel_mipmap_tree
*dst
);
1521 void brw_meta_fbo_stencil_blit(struct brw_context
*brw
,
1522 struct gl_framebuffer
*read_fb
,
1523 struct gl_framebuffer
*draw_fb
,
1524 GLfloat srcX0
, GLfloat srcY0
,
1525 GLfloat srcX1
, GLfloat srcY1
,
1526 GLfloat dstX0
, GLfloat dstY0
,
1527 GLfloat dstX1
, GLfloat dstY1
);
1529 void brw_meta_stencil_updownsample(struct brw_context
*brw
,
1530 struct intel_mipmap_tree
*src
,
1531 struct intel_mipmap_tree
*dst
);
1533 bool brw_meta_fast_clear(struct brw_context
*brw
,
1534 struct gl_framebuffer
*fb
,
1536 bool partial_clear
);
1539 brw_meta_resolve_color(struct brw_context
*brw
,
1540 struct intel_mipmap_tree
*mt
);
1542 brw_meta_fast_clear_free(struct brw_context
*brw
);
1545 /*======================================================================
1548 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1549 uint32_t depth_level
,
1550 uint32_t depth_layer
,
1551 struct intel_mipmap_tree
*stencil_mt
,
1552 uint32_t *out_tile_mask_x
,
1553 uint32_t *out_tile_mask_y
);
1554 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1555 GLbitfield clear_mask
);
1557 /* brw_object_purgeable.c */
1558 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1560 /*======================================================================
1563 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1564 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1565 void brw_emit_query_begin(struct brw_context
*brw
);
1566 void brw_emit_query_end(struct brw_context
*brw
);
1568 /** gen6_queryobj.c */
1569 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1570 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1571 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1572 void brw_store_register_mem64(struct brw_context
*brw
,
1573 drm_intel_bo
*bo
, uint32_t reg
, int idx
);
1575 /** intel_batchbuffer.c */
1576 void brw_load_register_mem(struct brw_context
*brw
,
1579 uint32_t read_domains
, uint32_t write_domain
,
1582 /*======================================================================
1585 void brw_debug_batch(struct brw_context
*brw
);
1586 void brw_annotate_aub(struct brw_context
*brw
);
1588 /*======================================================================
1591 void brw_validate_textures( struct brw_context
*brw
);
1594 /*======================================================================
1597 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1599 int brw_get_scratch_size(int size
);
1600 void brw_get_scratch_bo(struct brw_context
*brw
,
1601 drm_intel_bo
**scratch_bo
, int size
);
1602 void brw_init_shader_time(struct brw_context
*brw
);
1603 int brw_get_shader_time_index(struct brw_context
*brw
,
1604 struct gl_shader_program
*shader_prog
,
1605 struct gl_program
*prog
,
1606 enum shader_time_shader_type type
);
1607 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1608 void brw_destroy_shader_time(struct brw_context
*brw
);
1612 void brw_upload_urb_fence(struct brw_context
*brw
);
1616 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1618 /* brw_fs_reg_allocate.cpp
1620 void brw_fs_alloc_reg_sets(struct intel_screen
*screen
);
1622 /* brw_vec4_reg_allocate.cpp */
1623 void brw_vec4_alloc_reg_set(struct intel_screen
*screen
);
1626 int brw_disassemble_inst(FILE *file
, struct brw_context
*brw
,
1627 struct brw_inst
*inst
, bool is_compacted
);
1630 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1632 /* brw_draw_upload.c */
1633 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1634 const struct gl_client_array
*glarray
);
1636 static inline unsigned
1637 brw_get_index_type(GLenum type
)
1639 assert((type
== GL_UNSIGNED_BYTE
)
1640 || (type
== GL_UNSIGNED_SHORT
)
1641 || (type
== GL_UNSIGNED_INT
));
1643 /* The possible values for type are GL_UNSIGNED_BYTE (0x1401),
1644 * GL_UNSIGNED_SHORT (0x1403), and GL_UNSIGNED_INT (0x1405) which we want
1645 * to map to scale factors of 0, 1, and 2, respectively. These scale
1646 * factors are then left-shfited by 8 to be in the correct position in the
1647 * CMD_INDEX_BUFFER packet.
1649 * Subtracting 0x1401 gives 0, 2, and 4. Shifting left by 7 afterwards
1650 * gives 0x00000000, 0x00000100, and 0x00000200. These just happen to be
1651 * the values the need to be written in the CMD_INDEX_BUFFER packet.
1653 return (type
- 0x1401) << 7;
1656 void brw_prepare_vertices(struct brw_context
*brw
);
1658 /* brw_wm_surface_state.c */
1659 void brw_init_surface_formats(struct brw_context
*brw
);
1660 void brw_create_constant_surface(struct brw_context
*brw
,
1664 uint32_t *out_offset
,
1666 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1668 uint32_t *surf_offset
);
1670 brw_update_sol_surface(struct brw_context
*brw
,
1671 struct gl_buffer_object
*buffer_obj
,
1672 uint32_t *out_offset
, unsigned num_vector_components
,
1673 unsigned stride_dwords
, unsigned offset_dwords
);
1674 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1675 struct gl_shader
*shader
,
1676 struct brw_stage_state
*stage_state
,
1677 struct brw_stage_prog_data
*prog_data
,
1679 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1680 struct gl_shader_program
*prog
,
1681 struct brw_stage_state
*stage_state
,
1682 struct brw_stage_prog_data
*prog_data
);
1684 /* brw_surface_formats.c */
1685 bool brw_is_hiz_depth_format(struct brw_context
*ctx
, mesa_format format
);
1686 bool brw_render_target_supported(struct brw_context
*brw
,
1687 struct gl_renderbuffer
*rb
);
1688 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1690 /* brw_performance_monitor.c */
1691 void brw_init_performance_monitors(struct brw_context
*brw
);
1692 void brw_dump_perf_monitors(struct brw_context
*brw
);
1693 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1694 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1696 /* intel_buffer_objects.c */
1697 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1698 const char *bo_name
);
1699 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1700 const char *bo_name
);
1702 /* intel_extensions.c */
1703 extern void intelInitExtensions(struct gl_context
*ctx
);
1706 extern int intel_translate_shadow_compare_func(GLenum func
);
1707 extern int intel_translate_compare_func(GLenum func
);
1708 extern int intel_translate_stencil_op(GLenum op
);
1709 extern int intel_translate_logic_op(GLenum opcode
);
1711 /* intel_syncobj.c */
1712 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1715 struct gl_transform_feedback_object
*
1716 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1718 brw_delete_transform_feedback(struct gl_context
*ctx
,
1719 struct gl_transform_feedback_object
*obj
);
1721 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1722 struct gl_transform_feedback_object
*obj
);
1724 brw_end_transform_feedback(struct gl_context
*ctx
,
1725 struct gl_transform_feedback_object
*obj
);
1727 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1728 struct gl_transform_feedback_object
*obj
,
1731 /* gen7_sol_state.c */
1733 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1734 struct gl_transform_feedback_object
*obj
);
1736 gen7_end_transform_feedback(struct gl_context
*ctx
,
1737 struct gl_transform_feedback_object
*obj
);
1739 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1740 struct gl_transform_feedback_object
*obj
);
1742 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1743 struct gl_transform_feedback_object
*obj
);
1745 /* brw_blorp_blit.cpp */
1747 brw_blorp_framebuffer(struct brw_context
*brw
,
1748 struct gl_framebuffer
*readFb
,
1749 struct gl_framebuffer
*drawFb
,
1750 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1751 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1752 GLbitfield mask
, GLenum filter
);
1755 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1756 struct gl_renderbuffer
*src_rb
,
1757 struct gl_texture_image
*dst_image
,
1759 int srcX0
, int srcY0
,
1760 int dstX0
, int dstY0
,
1761 int width
, int height
);
1763 /* gen6_multisample_state.c */
1765 gen6_determine_sample_mask(struct brw_context
*brw
);
1768 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1769 unsigned num_samples
);
1771 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1773 gen6_get_sample_position(struct gl_context
*ctx
,
1774 struct gl_framebuffer
*fb
,
1778 gen6_set_sample_maps(struct gl_context
*ctx
);
1780 /* gen8_multisample_state.c */
1781 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1782 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1786 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1787 unsigned gs_size
, unsigned fs_size
);
1790 gen7_emit_urb_state(struct brw_context
*brw
,
1791 unsigned nr_vs_entries
, unsigned vs_size
,
1792 unsigned vs_start
, unsigned nr_gs_entries
,
1793 unsigned gs_size
, unsigned gs_start
);
1798 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1800 /*======================================================================
1801 * Inline conversion functions. These are better-typed than the
1802 * macros used previously:
1804 static inline struct brw_context
*
1805 brw_context( struct gl_context
*ctx
)
1807 return (struct brw_context
*)ctx
;
1810 static inline struct brw_vertex_program
*
1811 brw_vertex_program(struct gl_vertex_program
*p
)
1813 return (struct brw_vertex_program
*) p
;
1816 static inline const struct brw_vertex_program
*
1817 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1819 return (const struct brw_vertex_program
*) p
;
1822 static inline struct brw_geometry_program
*
1823 brw_geometry_program(struct gl_geometry_program
*p
)
1825 return (struct brw_geometry_program
*) p
;
1828 static inline struct brw_fragment_program
*
1829 brw_fragment_program(struct gl_fragment_program
*p
)
1831 return (struct brw_fragment_program
*) p
;
1834 static inline const struct brw_fragment_program
*
1835 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1837 return (const struct brw_fragment_program
*) p
;
1841 * Pre-gen6, the register file of the EUs was shared between threads,
1842 * and each thread used some subset allocated on a 16-register block
1843 * granularity. The unit states wanted these block counts.
1846 brw_register_blocks(int reg_count
)
1848 return ALIGN(reg_count
, 16) / 16 - 1;
1851 static inline uint32_t
1852 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1853 uint32_t prog_offset
)
1855 if (brw
->gen
>= 5) {
1856 /* Using state base address. */
1860 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1864 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1866 return brw
->cache
.bo
->offset64
+ prog_offset
;
1869 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1870 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1871 struct exec_list
*instructions
);
1872 bool brw_do_lower_unnormalized_offset(struct exec_list
*instructions
);
1874 struct opcode_desc
{
1880 extern const struct opcode_desc opcode_descs
[128];
1881 extern const char * const conditional_modifier
[16];
1884 brw_emit_depthbuffer(struct brw_context
*brw
);
1887 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1888 struct intel_mipmap_tree
*depth_mt
,
1889 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1890 uint32_t depth_surface_type
,
1891 struct intel_mipmap_tree
*stencil_mt
,
1892 bool hiz
, bool separate_stencil
,
1893 uint32_t width
, uint32_t height
,
1894 uint32_t tile_x
, uint32_t tile_y
);
1897 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1898 struct intel_mipmap_tree
*depth_mt
,
1899 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1900 uint32_t depth_surface_type
,
1901 struct intel_mipmap_tree
*stencil_mt
,
1902 bool hiz
, bool separate_stencil
,
1903 uint32_t width
, uint32_t height
,
1904 uint32_t tile_x
, uint32_t tile_y
);
1907 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1908 struct intel_mipmap_tree
*depth_mt
,
1909 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1910 uint32_t depth_surface_type
,
1911 struct intel_mipmap_tree
*stencil_mt
,
1912 bool hiz
, bool separate_stencil
,
1913 uint32_t width
, uint32_t height
,
1914 uint32_t tile_x
, uint32_t tile_y
);
1916 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1917 struct intel_mipmap_tree
*depth_mt
,
1918 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1919 uint32_t depth_surface_type
,
1920 struct intel_mipmap_tree
*stencil_mt
,
1921 bool hiz
, bool separate_stencil
,
1922 uint32_t width
, uint32_t height
,
1923 uint32_t tile_x
, uint32_t tile_y
);
1925 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1926 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);
1928 uint32_t get_hw_prim_for_gl_prim(int mode
);
1931 brw_setup_vue_key_clip_info(struct brw_context
*brw
,
1932 struct brw_vue_prog_key
*key
,
1933 bool program_uses_clip_distance
);
1936 gen6_upload_push_constants(struct brw_context
*brw
,
1937 const struct gl_program
*prog
,
1938 const struct brw_stage_prog_data
*prog_data
,
1939 struct brw_stage_state
*stage_state
,
1940 enum aub_state_struct_type type
);