2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
36 #include "intel_context.h"
37 #include "brw_structs.h"
38 #include "main/imports.h"
39 #include "main/macros.h"
47 * URB - uniform resource buffer. A mid-sized buffer which is
48 * partitioned between the fixed function units and used for passing
49 * values (vertices, primitives, constants) between them.
51 * CURBE - constant URB entry. An urb region (entry) used to hold
52 * constant values which the fixed function units can be instructed to
53 * preload into the GRF when spawning a thread.
55 * VUE - vertex URB entry. An urb entry holding a vertex and usually
56 * a vertex header. The header contains control information and
57 * things like primitive type, Begin/end flags and clip codes.
59 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
60 * unit holding rasterization and interpolation parameters.
62 * GRF - general register file. One of several register files
63 * addressable by programmed threads. The inputs (r0, payload, curbe,
64 * urb) of the thread are preloaded to this area before the thread is
65 * spawned. The registers are individually 8 dwords wide and suitable
66 * for general usage. Registers holding thread input values are not
67 * special and may be overwritten.
69 * MRF - message register file. Threads communicate (and terminate)
70 * by sending messages. Message parameters are placed in contiguous
71 * MRF registers. All program output is via these messages. URB
72 * entries are populated by sending a message to the shared URB
73 * function containing the new data, together with a control word,
74 * often an unmodified copy of R0.
76 * R0 - GRF register 0. Typically holds control information used when
77 * sending messages to other threads.
79 * EU or GEN4 EU: The name of the programmable subsystem of the
80 * i965 hardware. Threads are executed by the EU, the registers
81 * described above are part of the EU architecture.
83 * Fixed function units:
85 * CS - Command streamer. Notional first unit, little software
86 * interaction. Holds the URB entries used for constant data, ie the
89 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
90 * this unit is responsible for pulling vertices out of vertex buffers
91 * in vram and injecting them into the processing pipe as VUEs. If
92 * enabled, it first passes them to a VS thread which is a good place
93 * for the driver to implement any active vertex shader.
95 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
96 * enabled, incoming strips etc are passed to GS threads in individual
97 * line/triangle/point units. The GS thread may perform arbitary
98 * computation and emit whatever primtives with whatever vertices it
99 * chooses. This makes GS an excellent place to implement GL's
100 * unfilled polygon modes, though of course it is capable of much
101 * more. Additionally, GS is used to translate away primitives not
102 * handled by latter units, including Quads and Lineloops.
104 * CS - Clipper. Mesa's clipping algorithms are imported to run on
105 * this unit. The fixed function part performs cliptesting against
106 * the 6 fixed clipplanes and makes descisions on whether or not the
107 * incoming primitive needs to be passed to a thread for clipping.
108 * User clip planes are handled via cooperation with the VS thread.
110 * SF - Strips Fans or Setup: Triangles are prepared for
111 * rasterization. Interpolation coefficients are calculated.
112 * Flatshading and two-side lighting usually performed here.
114 * WM - Windower. Interpolation of vertex attributes performed here.
115 * Fragment shader implemented here. SIMD aspects of EU taken full
116 * advantage of, as pixels are processed in blocks of 16.
118 * CC - Color Calculator. No EU threads associated with this unit.
119 * Handles blending and (presumably) depth and stencil testing.
123 #define BRW_MAX_CURBE (32*16)
126 struct brw_instruction
;
127 struct brw_vs_prog_key
;
128 struct brw_wm_prog_key
;
129 struct brw_wm_prog_data
;
133 BRW_STATE_FRAGMENT_PROGRAM
,
134 BRW_STATE_GEOMETRY_PROGRAM
,
135 BRW_STATE_VERTEX_PROGRAM
,
136 BRW_STATE_CURBE_OFFSETS
,
137 BRW_STATE_REDUCED_PRIMITIVE
,
142 BRW_STATE_VS_BINDING_TABLE
,
143 BRW_STATE_GS_BINDING_TABLE
,
144 BRW_STATE_PS_BINDING_TABLE
,
148 BRW_STATE_INDEX_BUFFER
,
149 BRW_STATE_VS_CONSTBUF
,
150 BRW_STATE_PROGRAM_CACHE
,
151 BRW_STATE_STATE_BASE_ADDRESS
,
152 BRW_STATE_VUE_MAP_GEOM_OUT
,
153 BRW_STATE_TRANSFORM_FEEDBACK
,
154 BRW_STATE_RASTERIZER_DISCARD
,
156 BRW_STATE_UNIFORM_BUFFER
,
157 BRW_STATE_META_IN_PROGRESS
,
158 BRW_STATE_INTERPOLATION_MAP
,
162 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
163 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
164 #define BRW_NEW_GEOMETRY_PROGRAM (1 << BRW_STATE_GEOMETRY_PROGRAM)
165 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
166 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
167 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
168 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
169 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
170 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
171 #define BRW_NEW_SURFACES (1 << BRW_STATE_SURFACES)
172 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
173 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
174 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
175 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
176 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
178 * Used for any batch entry with a relocated pointer that will be used
179 * by any 3D rendering.
181 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
182 /** \see brw.state.depth_region */
183 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
184 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
185 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
186 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
187 #define BRW_NEW_VUE_MAP_GEOM_OUT (1 << BRW_STATE_VUE_MAP_GEOM_OUT)
188 #define BRW_NEW_TRANSFORM_FEEDBACK (1 << BRW_STATE_TRANSFORM_FEEDBACK)
189 #define BRW_NEW_RASTERIZER_DISCARD (1 << BRW_STATE_RASTERIZER_DISCARD)
190 #define BRW_NEW_STATS_WM (1 << BRW_STATE_STATS_WM)
191 #define BRW_NEW_UNIFORM_BUFFER (1 << BRW_STATE_UNIFORM_BUFFER)
192 #define BRW_NEW_META_IN_PROGRESS (1 << BRW_STATE_META_IN_PROGRESS)
193 #define BRW_NEW_INTERPOLATION_MAP (1 << BRW_STATE_INTERPOLATION_MAP)
195 struct brw_state_flags
{
196 /** State update flags signalled by mesa internals */
199 * State update flags signalled as the result of brw_tracked_state updates
202 /** State update flags signalled by brw_state_cache.c searches */
206 #define AUB_TRACE_TYPE_MASK 0x0000ff00
207 #define AUB_TRACE_TYPE_NOTYPE (0 << 8)
208 #define AUB_TRACE_TYPE_BATCH (1 << 8)
209 #define AUB_TRACE_TYPE_VERTEX_BUFFER (5 << 8)
210 #define AUB_TRACE_TYPE_2D_MAP (6 << 8)
211 #define AUB_TRACE_TYPE_CUBE_MAP (7 << 8)
212 #define AUB_TRACE_TYPE_VOLUME_MAP (9 << 8)
213 #define AUB_TRACE_TYPE_1D_MAP (10 << 8)
214 #define AUB_TRACE_TYPE_CONSTANT_BUFFER (11 << 8)
215 #define AUB_TRACE_TYPE_CONSTANT_URB (12 << 8)
216 #define AUB_TRACE_TYPE_INDEX_BUFFER (13 << 8)
217 #define AUB_TRACE_TYPE_GENERAL (14 << 8)
218 #define AUB_TRACE_TYPE_SURFACE (15 << 8)
221 * state_struct_type enum values are encoded with the top 16 bits representing
222 * the type to be delivered to the .aub file, and the bottom 16 bits
223 * representing the subtype. This macro performs the encoding.
225 #define ENCODE_SS_TYPE(type, subtype) (((type) << 16) | (subtype))
227 enum state_struct_type
{
228 AUB_TRACE_VS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 1),
229 AUB_TRACE_GS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 2),
230 AUB_TRACE_CLIP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 3),
231 AUB_TRACE_SF_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 4),
232 AUB_TRACE_WM_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 5),
233 AUB_TRACE_CC_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 6),
234 AUB_TRACE_CLIP_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 7),
235 AUB_TRACE_SF_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 8),
236 AUB_TRACE_CC_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x9),
237 AUB_TRACE_SAMPLER_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xa),
238 AUB_TRACE_KERNEL_INSTRUCTIONS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xb),
239 AUB_TRACE_SCRATCH_SPACE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xc),
240 AUB_TRACE_SAMPLER_DEFAULT_COLOR
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xd),
242 AUB_TRACE_SCISSOR_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x15),
243 AUB_TRACE_BLEND_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x16),
244 AUB_TRACE_DEPTH_STENCIL_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x17),
246 AUB_TRACE_VERTEX_BUFFER
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_VERTEX_BUFFER
, 0),
247 AUB_TRACE_BINDING_TABLE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x100),
248 AUB_TRACE_SURFACE_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x200),
249 AUB_TRACE_VS_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 0),
250 AUB_TRACE_WM_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 1),
254 * Decode a state_struct_type value to determine the type that should be
255 * stored in the .aub file.
257 static inline uint32_t AUB_TRACE_TYPE(enum state_struct_type ss_type
)
259 return (ss_type
& 0xFFFF0000) >> 16;
263 * Decode a state_struct_type value to determine the subtype that should be
264 * stored in the .aub file.
266 static inline uint32_t AUB_TRACE_SUBTYPE(enum state_struct_type ss_type
)
268 return ss_type
& 0xFFFF;
271 /** Subclass of Mesa vertex program */
272 struct brw_vertex_program
{
273 struct gl_vertex_program program
;
278 /** Subclass of Mesa geometry program */
279 struct brw_geometry_program
{
280 struct gl_geometry_program program
;
281 unsigned id
; /**< serial no. to identify geom progs, never re-used */
285 /** Subclass of Mesa fragment program */
286 struct brw_fragment_program
{
287 struct gl_fragment_program program
;
288 GLuint id
; /**< serial no. to identify frag progs, never re-used */
292 struct gl_shader base
;
296 /** Shader IR transformed for native compile, at link time. */
297 struct exec_list
*ir
;
300 /* Data about a particular attempt to compile a program. Note that
301 * there can be many of these, each in a different GL state
302 * corresponding to a different brw_wm_prog_key struct, with different
305 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
308 struct brw_wm_prog_data
{
309 GLuint curb_read_length
;
310 GLuint urb_read_length
;
312 GLuint first_curbe_grf
;
313 GLuint first_curbe_grf_16
;
315 GLuint reg_blocks_16
;
316 GLuint total_scratch
;
318 unsigned binding_table_size
;
320 GLuint nr_params
; /**< number of float params/constants */
321 GLuint nr_pull_params
;
324 uint32_t prog_offset_16
;
327 * Mask of which interpolation modes are required by the fragment shader.
328 * Used in hardware setup on gen6+.
330 uint32_t barycentric_interp_modes
;
332 /* Pointers to tracked values (only valid once
333 * _mesa_load_state_parameters has been called at runtime).
335 * These must be the last fields of the struct (see
336 * brw_wm_prog_data_compare()).
339 const float **pull_param
;
343 * Enum representing the i965-specific vertex results that don't correspond
344 * exactly to any element of gl_varying_slot. The values of this enum are
345 * assigned such that they don't conflict with gl_varying_slot.
349 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
350 BRW_VARYING_SLOT_PAD
,
352 * Technically this is not a varying but just a placeholder that
353 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
354 * builtin variable to be compiled correctly. see compile_sf_prog() for
357 BRW_VARYING_SLOT_PNTC
,
358 BRW_VARYING_SLOT_COUNT
363 * Data structure recording the relationship between the gl_varying_slot enum
364 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
365 * single octaword within the VUE (128 bits).
367 * Note that each BRW register contains 256 bits (2 octawords), so when
368 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
369 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
370 * in a vertex shader), each register corresponds to a single VUE slot, since
371 * it contains data for two separate vertices.
375 * Bitfield representing all varying slots that are (a) stored in this VUE
376 * map, and (b) actually written by the shader. Does not include any of
377 * the additional varying slots defined in brw_varying_slot.
379 GLbitfield64 slots_valid
;
382 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
383 * not stored in a slot (because they are not written, or because
384 * additional processing is applied before storing them in the VUE), the
387 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
390 * Map from VUE slot to gl_varying_slot value. For slots that do not
391 * directly correspond to a gl_varying_slot, the value comes from
394 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
395 * simplifies code that uses the value stored in slot_to_varying to
396 * create a bit mask).
398 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
401 * Total number of VUE slots in use
407 * Convert a VUE slot number into a byte offset within the VUE.
409 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
415 * Convert a vertex output (brw_varying_slot) into a byte offset within the
418 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
421 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
424 void brw_compute_vue_map(struct brw_context
*brw
, struct brw_vue_map
*vue_map
,
425 GLbitfield64 slots_valid
, bool userclip_active
);
429 * Mapping of VUE map slots to interpolation modes.
431 struct interpolation_mode_map
{
432 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
435 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
437 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
438 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
444 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
446 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
447 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
454 struct brw_sf_prog_data
{
455 GLuint urb_read_length
;
458 /* Each vertex may have upto 12 attributes, 4 components each,
459 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
462 * Actually we use 4 for each, so call it 12 rows.
464 GLuint urb_entry_size
;
467 struct brw_clip_prog_data
{
468 GLuint curb_read_length
; /* user planes? */
470 GLuint urb_read_length
;
474 struct brw_gs_prog_data
{
475 GLuint urb_read_length
;
479 * Gen6 transform feedback: Amount by which the streaming vertex buffer
480 * indices should be incremented each time the GS is invoked.
482 unsigned svbi_postincrement_value
;
486 /* Note: brw_vec4_prog_data_compare() must be updated when adding fields to
489 struct brw_vec4_prog_data
{
490 struct brw_vue_map vue_map
;
493 * Register where the thread expects to find input data from the URB
494 * (typically uniforms, followed by per-vertex inputs).
496 unsigned dispatch_grf_start_reg
;
498 GLuint curb_read_length
;
499 GLuint urb_read_length
;
501 GLuint nr_params
; /**< number of float params/constants */
502 GLuint nr_pull_params
; /**< number of dwords referenced by pull_param[] */
503 GLuint total_scratch
;
505 /* Used for calculating urb partitions. In the VS, this is the size of the
506 * URB entry used for both input and output to the thread. In the GS, this
507 * is the size of the URB entry used for output.
509 GLuint urb_entry_size
;
511 unsigned binding_table_size
;
513 /* These pointers must appear last. See brw_vec4_prog_data_compare(). */
515 const float **pull_param
;
519 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
522 struct brw_vs_prog_data
{
523 struct brw_vec4_prog_data base
;
525 GLbitfield64 inputs_read
;
531 /* Note: brw_vec4_gs_prog_data_compare() must be updated when adding fields to
534 struct brw_vec4_gs_prog_data
536 struct brw_vec4_prog_data base
;
539 * Size of an output vertex, measured in HWORDS (32 bytes).
541 unsigned output_vertex_size_hwords
;
543 unsigned output_topology
;
546 /** Number of texture sampler units */
547 #define BRW_MAX_TEX_UNIT 16
549 /** Max number of render targets in a shader */
550 #define BRW_MAX_DRAW_BUFFERS 8
553 * Max number of binding table entries used for stream output.
555 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
556 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
558 * On Gen6, the size of transform feedback data is limited not by the number
559 * of components but by the number of binding table entries we set aside. We
560 * use one binding table entry for a float, one entry for a vector, and one
561 * entry per matrix column. Since the only way we can communicate our
562 * transform feedback capabilities to the client is via
563 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
564 * worst case, in which all the varyings are floats, so we use up one binding
565 * table entry per component. Therefore we need to set aside at least 64
566 * binding table entries for use by transform feedback.
568 * Note: since we don't currently pack varyings, it is currently impossible
569 * for the client to actually use up all of these binding table entries--if
570 * all of their varyings were floats, they would run out of varying slots and
571 * fail to link. But that's a bug, so it seems prudent to go ahead and
572 * allocate the number of binding table entries we will need once the bug is
575 #define BRW_MAX_SOL_BINDINGS 64
577 /** Maximum number of actual buffers used for stream output */
578 #define BRW_MAX_SOL_BUFFERS 4
580 #define BRW_MAX_WM_UBOS 12
581 #define BRW_MAX_VS_UBOS 12
584 * Helpers to create Surface Binding Table indexes for draw buffers,
585 * textures, and constant buffers.
587 * Shader threads access surfaces via numeric handles, rather than directly
588 * using pointers. The binding table maps these numeric handles to the
589 * address of the actual buffer.
591 * For example, a shader might ask to sample from "surface 7." In this case,
592 * bind[7] would contain a pointer to a texture.
594 * Currently, our WM binding tables are (arbitrarily) programmed as follows:
596 * +-------------------------------+
597 * | 0 | Draw buffer 0 |
600 * | 7 | Draw buffer 7 |
601 * |-----|-------------------------|
602 * | 8 | WM Pull Constant Buffer |
603 * |-----|-------------------------|
607 * | 24 | Texture 15 |
608 * |-----|-------------------------|
613 * +-------------------------------+
615 * Our VS binding tables are programmed as follows:
617 * +-----+-------------------------+
618 * | 0 | VS Pull Constant Buffer |
619 * +-----+-------------------------+
623 * | 16 | Texture 15 |
624 * +-----+-------------------------+
629 * +-------------------------------+
631 * Our (gen6) GS binding tables are programmed as follows:
633 * +-----+-------------------------+
634 * | 0 | SOL Binding 0 |
637 * | 63 | SOL Binding 63 |
638 * +-----+-------------------------+
640 #define SURF_INDEX_DRAW(d) (d)
641 #define SURF_INDEX_FRAG_CONST_BUFFER (BRW_MAX_DRAW_BUFFERS + 1)
642 #define SURF_INDEX_TEXTURE(t) (BRW_MAX_DRAW_BUFFERS + 2 + (t))
643 #define SURF_INDEX_WM_UBO(u) (SURF_INDEX_TEXTURE(BRW_MAX_TEX_UNIT) + u)
644 #define SURF_INDEX_WM_SHADER_TIME (SURF_INDEX_WM_UBO(12))
645 /** Maximum size of the binding table. */
646 #define BRW_MAX_WM_SURFACES (SURF_INDEX_WM_SHADER_TIME + 1)
648 #define SURF_INDEX_VERT_CONST_BUFFER (0)
649 #define SURF_INDEX_VS_TEXTURE(t) (SURF_INDEX_VERT_CONST_BUFFER + 1 + (t))
650 #define SURF_INDEX_VS_UBO(u) (SURF_INDEX_VS_TEXTURE(BRW_MAX_TEX_UNIT) + u)
651 #define SURF_INDEX_VS_SHADER_TIME (SURF_INDEX_VS_UBO(12))
652 #define BRW_MAX_VS_SURFACES (SURF_INDEX_VS_SHADER_TIME + 1)
654 #define SURF_INDEX_SOL_BINDING(t) ((t))
655 #define BRW_MAX_GS_SURFACES SURF_INDEX_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
658 * Stride in bytes between shader_time entries.
660 * We separate entries by a cacheline to reduce traffic between EUs writing to
663 #define SHADER_TIME_STRIDE 64
670 BRW_BLORP_CONST_COLOR_PROG
,
675 BRW_SF_UNIT
, /* scissor state on gen6 */
687 struct brw_cache_item
{
689 * Effectively part of the key, cache_id identifies what kind of state
690 * buffer is involved, and also which brw->state.dirty.cache flag should
691 * be set when this cache item is chosen.
693 enum brw_cache_id cache_id
;
694 /** 32-bit hash of the key data */
696 GLuint key_size
; /* for variable-sized keys */
703 struct brw_cache_item
*next
;
707 typedef bool (*cache_aux_compare_func
)(const void *a
, const void *b
,
708 int aux_size
, const void *key
);
709 typedef void (*cache_aux_free_func
)(const void *aux
);
712 struct brw_context
*brw
;
714 struct brw_cache_item
**items
;
716 GLuint size
, n_items
;
718 uint32_t next_offset
;
722 * Optional functions used in determining whether the prog_data for a new
723 * cache item matches an existing cache item (in case there's relevant data
724 * outside of the prog_data). If NULL, a plain memcmp is done.
726 cache_aux_compare_func aux_compare
[BRW_MAX_CACHE
];
727 /** Optional functions for freeing other pointers attached to a prog_data. */
728 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
732 /* Considered adding a member to this struct to document which flags
733 * an update might raise so that ordering of the state atoms can be
734 * checked or derived at runtime. Dropped the idea in favor of having
735 * a debug mode where the state is monitored for flags which are
736 * raised that have already been tested against.
738 struct brw_tracked_state
{
739 struct brw_state_flags dirty
;
740 void (*emit
)( struct brw_context
*brw
);
743 enum shader_time_shader_type
{
756 /* Flags for brw->state.cache.
758 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
759 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
760 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
761 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
762 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
763 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
764 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
765 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
766 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
767 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
768 #define CACHE_NEW_GS_UNIT (1<<BRW_GS_UNIT)
769 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
770 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
771 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
772 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
774 struct brw_cached_batch_item
{
775 struct header
*header
;
777 struct brw_cached_batch_item
*next
;
782 /* Protect against a future where VERT_ATTRIB_MAX > 32. Wouldn't life
783 * be easier if C allowed arrays of packed elements?
785 #define ATTRIB_BIT_DWORDS ((VERT_ATTRIB_MAX+31)/32)
787 struct brw_vertex_buffer
{
788 /** Buffer object containing the uploaded vertex data */
791 /** Byte stride between elements in the uploaded array */
795 struct brw_vertex_element
{
796 const struct gl_client_array
*glarray
;
800 /** The corresponding Mesa vertex attribute */
801 gl_vert_attrib attrib
;
802 /** Offset of the first element within the buffer object */
806 struct brw_query_object
{
807 struct gl_query_object Base
;
809 /** Last query BO associated with this query. */
812 /** Last index in bo with query data for this object. */
818 * brw_context is derived from gl_context.
822 struct gl_context ctx
; /**< base class, must be first field */
826 void (*destroy
) (struct brw_context
* brw
);
827 void (*finish_batch
) (struct brw_context
* brw
);
828 void (*new_batch
) (struct brw_context
* brw
);
830 void (*update_texture_surface
)(struct gl_context
*ctx
,
832 uint32_t *binding_table
,
833 unsigned surf_index
);
834 void (*update_renderbuffer_surface
)(struct brw_context
*brw
,
835 struct gl_renderbuffer
*rb
,
838 void (*update_null_renderbuffer_surface
)(struct brw_context
*brw
,
840 void (*create_constant_surface
)(struct brw_context
*brw
,
844 uint32_t *out_offset
,
847 /** Upload a SAMPLER_STATE table. */
848 void (*upload_sampler_state_table
)(struct brw_context
*brw
,
849 struct gl_program
*prog
,
850 uint32_t sampler_count
,
851 uint32_t *sst_offset
,
852 uint32_t *sdc_offset
);
855 * Send the appropriate state packets to configure depth, stencil, and
856 * HiZ buffers (i965+ only)
858 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
859 struct intel_mipmap_tree
*depth_mt
,
860 uint32_t depth_offset
,
861 uint32_t depthbuffer_format
,
862 uint32_t depth_surface_type
,
863 struct intel_mipmap_tree
*stencil_mt
,
864 bool hiz
, bool separate_stencil
,
865 uint32_t width
, uint32_t height
,
866 uint32_t tile_x
, uint32_t tile_y
);
872 drm_intel_context
*hw_ctx
;
874 struct intel_batchbuffer batch
;
881 uint32_t buffer_offset
;
886 * Set if rendering has occured to the drawable's front buffer.
888 * This is used in the DRI2 case to detect that glFlush should also copy
889 * the contents of the fake front buffer to the real front buffer.
891 bool front_buffer_dirty
;
894 * Track whether front-buffer rendering is currently enabled
896 * A separate flag is used to track this in order to support MRT more
899 bool is_front_buffer_rendering
;
902 * Track whether front-buffer is the current read target.
904 * This is closely associated with is_front_buffer_rendering, but may
905 * be set separately. The DRI2 fake front buffer must be referenced
908 bool is_front_buffer_reading
;
910 /** Framerate throttling: @{ */
911 drm_intel_bo
*first_post_swapbuffers_batch
;
922 bool always_flush_batch
;
923 bool always_flush_cache
;
924 bool disable_throttling
;
927 driOptionCache optionCache
;
930 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
932 GLenum reduced_primitive
;
935 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
936 * variable is set, this is the flag indicating to do expensive work that
937 * might lead to a perf_debug() call.
941 uint32_t max_gtt_map_object_size
;
943 bool emit_state_always
;
953 bool has_separate_stencil
;
954 bool must_use_separate_stencil
;
957 bool has_surface_tile_offset
;
959 bool has_negative_rhw_bug
;
960 bool has_aa_line_parameters
;
964 * Some versions of Gen hardware don't do centroid interpolation correctly
965 * on unlit pixels, causing incorrect values for derivatives near triangle
966 * edges. Enabling this flag causes the fragment shader to use
967 * non-centroid interpolation for unlit pixels, at the expense of two extra
968 * fragment shader instructions.
970 bool needs_unlit_centroid_workaround
;
974 struct brw_state_flags dirty
;
977 struct brw_cache cache
;
978 struct brw_cached_batch_item
*cached_batch_items
;
980 /* Whether a meta-operation is in progress. */
981 bool meta_in_progress
;
984 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
985 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
987 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
991 /* Summary of size and varying of active arrays, so we can check
992 * for changes to this state:
994 unsigned int min_index
, max_index
;
996 /* Offset from start of vertex buffer so we can avoid redefining
997 * the same VB packed over and over again.
999 unsigned int start_vertex_bias
;
1004 * Index buffer for this draw_prims call.
1006 * Updates are signaled by BRW_NEW_INDICES.
1008 const struct _mesa_index_buffer
*ib
;
1010 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
1014 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
1015 * avoid re-uploading the IB packet over and over if we're actually
1016 * referencing the same index buffer.
1018 unsigned int start_vertex_offset
;
1021 /* Active vertex program:
1023 const struct gl_vertex_program
*vertex_program
;
1024 const struct gl_geometry_program
*geometry_program
;
1025 const struct gl_fragment_program
*fragment_program
;
1027 /* hw-dependent 3DSTATE_VF_STATISTICS opcode */
1028 uint32_t CMD_VF_STATISTICS
;
1029 /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
1030 uint32_t CMD_PIPELINE_SELECT
;
1033 * Platform specific constants containing the maximum number of threads
1034 * for each pipeline stage.
1040 /* BRW_NEW_URB_ALLOCATIONS:
1043 GLuint vsize
; /* vertex size plus header in urb registers */
1044 GLuint csize
; /* constant buffer size in urb registers */
1045 GLuint sfsize
; /* setup data size in urb registers */
1049 GLuint max_vs_entries
; /* Maximum number of VS entries */
1050 GLuint max_gs_entries
; /* Maximum number of GS entries */
1052 GLuint nr_vs_entries
;
1053 GLuint nr_gs_entries
;
1054 GLuint nr_clip_entries
;
1055 GLuint nr_sf_entries
;
1056 GLuint nr_cs_entries
;
1063 GLuint size
; /* Hardware URB size, in KB. */
1065 /* gen6: True if the most recently sent _3DSTATE_URB message allocated
1066 * URB space for the GS.
1068 bool gen6_gs_previously_active
;
1072 /* BRW_NEW_CURBE_OFFSETS:
1075 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1076 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1083 drm_intel_bo
*curbe_bo
;
1084 /** Offset within curbe_bo of space for current curbe entry */
1085 GLuint curbe_offset
;
1086 /** Offset within curbe_bo of space for next curbe entry */
1087 GLuint curbe_next_offset
;
1090 * Copy of the last set of CURBEs uploaded. Frequently we'll end up
1091 * in brw_curbe.c with the same set of constant data to be uploaded,
1092 * so we'd rather not upload new constants in that case (it can cause
1093 * a pipeline bubble since only up to 4 can be pipelined at a time).
1097 * Allocation for where to calculate the next set of CURBEs.
1098 * It's a hot enough path that malloc/free of that data matters.
1105 * Layout of vertex data exiting the geometry portion of the pipleine.
1106 * This comes from the geometry shader if one exists, otherwise from the
1109 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1111 struct brw_vue_map vue_map_geom_out
;
1114 struct brw_vs_prog_data
*prog_data
;
1116 drm_intel_bo
*scratch_bo
;
1117 drm_intel_bo
*const_bo
;
1118 /** Offset in the program cache to the VS program */
1119 uint32_t prog_offset
;
1120 uint32_t state_offset
;
1122 uint32_t push_const_offset
; /* Offset in the batchbuffer */
1123 int push_const_size
; /* in 256-bit register increments */
1125 /** @{ register allocator */
1127 struct ra_regs
*regs
;
1130 * Array of the ra classes for the unaligned contiguous register
1136 * Mapping for register-allocated objects in *regs to the first
1137 * GRF for that object.
1139 uint8_t *ra_reg_to_grf
;
1142 uint32_t bind_bo_offset
;
1143 uint32_t surf_offset
[BRW_MAX_VS_SURFACES
];
1145 /** SAMPLER_STATE count and table offset */
1146 uint32_t sampler_count
;
1147 uint32_t sampler_offset
;
1149 /** Offsets in the batch to sampler default colors (texture border color)
1151 uint32_t sdc_offset
[BRW_MAX_TEX_UNIT
];
1155 struct brw_gs_prog_data
*prog_data
;
1158 /** Offset in the program cache to the CLIP program pre-gen6 */
1159 uint32_t prog_offset
;
1160 uint32_t state_offset
;
1162 uint32_t bind_bo_offset
;
1163 uint32_t surf_offset
[BRW_MAX_GS_SURFACES
];
1167 struct brw_clip_prog_data
*prog_data
;
1169 /** Offset in the program cache to the CLIP program pre-gen6 */
1170 uint32_t prog_offset
;
1172 /* Offset in the batch to the CLIP state on pre-gen6. */
1173 uint32_t state_offset
;
1175 /* As of gen6, this is the offset in the batch to the CLIP VP,
1183 struct brw_sf_prog_data
*prog_data
;
1185 /** Offset in the program cache to the CLIP program pre-gen6 */
1186 uint32_t prog_offset
;
1187 uint32_t state_offset
;
1192 struct brw_wm_prog_data
*prog_data
;
1196 drm_intel_bo
*scratch_bo
;
1199 * Buffer object used in place of multisampled null render targets on
1200 * Gen6. See brw_update_null_renderbuffer_surface().
1202 drm_intel_bo
*multisampled_null_render_target_bo
;
1204 /** Offset in the program cache to the WM program */
1205 uint32_t prog_offset
;
1207 uint32_t state_offset
; /* offset in batchbuffer to pre-gen6 WM state */
1209 drm_intel_bo
*const_bo
; /* pull constant buffer. */
1211 * This is offset in the batch to the push constants on gen6.
1213 * Pre-gen6, push constants live in the CURBE.
1215 uint32_t push_const_offset
;
1217 /** Binding table of pointers to surf_bo entries */
1218 uint32_t bind_bo_offset
;
1219 uint32_t surf_offset
[BRW_MAX_WM_SURFACES
];
1221 /** SAMPLER_STATE count and table offset */
1222 uint32_t sampler_count
;
1223 uint32_t sampler_offset
;
1225 /** Offsets in the batch to sampler default colors (texture border color)
1227 uint32_t sdc_offset
[BRW_MAX_TEX_UNIT
];
1230 struct ra_regs
*regs
;
1232 /** Array of the ra classes for the unaligned contiguous
1233 * register block sizes used.
1238 * Mapping for register-allocated objects in *regs to the first
1239 * GRF for that object.
1241 uint8_t *ra_reg_to_grf
;
1244 * ra class for the aligned pairs we use for PLN, which doesn't
1245 * appear in *classes.
1247 int aligned_pairs_class
;
1253 uint32_t state_offset
;
1254 uint32_t blend_state_offset
;
1255 uint32_t depth_stencil_state_offset
;
1260 struct brw_query_object
*obj
;
1265 const struct brw_tracked_state
**atoms
;
1267 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1271 enum state_struct_type type
;
1272 } *state_batch_list
;
1273 int state_batch_count
;
1275 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1276 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1278 /* Interpolation modes, one byte per vue slot.
1279 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1281 struct interpolation_mode_map interpolation_mode
;
1283 /* PrimitiveRestart */
1286 bool enable_cut_index
;
1289 /** Computed depth/stencil/hiz state from the current attached
1290 * renderbuffers, valid only during the drawing state upload loop after
1291 * brw_workaround_depthstencil_alignment().
1294 struct intel_mipmap_tree
*depth_mt
;
1295 struct intel_mipmap_tree
*stencil_mt
;
1297 /* Inter-tile (page-aligned) byte offsets. */
1298 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1299 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1300 uint32_t tile_x
, tile_y
;
1303 uint32_t num_instances
;
1308 struct gl_shader_program
**shader_programs
;
1309 struct gl_program
**programs
;
1310 enum shader_time_shader_type
*types
;
1311 uint64_t *cumulative
;
1317 __DRIcontext
*driContext
;
1318 struct intel_screen
*intelScreen
;
1319 void (*saved_viewport
)(struct gl_context
*ctx
,
1320 GLint x
, GLint y
, GLsizei width
, GLsizei height
);
1323 /*======================================================================
1326 void brwInitVtbl( struct brw_context
*brw
);
1328 /*======================================================================
1331 bool brwCreateContext(int api
,
1332 const struct gl_config
*mesaVis
,
1333 __DRIcontext
*driContextPriv
,
1334 unsigned major_version
,
1335 unsigned minor_version
,
1338 void *sharedContextPrivate
);
1340 /*======================================================================
1343 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1344 uint32_t depth_level
,
1345 uint32_t depth_layer
,
1346 struct intel_mipmap_tree
*stencil_mt
,
1347 uint32_t *out_tile_mask_x
,
1348 uint32_t *out_tile_mask_y
);
1349 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1350 GLbitfield clear_mask
);
1352 /* brw_object_purgeable.c */
1353 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1355 /*======================================================================
1358 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1359 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1360 void brw_emit_query_begin(struct brw_context
*brw
);
1361 void brw_emit_query_end(struct brw_context
*brw
);
1363 /** gen6_queryobj.c */
1364 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1366 /*======================================================================
1369 void brw_debug_batch(struct brw_context
*brw
);
1370 void brw_annotate_aub(struct brw_context
*brw
);
1372 /*======================================================================
1375 void brw_validate_textures( struct brw_context
*brw
);
1378 /*======================================================================
1381 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1383 int brw_get_scratch_size(int size
);
1384 void brw_get_scratch_bo(struct brw_context
*brw
,
1385 drm_intel_bo
**scratch_bo
, int size
);
1386 void brw_init_shader_time(struct brw_context
*brw
);
1387 int brw_get_shader_time_index(struct brw_context
*brw
,
1388 struct gl_shader_program
*shader_prog
,
1389 struct gl_program
*prog
,
1390 enum shader_time_shader_type type
);
1391 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1392 void brw_destroy_shader_time(struct brw_context
*brw
);
1396 void brw_upload_urb_fence(struct brw_context
*brw
);
1400 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1402 /* brw_fs_reg_allocate.cpp
1404 void brw_fs_alloc_reg_sets(struct brw_context
*brw
);
1407 int brw_disasm (FILE *file
, struct brw_instruction
*inst
, int gen
);
1410 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1412 /* brw_draw_upload.c */
1413 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1414 const struct gl_client_array
*glarray
);
1415 unsigned brw_get_index_type(GLenum type
);
1417 /* brw_wm_surface_state.c */
1418 void brw_init_surface_formats(struct brw_context
*brw
);
1420 brw_update_sol_surface(struct brw_context
*brw
,
1421 struct gl_buffer_object
*buffer_obj
,
1422 uint32_t *out_offset
, unsigned num_vector_components
,
1423 unsigned stride_dwords
, unsigned offset_dwords
);
1424 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1425 struct gl_shader
*shader
,
1426 uint32_t *surf_offsets
);
1428 /* brw_surface_formats.c */
1429 bool brw_is_hiz_depth_format(struct brw_context
*ctx
, gl_format format
);
1430 bool brw_render_target_supported(struct brw_context
*brw
,
1431 struct gl_renderbuffer
*rb
);
1435 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1436 struct gl_transform_feedback_object
*obj
);
1438 brw_end_transform_feedback(struct gl_context
*ctx
,
1439 struct gl_transform_feedback_object
*obj
);
1441 /* gen7_sol_state.c */
1443 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1444 struct gl_transform_feedback_object
*obj
);
1446 gen7_end_transform_feedback(struct gl_context
*ctx
,
1447 struct gl_transform_feedback_object
*obj
);
1449 /* brw_blorp_blit.cpp */
1451 brw_blorp_framebuffer(struct brw_context
*brw
,
1452 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1453 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1454 GLbitfield mask
, GLenum filter
);
1457 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1458 struct gl_renderbuffer
*src_rb
,
1459 struct gl_texture_image
*dst_image
,
1461 int srcX0
, int srcY0
,
1462 int dstX0
, int dstY0
,
1463 int width
, int height
);
1465 /* gen6_multisample_state.c */
1467 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1468 unsigned num_samples
);
1470 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
,
1471 unsigned num_samples
, float coverage
,
1472 bool coverage_invert
, unsigned sample_mask
);
1474 gen6_get_sample_position(struct gl_context
*ctx
,
1475 struct gl_framebuffer
*fb
,
1481 gen7_allocate_push_constants(struct brw_context
*brw
);
1484 gen7_emit_urb_state(struct brw_context
*brw
, GLuint nr_vs_entries
,
1485 GLuint vs_size
, GLuint vs_start
);
1489 /*======================================================================
1490 * Inline conversion functions. These are better-typed than the
1491 * macros used previously:
1493 static INLINE
struct brw_context
*
1494 brw_context( struct gl_context
*ctx
)
1496 return (struct brw_context
*)ctx
;
1499 static INLINE
struct brw_vertex_program
*
1500 brw_vertex_program(struct gl_vertex_program
*p
)
1502 return (struct brw_vertex_program
*) p
;
1505 static INLINE
const struct brw_vertex_program
*
1506 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1508 return (const struct brw_vertex_program
*) p
;
1511 static INLINE
struct brw_fragment_program
*
1512 brw_fragment_program(struct gl_fragment_program
*p
)
1514 return (struct brw_fragment_program
*) p
;
1517 static INLINE
const struct brw_fragment_program
*
1518 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1520 return (const struct brw_fragment_program
*) p
;
1524 * Pre-gen6, the register file of the EUs was shared between threads,
1525 * and each thread used some subset allocated on a 16-register block
1526 * granularity. The unit states wanted these block counts.
1529 brw_register_blocks(int reg_count
)
1531 return ALIGN(reg_count
, 16) / 16 - 1;
1534 static inline uint32_t
1535 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1536 uint32_t prog_offset
)
1538 if (brw
->gen
>= 5) {
1539 /* Using state base address. */
1543 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1547 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1549 return brw
->cache
.bo
->offset
+ prog_offset
;
1552 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1553 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1554 struct exec_list
*instructions
);
1556 struct opcode_desc
{
1562 extern const struct opcode_desc opcode_descs
[128];
1565 brw_emit_depthbuffer(struct brw_context
*brw
);
1568 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1569 struct intel_mipmap_tree
*depth_mt
,
1570 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1571 uint32_t depth_surface_type
,
1572 struct intel_mipmap_tree
*stencil_mt
,
1573 bool hiz
, bool separate_stencil
,
1574 uint32_t width
, uint32_t height
,
1575 uint32_t tile_x
, uint32_t tile_y
);
1578 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1579 struct intel_mipmap_tree
*depth_mt
,
1580 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1581 uint32_t depth_surface_type
,
1582 struct intel_mipmap_tree
*stencil_mt
,
1583 bool hiz
, bool separate_stencil
,
1584 uint32_t width
, uint32_t height
,
1585 uint32_t tile_x
, uint32_t tile_y
);