2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
37 #include "main/macros.h"
38 #include "main/mtypes.h"
39 #include "brw_structs.h"
40 #include "compiler/brw_compiler.h"
43 #include "blorp/blorp.h"
45 #include <brw_bufmgr.h>
47 #include "common/gen_debug.h"
48 #include "intel_screen.h"
49 #include "intel_tex_obj.h"
56 * URB - uniform resource buffer. A mid-sized buffer which is
57 * partitioned between the fixed function units and used for passing
58 * values (vertices, primitives, constants) between them.
60 * CURBE - constant URB entry. An urb region (entry) used to hold
61 * constant values which the fixed function units can be instructed to
62 * preload into the GRF when spawning a thread.
64 * VUE - vertex URB entry. An urb entry holding a vertex and usually
65 * a vertex header. The header contains control information and
66 * things like primitive type, Begin/end flags and clip codes.
68 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
69 * unit holding rasterization and interpolation parameters.
71 * GRF - general register file. One of several register files
72 * addressable by programmed threads. The inputs (r0, payload, curbe,
73 * urb) of the thread are preloaded to this area before the thread is
74 * spawned. The registers are individually 8 dwords wide and suitable
75 * for general usage. Registers holding thread input values are not
76 * special and may be overwritten.
78 * MRF - message register file. Threads communicate (and terminate)
79 * by sending messages. Message parameters are placed in contiguous
80 * MRF registers. All program output is via these messages. URB
81 * entries are populated by sending a message to the shared URB
82 * function containing the new data, together with a control word,
83 * often an unmodified copy of R0.
85 * R0 - GRF register 0. Typically holds control information used when
86 * sending messages to other threads.
88 * EU or GEN4 EU: The name of the programmable subsystem of the
89 * i965 hardware. Threads are executed by the EU, the registers
90 * described above are part of the EU architecture.
92 * Fixed function units:
94 * CS - Command streamer. Notional first unit, little software
95 * interaction. Holds the URB entries used for constant data, ie the
98 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
99 * this unit is responsible for pulling vertices out of vertex buffers
100 * in vram and injecting them into the processing pipe as VUEs. If
101 * enabled, it first passes them to a VS thread which is a good place
102 * for the driver to implement any active vertex shader.
104 * HS - Hull Shader (Tessellation Control Shader)
106 * TE - Tessellation Engine (Tessellation Primitive Generation)
108 * DS - Domain Shader (Tessellation Evaluation Shader)
110 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
111 * enabled, incoming strips etc are passed to GS threads in individual
112 * line/triangle/point units. The GS thread may perform arbitary
113 * computation and emit whatever primtives with whatever vertices it
114 * chooses. This makes GS an excellent place to implement GL's
115 * unfilled polygon modes, though of course it is capable of much
116 * more. Additionally, GS is used to translate away primitives not
117 * handled by latter units, including Quads and Lineloops.
119 * CS - Clipper. Mesa's clipping algorithms are imported to run on
120 * this unit. The fixed function part performs cliptesting against
121 * the 6 fixed clipplanes and makes descisions on whether or not the
122 * incoming primitive needs to be passed to a thread for clipping.
123 * User clip planes are handled via cooperation with the VS thread.
125 * SF - Strips Fans or Setup: Triangles are prepared for
126 * rasterization. Interpolation coefficients are calculated.
127 * Flatshading and two-side lighting usually performed here.
129 * WM - Windower. Interpolation of vertex attributes performed here.
130 * Fragment shader implemented here. SIMD aspects of EU taken full
131 * advantage of, as pixels are processed in blocks of 16.
133 * CC - Color Calculator. No EU threads associated with this unit.
134 * Handles blending and (presumably) depth and stencil testing.
139 struct brw_vs_prog_key
;
140 struct brw_vue_prog_key
;
141 struct brw_wm_prog_key
;
142 struct brw_wm_prog_data
;
143 struct brw_cs_prog_key
;
144 struct brw_cs_prog_data
;
148 BRW_COMPUTE_PIPELINE
,
155 BRW_CACHE_BLORP_PROG
,
158 BRW_CACHE_FF_GS_PROG
,
169 /* brw_cache_ids must come first - see brw_program_cache.c */
170 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
171 BRW_STATE_FRAGMENT_PROGRAM
,
172 BRW_STATE_GEOMETRY_PROGRAM
,
173 BRW_STATE_TESS_PROGRAMS
,
174 BRW_STATE_VERTEX_PROGRAM
,
175 BRW_STATE_REDUCED_PRIMITIVE
,
176 BRW_STATE_PATCH_PRIMITIVE
,
181 BRW_STATE_BINDING_TABLE_POINTERS
,
184 BRW_STATE_DEFAULT_TESS_LEVELS
,
186 BRW_STATE_INDEX_BUFFER
,
187 BRW_STATE_VS_CONSTBUF
,
188 BRW_STATE_TCS_CONSTBUF
,
189 BRW_STATE_TES_CONSTBUF
,
190 BRW_STATE_GS_CONSTBUF
,
191 BRW_STATE_PROGRAM_CACHE
,
192 BRW_STATE_STATE_BASE_ADDRESS
,
193 BRW_STATE_VUE_MAP_GEOM_OUT
,
194 BRW_STATE_TRANSFORM_FEEDBACK
,
195 BRW_STATE_RASTERIZER_DISCARD
,
197 BRW_STATE_UNIFORM_BUFFER
,
198 BRW_STATE_ATOMIC_BUFFER
,
199 BRW_STATE_IMAGE_UNITS
,
200 BRW_STATE_META_IN_PROGRESS
,
201 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
202 BRW_STATE_NUM_SAMPLES
,
203 BRW_STATE_TEXTURE_BUFFER
,
204 BRW_STATE_GEN4_UNIT_STATE
,
208 BRW_STATE_SAMPLER_STATE_TABLE
,
209 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
210 BRW_STATE_COMPUTE_PROGRAM
,
211 BRW_STATE_CS_WORK_GROUPS
,
215 BRW_STATE_VIEWPORT_COUNT
,
216 BRW_STATE_CONSERVATIVE_RASTERIZATION
,
222 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
224 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
225 * When the currently bound shader program differs from the previous draw
226 * call, these will be flagged. They cover brw->{stage}_program and
227 * ctx->{Stage}Program->_Current.
229 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
230 * driver perspective. Even if the same shader is bound at the API level,
231 * we may need to switch between multiple versions of that shader to handle
232 * changes in non-orthagonal state.
234 * Additionally, multiple shader programs may have identical vertex shaders
235 * (for example), or compile down to the same code in the backend. We combine
236 * those into a single program cache entry.
238 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
239 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
241 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
242 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
243 * use the normal state upload paths), but the cache is still used. To avoid
244 * polluting the brw_program_cache code with special cases, we retain the
245 * dirty bit for now. It should eventually be removed.
247 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_PROG)
248 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
249 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
250 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
251 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
252 #define BRW_NEW_TCS_PROG_DATA (1ull << BRW_CACHE_TCS_PROG)
253 #define BRW_NEW_TES_PROG_DATA (1ull << BRW_CACHE_TES_PROG)
254 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
255 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
256 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
257 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
258 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
259 #define BRW_NEW_TESS_PROGRAMS (1ull << BRW_STATE_TESS_PROGRAMS)
260 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
261 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
262 #define BRW_NEW_PATCH_PRIMITIVE (1ull << BRW_STATE_PATCH_PRIMITIVE)
263 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
264 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
265 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
266 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
267 #define BRW_NEW_BINDING_TABLE_POINTERS (1ull << BRW_STATE_BINDING_TABLE_POINTERS)
268 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
269 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
270 #define BRW_NEW_DEFAULT_TESS_LEVELS (1ull << BRW_STATE_DEFAULT_TESS_LEVELS)
272 * Used for any batch entry with a relocated pointer that will be used
273 * by any 3D rendering.
275 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
276 /** \see brw.state.depth_region */
277 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
278 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
279 #define BRW_NEW_TCS_CONSTBUF (1ull << BRW_STATE_TCS_CONSTBUF)
280 #define BRW_NEW_TES_CONSTBUF (1ull << BRW_STATE_TES_CONSTBUF)
281 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
282 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
283 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
284 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
285 #define BRW_NEW_VIEWPORT_COUNT (1ull << BRW_STATE_VIEWPORT_COUNT)
286 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
287 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
288 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
289 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
290 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
291 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
292 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
293 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
294 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
295 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
296 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
297 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
298 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
299 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
300 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
301 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
302 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
303 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
304 #define BRW_NEW_URB_SIZE (1ull << BRW_STATE_URB_SIZE)
305 #define BRW_NEW_CC_STATE (1ull << BRW_STATE_CC_STATE)
306 #define BRW_NEW_BLORP (1ull << BRW_STATE_BLORP)
307 #define BRW_NEW_CONSERVATIVE_RASTERIZATION (1ull << BRW_STATE_CONSERVATIVE_RASTERIZATION)
308 #define BRW_NEW_DRAW_CALL (1ull << BRW_STATE_DRAW_CALL)
310 struct brw_state_flags
{
311 /** State update flags signalled by mesa internals */
314 * State update flags signalled as the result of brw_tracked_state updates
320 /** Subclass of Mesa program */
322 struct gl_program program
;
329 struct brw_ff_gs_prog_data
{
330 GLuint urb_read_length
;
334 * Gen6 transform feedback: Amount by which the streaming vertex buffer
335 * indices should be incremented each time the GS is invoked.
337 unsigned svbi_postincrement_value
;
340 /** Number of texture sampler units */
341 #define BRW_MAX_TEX_UNIT 32
343 /** Max number of UBOs in a shader */
344 #define BRW_MAX_UBO 14
346 /** Max number of SSBOs in a shader */
347 #define BRW_MAX_SSBO 12
349 /** Max number of atomic counter buffer objects in a shader */
350 #define BRW_MAX_ABO 16
352 /** Max number of image uniforms in a shader */
353 #define BRW_MAX_IMAGES 32
355 /** Maximum number of actual buffers used for stream output */
356 #define BRW_MAX_SOL_BUFFERS 4
358 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
359 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
364 2 + /* shader time, pull constants */ \
365 1 /* cs num work groups */)
368 struct brw_context
*brw
;
370 struct brw_cache_item
**items
;
373 GLuint size
, n_items
;
375 uint32_t next_offset
;
379 /* Considered adding a member to this struct to document which flags
380 * an update might raise so that ordering of the state atoms can be
381 * checked or derived at runtime. Dropped the idea in favor of having
382 * a debug mode where the state is monitored for flags which are
383 * raised that have already been tested against.
385 struct brw_tracked_state
{
386 struct brw_state_flags dirty
;
387 void (*emit
)( struct brw_context
*brw
);
390 enum shader_time_shader_type
{
401 struct brw_vertex_buffer
{
402 /** Buffer object containing the uploaded vertex data */
406 /** Byte stride between elements in the uploaded array */
410 struct brw_vertex_element
{
411 const struct gl_vertex_array
*glarray
;
415 /** Offset of the first element within the buffer object */
419 struct brw_query_object
{
420 struct gl_query_object Base
;
422 /** Last query BO associated with this query. */
425 /** Last index in bo with query data for this object. */
428 /** True if we know the batch has been flushed since we ended the query. */
438 struct intel_batchbuffer
{
439 /** Current batchbuffer being queued up. */
441 /** Last BO submitted to the hardware. Used for glFinish(). */
442 struct brw_bo
*last_bo
;
445 uint16_t emit
, total
;
447 uint16_t reserved_space
;
451 #define BATCH_SZ (8192*sizeof(uint32_t))
453 uint32_t state_batch_offset
;
454 enum brw_gpu_ring ring
;
455 bool needs_sol_reset
;
456 bool state_base_address_emitted
;
458 struct drm_i915_gem_relocation_entry
*relocs
;
460 int reloc_array_size
;
461 /** The validation list */
462 struct drm_i915_gem_exec_object2
*exec_objects
;
463 struct brw_bo
**exec_bos
;
466 /** The amount of aperture space (in bytes) used by all exec_bos */
475 /** Map from batch offset to brw_state_batch data (with DEBUG_BATCH) */
476 struct hash_table
*state_batch_sizes
;
479 #define BRW_MAX_XFB_STREAMS 4
481 struct brw_transform_feedback_object
{
482 struct gl_transform_feedback_object base
;
484 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
485 struct brw_bo
*offset_bo
;
487 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
490 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
491 GLenum primitive_mode
;
494 * The maximum number of vertices that we can write without overflowing
495 * any of the buffers currently being used for transform feedback.
500 * Count of primitives generated during this transform feedback operation.
503 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
504 struct brw_bo
*prim_count_bo
;
505 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
509 * Number of vertices written between last Begin/EndTransformFeedback().
511 * Used to implement DrawTransformFeedback().
513 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
514 bool vertices_written_valid
;
518 * Data shared between each programmable stage in the pipeline (vs, gs, and
521 struct brw_stage_state
523 gl_shader_stage stage
;
524 struct brw_stage_prog_data
*prog_data
;
527 * Optional scratch buffer used to store spilled register values and
528 * variably-indexed GRF arrays.
530 * The contents of this buffer are short-lived so the same memory can be
531 * re-used at will for multiple shader programs (executed by the same fixed
532 * function). However reusing a scratch BO for which shader invocations
533 * are still in flight with a per-thread scratch slot size other than the
534 * original can cause threads with different scratch slot size and FFTID
535 * (which may be executed in parallel depending on the shader stage and
536 * hardware generation) to map to an overlapping region of the scratch
537 * space, which can potentially lead to mutual scratch space corruption.
538 * For that reason if you borrow this scratch buffer you should only be
539 * using the slot size given by the \c per_thread_scratch member below,
540 * unless you're taking additional measures to synchronize thread execution
541 * across slot size changes.
543 struct brw_bo
*scratch_bo
;
546 * Scratch slot size allocated for each thread in the buffer object given
549 uint32_t per_thread_scratch
;
551 /** Offset in the program cache to the program */
552 uint32_t prog_offset
;
554 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
555 uint32_t state_offset
;
557 struct brw_bo
*push_const_bo
; /* NULL if using the batchbuffer */
558 uint32_t push_const_offset
; /* Offset in the push constant BO or batch */
559 int push_const_size
; /* in 256-bit register increments */
561 /* Binding table: pointers to SURFACE_STATE entries. */
562 uint32_t bind_bo_offset
;
563 uint32_t surf_offset
[BRW_MAX_SURFACES
];
565 /** SAMPLER_STATE count and table offset */
566 uint32_t sampler_count
;
567 uint32_t sampler_offset
;
569 /** Need to re-emit 3DSTATE_CONSTANT_XS? */
570 bool push_constants_dirty
;
573 enum brw_predicate_state
{
574 /* The first two states are used if we can determine whether to draw
575 * without having to look at the values in the query object buffer. This
576 * will happen if there is no conditional render in progress, if the query
577 * object is already completed or if something else has already added
578 * samples to the preliminary result such as via a BLT command.
580 BRW_PREDICATE_STATE_RENDER
,
581 BRW_PREDICATE_STATE_DONT_RENDER
,
582 /* In this case whether to draw or not depends on the result of an
583 * MI_PREDICATE command so the predicate enable bit needs to be checked.
585 BRW_PREDICATE_STATE_USE_BIT
,
586 /* In this case, either MI_PREDICATE doesn't exist or we lack the
587 * necessary kernel features to use it. Stall for the query result.
589 BRW_PREDICATE_STATE_STALL_FOR_QUERY
,
594 struct gen_l3_config
;
596 enum brw_query_kind
{
601 struct brw_perf_query_info
603 enum brw_query_kind kind
;
606 struct brw_perf_query_counter
*counters
;
611 uint64_t oa_metrics_set_id
;
614 /* For indexing into the accumulator[] ... */
616 int gpu_clock_offset
;
623 * brw_context is derived from gl_context.
627 struct gl_context ctx
; /**< base class, must be first field */
631 uint32_t (*update_renderbuffer_surface
)(struct brw_context
*brw
,
632 struct gl_renderbuffer
*rb
,
633 uint32_t flags
, unsigned unit
,
634 uint32_t surf_index
);
635 void (*emit_null_surface_state
)(struct brw_context
*brw
,
639 uint32_t *out_offset
);
642 * Send the appropriate state packets to configure depth, stencil, and
643 * HiZ buffers (i965+ only)
645 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
646 struct intel_mipmap_tree
*depth_mt
,
647 uint32_t depth_offset
,
648 uint32_t depthbuffer_format
,
649 uint32_t depth_surface_type
,
650 struct intel_mipmap_tree
*stencil_mt
,
651 bool hiz
, bool separate_stencil
,
652 uint32_t width
, uint32_t height
,
653 uint32_t tile_x
, uint32_t tile_y
);
656 * Emit an MI_REPORT_PERF_COUNT command packet.
658 * This asks the GPU to write a report of the current OA counter values
659 * into @bo at the given offset and containing the given @report_id
660 * which we can cross-reference when parsing the report (gen7+ only).
662 void (*emit_mi_report_perf_count
)(struct brw_context
*brw
,
664 uint32_t offset_in_bytes
,
668 struct brw_bufmgr
*bufmgr
;
672 /** BO for post-sync nonzero writes for gen6 workaround. */
673 struct brw_bo
*workaround_bo
;
674 uint8_t pipe_controls_since_last_cs_stall
;
677 * Set of struct brw_bo * that have been rendered to within this batchbuffer
678 * and would need flushing before being used from another cache domain that
679 * isn't coherent with it (i.e. the sampler).
681 struct set
*render_cache
;
684 * Number of resets observed in the system at context creation.
686 * This is tracked in the context so that we can determine that another
687 * reset has occurred.
689 uint32_t reset_count
;
691 struct intel_batchbuffer batch
;
697 uint32_t next_offset
;
701 * Set if rendering has occurred to the drawable's front buffer.
703 * This is used in the DRI2 case to detect that glFlush should also copy
704 * the contents of the fake front buffer to the real front buffer.
706 bool front_buffer_dirty
;
708 /** Framerate throttling: @{ */
709 struct brw_bo
*throttle_batch
[2];
711 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
712 * frame of rendering to complete. This gives a very precise cap to the
713 * latency between input and output such that rendering never gets more
714 * than a frame behind the user. (With the caveat that we technically are
715 * not using the SwapBuffers itself as a barrier but the first batch
716 * submitted afterwards, which may be immediately prior to the next
719 bool need_swap_throttle
;
721 /** General throttling, not caught by throttling between SwapBuffers */
722 bool need_flush_throttle
;
732 bool always_flush_batch
;
733 bool always_flush_cache
;
734 bool disable_throttling
;
736 bool dual_color_blend_by_location
;
738 driOptionCache optionCache
;
741 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
743 GLenum reduced_primitive
;
746 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
747 * variable is set, this is the flag indicating to do expensive work that
748 * might lead to a perf_debug() call.
752 uint64_t max_gtt_map_object_size
;
764 bool has_separate_stencil
;
765 bool must_use_separate_stencil
;
768 bool has_surface_tile_offset
;
770 bool has_negative_rhw_bug
;
775 * Some versions of Gen hardware don't do centroid interpolation correctly
776 * on unlit pixels, causing incorrect values for derivatives near triangle
777 * edges. Enabling this flag causes the fragment shader to use
778 * non-centroid interpolation for unlit pixels, at the expense of two extra
779 * fragment shader instructions.
781 bool needs_unlit_centroid_workaround
;
783 /** Derived stencil states. */
784 bool stencil_enabled
;
785 bool stencil_two_sided
;
786 bool stencil_write_enabled
;
787 /** Derived polygon state. */
788 bool polygon_front_bit
; /**< 0=GL_CCW, 1=GL_CW */
790 struct isl_device isl_dev
;
792 struct blorp_context blorp
;
796 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
799 enum brw_pipeline last_pipeline
;
801 struct brw_cache cache
;
803 /** IDs for meta stencil blit shader programs. */
804 struct gl_shader_program
*meta_stencil_blit_programs
[2];
806 /* Whether a meta-operation is in progress. */
807 bool meta_in_progress
;
809 /* Whether the last depth/stencil packets were both NULL. */
810 bool no_depth_or_stencil
;
812 /* The last PMA stall bits programmed. */
813 uint32_t pma_stall_bits
;
817 /** The value of gl_BaseVertex for the current _mesa_prim. */
820 /** The value of gl_BaseInstance for the current _mesa_prim. */
825 * Buffer and offset used for GL_ARB_shader_draw_parameters
826 * (for now, only gl_BaseVertex).
828 struct brw_bo
*draw_params_bo
;
829 uint32_t draw_params_offset
;
832 * The value of gl_DrawID for the current _mesa_prim. This always comes
833 * in from it's own vertex buffer since it's not part of the indirect
837 struct brw_bo
*draw_id_bo
;
838 uint32_t draw_id_offset
;
843 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
844 * an indirect call, and num_work_groups_offset is valid. Otherwise,
845 * num_work_groups is set based on glDispatchCompute.
847 struct brw_bo
*num_work_groups_bo
;
848 GLintptr num_work_groups_offset
;
849 const GLuint
*num_work_groups
;
853 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
854 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
856 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
860 /* Summary of size and varying of active arrays, so we can check
861 * for changes to this state:
863 bool index_bounds_valid
;
864 unsigned int min_index
, max_index
;
866 /* Offset from start of vertex buffer so we can avoid redefining
867 * the same VB packed over and over again.
869 unsigned int start_vertex_bias
;
872 * Certain vertex attribute formats aren't natively handled by the
873 * hardware and require special VS code to fix up their values.
875 * These bitfields indicate which workarounds are needed.
877 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
882 * Index buffer for this draw_prims call.
884 * Updates are signaled by BRW_NEW_INDICES.
886 const struct _mesa_index_buffer
*ib
;
888 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
893 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
894 * avoid re-uploading the IB packet over and over if we're actually
895 * referencing the same index buffer.
897 unsigned int start_vertex_offset
;
900 /* Active vertex program:
902 const struct gl_program
*vertex_program
;
903 const struct gl_program
*geometry_program
;
904 const struct gl_program
*tess_ctrl_program
;
905 const struct gl_program
*tess_eval_program
;
906 const struct gl_program
*fragment_program
;
907 const struct gl_program
*compute_program
;
910 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
911 * that we don't have to reemit that state every time we change FBOs.
915 /* BRW_NEW_URB_ALLOCATIONS:
918 GLuint vsize
; /* vertex size plus header in urb registers */
919 GLuint gsize
; /* GS output size in urb registers */
920 GLuint hsize
; /* Tessellation control output size in urb registers */
921 GLuint dsize
; /* Tessellation evaluation output size in urb registers */
922 GLuint csize
; /* constant buffer size in urb registers */
923 GLuint sfsize
; /* setup data size in urb registers */
927 GLuint nr_vs_entries
;
928 GLuint nr_hs_entries
;
929 GLuint nr_ds_entries
;
930 GLuint nr_gs_entries
;
931 GLuint nr_clip_entries
;
932 GLuint nr_sf_entries
;
933 GLuint nr_cs_entries
;
943 * URB size in the current configuration. The units this is expressed
944 * in are somewhat inconsistent, see gen_device_info::urb::size.
946 * FINISHME: Represent the URB size consistently in KB on all platforms.
950 /* True if the most recently sent _3DSTATE_URB message allocated
951 * URB space for the GS.
955 /* True if the most recently sent _3DSTATE_URB message allocated
956 * URB space for the HS and DS.
962 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
964 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
965 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
973 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
974 * for upload to the CURBE.
976 struct brw_bo
*curbe_bo
;
977 /** Offset within curbe_bo of space for current curbe entry */
982 * Layout of vertex data exiting the geometry portion of the pipleine.
983 * This comes from the last enabled shader stage (GS, DS, or VS).
985 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
987 struct brw_vue_map vue_map_geom_out
;
990 struct brw_stage_state base
;
994 struct brw_stage_state base
;
998 struct brw_stage_state base
;
1002 struct brw_stage_state base
;
1005 * True if the 3DSTATE_GS command most recently emitted to the 3D
1006 * pipeline enabled the GS; false otherwise.
1012 struct brw_ff_gs_prog_data
*prog_data
;
1015 /** Offset in the program cache to the CLIP program pre-gen6 */
1016 uint32_t prog_offset
;
1017 uint32_t state_offset
;
1019 uint32_t bind_bo_offset
;
1021 * Surface offsets for the binding table. We only need surfaces to
1022 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1023 * need in this case.
1025 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1029 struct brw_clip_prog_data
*prog_data
;
1031 /** Offset in the program cache to the CLIP program pre-gen6 */
1032 uint32_t prog_offset
;
1034 /* Offset in the batch to the CLIP state on pre-gen6. */
1035 uint32_t state_offset
;
1037 /* As of gen6, this is the offset in the batch to the CLIP VP,
1043 * The number of viewports to use. If gl_ViewportIndex is written,
1044 * we can have up to ctx->Const.MaxViewports viewports. If not,
1045 * the viewport index is always 0, so we can only emit one.
1047 uint8_t viewport_count
;
1052 struct brw_sf_prog_data
*prog_data
;
1054 /** Offset in the program cache to the CLIP program pre-gen6 */
1055 uint32_t prog_offset
;
1056 uint32_t state_offset
;
1061 struct brw_stage_state base
;
1066 * Buffer object used in place of multisampled null render targets on
1067 * Gen6. See brw_emit_null_surface_state().
1069 struct brw_bo
*multisampled_null_render_target_bo
;
1070 uint32_t fast_clear_op
;
1076 struct brw_stage_state base
;
1080 uint32_t state_offset
;
1081 uint32_t blend_state_offset
;
1082 uint32_t depth_stencil_state_offset
;
1087 struct brw_query_object
*obj
;
1092 enum brw_predicate_state state
;
1097 /* Variables referenced in the XML meta data for OA performance
1098 * counters, e.g in the normalization equations.
1100 * All uint64_t for consistent operand types in generated code
1103 uint64_t timestamp_frequency
; /** $GpuTimestampFrequency */
1104 uint64_t n_eus
; /** $EuCoresTotalCount */
1105 uint64_t n_eu_slices
; /** $EuSlicesTotalCount */
1106 uint64_t n_eu_sub_slices
; /** $EuSubslicesTotalCount */
1107 uint64_t eu_threads_count
; /** $EuThreadsCount */
1108 uint64_t slice_mask
; /** $SliceMask */
1109 uint64_t subslice_mask
; /** $SubsliceMask */
1110 uint64_t gt_min_freq
; /** $GpuMinFrequency */
1111 uint64_t gt_max_freq
; /** $GpuMaxFrequency */
1114 /* OA metric sets, indexed by GUID, as know by Mesa at build time,
1115 * to cross-reference with the GUIDs of configs advertised by the
1118 struct hash_table
*oa_metrics_table
;
1120 struct brw_perf_query_info
*queries
;
1123 /* The i915 perf stream we open to setup + enable the OA counters */
1126 /* An i915 perf stream fd gives exclusive access to the OA unit that will
1127 * report counter snapshots for a specific counter set/profile in a
1128 * specific layout/format so we can only start OA queries that are
1129 * compatible with the currently open fd...
1131 int current_oa_metrics_set_id
;
1132 int current_oa_format
;
1134 /* List of buffers containing OA reports */
1135 struct exec_list sample_buffers
;
1137 /* Cached list of empty sample buffers */
1138 struct exec_list free_sample_buffers
;
1140 int n_active_oa_queries
;
1141 int n_active_pipeline_stats_queries
;
1143 /* The number of queries depending on running OA counters which
1144 * extends beyond brw_end_perf_query() since we need to wait until
1145 * the last MI_RPC command has parsed by the GPU.
1147 * Accurate accounting is important here as emitting an
1148 * MI_REPORT_PERF_COUNT command while the OA unit is disabled will
1149 * effectively hang the gpu.
1153 /* To help catch an spurious problem with the hardware or perf
1154 * forwarding samples, we emit each MI_REPORT_PERF_COUNT command
1155 * with a unique ID that we can explicitly check for...
1157 int next_query_start_report_id
;
1160 * An array of queries whose results haven't yet been assembled
1161 * based on the data in buffer objects.
1163 * These may be active, or have already ended. However, the
1164 * results have not been requested.
1166 struct brw_perf_query_object
**unaccumulated
;
1167 int unaccumulated_elements
;
1168 int unaccumulated_array_size
;
1170 /* The total number of query objects so we can relinquish
1171 * our exclusive access to perf if the application deletes
1172 * all of its objects. (NB: We only disable perf while
1173 * there are no active queries)
1175 int n_query_instances
;
1178 int num_atoms
[BRW_NUM_PIPELINES
];
1179 const struct brw_tracked_state render_atoms
[76];
1180 const struct brw_tracked_state compute_atoms
[11];
1182 const enum isl_format
*mesa_to_isl_render_format
;
1183 const bool *mesa_format_supports_render
;
1185 /* PrimitiveRestart */
1188 bool enable_cut_index
;
1191 /** Computed depth/stencil/hiz state from the current attached
1192 * renderbuffers, valid only during the drawing state upload loop after
1193 * brw_workaround_depthstencil_alignment().
1196 /* Inter-tile (page-aligned) byte offsets. */
1197 uint32_t depth_offset
;
1198 /* Intra-tile x,y offsets for drawing to combined depth-stencil. Only
1201 uint32_t tile_x
, tile_y
;
1204 uint32_t num_instances
;
1209 const struct gen_l3_config
*config
;
1216 enum shader_time_shader_type
*types
;
1217 struct shader_times
*cumulative
;
1223 struct brw_fast_clear_state
*fast_clear_state
;
1225 /* Array of flags telling if auxiliary buffer is disabled for corresponding
1226 * renderbuffer. If draw_aux_buffer_disabled[i] is set then use of
1227 * auxiliary buffer for gl_framebuffer::_ColorDrawBuffers[i] is
1229 * This is needed in case the same underlying buffer is also configured
1230 * to be sampled but with a format that the sampling engine can't treat
1231 * compressed or fast cleared.
1233 bool draw_aux_buffer_disabled
[MAX_DRAW_BUFFERS
];
1235 __DRIcontext
*driContext
;
1236 struct intel_screen
*screen
;
1240 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1242 /*======================================================================
1245 extern const char *const brw_vendor_string
;
1248 brw_get_renderer_string(const struct intel_screen
*screen
);
1251 DRI_CONF_BO_REUSE_DISABLED
,
1252 DRI_CONF_BO_REUSE_ALL
1255 void intel_update_renderbuffers(__DRIcontext
*context
,
1256 __DRIdrawable
*drawable
);
1257 void intel_prepare_render(struct brw_context
*brw
);
1259 void brw_predraw_resolve_inputs(struct brw_context
*brw
);
1261 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1262 __DRIdrawable
*drawable
);
1264 GLboolean
brwCreateContext(gl_api api
,
1265 const struct gl_config
*mesaVis
,
1266 __DRIcontext
*driContextPriv
,
1267 unsigned major_version
,
1268 unsigned minor_version
,
1272 void *sharedContextPrivate
);
1274 /*======================================================================
1278 brw_meta_resolve_color(struct brw_context
*brw
,
1279 struct intel_mipmap_tree
*mt
);
1281 /*======================================================================
1284 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1285 GLbitfield clear_mask
);
1287 /* brw_object_purgeable.c */
1288 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1290 /*======================================================================
1293 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1294 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1295 void brw_emit_query_begin(struct brw_context
*brw
);
1296 void brw_emit_query_end(struct brw_context
*brw
);
1297 void brw_query_counter(struct gl_context
*ctx
, struct gl_query_object
*q
);
1298 bool brw_is_query_pipelined(struct brw_query_object
*query
);
1299 uint64_t brw_timebase_scale(struct brw_context
*brw
, uint64_t gpu_timestamp
);
1300 uint64_t brw_raw_timestamp_delta(struct brw_context
*brw
,
1301 uint64_t time0
, uint64_t time1
);
1303 /** gen6_queryobj.c */
1304 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1305 void brw_write_timestamp(struct brw_context
*brw
, struct brw_bo
*bo
, int idx
);
1306 void brw_write_depth_count(struct brw_context
*brw
, struct brw_bo
*bo
, int idx
);
1308 /** hsw_queryobj.c */
1309 void hsw_overflow_result_to_gpr0(struct brw_context
*brw
,
1310 struct brw_query_object
*query
,
1312 void hsw_init_queryobj_functions(struct dd_function_table
*functions
);
1314 /** brw_conditional_render.c */
1315 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1316 bool brw_check_conditional_render(struct brw_context
*brw
);
1318 /** intel_batchbuffer.c */
1319 void brw_load_register_mem(struct brw_context
*brw
,
1322 uint32_t read_domains
, uint32_t write_domain
,
1324 void brw_load_register_mem64(struct brw_context
*brw
,
1327 uint32_t read_domains
, uint32_t write_domain
,
1329 void brw_store_register_mem32(struct brw_context
*brw
,
1330 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
);
1331 void brw_store_register_mem64(struct brw_context
*brw
,
1332 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
);
1333 void brw_load_register_imm32(struct brw_context
*brw
,
1334 uint32_t reg
, uint32_t imm
);
1335 void brw_load_register_imm64(struct brw_context
*brw
,
1336 uint32_t reg
, uint64_t imm
);
1337 void brw_load_register_reg(struct brw_context
*brw
, uint32_t src
,
1339 void brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
,
1341 void brw_store_data_imm32(struct brw_context
*brw
, struct brw_bo
*bo
,
1342 uint32_t offset
, uint32_t imm
);
1343 void brw_store_data_imm64(struct brw_context
*brw
, struct brw_bo
*bo
,
1344 uint32_t offset
, uint64_t imm
);
1346 /*======================================================================
1347 * intel_tex_validate.c
1349 void brw_validate_textures( struct brw_context
*brw
);
1352 /*======================================================================
1356 key_debug(struct brw_context
*brw
, const char *name
, int a
, int b
)
1359 perf_debug(" %s %d->%d\n", name
, a
, b
);
1365 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1367 void brw_get_scratch_bo(struct brw_context
*brw
,
1368 struct brw_bo
**scratch_bo
, int size
);
1369 void brw_alloc_stage_scratch(struct brw_context
*brw
,
1370 struct brw_stage_state
*stage_state
,
1371 unsigned per_thread_size
,
1372 unsigned thread_count
);
1373 void brw_init_shader_time(struct brw_context
*brw
);
1374 int brw_get_shader_time_index(struct brw_context
*brw
,
1375 struct gl_program
*prog
,
1376 enum shader_time_shader_type type
,
1378 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1379 void brw_destroy_shader_time(struct brw_context
*brw
);
1383 void brw_calculate_urb_fence(struct brw_context
*brw
, unsigned csize
,
1384 unsigned vsize
, unsigned sfsize
);
1385 void brw_upload_urb_fence(struct brw_context
*brw
);
1389 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1392 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1394 /* brw_draw_upload.c */
1395 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1396 const struct gl_vertex_array
*glarray
);
1398 static inline unsigned
1399 brw_get_index_type(unsigned index_size
)
1401 /* The hw needs 0x00, 0x01, and 0x02 for ubyte, ushort, and uint,
1404 return index_size
>> 1;
1407 void brw_prepare_vertices(struct brw_context
*brw
);
1409 /* brw_wm_surface_state.c */
1410 void brw_create_constant_surface(struct brw_context
*brw
,
1414 uint32_t *out_offset
);
1415 void brw_create_buffer_surface(struct brw_context
*brw
,
1419 uint32_t *out_offset
);
1420 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1422 uint32_t *surf_offset
);
1424 brw_update_sol_surface(struct brw_context
*brw
,
1425 struct gl_buffer_object
*buffer_obj
,
1426 uint32_t *out_offset
, unsigned num_vector_components
,
1427 unsigned stride_dwords
, unsigned offset_dwords
);
1428 void brw_upload_ubo_surfaces(struct brw_context
*brw
, struct gl_program
*prog
,
1429 struct brw_stage_state
*stage_state
,
1430 struct brw_stage_prog_data
*prog_data
);
1431 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1432 const struct gl_program
*prog
,
1433 struct brw_stage_state
*stage_state
,
1434 struct brw_stage_prog_data
*prog_data
);
1435 void brw_upload_image_surfaces(struct brw_context
*brw
,
1436 const struct gl_program
*prog
,
1437 struct brw_stage_state
*stage_state
,
1438 struct brw_stage_prog_data
*prog_data
);
1440 /* brw_surface_formats.c */
1441 void intel_screen_init_surface_formats(struct intel_screen
*screen
);
1442 void brw_init_surface_formats(struct brw_context
*brw
);
1443 bool brw_render_target_supported(struct brw_context
*brw
,
1444 struct gl_renderbuffer
*rb
);
1445 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1447 /* brw_performance_query.c */
1448 void brw_init_performance_queries(struct brw_context
*brw
);
1450 /* intel_extensions.c */
1451 extern void intelInitExtensions(struct gl_context
*ctx
);
1454 extern int intel_translate_shadow_compare_func(GLenum func
);
1455 extern int intel_translate_compare_func(GLenum func
);
1456 extern int intel_translate_stencil_op(GLenum op
);
1457 extern int intel_translate_logic_op(GLenum opcode
);
1460 void brw_init_syncobj_functions(struct dd_function_table
*functions
);
1463 struct gl_transform_feedback_object
*
1464 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1466 brw_delete_transform_feedback(struct gl_context
*ctx
,
1467 struct gl_transform_feedback_object
*obj
);
1469 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1470 struct gl_transform_feedback_object
*obj
);
1472 brw_end_transform_feedback(struct gl_context
*ctx
,
1473 struct gl_transform_feedback_object
*obj
);
1475 brw_pause_transform_feedback(struct gl_context
*ctx
,
1476 struct gl_transform_feedback_object
*obj
);
1478 brw_resume_transform_feedback(struct gl_context
*ctx
,
1479 struct gl_transform_feedback_object
*obj
);
1481 brw_save_primitives_written_counters(struct brw_context
*brw
,
1482 struct brw_transform_feedback_object
*obj
);
1484 brw_compute_xfb_vertices_written(struct brw_context
*brw
,
1485 struct brw_transform_feedback_object
*obj
);
1487 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1488 struct gl_transform_feedback_object
*obj
,
1491 /* gen7_sol_state.c */
1493 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1494 struct gl_transform_feedback_object
*obj
);
1496 gen7_end_transform_feedback(struct gl_context
*ctx
,
1497 struct gl_transform_feedback_object
*obj
);
1499 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1500 struct gl_transform_feedback_object
*obj
);
1502 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1503 struct gl_transform_feedback_object
*obj
);
1507 hsw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1508 struct gl_transform_feedback_object
*obj
);
1510 hsw_end_transform_feedback(struct gl_context
*ctx
,
1511 struct gl_transform_feedback_object
*obj
);
1513 hsw_pause_transform_feedback(struct gl_context
*ctx
,
1514 struct gl_transform_feedback_object
*obj
);
1516 hsw_resume_transform_feedback(struct gl_context
*ctx
,
1517 struct gl_transform_feedback_object
*obj
);
1519 /* brw_blorp_blit.cpp */
1521 brw_blorp_framebuffer(struct brw_context
*brw
,
1522 struct gl_framebuffer
*readFb
,
1523 struct gl_framebuffer
*drawFb
,
1524 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1525 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1526 GLbitfield mask
, GLenum filter
);
1529 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1530 struct gl_renderbuffer
*src_rb
,
1531 struct gl_texture_image
*dst_image
,
1533 int srcX0
, int srcY0
,
1534 int dstX0
, int dstY0
,
1535 int width
, int height
);
1538 gen6_get_sample_position(struct gl_context
*ctx
,
1539 struct gl_framebuffer
*fb
,
1543 gen6_set_sample_maps(struct gl_context
*ctx
);
1545 /* gen8_multisample_state.c */
1546 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1547 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1551 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1552 unsigned hs_size
, unsigned ds_size
,
1553 unsigned gs_size
, unsigned fs_size
);
1556 gen6_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1557 bool gs_present
, unsigned gs_size
);
1559 gen7_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1560 bool gs_present
, bool tess_present
);
1564 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1566 brw_check_for_reset(struct brw_context
*brw
);
1570 brw_init_compute_functions(struct dd_function_table
*functions
);
1572 /*======================================================================
1573 * Inline conversion functions. These are better-typed than the
1574 * macros used previously:
1576 static inline struct brw_context
*
1577 brw_context( struct gl_context
*ctx
)
1579 return (struct brw_context
*)ctx
;
1582 static inline struct brw_program
*
1583 brw_program(struct gl_program
*p
)
1585 return (struct brw_program
*) p
;
1588 static inline const struct brw_program
*
1589 brw_program_const(const struct gl_program
*p
)
1591 return (const struct brw_program
*) p
;
1595 brw_depth_writes_enabled(const struct brw_context
*brw
)
1597 const struct gl_context
*ctx
= &brw
->ctx
;
1599 /* We consider depth writes disabled if the depth function is GL_EQUAL,
1600 * because it would just overwrite the existing depth value with itself.
1602 * These bonus depth writes not only use bandwidth, but they also can
1603 * prevent early depth processing. For example, if the pixel shader
1604 * discards, the hardware must invoke the to determine whether or not
1605 * to do the depth write. If writes are disabled, we may still be able
1606 * to do the depth test before the shader, and skip the shader execution.
1608 * The Broadwell 3DSTATE_WM_DEPTH_STENCIL documentation also contains
1609 * a programming note saying to disable depth writes for EQUAL.
1611 return ctx
->Depth
.Test
&& ctx
->Depth
.Mask
&& ctx
->Depth
.Func
!= GL_EQUAL
;
1615 brw_emit_depthbuffer(struct brw_context
*brw
);
1618 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1619 struct intel_mipmap_tree
*depth_mt
,
1620 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1621 uint32_t depth_surface_type
,
1622 struct intel_mipmap_tree
*stencil_mt
,
1623 bool hiz
, bool separate_stencil
,
1624 uint32_t width
, uint32_t height
,
1625 uint32_t tile_x
, uint32_t tile_y
);
1628 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1629 struct intel_mipmap_tree
*depth_mt
,
1630 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1631 uint32_t depth_surface_type
,
1632 struct intel_mipmap_tree
*stencil_mt
,
1633 bool hiz
, bool separate_stencil
,
1634 uint32_t width
, uint32_t height
,
1635 uint32_t tile_x
, uint32_t tile_y
);
1638 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1639 struct intel_mipmap_tree
*depth_mt
,
1640 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1641 uint32_t depth_surface_type
,
1642 struct intel_mipmap_tree
*stencil_mt
,
1643 bool hiz
, bool separate_stencil
,
1644 uint32_t width
, uint32_t height
,
1645 uint32_t tile_x
, uint32_t tile_y
);
1647 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1648 struct intel_mipmap_tree
*depth_mt
,
1649 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1650 uint32_t depth_surface_type
,
1651 struct intel_mipmap_tree
*stencil_mt
,
1652 bool hiz
, bool separate_stencil
,
1653 uint32_t width
, uint32_t height
,
1654 uint32_t tile_x
, uint32_t tile_y
);
1656 uint32_t get_hw_prim_for_gl_prim(int mode
);
1659 gen6_upload_push_constants(struct brw_context
*brw
,
1660 const struct gl_program
*prog
,
1661 const struct brw_stage_prog_data
*prog_data
,
1662 struct brw_stage_state
*stage_state
);
1665 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
1666 const struct intel_mipmap_tree
*mt
);
1668 /* brw_pipe_control.c */
1669 int brw_init_pipe_control(struct brw_context
*brw
,
1670 const struct gen_device_info
*info
);
1671 void brw_fini_pipe_control(struct brw_context
*brw
);
1673 void brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
);
1674 void brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
1675 struct brw_bo
*bo
, uint32_t offset
,
1677 void brw_emit_end_of_pipe_sync(struct brw_context
*brw
, uint32_t flags
);
1678 void brw_emit_mi_flush(struct brw_context
*brw
);
1679 void brw_emit_post_sync_nonzero_flush(struct brw_context
*brw
);
1680 void brw_emit_depth_stall_flushes(struct brw_context
*brw
);
1681 void gen7_emit_vs_workaround_flush(struct brw_context
*brw
);
1682 void gen7_emit_cs_stall_flush(struct brw_context
*brw
);
1684 /* brw_queryformat.c */
1685 void brw_query_internal_format(struct gl_context
*ctx
, GLenum target
,
1686 GLenum internalFormat
, GLenum pname
,