2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
37 #include "main/macros.h"
38 #include "main/mtypes.h"
39 #include "brw_structs.h"
40 #include "compiler/brw_compiler.h"
43 #include "blorp/blorp.h"
45 #include <brw_bufmgr.h>
47 #include "common/gen_debug.h"
48 #include "intel_screen.h"
49 #include "intel_tex_obj.h"
56 * URB - uniform resource buffer. A mid-sized buffer which is
57 * partitioned between the fixed function units and used for passing
58 * values (vertices, primitives, constants) between them.
60 * CURBE - constant URB entry. An urb region (entry) used to hold
61 * constant values which the fixed function units can be instructed to
62 * preload into the GRF when spawning a thread.
64 * VUE - vertex URB entry. An urb entry holding a vertex and usually
65 * a vertex header. The header contains control information and
66 * things like primitive type, Begin/end flags and clip codes.
68 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
69 * unit holding rasterization and interpolation parameters.
71 * GRF - general register file. One of several register files
72 * addressable by programmed threads. The inputs (r0, payload, curbe,
73 * urb) of the thread are preloaded to this area before the thread is
74 * spawned. The registers are individually 8 dwords wide and suitable
75 * for general usage. Registers holding thread input values are not
76 * special and may be overwritten.
78 * MRF - message register file. Threads communicate (and terminate)
79 * by sending messages. Message parameters are placed in contiguous
80 * MRF registers. All program output is via these messages. URB
81 * entries are populated by sending a message to the shared URB
82 * function containing the new data, together with a control word,
83 * often an unmodified copy of R0.
85 * R0 - GRF register 0. Typically holds control information used when
86 * sending messages to other threads.
88 * EU or GEN4 EU: The name of the programmable subsystem of the
89 * i965 hardware. Threads are executed by the EU, the registers
90 * described above are part of the EU architecture.
92 * Fixed function units:
94 * CS - Command streamer. Notional first unit, little software
95 * interaction. Holds the URB entries used for constant data, ie the
98 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
99 * this unit is responsible for pulling vertices out of vertex buffers
100 * in vram and injecting them into the processing pipe as VUEs. If
101 * enabled, it first passes them to a VS thread which is a good place
102 * for the driver to implement any active vertex shader.
104 * HS - Hull Shader (Tessellation Control Shader)
106 * TE - Tessellation Engine (Tessellation Primitive Generation)
108 * DS - Domain Shader (Tessellation Evaluation Shader)
110 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
111 * enabled, incoming strips etc are passed to GS threads in individual
112 * line/triangle/point units. The GS thread may perform arbitary
113 * computation and emit whatever primtives with whatever vertices it
114 * chooses. This makes GS an excellent place to implement GL's
115 * unfilled polygon modes, though of course it is capable of much
116 * more. Additionally, GS is used to translate away primitives not
117 * handled by latter units, including Quads and Lineloops.
119 * CS - Clipper. Mesa's clipping algorithms are imported to run on
120 * this unit. The fixed function part performs cliptesting against
121 * the 6 fixed clipplanes and makes descisions on whether or not the
122 * incoming primitive needs to be passed to a thread for clipping.
123 * User clip planes are handled via cooperation with the VS thread.
125 * SF - Strips Fans or Setup: Triangles are prepared for
126 * rasterization. Interpolation coefficients are calculated.
127 * Flatshading and two-side lighting usually performed here.
129 * WM - Windower. Interpolation of vertex attributes performed here.
130 * Fragment shader implemented here. SIMD aspects of EU taken full
131 * advantage of, as pixels are processed in blocks of 16.
133 * CC - Color Calculator. No EU threads associated with this unit.
134 * Handles blending and (presumably) depth and stencil testing.
139 struct brw_vs_prog_key
;
140 struct brw_vue_prog_key
;
141 struct brw_wm_prog_key
;
142 struct brw_wm_prog_data
;
143 struct brw_cs_prog_key
;
144 struct brw_cs_prog_data
;
148 BRW_COMPUTE_PIPELINE
,
155 BRW_CACHE_BLORP_PROG
,
158 BRW_CACHE_FF_GS_PROG
,
169 /* brw_cache_ids must come first - see brw_program_cache.c */
170 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
171 BRW_STATE_FRAGMENT_PROGRAM
,
172 BRW_STATE_GEOMETRY_PROGRAM
,
173 BRW_STATE_TESS_PROGRAMS
,
174 BRW_STATE_VERTEX_PROGRAM
,
175 BRW_STATE_REDUCED_PRIMITIVE
,
176 BRW_STATE_PATCH_PRIMITIVE
,
181 BRW_STATE_BINDING_TABLE_POINTERS
,
184 BRW_STATE_DEFAULT_TESS_LEVELS
,
186 BRW_STATE_INDEX_BUFFER
,
187 BRW_STATE_VS_CONSTBUF
,
188 BRW_STATE_TCS_CONSTBUF
,
189 BRW_STATE_TES_CONSTBUF
,
190 BRW_STATE_GS_CONSTBUF
,
191 BRW_STATE_PROGRAM_CACHE
,
192 BRW_STATE_STATE_BASE_ADDRESS
,
193 BRW_STATE_VUE_MAP_GEOM_OUT
,
194 BRW_STATE_TRANSFORM_FEEDBACK
,
195 BRW_STATE_RASTERIZER_DISCARD
,
197 BRW_STATE_UNIFORM_BUFFER
,
198 BRW_STATE_ATOMIC_BUFFER
,
199 BRW_STATE_IMAGE_UNITS
,
200 BRW_STATE_META_IN_PROGRESS
,
201 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
202 BRW_STATE_NUM_SAMPLES
,
203 BRW_STATE_TEXTURE_BUFFER
,
204 BRW_STATE_GEN4_UNIT_STATE
,
208 BRW_STATE_SAMPLER_STATE_TABLE
,
209 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
210 BRW_STATE_COMPUTE_PROGRAM
,
211 BRW_STATE_CS_WORK_GROUPS
,
215 BRW_STATE_VIEWPORT_COUNT
,
216 BRW_STATE_CONSERVATIVE_RASTERIZATION
,
222 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
224 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
225 * When the currently bound shader program differs from the previous draw
226 * call, these will be flagged. They cover brw->{stage}_program and
227 * ctx->{Stage}Program->_Current.
229 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
230 * driver perspective. Even if the same shader is bound at the API level,
231 * we may need to switch between multiple versions of that shader to handle
232 * changes in non-orthagonal state.
234 * Additionally, multiple shader programs may have identical vertex shaders
235 * (for example), or compile down to the same code in the backend. We combine
236 * those into a single program cache entry.
238 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
239 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
241 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
242 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
243 * use the normal state upload paths), but the cache is still used. To avoid
244 * polluting the brw_program_cache code with special cases, we retain the
245 * dirty bit for now. It should eventually be removed.
247 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_PROG)
248 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
249 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
250 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
251 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
252 #define BRW_NEW_TCS_PROG_DATA (1ull << BRW_CACHE_TCS_PROG)
253 #define BRW_NEW_TES_PROG_DATA (1ull << BRW_CACHE_TES_PROG)
254 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
255 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
256 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
257 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
258 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
259 #define BRW_NEW_TESS_PROGRAMS (1ull << BRW_STATE_TESS_PROGRAMS)
260 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
261 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
262 #define BRW_NEW_PATCH_PRIMITIVE (1ull << BRW_STATE_PATCH_PRIMITIVE)
263 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
264 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
265 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
266 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
267 #define BRW_NEW_BINDING_TABLE_POINTERS (1ull << BRW_STATE_BINDING_TABLE_POINTERS)
268 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
269 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
270 #define BRW_NEW_DEFAULT_TESS_LEVELS (1ull << BRW_STATE_DEFAULT_TESS_LEVELS)
272 * Used for any batch entry with a relocated pointer that will be used
273 * by any 3D rendering.
275 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
276 /** \see brw.state.depth_region */
277 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
278 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
279 #define BRW_NEW_TCS_CONSTBUF (1ull << BRW_STATE_TCS_CONSTBUF)
280 #define BRW_NEW_TES_CONSTBUF (1ull << BRW_STATE_TES_CONSTBUF)
281 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
282 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
283 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
284 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
285 #define BRW_NEW_VIEWPORT_COUNT (1ull << BRW_STATE_VIEWPORT_COUNT)
286 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
287 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
288 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
289 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
290 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
291 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
292 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
293 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
294 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
295 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
296 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
297 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
298 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
299 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
300 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
301 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
302 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
303 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
304 #define BRW_NEW_URB_SIZE (1ull << BRW_STATE_URB_SIZE)
305 #define BRW_NEW_CC_STATE (1ull << BRW_STATE_CC_STATE)
306 #define BRW_NEW_BLORP (1ull << BRW_STATE_BLORP)
307 #define BRW_NEW_CONSERVATIVE_RASTERIZATION (1ull << BRW_STATE_CONSERVATIVE_RASTERIZATION)
308 #define BRW_NEW_DRAW_CALL (1ull << BRW_STATE_DRAW_CALL)
310 struct brw_state_flags
{
311 /** State update flags signalled by mesa internals */
314 * State update flags signalled as the result of brw_tracked_state updates
320 /** Subclass of Mesa program */
322 struct gl_program program
;
329 struct brw_ff_gs_prog_data
{
330 GLuint urb_read_length
;
334 * Gen6 transform feedback: Amount by which the streaming vertex buffer
335 * indices should be incremented each time the GS is invoked.
337 unsigned svbi_postincrement_value
;
340 /** Number of texture sampler units */
341 #define BRW_MAX_TEX_UNIT 32
343 /** Max number of UBOs in a shader */
344 #define BRW_MAX_UBO 14
346 /** Max number of SSBOs in a shader */
347 #define BRW_MAX_SSBO 12
349 /** Max number of atomic counter buffer objects in a shader */
350 #define BRW_MAX_ABO 16
352 /** Max number of image uniforms in a shader */
353 #define BRW_MAX_IMAGES 32
355 /** Maximum number of actual buffers used for stream output */
356 #define BRW_MAX_SOL_BUFFERS 4
358 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
359 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
364 2 + /* shader time, pull constants */ \
365 1 /* cs num work groups */)
368 struct brw_context
*brw
;
370 struct brw_cache_item
**items
;
373 GLuint size
, n_items
;
375 uint32_t next_offset
;
378 /* Considered adding a member to this struct to document which flags
379 * an update might raise so that ordering of the state atoms can be
380 * checked or derived at runtime. Dropped the idea in favor of having
381 * a debug mode where the state is monitored for flags which are
382 * raised that have already been tested against.
384 struct brw_tracked_state
{
385 struct brw_state_flags dirty
;
386 void (*emit
)( struct brw_context
*brw
);
389 enum shader_time_shader_type
{
400 struct brw_vertex_buffer
{
401 /** Buffer object containing the uploaded vertex data */
405 /** Byte stride between elements in the uploaded array */
409 struct brw_vertex_element
{
410 const struct gl_vertex_array
*glarray
;
414 /** Offset of the first element within the buffer object */
418 struct brw_query_object
{
419 struct gl_query_object Base
;
421 /** Last query BO associated with this query. */
424 /** Last index in bo with query data for this object. */
427 /** True if we know the batch has been flushed since we ended the query. */
437 struct intel_batchbuffer
{
438 /** Current batchbuffer being queued up. */
440 /** Last BO submitted to the hardware. Used for glFinish(). */
441 struct brw_bo
*last_bo
;
444 uint16_t emit
, total
;
446 uint16_t reserved_space
;
450 #define BATCH_SZ (8192*sizeof(uint32_t))
452 uint32_t state_batch_offset
;
453 enum brw_gpu_ring ring
;
454 bool needs_sol_reset
;
455 bool state_base_address_emitted
;
457 struct drm_i915_gem_relocation_entry
*relocs
;
459 int reloc_array_size
;
461 /** The validation list */
462 struct drm_i915_gem_exec_object2
*validation_list
;
463 struct brw_bo
**exec_bos
;
467 /** The amount of aperture space (in bytes) used by all exec_bos */
476 /** Map from batch offset to brw_state_batch data (with DEBUG_BATCH) */
477 struct hash_table
*state_batch_sizes
;
480 #define BRW_MAX_XFB_STREAMS 4
482 struct brw_transform_feedback_object
{
483 struct gl_transform_feedback_object base
;
485 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
486 struct brw_bo
*offset_bo
;
488 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
491 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
492 GLenum primitive_mode
;
495 * The maximum number of vertices that we can write without overflowing
496 * any of the buffers currently being used for transform feedback.
501 * Count of primitives generated during this transform feedback operation.
504 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
505 struct brw_bo
*prim_count_bo
;
506 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
510 * Number of vertices written between last Begin/EndTransformFeedback().
512 * Used to implement DrawTransformFeedback().
514 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
515 bool vertices_written_valid
;
519 * Data shared between each programmable stage in the pipeline (vs, gs, and
522 struct brw_stage_state
524 gl_shader_stage stage
;
525 struct brw_stage_prog_data
*prog_data
;
528 * Optional scratch buffer used to store spilled register values and
529 * variably-indexed GRF arrays.
531 * The contents of this buffer are short-lived so the same memory can be
532 * re-used at will for multiple shader programs (executed by the same fixed
533 * function). However reusing a scratch BO for which shader invocations
534 * are still in flight with a per-thread scratch slot size other than the
535 * original can cause threads with different scratch slot size and FFTID
536 * (which may be executed in parallel depending on the shader stage and
537 * hardware generation) to map to an overlapping region of the scratch
538 * space, which can potentially lead to mutual scratch space corruption.
539 * For that reason if you borrow this scratch buffer you should only be
540 * using the slot size given by the \c per_thread_scratch member below,
541 * unless you're taking additional measures to synchronize thread execution
542 * across slot size changes.
544 struct brw_bo
*scratch_bo
;
547 * Scratch slot size allocated for each thread in the buffer object given
550 uint32_t per_thread_scratch
;
552 /** Offset in the program cache to the program */
553 uint32_t prog_offset
;
555 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
556 uint32_t state_offset
;
558 struct brw_bo
*push_const_bo
; /* NULL if using the batchbuffer */
559 uint32_t push_const_offset
; /* Offset in the push constant BO or batch */
560 int push_const_size
; /* in 256-bit register increments */
562 /* Binding table: pointers to SURFACE_STATE entries. */
563 uint32_t bind_bo_offset
;
564 uint32_t surf_offset
[BRW_MAX_SURFACES
];
566 /** SAMPLER_STATE count and table offset */
567 uint32_t sampler_count
;
568 uint32_t sampler_offset
;
570 /** Need to re-emit 3DSTATE_CONSTANT_XS? */
571 bool push_constants_dirty
;
574 enum brw_predicate_state
{
575 /* The first two states are used if we can determine whether to draw
576 * without having to look at the values in the query object buffer. This
577 * will happen if there is no conditional render in progress, if the query
578 * object is already completed or if something else has already added
579 * samples to the preliminary result such as via a BLT command.
581 BRW_PREDICATE_STATE_RENDER
,
582 BRW_PREDICATE_STATE_DONT_RENDER
,
583 /* In this case whether to draw or not depends on the result of an
584 * MI_PREDICATE command so the predicate enable bit needs to be checked.
586 BRW_PREDICATE_STATE_USE_BIT
,
587 /* In this case, either MI_PREDICATE doesn't exist or we lack the
588 * necessary kernel features to use it. Stall for the query result.
590 BRW_PREDICATE_STATE_STALL_FOR_QUERY
,
595 struct gen_l3_config
;
597 enum brw_query_kind
{
602 struct brw_perf_query_info
604 enum brw_query_kind kind
;
607 struct brw_perf_query_counter
*counters
;
612 uint64_t oa_metrics_set_id
;
615 /* For indexing into the accumulator[] ... */
617 int gpu_clock_offset
;
624 * brw_context is derived from gl_context.
628 struct gl_context ctx
; /**< base class, must be first field */
632 uint32_t (*update_renderbuffer_surface
)(struct brw_context
*brw
,
633 struct gl_renderbuffer
*rb
,
634 uint32_t flags
, unsigned unit
,
635 uint32_t surf_index
);
636 void (*emit_null_surface_state
)(struct brw_context
*brw
,
640 uint32_t *out_offset
);
643 * Send the appropriate state packets to configure depth, stencil, and
644 * HiZ buffers (i965+ only)
646 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
647 struct intel_mipmap_tree
*depth_mt
,
648 uint32_t depth_offset
,
649 uint32_t depthbuffer_format
,
650 uint32_t depth_surface_type
,
651 struct intel_mipmap_tree
*stencil_mt
,
652 bool hiz
, bool separate_stencil
,
653 uint32_t width
, uint32_t height
,
654 uint32_t tile_x
, uint32_t tile_y
);
657 * Emit an MI_REPORT_PERF_COUNT command packet.
659 * This asks the GPU to write a report of the current OA counter values
660 * into @bo at the given offset and containing the given @report_id
661 * which we can cross-reference when parsing the report (gen7+ only).
663 void (*emit_mi_report_perf_count
)(struct brw_context
*brw
,
665 uint32_t offset_in_bytes
,
669 struct brw_bufmgr
*bufmgr
;
673 /** BO for post-sync nonzero writes for gen6 workaround. */
674 struct brw_bo
*workaround_bo
;
675 uint8_t pipe_controls_since_last_cs_stall
;
678 * Set of struct brw_bo * that have been rendered to within this batchbuffer
679 * and would need flushing before being used from another cache domain that
680 * isn't coherent with it (i.e. the sampler).
682 struct set
*render_cache
;
685 * Number of resets observed in the system at context creation.
687 * This is tracked in the context so that we can determine that another
688 * reset has occurred.
690 uint32_t reset_count
;
692 struct intel_batchbuffer batch
;
698 uint32_t next_offset
;
702 * Set if rendering has occurred to the drawable's front buffer.
704 * This is used in the DRI2 case to detect that glFlush should also copy
705 * the contents of the fake front buffer to the real front buffer.
707 bool front_buffer_dirty
;
709 /** Framerate throttling: @{ */
710 struct brw_bo
*throttle_batch
[2];
712 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
713 * frame of rendering to complete. This gives a very precise cap to the
714 * latency between input and output such that rendering never gets more
715 * than a frame behind the user. (With the caveat that we technically are
716 * not using the SwapBuffers itself as a barrier but the first batch
717 * submitted afterwards, which may be immediately prior to the next
720 bool need_swap_throttle
;
722 /** General throttling, not caught by throttling between SwapBuffers */
723 bool need_flush_throttle
;
733 bool always_flush_batch
;
734 bool always_flush_cache
;
735 bool disable_throttling
;
737 bool dual_color_blend_by_location
;
739 driOptionCache optionCache
;
742 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
744 GLenum reduced_primitive
;
747 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
748 * variable is set, this is the flag indicating to do expensive work that
749 * might lead to a perf_debug() call.
753 uint64_t max_gtt_map_object_size
;
765 bool has_separate_stencil
;
766 bool must_use_separate_stencil
;
769 bool has_surface_tile_offset
;
771 bool has_negative_rhw_bug
;
776 * Some versions of Gen hardware don't do centroid interpolation correctly
777 * on unlit pixels, causing incorrect values for derivatives near triangle
778 * edges. Enabling this flag causes the fragment shader to use
779 * non-centroid interpolation for unlit pixels, at the expense of two extra
780 * fragment shader instructions.
782 bool needs_unlit_centroid_workaround
;
784 /** Derived stencil states. */
785 bool stencil_enabled
;
786 bool stencil_two_sided
;
787 bool stencil_write_enabled
;
788 /** Derived polygon state. */
789 bool polygon_front_bit
; /**< 0=GL_CCW, 1=GL_CW */
791 struct isl_device isl_dev
;
793 struct blorp_context blorp
;
797 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
800 enum brw_pipeline last_pipeline
;
802 struct brw_cache cache
;
804 /** IDs for meta stencil blit shader programs. */
805 struct gl_shader_program
*meta_stencil_blit_programs
[2];
807 /* Whether a meta-operation is in progress. */
808 bool meta_in_progress
;
810 /* Whether the last depth/stencil packets were both NULL. */
811 bool no_depth_or_stencil
;
813 /* The last PMA stall bits programmed. */
814 uint32_t pma_stall_bits
;
818 /** The value of gl_BaseVertex for the current _mesa_prim. */
821 /** The value of gl_BaseInstance for the current _mesa_prim. */
826 * Buffer and offset used for GL_ARB_shader_draw_parameters
827 * (for now, only gl_BaseVertex).
829 struct brw_bo
*draw_params_bo
;
830 uint32_t draw_params_offset
;
833 * The value of gl_DrawID for the current _mesa_prim. This always comes
834 * in from it's own vertex buffer since it's not part of the indirect
838 struct brw_bo
*draw_id_bo
;
839 uint32_t draw_id_offset
;
844 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
845 * an indirect call, and num_work_groups_offset is valid. Otherwise,
846 * num_work_groups is set based on glDispatchCompute.
848 struct brw_bo
*num_work_groups_bo
;
849 GLintptr num_work_groups_offset
;
850 const GLuint
*num_work_groups
;
854 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
855 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
857 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
861 /* Summary of size and varying of active arrays, so we can check
862 * for changes to this state:
864 bool index_bounds_valid
;
865 unsigned int min_index
, max_index
;
867 /* Offset from start of vertex buffer so we can avoid redefining
868 * the same VB packed over and over again.
870 unsigned int start_vertex_bias
;
873 * Certain vertex attribute formats aren't natively handled by the
874 * hardware and require special VS code to fix up their values.
876 * These bitfields indicate which workarounds are needed.
878 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
883 * Index buffer for this draw_prims call.
885 * Updates are signaled by BRW_NEW_INDICES.
887 const struct _mesa_index_buffer
*ib
;
889 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
894 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
895 * avoid re-uploading the IB packet over and over if we're actually
896 * referencing the same index buffer.
898 unsigned int start_vertex_offset
;
901 /* Active vertex program:
903 const struct gl_program
*vertex_program
;
904 const struct gl_program
*geometry_program
;
905 const struct gl_program
*tess_ctrl_program
;
906 const struct gl_program
*tess_eval_program
;
907 const struct gl_program
*fragment_program
;
908 const struct gl_program
*compute_program
;
911 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
912 * that we don't have to reemit that state every time we change FBOs.
916 /* BRW_NEW_URB_ALLOCATIONS:
919 GLuint vsize
; /* vertex size plus header in urb registers */
920 GLuint gsize
; /* GS output size in urb registers */
921 GLuint hsize
; /* Tessellation control output size in urb registers */
922 GLuint dsize
; /* Tessellation evaluation output size in urb registers */
923 GLuint csize
; /* constant buffer size in urb registers */
924 GLuint sfsize
; /* setup data size in urb registers */
928 GLuint nr_vs_entries
;
929 GLuint nr_hs_entries
;
930 GLuint nr_ds_entries
;
931 GLuint nr_gs_entries
;
932 GLuint nr_clip_entries
;
933 GLuint nr_sf_entries
;
934 GLuint nr_cs_entries
;
944 * URB size in the current configuration. The units this is expressed
945 * in are somewhat inconsistent, see gen_device_info::urb::size.
947 * FINISHME: Represent the URB size consistently in KB on all platforms.
951 /* True if the most recently sent _3DSTATE_URB message allocated
952 * URB space for the GS.
956 /* True if the most recently sent _3DSTATE_URB message allocated
957 * URB space for the HS and DS.
963 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
965 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
966 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
974 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
975 * for upload to the CURBE.
977 struct brw_bo
*curbe_bo
;
978 /** Offset within curbe_bo of space for current curbe entry */
983 * Layout of vertex data exiting the geometry portion of the pipleine.
984 * This comes from the last enabled shader stage (GS, DS, or VS).
986 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
988 struct brw_vue_map vue_map_geom_out
;
991 struct brw_stage_state base
;
995 struct brw_stage_state base
;
999 struct brw_stage_state base
;
1003 struct brw_stage_state base
;
1006 * True if the 3DSTATE_GS command most recently emitted to the 3D
1007 * pipeline enabled the GS; false otherwise.
1013 struct brw_ff_gs_prog_data
*prog_data
;
1016 /** Offset in the program cache to the CLIP program pre-gen6 */
1017 uint32_t prog_offset
;
1018 uint32_t state_offset
;
1020 uint32_t bind_bo_offset
;
1022 * Surface offsets for the binding table. We only need surfaces to
1023 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1024 * need in this case.
1026 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1030 struct brw_clip_prog_data
*prog_data
;
1032 /** Offset in the program cache to the CLIP program pre-gen6 */
1033 uint32_t prog_offset
;
1035 /* Offset in the batch to the CLIP state on pre-gen6. */
1036 uint32_t state_offset
;
1038 /* As of gen6, this is the offset in the batch to the CLIP VP,
1044 * The number of viewports to use. If gl_ViewportIndex is written,
1045 * we can have up to ctx->Const.MaxViewports viewports. If not,
1046 * the viewport index is always 0, so we can only emit one.
1048 uint8_t viewport_count
;
1053 struct brw_sf_prog_data
*prog_data
;
1055 /** Offset in the program cache to the CLIP program pre-gen6 */
1056 uint32_t prog_offset
;
1057 uint32_t state_offset
;
1062 struct brw_stage_state base
;
1067 * Buffer object used in place of multisampled null render targets on
1068 * Gen6. See brw_emit_null_surface_state().
1070 struct brw_bo
*multisampled_null_render_target_bo
;
1071 uint32_t fast_clear_op
;
1077 struct brw_stage_state base
;
1081 uint32_t state_offset
;
1082 uint32_t blend_state_offset
;
1083 uint32_t depth_stencil_state_offset
;
1088 struct brw_query_object
*obj
;
1093 enum brw_predicate_state state
;
1098 /* Variables referenced in the XML meta data for OA performance
1099 * counters, e.g in the normalization equations.
1101 * All uint64_t for consistent operand types in generated code
1104 uint64_t timestamp_frequency
; /** $GpuTimestampFrequency */
1105 uint64_t n_eus
; /** $EuCoresTotalCount */
1106 uint64_t n_eu_slices
; /** $EuSlicesTotalCount */
1107 uint64_t n_eu_sub_slices
; /** $EuSubslicesTotalCount */
1108 uint64_t eu_threads_count
; /** $EuThreadsCount */
1109 uint64_t slice_mask
; /** $SliceMask */
1110 uint64_t subslice_mask
; /** $SubsliceMask */
1111 uint64_t gt_min_freq
; /** $GpuMinFrequency */
1112 uint64_t gt_max_freq
; /** $GpuMaxFrequency */
1115 /* OA metric sets, indexed by GUID, as know by Mesa at build time,
1116 * to cross-reference with the GUIDs of configs advertised by the
1119 struct hash_table
*oa_metrics_table
;
1121 struct brw_perf_query_info
*queries
;
1124 /* The i915 perf stream we open to setup + enable the OA counters */
1127 /* An i915 perf stream fd gives exclusive access to the OA unit that will
1128 * report counter snapshots for a specific counter set/profile in a
1129 * specific layout/format so we can only start OA queries that are
1130 * compatible with the currently open fd...
1132 int current_oa_metrics_set_id
;
1133 int current_oa_format
;
1135 /* List of buffers containing OA reports */
1136 struct exec_list sample_buffers
;
1138 /* Cached list of empty sample buffers */
1139 struct exec_list free_sample_buffers
;
1141 int n_active_oa_queries
;
1142 int n_active_pipeline_stats_queries
;
1144 /* The number of queries depending on running OA counters which
1145 * extends beyond brw_end_perf_query() since we need to wait until
1146 * the last MI_RPC command has parsed by the GPU.
1148 * Accurate accounting is important here as emitting an
1149 * MI_REPORT_PERF_COUNT command while the OA unit is disabled will
1150 * effectively hang the gpu.
1154 /* To help catch an spurious problem with the hardware or perf
1155 * forwarding samples, we emit each MI_REPORT_PERF_COUNT command
1156 * with a unique ID that we can explicitly check for...
1158 int next_query_start_report_id
;
1161 * An array of queries whose results haven't yet been assembled
1162 * based on the data in buffer objects.
1164 * These may be active, or have already ended. However, the
1165 * results have not been requested.
1167 struct brw_perf_query_object
**unaccumulated
;
1168 int unaccumulated_elements
;
1169 int unaccumulated_array_size
;
1171 /* The total number of query objects so we can relinquish
1172 * our exclusive access to perf if the application deletes
1173 * all of its objects. (NB: We only disable perf while
1174 * there are no active queries)
1176 int n_query_instances
;
1179 int num_atoms
[BRW_NUM_PIPELINES
];
1180 const struct brw_tracked_state render_atoms
[76];
1181 const struct brw_tracked_state compute_atoms
[11];
1183 const enum isl_format
*mesa_to_isl_render_format
;
1184 const bool *mesa_format_supports_render
;
1186 /* PrimitiveRestart */
1189 bool enable_cut_index
;
1192 /** Computed depth/stencil/hiz state from the current attached
1193 * renderbuffers, valid only during the drawing state upload loop after
1194 * brw_workaround_depthstencil_alignment().
1197 /* Inter-tile (page-aligned) byte offsets. */
1198 uint32_t depth_offset
;
1199 /* Intra-tile x,y offsets for drawing to combined depth-stencil. Only
1202 uint32_t tile_x
, tile_y
;
1205 uint32_t num_instances
;
1210 const struct gen_l3_config
*config
;
1217 enum shader_time_shader_type
*types
;
1218 struct shader_times
*cumulative
;
1224 struct brw_fast_clear_state
*fast_clear_state
;
1226 /* Array of flags telling if auxiliary buffer is disabled for corresponding
1227 * renderbuffer. If draw_aux_buffer_disabled[i] is set then use of
1228 * auxiliary buffer for gl_framebuffer::_ColorDrawBuffers[i] is
1230 * This is needed in case the same underlying buffer is also configured
1231 * to be sampled but with a format that the sampling engine can't treat
1232 * compressed or fast cleared.
1234 bool draw_aux_buffer_disabled
[MAX_DRAW_BUFFERS
];
1236 __DRIcontext
*driContext
;
1237 struct intel_screen
*screen
;
1241 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1243 /*======================================================================
1246 extern const char *const brw_vendor_string
;
1249 brw_get_renderer_string(const struct intel_screen
*screen
);
1252 DRI_CONF_BO_REUSE_DISABLED
,
1253 DRI_CONF_BO_REUSE_ALL
1256 void intel_update_renderbuffers(__DRIcontext
*context
,
1257 __DRIdrawable
*drawable
);
1258 void intel_prepare_render(struct brw_context
*brw
);
1260 void brw_predraw_resolve_inputs(struct brw_context
*brw
);
1262 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1263 __DRIdrawable
*drawable
);
1265 GLboolean
brwCreateContext(gl_api api
,
1266 const struct gl_config
*mesaVis
,
1267 __DRIcontext
*driContextPriv
,
1268 unsigned major_version
,
1269 unsigned minor_version
,
1273 void *sharedContextPrivate
);
1275 /*======================================================================
1279 brw_meta_resolve_color(struct brw_context
*brw
,
1280 struct intel_mipmap_tree
*mt
);
1282 /*======================================================================
1285 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1286 GLbitfield clear_mask
);
1288 /* brw_object_purgeable.c */
1289 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1291 /*======================================================================
1294 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1295 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1296 void brw_emit_query_begin(struct brw_context
*brw
);
1297 void brw_emit_query_end(struct brw_context
*brw
);
1298 void brw_query_counter(struct gl_context
*ctx
, struct gl_query_object
*q
);
1299 bool brw_is_query_pipelined(struct brw_query_object
*query
);
1300 uint64_t brw_timebase_scale(struct brw_context
*brw
, uint64_t gpu_timestamp
);
1301 uint64_t brw_raw_timestamp_delta(struct brw_context
*brw
,
1302 uint64_t time0
, uint64_t time1
);
1304 /** gen6_queryobj.c */
1305 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1306 void brw_write_timestamp(struct brw_context
*brw
, struct brw_bo
*bo
, int idx
);
1307 void brw_write_depth_count(struct brw_context
*brw
, struct brw_bo
*bo
, int idx
);
1309 /** hsw_queryobj.c */
1310 void hsw_overflow_result_to_gpr0(struct brw_context
*brw
,
1311 struct brw_query_object
*query
,
1313 void hsw_init_queryobj_functions(struct dd_function_table
*functions
);
1315 /** brw_conditional_render.c */
1316 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1317 bool brw_check_conditional_render(struct brw_context
*brw
);
1319 /** intel_batchbuffer.c */
1320 void brw_load_register_mem(struct brw_context
*brw
,
1323 uint32_t read_domains
, uint32_t write_domain
,
1325 void brw_load_register_mem64(struct brw_context
*brw
,
1328 uint32_t read_domains
, uint32_t write_domain
,
1330 void brw_store_register_mem32(struct brw_context
*brw
,
1331 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
);
1332 void brw_store_register_mem64(struct brw_context
*brw
,
1333 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
);
1334 void brw_load_register_imm32(struct brw_context
*brw
,
1335 uint32_t reg
, uint32_t imm
);
1336 void brw_load_register_imm64(struct brw_context
*brw
,
1337 uint32_t reg
, uint64_t imm
);
1338 void brw_load_register_reg(struct brw_context
*brw
, uint32_t src
,
1340 void brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
,
1342 void brw_store_data_imm32(struct brw_context
*brw
, struct brw_bo
*bo
,
1343 uint32_t offset
, uint32_t imm
);
1344 void brw_store_data_imm64(struct brw_context
*brw
, struct brw_bo
*bo
,
1345 uint32_t offset
, uint64_t imm
);
1347 /*======================================================================
1348 * intel_tex_validate.c
1350 void brw_validate_textures( struct brw_context
*brw
);
1353 /*======================================================================
1357 key_debug(struct brw_context
*brw
, const char *name
, int a
, int b
)
1360 perf_debug(" %s %d->%d\n", name
, a
, b
);
1366 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1368 void brw_get_scratch_bo(struct brw_context
*brw
,
1369 struct brw_bo
**scratch_bo
, int size
);
1370 void brw_alloc_stage_scratch(struct brw_context
*brw
,
1371 struct brw_stage_state
*stage_state
,
1372 unsigned per_thread_size
,
1373 unsigned thread_count
);
1374 void brw_init_shader_time(struct brw_context
*brw
);
1375 int brw_get_shader_time_index(struct brw_context
*brw
,
1376 struct gl_program
*prog
,
1377 enum shader_time_shader_type type
,
1379 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1380 void brw_destroy_shader_time(struct brw_context
*brw
);
1384 void brw_calculate_urb_fence(struct brw_context
*brw
, unsigned csize
,
1385 unsigned vsize
, unsigned sfsize
);
1386 void brw_upload_urb_fence(struct brw_context
*brw
);
1390 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1393 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1395 /* brw_draw_upload.c */
1396 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1397 const struct gl_vertex_array
*glarray
);
1399 static inline unsigned
1400 brw_get_index_type(unsigned index_size
)
1402 /* The hw needs 0x00, 0x01, and 0x02 for ubyte, ushort, and uint,
1405 return index_size
>> 1;
1408 void brw_prepare_vertices(struct brw_context
*brw
);
1410 /* brw_wm_surface_state.c */
1411 void brw_create_constant_surface(struct brw_context
*brw
,
1415 uint32_t *out_offset
);
1416 void brw_create_buffer_surface(struct brw_context
*brw
,
1420 uint32_t *out_offset
);
1421 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1423 uint32_t *surf_offset
);
1425 brw_update_sol_surface(struct brw_context
*brw
,
1426 struct gl_buffer_object
*buffer_obj
,
1427 uint32_t *out_offset
, unsigned num_vector_components
,
1428 unsigned stride_dwords
, unsigned offset_dwords
);
1429 void brw_upload_ubo_surfaces(struct brw_context
*brw
, struct gl_program
*prog
,
1430 struct brw_stage_state
*stage_state
,
1431 struct brw_stage_prog_data
*prog_data
);
1432 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1433 const struct gl_program
*prog
,
1434 struct brw_stage_state
*stage_state
,
1435 struct brw_stage_prog_data
*prog_data
);
1436 void brw_upload_image_surfaces(struct brw_context
*brw
,
1437 const struct gl_program
*prog
,
1438 struct brw_stage_state
*stage_state
,
1439 struct brw_stage_prog_data
*prog_data
);
1441 /* brw_surface_formats.c */
1442 void intel_screen_init_surface_formats(struct intel_screen
*screen
);
1443 void brw_init_surface_formats(struct brw_context
*brw
);
1444 bool brw_render_target_supported(struct brw_context
*brw
,
1445 struct gl_renderbuffer
*rb
);
1446 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1448 /* brw_performance_query.c */
1449 void brw_init_performance_queries(struct brw_context
*brw
);
1451 /* intel_extensions.c */
1452 extern void intelInitExtensions(struct gl_context
*ctx
);
1455 extern int intel_translate_shadow_compare_func(GLenum func
);
1456 extern int intel_translate_compare_func(GLenum func
);
1457 extern int intel_translate_stencil_op(GLenum op
);
1458 extern int intel_translate_logic_op(GLenum opcode
);
1461 void brw_init_syncobj_functions(struct dd_function_table
*functions
);
1464 struct gl_transform_feedback_object
*
1465 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1467 brw_delete_transform_feedback(struct gl_context
*ctx
,
1468 struct gl_transform_feedback_object
*obj
);
1470 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1471 struct gl_transform_feedback_object
*obj
);
1473 brw_end_transform_feedback(struct gl_context
*ctx
,
1474 struct gl_transform_feedback_object
*obj
);
1476 brw_pause_transform_feedback(struct gl_context
*ctx
,
1477 struct gl_transform_feedback_object
*obj
);
1479 brw_resume_transform_feedback(struct gl_context
*ctx
,
1480 struct gl_transform_feedback_object
*obj
);
1482 brw_save_primitives_written_counters(struct brw_context
*brw
,
1483 struct brw_transform_feedback_object
*obj
);
1485 brw_compute_xfb_vertices_written(struct brw_context
*brw
,
1486 struct brw_transform_feedback_object
*obj
);
1488 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1489 struct gl_transform_feedback_object
*obj
,
1492 /* gen7_sol_state.c */
1494 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1495 struct gl_transform_feedback_object
*obj
);
1497 gen7_end_transform_feedback(struct gl_context
*ctx
,
1498 struct gl_transform_feedback_object
*obj
);
1500 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1501 struct gl_transform_feedback_object
*obj
);
1503 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1504 struct gl_transform_feedback_object
*obj
);
1508 hsw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1509 struct gl_transform_feedback_object
*obj
);
1511 hsw_end_transform_feedback(struct gl_context
*ctx
,
1512 struct gl_transform_feedback_object
*obj
);
1514 hsw_pause_transform_feedback(struct gl_context
*ctx
,
1515 struct gl_transform_feedback_object
*obj
);
1517 hsw_resume_transform_feedback(struct gl_context
*ctx
,
1518 struct gl_transform_feedback_object
*obj
);
1520 /* brw_blorp_blit.cpp */
1522 brw_blorp_framebuffer(struct brw_context
*brw
,
1523 struct gl_framebuffer
*readFb
,
1524 struct gl_framebuffer
*drawFb
,
1525 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1526 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1527 GLbitfield mask
, GLenum filter
);
1530 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1531 struct gl_renderbuffer
*src_rb
,
1532 struct gl_texture_image
*dst_image
,
1534 int srcX0
, int srcY0
,
1535 int dstX0
, int dstY0
,
1536 int width
, int height
);
1539 gen6_get_sample_position(struct gl_context
*ctx
,
1540 struct gl_framebuffer
*fb
,
1544 gen6_set_sample_maps(struct gl_context
*ctx
);
1546 /* gen8_multisample_state.c */
1547 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1548 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1552 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1553 unsigned hs_size
, unsigned ds_size
,
1554 unsigned gs_size
, unsigned fs_size
);
1557 gen6_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1558 bool gs_present
, unsigned gs_size
);
1560 gen7_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1561 bool gs_present
, bool tess_present
);
1565 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1567 brw_check_for_reset(struct brw_context
*brw
);
1571 brw_init_compute_functions(struct dd_function_table
*functions
);
1573 /*======================================================================
1574 * Inline conversion functions. These are better-typed than the
1575 * macros used previously:
1577 static inline struct brw_context
*
1578 brw_context( struct gl_context
*ctx
)
1580 return (struct brw_context
*)ctx
;
1583 static inline struct brw_program
*
1584 brw_program(struct gl_program
*p
)
1586 return (struct brw_program
*) p
;
1589 static inline const struct brw_program
*
1590 brw_program_const(const struct gl_program
*p
)
1592 return (const struct brw_program
*) p
;
1596 brw_depth_writes_enabled(const struct brw_context
*brw
)
1598 const struct gl_context
*ctx
= &brw
->ctx
;
1600 /* We consider depth writes disabled if the depth function is GL_EQUAL,
1601 * because it would just overwrite the existing depth value with itself.
1603 * These bonus depth writes not only use bandwidth, but they also can
1604 * prevent early depth processing. For example, if the pixel shader
1605 * discards, the hardware must invoke the to determine whether or not
1606 * to do the depth write. If writes are disabled, we may still be able
1607 * to do the depth test before the shader, and skip the shader execution.
1609 * The Broadwell 3DSTATE_WM_DEPTH_STENCIL documentation also contains
1610 * a programming note saying to disable depth writes for EQUAL.
1612 return ctx
->Depth
.Test
&& ctx
->Depth
.Mask
&& ctx
->Depth
.Func
!= GL_EQUAL
;
1616 brw_emit_depthbuffer(struct brw_context
*brw
);
1619 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1620 struct intel_mipmap_tree
*depth_mt
,
1621 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1622 uint32_t depth_surface_type
,
1623 struct intel_mipmap_tree
*stencil_mt
,
1624 bool hiz
, bool separate_stencil
,
1625 uint32_t width
, uint32_t height
,
1626 uint32_t tile_x
, uint32_t tile_y
);
1629 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1630 struct intel_mipmap_tree
*depth_mt
,
1631 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1632 uint32_t depth_surface_type
,
1633 struct intel_mipmap_tree
*stencil_mt
,
1634 bool hiz
, bool separate_stencil
,
1635 uint32_t width
, uint32_t height
,
1636 uint32_t tile_x
, uint32_t tile_y
);
1639 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1640 struct intel_mipmap_tree
*depth_mt
,
1641 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1642 uint32_t depth_surface_type
,
1643 struct intel_mipmap_tree
*stencil_mt
,
1644 bool hiz
, bool separate_stencil
,
1645 uint32_t width
, uint32_t height
,
1646 uint32_t tile_x
, uint32_t tile_y
);
1648 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1649 struct intel_mipmap_tree
*depth_mt
,
1650 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1651 uint32_t depth_surface_type
,
1652 struct intel_mipmap_tree
*stencil_mt
,
1653 bool hiz
, bool separate_stencil
,
1654 uint32_t width
, uint32_t height
,
1655 uint32_t tile_x
, uint32_t tile_y
);
1657 uint32_t get_hw_prim_for_gl_prim(int mode
);
1660 gen6_upload_push_constants(struct brw_context
*brw
,
1661 const struct gl_program
*prog
,
1662 const struct brw_stage_prog_data
*prog_data
,
1663 struct brw_stage_state
*stage_state
);
1666 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
1667 const struct intel_mipmap_tree
*mt
);
1669 /* brw_pipe_control.c */
1670 int brw_init_pipe_control(struct brw_context
*brw
,
1671 const struct gen_device_info
*info
);
1672 void brw_fini_pipe_control(struct brw_context
*brw
);
1674 void brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
);
1675 void brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
1676 struct brw_bo
*bo
, uint32_t offset
,
1678 void brw_emit_end_of_pipe_sync(struct brw_context
*brw
, uint32_t flags
);
1679 void brw_emit_mi_flush(struct brw_context
*brw
);
1680 void brw_emit_post_sync_nonzero_flush(struct brw_context
*brw
);
1681 void brw_emit_depth_stall_flushes(struct brw_context
*brw
);
1682 void gen7_emit_vs_workaround_flush(struct brw_context
*brw
);
1683 void gen7_emit_cs_stall_flush(struct brw_context
*brw
);
1685 /* brw_queryformat.c */
1686 void brw_query_internal_format(struct gl_context
*ctx
, GLenum target
,
1687 GLenum internalFormat
, GLenum pname
,