2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
38 #include "main/imports.h"
39 #include "main/macros.h"
41 #include "main/mtypes.h"
42 #include "brw_structs.h"
46 /* Evil hack for using libdrm in a c++ compiler. */
51 #include <intel_bufmgr.h>
61 #include "intel_debug.h"
62 #include "intel_screen.h"
63 #include "intel_tex_obj.h"
64 #include "intel_resolve_map.h"
68 * URB - uniform resource buffer. A mid-sized buffer which is
69 * partitioned between the fixed function units and used for passing
70 * values (vertices, primitives, constants) between them.
72 * CURBE - constant URB entry. An urb region (entry) used to hold
73 * constant values which the fixed function units can be instructed to
74 * preload into the GRF when spawning a thread.
76 * VUE - vertex URB entry. An urb entry holding a vertex and usually
77 * a vertex header. The header contains control information and
78 * things like primitive type, Begin/end flags and clip codes.
80 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
81 * unit holding rasterization and interpolation parameters.
83 * GRF - general register file. One of several register files
84 * addressable by programmed threads. The inputs (r0, payload, curbe,
85 * urb) of the thread are preloaded to this area before the thread is
86 * spawned. The registers are individually 8 dwords wide and suitable
87 * for general usage. Registers holding thread input values are not
88 * special and may be overwritten.
90 * MRF - message register file. Threads communicate (and terminate)
91 * by sending messages. Message parameters are placed in contiguous
92 * MRF registers. All program output is via these messages. URB
93 * entries are populated by sending a message to the shared URB
94 * function containing the new data, together with a control word,
95 * often an unmodified copy of R0.
97 * R0 - GRF register 0. Typically holds control information used when
98 * sending messages to other threads.
100 * EU or GEN4 EU: The name of the programmable subsystem of the
101 * i965 hardware. Threads are executed by the EU, the registers
102 * described above are part of the EU architecture.
104 * Fixed function units:
106 * CS - Command streamer. Notional first unit, little software
107 * interaction. Holds the URB entries used for constant data, ie the
110 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
111 * this unit is responsible for pulling vertices out of vertex buffers
112 * in vram and injecting them into the processing pipe as VUEs. If
113 * enabled, it first passes them to a VS thread which is a good place
114 * for the driver to implement any active vertex shader.
116 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
117 * enabled, incoming strips etc are passed to GS threads in individual
118 * line/triangle/point units. The GS thread may perform arbitary
119 * computation and emit whatever primtives with whatever vertices it
120 * chooses. This makes GS an excellent place to implement GL's
121 * unfilled polygon modes, though of course it is capable of much
122 * more. Additionally, GS is used to translate away primitives not
123 * handled by latter units, including Quads and Lineloops.
125 * CS - Clipper. Mesa's clipping algorithms are imported to run on
126 * this unit. The fixed function part performs cliptesting against
127 * the 6 fixed clipplanes and makes descisions on whether or not the
128 * incoming primitive needs to be passed to a thread for clipping.
129 * User clip planes are handled via cooperation with the VS thread.
131 * SF - Strips Fans or Setup: Triangles are prepared for
132 * rasterization. Interpolation coefficients are calculated.
133 * Flatshading and two-side lighting usually performed here.
135 * WM - Windower. Interpolation of vertex attributes performed here.
136 * Fragment shader implemented here. SIMD aspects of EU taken full
137 * advantage of, as pixels are processed in blocks of 16.
139 * CC - Color Calculator. No EU threads associated with this unit.
140 * Handles blending and (presumably) depth and stencil testing.
143 #define BRW_MAX_CURBE (32*16)
146 struct brw_instruction
;
147 struct brw_vs_prog_key
;
148 struct brw_vec4_prog_key
;
149 struct brw_wm_prog_key
;
150 struct brw_wm_prog_data
;
154 BRW_STATE_FRAGMENT_PROGRAM
,
155 BRW_STATE_GEOMETRY_PROGRAM
,
156 BRW_STATE_VERTEX_PROGRAM
,
157 BRW_STATE_CURBE_OFFSETS
,
158 BRW_STATE_REDUCED_PRIMITIVE
,
163 BRW_STATE_VS_BINDING_TABLE
,
164 BRW_STATE_GS_BINDING_TABLE
,
165 BRW_STATE_PS_BINDING_TABLE
,
169 BRW_STATE_INDEX_BUFFER
,
170 BRW_STATE_VS_CONSTBUF
,
171 BRW_STATE_GS_CONSTBUF
,
172 BRW_STATE_PROGRAM_CACHE
,
173 BRW_STATE_STATE_BASE_ADDRESS
,
174 BRW_STATE_VUE_MAP_VS
,
175 BRW_STATE_VUE_MAP_GEOM_OUT
,
176 BRW_STATE_TRANSFORM_FEEDBACK
,
177 BRW_STATE_RASTERIZER_DISCARD
,
179 BRW_STATE_UNIFORM_BUFFER
,
180 BRW_STATE_ATOMIC_BUFFER
,
181 BRW_STATE_META_IN_PROGRESS
,
182 BRW_STATE_INTERPOLATION_MAP
,
183 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
187 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
188 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
189 #define BRW_NEW_GEOMETRY_PROGRAM (1 << BRW_STATE_GEOMETRY_PROGRAM)
190 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
191 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
192 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
193 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
194 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
195 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
196 #define BRW_NEW_SURFACES (1 << BRW_STATE_SURFACES)
197 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
198 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
199 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
200 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
201 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
203 * Used for any batch entry with a relocated pointer that will be used
204 * by any 3D rendering.
206 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
207 /** \see brw.state.depth_region */
208 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
209 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
210 #define BRW_NEW_GS_CONSTBUF (1 << BRW_STATE_GS_CONSTBUF)
211 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
212 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
213 #define BRW_NEW_VUE_MAP_VS (1 << BRW_STATE_VUE_MAP_VS)
214 #define BRW_NEW_VUE_MAP_GEOM_OUT (1 << BRW_STATE_VUE_MAP_GEOM_OUT)
215 #define BRW_NEW_TRANSFORM_FEEDBACK (1 << BRW_STATE_TRANSFORM_FEEDBACK)
216 #define BRW_NEW_RASTERIZER_DISCARD (1 << BRW_STATE_RASTERIZER_DISCARD)
217 #define BRW_NEW_STATS_WM (1 << BRW_STATE_STATS_WM)
218 #define BRW_NEW_UNIFORM_BUFFER (1 << BRW_STATE_UNIFORM_BUFFER)
219 #define BRW_NEW_ATOMIC_BUFFER (1 << BRW_STATE_ATOMIC_BUFFER)
220 #define BRW_NEW_META_IN_PROGRESS (1 << BRW_STATE_META_IN_PROGRESS)
221 #define BRW_NEW_INTERPOLATION_MAP (1 << BRW_STATE_INTERPOLATION_MAP)
222 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1 << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
224 struct brw_state_flags
{
225 /** State update flags signalled by mesa internals */
228 * State update flags signalled as the result of brw_tracked_state updates
231 /** State update flags signalled by brw_state_cache.c searches */
235 #define AUB_TRACE_TYPE_MASK 0x0000ff00
236 #define AUB_TRACE_TYPE_NOTYPE (0 << 8)
237 #define AUB_TRACE_TYPE_BATCH (1 << 8)
238 #define AUB_TRACE_TYPE_VERTEX_BUFFER (5 << 8)
239 #define AUB_TRACE_TYPE_2D_MAP (6 << 8)
240 #define AUB_TRACE_TYPE_CUBE_MAP (7 << 8)
241 #define AUB_TRACE_TYPE_VOLUME_MAP (9 << 8)
242 #define AUB_TRACE_TYPE_1D_MAP (10 << 8)
243 #define AUB_TRACE_TYPE_CONSTANT_BUFFER (11 << 8)
244 #define AUB_TRACE_TYPE_CONSTANT_URB (12 << 8)
245 #define AUB_TRACE_TYPE_INDEX_BUFFER (13 << 8)
246 #define AUB_TRACE_TYPE_GENERAL (14 << 8)
247 #define AUB_TRACE_TYPE_SURFACE (15 << 8)
250 * state_struct_type enum values are encoded with the top 16 bits representing
251 * the type to be delivered to the .aub file, and the bottom 16 bits
252 * representing the subtype. This macro performs the encoding.
254 #define ENCODE_SS_TYPE(type, subtype) (((type) << 16) | (subtype))
256 enum state_struct_type
{
257 AUB_TRACE_VS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 1),
258 AUB_TRACE_GS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 2),
259 AUB_TRACE_CLIP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 3),
260 AUB_TRACE_SF_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 4),
261 AUB_TRACE_WM_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 5),
262 AUB_TRACE_CC_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 6),
263 AUB_TRACE_CLIP_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 7),
264 AUB_TRACE_SF_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 8),
265 AUB_TRACE_CC_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x9),
266 AUB_TRACE_SAMPLER_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xa),
267 AUB_TRACE_KERNEL_INSTRUCTIONS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xb),
268 AUB_TRACE_SCRATCH_SPACE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xc),
269 AUB_TRACE_SAMPLER_DEFAULT_COLOR
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xd),
271 AUB_TRACE_SCISSOR_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x15),
272 AUB_TRACE_BLEND_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x16),
273 AUB_TRACE_DEPTH_STENCIL_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x17),
275 AUB_TRACE_VERTEX_BUFFER
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_VERTEX_BUFFER
, 0),
276 AUB_TRACE_BINDING_TABLE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x100),
277 AUB_TRACE_SURFACE_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x200),
278 AUB_TRACE_VS_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 0),
279 AUB_TRACE_WM_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 1),
283 * Decode a state_struct_type value to determine the type that should be
284 * stored in the .aub file.
286 static inline uint32_t AUB_TRACE_TYPE(enum state_struct_type ss_type
)
288 return (ss_type
& 0xFFFF0000) >> 16;
292 * Decode a state_struct_type value to determine the subtype that should be
293 * stored in the .aub file.
295 static inline uint32_t AUB_TRACE_SUBTYPE(enum state_struct_type ss_type
)
297 return ss_type
& 0xFFFF;
300 /** Subclass of Mesa vertex program */
301 struct brw_vertex_program
{
302 struct gl_vertex_program program
;
307 /** Subclass of Mesa geometry program */
308 struct brw_geometry_program
{
309 struct gl_geometry_program program
;
310 unsigned id
; /**< serial no. to identify geom progs, never re-used */
314 /** Subclass of Mesa fragment program */
315 struct brw_fragment_program
{
316 struct gl_fragment_program program
;
317 GLuint id
; /**< serial no. to identify frag progs, never re-used */
321 /** Subclass of Mesa compute program */
322 struct brw_compute_program
{
323 struct gl_compute_program program
;
324 unsigned id
; /**< serial no. to identify compute progs, never re-used */
329 struct gl_shader base
;
334 /* Note: If adding fields that need anything besides a normal memcmp() for
335 * comparing them, be sure to go fix brw_stage_prog_data_compare().
337 struct brw_stage_prog_data
{
339 /** size of our binding table. */
343 * surface indices for the various groups of surfaces
345 uint32_t pull_constants_start
;
346 uint32_t texture_start
;
347 uint32_t gather_texture_start
;
350 uint32_t shader_time_start
;
354 GLuint nr_params
; /**< number of float params/constants */
355 GLuint nr_pull_params
;
357 /* Pointers to tracked values (only valid once
358 * _mesa_load_state_parameters has been called at runtime).
360 * These must be the last fields of the struct (see
361 * brw_stage_prog_data_compare()).
364 const float **pull_param
;
367 /* Data about a particular attempt to compile a program. Note that
368 * there can be many of these, each in a different GL state
369 * corresponding to a different brw_wm_prog_key struct, with different
372 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
375 struct brw_wm_prog_data
{
376 struct brw_stage_prog_data base
;
378 GLuint curb_read_length
;
379 GLuint num_varying_inputs
;
381 GLuint first_curbe_grf
;
382 GLuint first_curbe_grf_16
;
384 GLuint reg_blocks_16
;
385 GLuint total_scratch
;
389 * surface indices the WM-specific surfaces
391 uint32_t render_target_start
;
396 bool uses_pos_offset
;
398 uint32_t prog_offset_16
;
401 * Mask of which interpolation modes are required by the fragment shader.
402 * Used in hardware setup on gen6+.
404 uint32_t barycentric_interp_modes
;
407 * Map from gl_varying_slot to the position within the FS setup data
408 * payload where the varying's attribute vertex deltas should be delivered.
409 * For varying slots that are not used by the FS, the value is -1.
411 int urb_setup
[VARYING_SLOT_MAX
];
415 * Enum representing the i965-specific vertex results that don't correspond
416 * exactly to any element of gl_varying_slot. The values of this enum are
417 * assigned such that they don't conflict with gl_varying_slot.
421 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
422 BRW_VARYING_SLOT_PAD
,
424 * Technically this is not a varying but just a placeholder that
425 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
426 * builtin variable to be compiled correctly. see compile_sf_prog() for
429 BRW_VARYING_SLOT_PNTC
,
430 BRW_VARYING_SLOT_COUNT
435 * Data structure recording the relationship between the gl_varying_slot enum
436 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
437 * single octaword within the VUE (128 bits).
439 * Note that each BRW register contains 256 bits (2 octawords), so when
440 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
441 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
442 * in a vertex shader), each register corresponds to a single VUE slot, since
443 * it contains data for two separate vertices.
447 * Bitfield representing all varying slots that are (a) stored in this VUE
448 * map, and (b) actually written by the shader. Does not include any of
449 * the additional varying slots defined in brw_varying_slot.
451 GLbitfield64 slots_valid
;
454 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
455 * not stored in a slot (because they are not written, or because
456 * additional processing is applied before storing them in the VUE), the
459 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
462 * Map from VUE slot to gl_varying_slot value. For slots that do not
463 * directly correspond to a gl_varying_slot, the value comes from
466 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
467 * simplifies code that uses the value stored in slot_to_varying to
468 * create a bit mask).
470 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
473 * Total number of VUE slots in use
479 * Convert a VUE slot number into a byte offset within the VUE.
481 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
487 * Convert a vertex output (brw_varying_slot) into a byte offset within the
490 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
493 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
496 void brw_compute_vue_map(struct brw_context
*brw
, struct brw_vue_map
*vue_map
,
497 GLbitfield64 slots_valid
);
501 * Bitmask indicating which fragment shader inputs represent varyings (and
502 * hence have to be delivered to the fragment shader by the SF/SBE stage).
504 #define BRW_FS_VARYING_INPUT_MASK \
505 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
506 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
510 * Mapping of VUE map slots to interpolation modes.
512 struct interpolation_mode_map
{
513 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
516 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
518 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
519 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
525 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
527 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
528 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
535 struct brw_sf_prog_data
{
536 GLuint urb_read_length
;
539 /* Each vertex may have upto 12 attributes, 4 components each,
540 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
543 * Actually we use 4 for each, so call it 12 rows.
545 GLuint urb_entry_size
;
550 * We always program SF to start reading at an offset of 1 (2 varying slots)
551 * from the start of the vertex URB entry. This causes it to skip:
552 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
553 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
555 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
558 struct brw_clip_prog_data
{
559 GLuint curb_read_length
; /* user planes? */
561 GLuint urb_read_length
;
565 struct brw_ff_gs_prog_data
{
566 GLuint urb_read_length
;
570 * Gen6 transform feedback: Amount by which the streaming vertex buffer
571 * indices should be incremented each time the GS is invoked.
573 unsigned svbi_postincrement_value
;
577 /* Note: brw_vec4_prog_data_compare() must be updated when adding fields to
580 struct brw_vec4_prog_data
{
581 struct brw_stage_prog_data base
;
582 struct brw_vue_map vue_map
;
585 * Register where the thread expects to find input data from the URB
586 * (typically uniforms, followed by per-vertex inputs).
588 unsigned dispatch_grf_start_reg
;
590 GLuint curb_read_length
;
591 GLuint urb_read_length
;
593 GLuint total_scratch
;
595 /* Used for calculating urb partitions. In the VS, this is the size of the
596 * URB entry used for both input and output to the thread. In the GS, this
597 * is the size of the URB entry used for output.
599 GLuint urb_entry_size
;
603 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
606 struct brw_vs_prog_data
{
607 struct brw_vec4_prog_data base
;
609 GLbitfield64 inputs_read
;
615 /* Note: brw_gs_prog_data_compare() must be updated when adding fields to
618 struct brw_gs_prog_data
620 struct brw_vec4_prog_data base
;
623 * Size of an output vertex, measured in HWORDS (32 bytes).
625 unsigned output_vertex_size_hwords
;
627 unsigned output_topology
;
630 * Size of the control data (cut bits or StreamID bits), in hwords (32
631 * bytes). 0 if there is no control data.
633 unsigned control_data_header_size_hwords
;
636 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
637 * if the control data is StreamID bits, or
638 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
639 * Ignored if control_data_header_size is 0.
641 unsigned control_data_format
;
643 bool include_primitive_id
;
648 * True if the thread should be dispatched in DUAL_INSTANCE mode, false if
649 * it should be dispatched in DUAL_OBJECT mode.
651 bool dual_instanced_dispatch
;
654 /** Number of texture sampler units */
655 #define BRW_MAX_TEX_UNIT 32
657 /** Max number of render targets in a shader */
658 #define BRW_MAX_DRAW_BUFFERS 8
660 /** Max number of atomic counter buffer objects in a shader */
661 #define BRW_MAX_ABO 16
664 * Max number of binding table entries used for stream output.
666 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
667 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
669 * On Gen6, the size of transform feedback data is limited not by the number
670 * of components but by the number of binding table entries we set aside. We
671 * use one binding table entry for a float, one entry for a vector, and one
672 * entry per matrix column. Since the only way we can communicate our
673 * transform feedback capabilities to the client is via
674 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
675 * worst case, in which all the varyings are floats, so we use up one binding
676 * table entry per component. Therefore we need to set aside at least 64
677 * binding table entries for use by transform feedback.
679 * Note: since we don't currently pack varyings, it is currently impossible
680 * for the client to actually use up all of these binding table entries--if
681 * all of their varyings were floats, they would run out of varying slots and
682 * fail to link. But that's a bug, so it seems prudent to go ahead and
683 * allocate the number of binding table entries we will need once the bug is
686 #define BRW_MAX_SOL_BINDINGS 64
688 /** Maximum number of actual buffers used for stream output */
689 #define BRW_MAX_SOL_BUFFERS 4
691 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
692 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
695 2 /* shader time, pull constants */)
697 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
698 #define BRW_MAX_GEN6_GS_SURFACES SURF_INDEX_GEN6_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
701 * Stride in bytes between shader_time entries.
703 * We separate entries by a cacheline to reduce traffic between EUs writing to
706 #define SHADER_TIME_STRIDE 64
713 BRW_BLORP_CONST_COLOR_PROG
,
718 BRW_SF_UNIT
, /* scissor state on gen6 */
731 struct brw_cache_item
{
733 * Effectively part of the key, cache_id identifies what kind of state
734 * buffer is involved, and also which brw->state.dirty.cache flag should
735 * be set when this cache item is chosen.
737 enum brw_cache_id cache_id
;
738 /** 32-bit hash of the key data */
740 GLuint key_size
; /* for variable-sized keys */
747 struct brw_cache_item
*next
;
751 typedef bool (*cache_aux_compare_func
)(const void *a
, const void *b
);
752 typedef void (*cache_aux_free_func
)(const void *aux
);
755 struct brw_context
*brw
;
757 struct brw_cache_item
**items
;
759 GLuint size
, n_items
;
761 uint32_t next_offset
;
765 * Optional functions used in determining whether the prog_data for a new
766 * cache item matches an existing cache item (in case there's relevant data
767 * outside of the prog_data). If NULL, a plain memcmp is done.
769 cache_aux_compare_func aux_compare
[BRW_MAX_CACHE
];
770 /** Optional functions for freeing other pointers attached to a prog_data. */
771 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
775 /* Considered adding a member to this struct to document which flags
776 * an update might raise so that ordering of the state atoms can be
777 * checked or derived at runtime. Dropped the idea in favor of having
778 * a debug mode where the state is monitored for flags which are
779 * raised that have already been tested against.
781 struct brw_tracked_state
{
782 struct brw_state_flags dirty
;
783 void (*emit
)( struct brw_context
*brw
);
786 enum shader_time_shader_type
{
802 /* Flags for brw->state.cache.
804 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
805 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
806 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
807 #define CACHE_NEW_BLORP_BLIT_PROG (1<<BRW_BLORP_BLIT_PROG)
808 #define CACHE_NEW_BLORP_CONST_COLOR_PROG (1<<BRW_BLORP_CONST_COLOR_PROG)
809 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
810 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
811 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
812 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
813 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
814 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
815 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
816 #define CACHE_NEW_FF_GS_UNIT (1<<BRW_FF_GS_UNIT)
817 #define CACHE_NEW_FF_GS_PROG (1<<BRW_FF_GS_PROG)
818 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
819 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
820 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
821 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
823 struct brw_cached_batch_item
{
824 struct header
*header
;
826 struct brw_cached_batch_item
*next
;
829 struct brw_vertex_buffer
{
830 /** Buffer object containing the uploaded vertex data */
833 /** Byte stride between elements in the uploaded array */
837 struct brw_vertex_element
{
838 const struct gl_client_array
*glarray
;
842 /** The corresponding Mesa vertex attribute */
843 gl_vert_attrib attrib
;
844 /** Offset of the first element within the buffer object */
848 struct brw_query_object
{
849 struct gl_query_object Base
;
851 /** Last query BO associated with this query. */
854 /** Last index in bo with query data for this object. */
858 struct intel_sync_object
{
859 struct gl_sync_object Base
;
861 /** Batch associated with this sync object */
871 struct intel_batchbuffer
{
872 /** Current batchbuffer being queued up. */
874 /** Last BO submitted to the hardware. Used for glFinish(). */
875 drm_intel_bo
*last_bo
;
876 /** BO for post-sync nonzero writes for gen6 workaround. */
877 drm_intel_bo
*workaround_bo
;
878 bool need_workaround_flush
;
880 struct cached_batch_item
*cached_items
;
882 uint16_t emit
, total
;
883 uint16_t used
, reserved_space
;
886 #define BATCH_SZ (8192*sizeof(uint32_t))
888 uint32_t state_batch_offset
;
889 enum brw_gpu_ring ring
;
890 bool needs_sol_reset
;
898 #define BRW_MAX_XFB_STREAMS 4
900 struct brw_transform_feedback_object
{
901 struct gl_transform_feedback_object base
;
903 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
904 drm_intel_bo
*offset_bo
;
906 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
909 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
910 GLenum primitive_mode
;
913 * Count of primitives generated during this transform feedback operation.
916 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
917 drm_intel_bo
*prim_count_bo
;
918 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
922 * Number of vertices written between last Begin/EndTransformFeedback().
924 * Used to implement DrawTransformFeedback().
926 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
927 bool vertices_written_valid
;
931 * Data shared between each programmable stage in the pipeline (vs, gs, and
934 struct brw_stage_state
936 struct brw_stage_prog_data
*prog_data
;
939 * Optional scratch buffer used to store spilled register values and
940 * variably-indexed GRF arrays.
942 drm_intel_bo
*scratch_bo
;
944 /** Pull constant buffer */
945 drm_intel_bo
*const_bo
;
947 /** Offset in the program cache to the program */
948 uint32_t prog_offset
;
950 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
951 uint32_t state_offset
;
953 uint32_t push_const_offset
; /* Offset in the batchbuffer */
954 int push_const_size
; /* in 256-bit register increments */
956 /* Binding table: pointers to SURFACE_STATE entries. */
957 uint32_t bind_bo_offset
;
958 uint32_t surf_offset
[BRW_MAX_SURFACES
];
960 /** SAMPLER_STATE count and table offset */
961 uint32_t sampler_count
;
962 uint32_t sampler_offset
;
964 /** Offsets in the batch to sampler default colors (texture border color) */
965 uint32_t sdc_offset
[BRW_MAX_TEX_UNIT
];
970 * brw_context is derived from gl_context.
974 struct gl_context ctx
; /**< base class, must be first field */
978 void (*update_texture_surface
)(struct gl_context
*ctx
,
980 uint32_t *surf_offset
,
982 void (*update_renderbuffer_surface
)(struct brw_context
*brw
,
983 struct gl_renderbuffer
*rb
,
986 void (*update_null_renderbuffer_surface
)(struct brw_context
*brw
,
989 void (*create_raw_surface
)(struct brw_context
*brw
,
993 uint32_t *out_offset
,
995 void (*emit_buffer_surface_state
)(struct brw_context
*brw
,
996 uint32_t *out_offset
,
998 unsigned buffer_offset
,
999 unsigned surface_format
,
1000 unsigned buffer_size
,
1005 /** Upload a SAMPLER_STATE table. */
1006 void (*upload_sampler_state_table
)(struct brw_context
*brw
,
1007 struct gl_program
*prog
,
1008 uint32_t sampler_count
,
1009 uint32_t *sst_offset
,
1010 uint32_t *sdc_offset
);
1013 * Send the appropriate state packets to configure depth, stencil, and
1014 * HiZ buffers (i965+ only)
1016 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
1017 struct intel_mipmap_tree
*depth_mt
,
1018 uint32_t depth_offset
,
1019 uint32_t depthbuffer_format
,
1020 uint32_t depth_surface_type
,
1021 struct intel_mipmap_tree
*stencil_mt
,
1022 bool hiz
, bool separate_stencil
,
1023 uint32_t width
, uint32_t height
,
1024 uint32_t tile_x
, uint32_t tile_y
);
1030 drm_intel_context
*hw_ctx
;
1033 * Number of resets observed in the system at context creation.
1035 * This is tracked in the context so that we can determine that another
1036 * reset has occured.
1038 uint32_t reset_count
;
1040 struct intel_batchbuffer batch
;
1046 uint32_t buffer_len
;
1047 uint32_t buffer_offset
;
1052 * Set if rendering has occured to the drawable's front buffer.
1054 * This is used in the DRI2 case to detect that glFlush should also copy
1055 * the contents of the fake front buffer to the real front buffer.
1057 bool front_buffer_dirty
;
1060 * Track whether front-buffer rendering is currently enabled
1062 * A separate flag is used to track this in order to support MRT more
1065 bool is_front_buffer_rendering
;
1068 * Track whether front-buffer is the current read target.
1070 * This is closely associated with is_front_buffer_rendering, but may
1071 * be set separately. The DRI2 fake front buffer must be referenced
1074 bool is_front_buffer_reading
;
1076 /** Framerate throttling: @{ */
1077 drm_intel_bo
*first_post_swapbuffers_batch
;
1088 bool always_flush_batch
;
1089 bool always_flush_cache
;
1090 bool disable_throttling
;
1092 bool disable_derivative_optimization
;
1094 driOptionCache optionCache
;
1097 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
1099 GLenum reduced_primitive
;
1102 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
1103 * variable is set, this is the flag indicating to do expensive work that
1104 * might lead to a perf_debug() call.
1108 uint32_t max_gtt_map_object_size
;
1118 bool has_separate_stencil
;
1119 bool must_use_separate_stencil
;
1122 bool has_surface_tile_offset
;
1124 bool has_negative_rhw_bug
;
1128 * Some versions of Gen hardware don't do centroid interpolation correctly
1129 * on unlit pixels, causing incorrect values for derivatives near triangle
1130 * edges. Enabling this flag causes the fragment shader to use
1131 * non-centroid interpolation for unlit pixels, at the expense of two extra
1132 * fragment shader instructions.
1134 bool needs_unlit_centroid_workaround
;
1138 struct brw_state_flags dirty
;
1141 struct brw_cache cache
;
1142 struct brw_cached_batch_item
*cached_batch_items
;
1144 /* Whether a meta-operation is in progress. */
1145 bool meta_in_progress
;
1148 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
1149 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
1151 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
1155 /* Summary of size and varying of active arrays, so we can check
1156 * for changes to this state:
1158 unsigned int min_index
, max_index
;
1160 /* Offset from start of vertex buffer so we can avoid redefining
1161 * the same VB packed over and over again.
1163 unsigned int start_vertex_bias
;
1168 * Index buffer for this draw_prims call.
1170 * Updates are signaled by BRW_NEW_INDICES.
1172 const struct _mesa_index_buffer
*ib
;
1174 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
1178 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
1179 * avoid re-uploading the IB packet over and over if we're actually
1180 * referencing the same index buffer.
1182 unsigned int start_vertex_offset
;
1185 /* Active vertex program:
1187 const struct gl_vertex_program
*vertex_program
;
1188 const struct gl_geometry_program
*geometry_program
;
1189 const struct gl_fragment_program
*fragment_program
;
1191 /* hw-dependent 3DSTATE_VF_STATISTICS opcode */
1192 uint32_t CMD_VF_STATISTICS
;
1193 /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
1194 uint32_t CMD_PIPELINE_SELECT
;
1197 * Platform specific constants containing the maximum number of threads
1198 * for each pipeline stage.
1204 /* BRW_NEW_URB_ALLOCATIONS:
1207 GLuint vsize
; /* vertex size plus header in urb registers */
1208 GLuint csize
; /* constant buffer size in urb registers */
1209 GLuint sfsize
; /* setup data size in urb registers */
1213 GLuint min_vs_entries
; /* Minimum number of VS entries */
1214 GLuint max_vs_entries
; /* Maximum number of VS entries */
1215 GLuint max_gs_entries
; /* Maximum number of GS entries */
1217 GLuint nr_vs_entries
;
1218 GLuint nr_gs_entries
;
1219 GLuint nr_clip_entries
;
1220 GLuint nr_sf_entries
;
1221 GLuint nr_cs_entries
;
1228 GLuint size
; /* Hardware URB size, in KB. */
1230 /* gen6: True if the most recently sent _3DSTATE_URB message allocated
1231 * URB space for the GS.
1233 bool gen6_gs_previously_active
;
1237 /* BRW_NEW_CURBE_OFFSETS:
1240 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1241 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1248 drm_intel_bo
*curbe_bo
;
1249 /** Offset within curbe_bo of space for current curbe entry */
1250 GLuint curbe_offset
;
1251 /** Offset within curbe_bo of space for next curbe entry */
1252 GLuint curbe_next_offset
;
1255 * Copy of the last set of CURBEs uploaded. Frequently we'll end up
1256 * in brw_curbe.c with the same set of constant data to be uploaded,
1257 * so we'd rather not upload new constants in that case (it can cause
1258 * a pipeline bubble since only up to 4 can be pipelined at a time).
1262 * Allocation for where to calculate the next set of CURBEs.
1263 * It's a hot enough path that malloc/free of that data matters.
1270 * Layout of vertex data exiting the vertex shader.
1272 * BRW_NEW_VUE_MAP_VS is flagged when this VUE map changes.
1274 struct brw_vue_map vue_map_vs
;
1277 * Layout of vertex data exiting the geometry portion of the pipleine.
1278 * This comes from the geometry shader if one exists, otherwise from the
1281 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1283 struct brw_vue_map vue_map_geom_out
;
1286 * Data structures used by all vec4 program compiles (not specific to any
1287 * particular program).
1290 struct ra_regs
*regs
;
1293 * Array of the ra classes for the unaligned contiguous register
1299 * Mapping for register-allocated objects in *regs to the first
1300 * GRF for that object.
1302 uint8_t *ra_reg_to_grf
;
1306 struct brw_stage_state base
;
1307 struct brw_vs_prog_data
*prog_data
;
1311 struct brw_stage_state base
;
1312 struct brw_gs_prog_data
*prog_data
;
1315 * True if the 3DSTATE_GS command most recently emitted to the 3D
1316 * pipeline enabled the GS; false otherwise.
1322 struct brw_ff_gs_prog_data
*prog_data
;
1325 /** Offset in the program cache to the CLIP program pre-gen6 */
1326 uint32_t prog_offset
;
1327 uint32_t state_offset
;
1329 uint32_t bind_bo_offset
;
1330 uint32_t surf_offset
[BRW_MAX_GEN6_GS_SURFACES
];
1334 struct brw_clip_prog_data
*prog_data
;
1336 /** Offset in the program cache to the CLIP program pre-gen6 */
1337 uint32_t prog_offset
;
1339 /* Offset in the batch to the CLIP state on pre-gen6. */
1340 uint32_t state_offset
;
1342 /* As of gen6, this is the offset in the batch to the CLIP VP,
1350 struct brw_sf_prog_data
*prog_data
;
1352 /** Offset in the program cache to the CLIP program pre-gen6 */
1353 uint32_t prog_offset
;
1354 uint32_t state_offset
;
1359 struct brw_stage_state base
;
1360 struct brw_wm_prog_data
*prog_data
;
1365 * Buffer object used in place of multisampled null render targets on
1366 * Gen6. See brw_update_null_renderbuffer_surface().
1368 drm_intel_bo
*multisampled_null_render_target_bo
;
1371 struct ra_regs
*regs
;
1374 * Array of the ra classes for the unaligned contiguous register
1375 * block sizes used, indexed by register size.
1380 * Mapping for register-allocated objects in *regs to the first
1381 * GRF for that object.
1383 uint8_t *ra_reg_to_grf
;
1386 * ra class for the aligned pairs we use for PLN, which doesn't
1387 * appear in *classes.
1389 int aligned_pairs_class
;
1395 uint32_t state_offset
;
1396 uint32_t blend_state_offset
;
1397 uint32_t depth_stencil_state_offset
;
1402 struct brw_query_object
*obj
;
1407 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1408 const int *statistics_registers
;
1410 /** The number of active monitors using OA counters. */
1414 * A buffer object storing OA counter snapshots taken at the start and
1415 * end of each batch (creating "bookends" around the batch).
1417 drm_intel_bo
*bookend_bo
;
1419 /** The number of snapshots written to bookend_bo. */
1420 int bookend_snapshots
;
1423 * An array of monitors whose results haven't yet been assembled based on
1424 * the data in buffer objects.
1426 * These may be active, or have already ended. However, the results
1427 * have not been requested.
1429 struct brw_perf_monitor_object
**unresolved
;
1430 int unresolved_elements
;
1431 int unresolved_array_size
;
1434 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1435 * the counter which MI_REPORT_PERF_COUNT stores there.
1437 const int *oa_snapshot_layout
;
1439 /** Number of 32-bit entries in a hardware counter snapshot. */
1440 int entries_per_oa_snapshot
;
1444 const struct brw_tracked_state
**atoms
;
1446 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1450 enum state_struct_type type
;
1451 } *state_batch_list
;
1452 int state_batch_count
;
1454 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1455 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1457 /* Interpolation modes, one byte per vue slot.
1458 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1460 struct interpolation_mode_map interpolation_mode
;
1462 /* PrimitiveRestart */
1465 bool enable_cut_index
;
1468 /** Computed depth/stencil/hiz state from the current attached
1469 * renderbuffers, valid only during the drawing state upload loop after
1470 * brw_workaround_depthstencil_alignment().
1473 struct intel_mipmap_tree
*depth_mt
;
1474 struct intel_mipmap_tree
*stencil_mt
;
1476 /* Inter-tile (page-aligned) byte offsets. */
1477 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1478 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1479 uint32_t tile_x
, tile_y
;
1482 uint32_t num_instances
;
1487 struct gl_shader_program
**shader_programs
;
1488 struct gl_program
**programs
;
1489 enum shader_time_shader_type
*types
;
1490 uint64_t *cumulative
;
1496 __DRIcontext
*driContext
;
1497 struct intel_screen
*intelScreen
;
1501 is_power_of_two(uint32_t value
)
1503 return (value
& (value
- 1)) == 0;
1506 /*======================================================================
1509 void brwInitVtbl( struct brw_context
*brw
);
1512 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1514 /*======================================================================
1517 extern const char *const brw_vendor_string
;
1519 extern const char *brw_get_renderer_string(unsigned deviceID
);
1521 extern void intelFinish(struct gl_context
* ctx
);
1524 DRI_CONF_BO_REUSE_DISABLED
,
1525 DRI_CONF_BO_REUSE_ALL
1528 void intel_update_renderbuffers(__DRIcontext
*context
,
1529 __DRIdrawable
*drawable
);
1530 void intel_prepare_render(struct brw_context
*brw
);
1532 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1533 __DRIdrawable
*drawable
);
1535 GLboolean
brwCreateContext(gl_api api
,
1536 const struct gl_config
*mesaVis
,
1537 __DRIcontext
*driContextPriv
,
1538 unsigned major_version
,
1539 unsigned minor_version
,
1543 void *sharedContextPrivate
);
1545 /*======================================================================
1548 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1549 uint32_t depth_level
,
1550 uint32_t depth_layer
,
1551 struct intel_mipmap_tree
*stencil_mt
,
1552 uint32_t *out_tile_mask_x
,
1553 uint32_t *out_tile_mask_y
);
1554 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1555 GLbitfield clear_mask
);
1557 /* brw_object_purgeable.c */
1558 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1560 /*======================================================================
1563 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1564 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1565 void brw_emit_query_begin(struct brw_context
*brw
);
1566 void brw_emit_query_end(struct brw_context
*brw
);
1568 /** gen6_queryobj.c */
1569 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1570 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1571 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1572 void brw_store_register_mem64(struct brw_context
*brw
,
1573 drm_intel_bo
*bo
, uint32_t reg
, int idx
);
1575 /** intel_batchbuffer.c */
1576 void brw_load_register_mem(struct brw_context
*brw
,
1579 uint32_t read_domains
, uint32_t write_domain
,
1582 /*======================================================================
1585 void brw_debug_batch(struct brw_context
*brw
);
1586 void brw_annotate_aub(struct brw_context
*brw
);
1588 /*======================================================================
1591 void brw_validate_textures( struct brw_context
*brw
);
1594 /*======================================================================
1597 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1599 int brw_get_scratch_size(int size
);
1600 void brw_get_scratch_bo(struct brw_context
*brw
,
1601 drm_intel_bo
**scratch_bo
, int size
);
1602 void brw_init_shader_time(struct brw_context
*brw
);
1603 int brw_get_shader_time_index(struct brw_context
*brw
,
1604 struct gl_shader_program
*shader_prog
,
1605 struct gl_program
*prog
,
1606 enum shader_time_shader_type type
);
1607 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1608 void brw_destroy_shader_time(struct brw_context
*brw
);
1612 void brw_upload_urb_fence(struct brw_context
*brw
);
1616 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1618 /* brw_fs_reg_allocate.cpp
1620 void brw_fs_alloc_reg_sets(struct brw_context
*brw
);
1622 /* brw_vec4_reg_allocate.cpp */
1623 void brw_vec4_alloc_reg_set(struct brw_context
*brw
);
1626 int brw_disasm (FILE *file
, struct brw_instruction
*inst
, int gen
);
1629 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1631 /* brw_draw_upload.c */
1632 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1633 const struct gl_client_array
*glarray
);
1634 unsigned brw_get_index_type(GLenum type
);
1635 void brw_prepare_vertices(struct brw_context
*brw
);
1637 /* brw_wm_surface_state.c */
1638 void brw_init_surface_formats(struct brw_context
*brw
);
1639 void brw_create_constant_surface(struct brw_context
*brw
,
1643 uint32_t *out_offset
,
1645 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1647 uint32_t *surf_offset
);
1649 brw_update_sol_surface(struct brw_context
*brw
,
1650 struct gl_buffer_object
*buffer_obj
,
1651 uint32_t *out_offset
, unsigned num_vector_components
,
1652 unsigned stride_dwords
, unsigned offset_dwords
);
1653 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1654 struct gl_shader
*shader
,
1655 struct brw_stage_state
*stage_state
,
1656 struct brw_stage_prog_data
*prog_data
);
1657 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1658 struct gl_shader_program
*prog
,
1659 struct brw_stage_state
*stage_state
,
1660 struct brw_stage_prog_data
*prog_data
);
1662 /* brw_surface_formats.c */
1663 bool brw_is_hiz_depth_format(struct brw_context
*ctx
, mesa_format format
);
1664 bool brw_render_target_supported(struct brw_context
*brw
,
1665 struct gl_renderbuffer
*rb
);
1666 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1668 /* brw_performance_monitor.c */
1669 void brw_init_performance_monitors(struct brw_context
*brw
);
1670 void brw_dump_perf_monitors(struct brw_context
*brw
);
1671 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1672 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1674 /* intel_buffer_objects.c */
1675 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1676 const char *bo_name
);
1677 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1678 const char *bo_name
);
1680 /* intel_extensions.c */
1681 extern void intelInitExtensions(struct gl_context
*ctx
);
1684 extern int intel_translate_shadow_compare_func(GLenum func
);
1685 extern int intel_translate_compare_func(GLenum func
);
1686 extern int intel_translate_stencil_op(GLenum op
);
1687 extern int intel_translate_logic_op(GLenum opcode
);
1689 /* intel_syncobj.c */
1690 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1693 struct gl_transform_feedback_object
*
1694 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1696 brw_delete_transform_feedback(struct gl_context
*ctx
,
1697 struct gl_transform_feedback_object
*obj
);
1699 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1700 struct gl_transform_feedback_object
*obj
);
1702 brw_end_transform_feedback(struct gl_context
*ctx
,
1703 struct gl_transform_feedback_object
*obj
);
1705 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1706 struct gl_transform_feedback_object
*obj
,
1709 /* gen7_sol_state.c */
1711 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1712 struct gl_transform_feedback_object
*obj
);
1714 gen7_end_transform_feedback(struct gl_context
*ctx
,
1715 struct gl_transform_feedback_object
*obj
);
1717 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1718 struct gl_transform_feedback_object
*obj
);
1720 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1721 struct gl_transform_feedback_object
*obj
);
1723 /* brw_blorp_blit.cpp */
1725 brw_blorp_framebuffer(struct brw_context
*brw
,
1726 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1727 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1728 GLbitfield mask
, GLenum filter
);
1731 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1732 struct gl_renderbuffer
*src_rb
,
1733 struct gl_texture_image
*dst_image
,
1735 int srcX0
, int srcY0
,
1736 int dstX0
, int dstY0
,
1737 int width
, int height
);
1739 /* gen6_multisample_state.c */
1741 gen6_determine_sample_mask(struct brw_context
*brw
);
1744 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1745 unsigned num_samples
);
1747 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1749 gen6_get_sample_position(struct gl_context
*ctx
,
1750 struct gl_framebuffer
*fb
,
1754 /* gen8_multisample_state.c */
1755 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1756 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1760 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1761 unsigned gs_size
, unsigned fs_size
);
1764 gen7_emit_urb_state(struct brw_context
*brw
,
1765 unsigned nr_vs_entries
, unsigned vs_size
,
1766 unsigned vs_start
, unsigned nr_gs_entries
,
1767 unsigned gs_size
, unsigned gs_start
);
1772 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1774 /*======================================================================
1775 * Inline conversion functions. These are better-typed than the
1776 * macros used previously:
1778 static inline struct brw_context
*
1779 brw_context( struct gl_context
*ctx
)
1781 return (struct brw_context
*)ctx
;
1784 static inline struct brw_vertex_program
*
1785 brw_vertex_program(struct gl_vertex_program
*p
)
1787 return (struct brw_vertex_program
*) p
;
1790 static inline const struct brw_vertex_program
*
1791 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1793 return (const struct brw_vertex_program
*) p
;
1796 static inline struct brw_geometry_program
*
1797 brw_geometry_program(struct gl_geometry_program
*p
)
1799 return (struct brw_geometry_program
*) p
;
1802 static inline struct brw_fragment_program
*
1803 brw_fragment_program(struct gl_fragment_program
*p
)
1805 return (struct brw_fragment_program
*) p
;
1808 static inline const struct brw_fragment_program
*
1809 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1811 return (const struct brw_fragment_program
*) p
;
1815 * Pre-gen6, the register file of the EUs was shared between threads,
1816 * and each thread used some subset allocated on a 16-register block
1817 * granularity. The unit states wanted these block counts.
1820 brw_register_blocks(int reg_count
)
1822 return ALIGN(reg_count
, 16) / 16 - 1;
1825 static inline uint32_t
1826 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1827 uint32_t prog_offset
)
1829 if (brw
->gen
>= 5) {
1830 /* Using state base address. */
1834 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1838 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1840 return brw
->cache
.bo
->offset64
+ prog_offset
;
1843 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1844 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1845 struct exec_list
*instructions
);
1846 bool brw_do_lower_unnormalized_offset(struct exec_list
*instructions
);
1848 struct opcode_desc
{
1854 extern const struct opcode_desc opcode_descs
[128];
1855 extern const char * const conditional_modifier
[16];
1856 extern const char * const reg_encoding
[8];
1859 brw_emit_depthbuffer(struct brw_context
*brw
);
1862 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1863 struct intel_mipmap_tree
*depth_mt
,
1864 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1865 uint32_t depth_surface_type
,
1866 struct intel_mipmap_tree
*stencil_mt
,
1867 bool hiz
, bool separate_stencil
,
1868 uint32_t width
, uint32_t height
,
1869 uint32_t tile_x
, uint32_t tile_y
);
1872 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1873 struct intel_mipmap_tree
*depth_mt
,
1874 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1875 uint32_t depth_surface_type
,
1876 struct intel_mipmap_tree
*stencil_mt
,
1877 bool hiz
, bool separate_stencil
,
1878 uint32_t width
, uint32_t height
,
1879 uint32_t tile_x
, uint32_t tile_y
);
1881 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1882 struct intel_mipmap_tree
*depth_mt
,
1883 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1884 uint32_t depth_surface_type
,
1885 struct intel_mipmap_tree
*stencil_mt
,
1886 bool hiz
, bool separate_stencil
,
1887 uint32_t width
, uint32_t height
,
1888 uint32_t tile_x
, uint32_t tile_y
);
1890 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1891 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);
1893 extern const GLuint prim_to_hw_prim
[GL_TRIANGLE_STRIP_ADJACENCY
+1];
1896 brw_setup_vec4_key_clip_info(struct brw_context
*brw
,
1897 struct brw_vec4_prog_key
*key
,
1898 bool program_uses_clip_distance
);
1901 gen6_upload_vec4_push_constants(struct brw_context
*brw
,
1902 const struct gl_program
*prog
,
1903 const struct brw_vec4_prog_data
*prog_data
,
1904 struct brw_stage_state
*stage_state
,
1905 enum state_struct_type type
);
1907 /* ================================================================
1908 * From linux kernel i386 header files, copes with odd sizes better
1909 * than COPY_DWORDS would:
1910 * XXX Put this in src/mesa/main/imports.h ???
1912 #if defined(i386) || defined(__i386__)
1913 static inline void * __memcpy(void * to
, const void * from
, size_t n
)
1916 __asm__
__volatile__(
1921 "1:\ttestb $1,%b4\n\t"
1925 : "=&c" (d0
), "=&D" (d1
), "=&S" (d2
)
1926 :"0" (n
/4), "q" (n
),"1" ((long) to
),"2" ((long) from
)
1931 #define __memcpy(a,b,c) memcpy(a,b,c)