2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
37 #include "main/macros.h"
38 #include "main/mtypes.h"
39 #include "brw_structs.h"
40 #include "brw_compiler.h"
41 #include "intel_aub.h"
44 #include "blorp/blorp.h"
46 #include <intel_bufmgr.h>
48 #include "intel_debug.h"
49 #include "intel_screen.h"
50 #include "intel_tex_obj.h"
51 #include "intel_resolve_map.h"
58 * URB - uniform resource buffer. A mid-sized buffer which is
59 * partitioned between the fixed function units and used for passing
60 * values (vertices, primitives, constants) between them.
62 * CURBE - constant URB entry. An urb region (entry) used to hold
63 * constant values which the fixed function units can be instructed to
64 * preload into the GRF when spawning a thread.
66 * VUE - vertex URB entry. An urb entry holding a vertex and usually
67 * a vertex header. The header contains control information and
68 * things like primitive type, Begin/end flags and clip codes.
70 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
71 * unit holding rasterization and interpolation parameters.
73 * GRF - general register file. One of several register files
74 * addressable by programmed threads. The inputs (r0, payload, curbe,
75 * urb) of the thread are preloaded to this area before the thread is
76 * spawned. The registers are individually 8 dwords wide and suitable
77 * for general usage. Registers holding thread input values are not
78 * special and may be overwritten.
80 * MRF - message register file. Threads communicate (and terminate)
81 * by sending messages. Message parameters are placed in contiguous
82 * MRF registers. All program output is via these messages. URB
83 * entries are populated by sending a message to the shared URB
84 * function containing the new data, together with a control word,
85 * often an unmodified copy of R0.
87 * R0 - GRF register 0. Typically holds control information used when
88 * sending messages to other threads.
90 * EU or GEN4 EU: The name of the programmable subsystem of the
91 * i965 hardware. Threads are executed by the EU, the registers
92 * described above are part of the EU architecture.
94 * Fixed function units:
96 * CS - Command streamer. Notional first unit, little software
97 * interaction. Holds the URB entries used for constant data, ie the
100 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
101 * this unit is responsible for pulling vertices out of vertex buffers
102 * in vram and injecting them into the processing pipe as VUEs. If
103 * enabled, it first passes them to a VS thread which is a good place
104 * for the driver to implement any active vertex shader.
106 * HS - Hull Shader (Tessellation Control Shader)
108 * TE - Tessellation Engine (Tessellation Primitive Generation)
110 * DS - Domain Shader (Tessellation Evaluation Shader)
112 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
113 * enabled, incoming strips etc are passed to GS threads in individual
114 * line/triangle/point units. The GS thread may perform arbitary
115 * computation and emit whatever primtives with whatever vertices it
116 * chooses. This makes GS an excellent place to implement GL's
117 * unfilled polygon modes, though of course it is capable of much
118 * more. Additionally, GS is used to translate away primitives not
119 * handled by latter units, including Quads and Lineloops.
121 * CS - Clipper. Mesa's clipping algorithms are imported to run on
122 * this unit. The fixed function part performs cliptesting against
123 * the 6 fixed clipplanes and makes descisions on whether or not the
124 * incoming primitive needs to be passed to a thread for clipping.
125 * User clip planes are handled via cooperation with the VS thread.
127 * SF - Strips Fans or Setup: Triangles are prepared for
128 * rasterization. Interpolation coefficients are calculated.
129 * Flatshading and two-side lighting usually performed here.
131 * WM - Windower. Interpolation of vertex attributes performed here.
132 * Fragment shader implemented here. SIMD aspects of EU taken full
133 * advantage of, as pixels are processed in blocks of 16.
135 * CC - Color Calculator. No EU threads associated with this unit.
136 * Handles blending and (presumably) depth and stencil testing.
141 struct brw_vs_prog_key
;
142 struct brw_vue_prog_key
;
143 struct brw_wm_prog_key
;
144 struct brw_wm_prog_data
;
145 struct brw_cs_prog_key
;
146 struct brw_cs_prog_data
;
150 BRW_COMPUTE_PIPELINE
,
157 BRW_CACHE_BLORP_PROG
,
160 BRW_CACHE_FF_GS_PROG
,
171 /* brw_cache_ids must come first - see brw_program_cache.c */
172 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
173 BRW_STATE_FRAGMENT_PROGRAM
,
174 BRW_STATE_GEOMETRY_PROGRAM
,
175 BRW_STATE_TESS_PROGRAMS
,
176 BRW_STATE_VERTEX_PROGRAM
,
177 BRW_STATE_CURBE_OFFSETS
,
178 BRW_STATE_REDUCED_PRIMITIVE
,
179 BRW_STATE_PATCH_PRIMITIVE
,
184 BRW_STATE_BINDING_TABLE_POINTERS
,
187 BRW_STATE_DEFAULT_TESS_LEVELS
,
189 BRW_STATE_INDEX_BUFFER
,
190 BRW_STATE_VS_CONSTBUF
,
191 BRW_STATE_TCS_CONSTBUF
,
192 BRW_STATE_TES_CONSTBUF
,
193 BRW_STATE_GS_CONSTBUF
,
194 BRW_STATE_PROGRAM_CACHE
,
195 BRW_STATE_STATE_BASE_ADDRESS
,
196 BRW_STATE_VUE_MAP_GEOM_OUT
,
197 BRW_STATE_TRANSFORM_FEEDBACK
,
198 BRW_STATE_RASTERIZER_DISCARD
,
200 BRW_STATE_UNIFORM_BUFFER
,
201 BRW_STATE_ATOMIC_BUFFER
,
202 BRW_STATE_IMAGE_UNITS
,
203 BRW_STATE_META_IN_PROGRESS
,
204 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
205 BRW_STATE_NUM_SAMPLES
,
206 BRW_STATE_TEXTURE_BUFFER
,
207 BRW_STATE_GEN4_UNIT_STATE
,
211 BRW_STATE_SAMPLER_STATE_TABLE
,
212 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
213 BRW_STATE_COMPUTE_PROGRAM
,
214 BRW_STATE_CS_WORK_GROUPS
,
218 BRW_STATE_VIEWPORT_COUNT
,
219 BRW_STATE_CONSERVATIVE_RASTERIZATION
,
224 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
226 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
227 * When the currently bound shader program differs from the previous draw
228 * call, these will be flagged. They cover brw->{stage}_program and
229 * ctx->{Stage}Program->_Current.
231 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
232 * driver perspective. Even if the same shader is bound at the API level,
233 * we may need to switch between multiple versions of that shader to handle
234 * changes in non-orthagonal state.
236 * Additionally, multiple shader programs may have identical vertex shaders
237 * (for example), or compile down to the same code in the backend. We combine
238 * those into a single program cache entry.
240 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
241 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
243 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
244 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
245 * use the normal state upload paths), but the cache is still used. To avoid
246 * polluting the brw_program_cache code with special cases, we retain the
247 * dirty bit for now. It should eventually be removed.
249 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_PROG)
250 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
251 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
252 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
253 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
254 #define BRW_NEW_TCS_PROG_DATA (1ull << BRW_CACHE_TCS_PROG)
255 #define BRW_NEW_TES_PROG_DATA (1ull << BRW_CACHE_TES_PROG)
256 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
257 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
258 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
259 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
260 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
261 #define BRW_NEW_TESS_PROGRAMS (1ull << BRW_STATE_TESS_PROGRAMS)
262 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
263 #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
264 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
265 #define BRW_NEW_PATCH_PRIMITIVE (1ull << BRW_STATE_PATCH_PRIMITIVE)
266 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
267 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
268 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
269 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
270 #define BRW_NEW_BINDING_TABLE_POINTERS (1ull << BRW_STATE_BINDING_TABLE_POINTERS)
271 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
272 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
273 #define BRW_NEW_DEFAULT_TESS_LEVELS (1ull << BRW_STATE_DEFAULT_TESS_LEVELS)
275 * Used for any batch entry with a relocated pointer that will be used
276 * by any 3D rendering.
278 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
279 /** \see brw.state.depth_region */
280 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
281 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
282 #define BRW_NEW_TCS_CONSTBUF (1ull << BRW_STATE_TCS_CONSTBUF)
283 #define BRW_NEW_TES_CONSTBUF (1ull << BRW_STATE_TES_CONSTBUF)
284 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
285 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
286 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
287 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
288 #define BRW_NEW_VIEWPORT_COUNT (1ull << BRW_STATE_VIEWPORT_COUNT)
289 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
290 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
291 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
292 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
293 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
294 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
295 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
296 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
297 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
298 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
299 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
300 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
301 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
302 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
303 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
304 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
305 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
306 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
307 #define BRW_NEW_URB_SIZE (1ull << BRW_STATE_URB_SIZE)
308 #define BRW_NEW_CC_STATE (1ull << BRW_STATE_CC_STATE)
309 #define BRW_NEW_BLORP (1ull << BRW_STATE_BLORP)
310 #define BRW_NEW_CONSERVATIVE_RASTERIZATION (1ull << BRW_STATE_CONSERVATIVE_RASTERIZATION)
312 struct brw_state_flags
{
313 /** State update flags signalled by mesa internals */
316 * State update flags signalled as the result of brw_tracked_state updates
322 /** Subclass of Mesa program */
324 struct gl_program program
;
332 * Bitmask indicating which fragment shader inputs represent varyings (and
333 * hence have to be delivered to the fragment shader by the SF/SBE stage).
335 #define BRW_FS_VARYING_INPUT_MASK \
336 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
337 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
340 struct brw_sf_prog_data
{
341 GLuint urb_read_length
;
344 /* Each vertex may have upto 12 attributes, 4 components each,
345 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
348 * Actually we use 4 for each, so call it 12 rows.
350 GLuint urb_entry_size
;
355 * We always program SF to start reading at an offset of 1 (2 varying slots)
356 * from the start of the vertex URB entry. This causes it to skip:
357 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
358 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
360 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
363 struct brw_clip_prog_data
{
364 GLuint curb_read_length
; /* user planes? */
366 GLuint urb_read_length
;
370 struct brw_ff_gs_prog_data
{
371 GLuint urb_read_length
;
375 * Gen6 transform feedback: Amount by which the streaming vertex buffer
376 * indices should be incremented each time the GS is invoked.
378 unsigned svbi_postincrement_value
;
381 /** Number of texture sampler units */
382 #define BRW_MAX_TEX_UNIT 32
384 /** Max number of render targets in a shader */
385 #define BRW_MAX_DRAW_BUFFERS 8
387 /** Max number of UBOs in a shader */
388 #define BRW_MAX_UBO 14
390 /** Max number of SSBOs in a shader */
391 #define BRW_MAX_SSBO 12
393 /** Max number of atomic counter buffer objects in a shader */
394 #define BRW_MAX_ABO 16
396 /** Max number of image uniforms in a shader */
397 #define BRW_MAX_IMAGES 32
400 * Max number of binding table entries used for stream output.
402 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
403 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
405 * On Gen6, the size of transform feedback data is limited not by the number
406 * of components but by the number of binding table entries we set aside. We
407 * use one binding table entry for a float, one entry for a vector, and one
408 * entry per matrix column. Since the only way we can communicate our
409 * transform feedback capabilities to the client is via
410 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
411 * worst case, in which all the varyings are floats, so we use up one binding
412 * table entry per component. Therefore we need to set aside at least 64
413 * binding table entries for use by transform feedback.
415 * Note: since we don't currently pack varyings, it is currently impossible
416 * for the client to actually use up all of these binding table entries--if
417 * all of their varyings were floats, they would run out of varying slots and
418 * fail to link. But that's a bug, so it seems prudent to go ahead and
419 * allocate the number of binding table entries we will need once the bug is
422 #define BRW_MAX_SOL_BINDINGS 64
424 /** Maximum number of actual buffers used for stream output */
425 #define BRW_MAX_SOL_BUFFERS 4
427 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
428 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
433 2 + /* shader time, pull constants */ \
434 1 /* cs num work groups */)
436 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
439 * Stride in bytes between shader_time entries.
441 * We separate entries by a cacheline to reduce traffic between EUs writing to
444 #define SHADER_TIME_STRIDE 64
447 struct brw_context
*brw
;
449 struct brw_cache_item
**items
;
451 GLuint size
, n_items
;
453 uint32_t next_offset
;
458 /* Considered adding a member to this struct to document which flags
459 * an update might raise so that ordering of the state atoms can be
460 * checked or derived at runtime. Dropped the idea in favor of having
461 * a debug mode where the state is monitored for flags which are
462 * raised that have already been tested against.
464 struct brw_tracked_state
{
465 struct brw_state_flags dirty
;
466 void (*emit
)( struct brw_context
*brw
);
469 enum shader_time_shader_type
{
480 struct brw_vertex_buffer
{
481 /** Buffer object containing the uploaded vertex data */
485 /** Byte stride between elements in the uploaded array */
489 struct brw_vertex_element
{
490 const struct gl_vertex_array
*glarray
;
494 /** Offset of the first element within the buffer object */
498 struct brw_query_object
{
499 struct gl_query_object Base
;
501 /** Last query BO associated with this query. */
504 /** Last index in bo with query data for this object. */
507 /** True if we know the batch has been flushed since we ended the query. */
517 struct intel_batchbuffer
{
518 /** Current batchbuffer being queued up. */
520 /** Last BO submitted to the hardware. Used for glFinish(). */
521 drm_intel_bo
*last_bo
;
524 uint16_t emit
, total
;
526 uint16_t reserved_space
;
530 #define BATCH_SZ (8192*sizeof(uint32_t))
532 uint32_t state_batch_offset
;
533 enum brw_gpu_ring ring
;
534 bool needs_sol_reset
;
535 bool state_base_address_emitted
;
543 #define MAX_GS_INPUT_VERTICES 6
545 #define BRW_MAX_XFB_STREAMS 4
547 struct brw_transform_feedback_object
{
548 struct gl_transform_feedback_object base
;
550 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
551 drm_intel_bo
*offset_bo
;
553 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
556 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
557 GLenum primitive_mode
;
560 * Count of primitives generated during this transform feedback operation.
563 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
564 drm_intel_bo
*prim_count_bo
;
565 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
569 * Number of vertices written between last Begin/EndTransformFeedback().
571 * Used to implement DrawTransformFeedback().
573 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
574 bool vertices_written_valid
;
578 * Data shared between each programmable stage in the pipeline (vs, gs, and
581 struct brw_stage_state
583 gl_shader_stage stage
;
584 struct brw_stage_prog_data
*prog_data
;
587 * Optional scratch buffer used to store spilled register values and
588 * variably-indexed GRF arrays.
590 * The contents of this buffer are short-lived so the same memory can be
591 * re-used at will for multiple shader programs (executed by the same fixed
592 * function). However reusing a scratch BO for which shader invocations
593 * are still in flight with a per-thread scratch slot size other than the
594 * original can cause threads with different scratch slot size and FFTID
595 * (which may be executed in parallel depending on the shader stage and
596 * hardware generation) to map to an overlapping region of the scratch
597 * space, which can potentially lead to mutual scratch space corruption.
598 * For that reason if you borrow this scratch buffer you should only be
599 * using the slot size given by the \c per_thread_scratch member below,
600 * unless you're taking additional measures to synchronize thread execution
601 * across slot size changes.
603 drm_intel_bo
*scratch_bo
;
606 * Scratch slot size allocated for each thread in the buffer object given
609 uint32_t per_thread_scratch
;
611 /** Offset in the program cache to the program */
612 uint32_t prog_offset
;
614 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
615 uint32_t state_offset
;
617 uint32_t push_const_offset
; /* Offset in the batchbuffer */
618 int push_const_size
; /* in 256-bit register increments */
620 /* Binding table: pointers to SURFACE_STATE entries. */
621 uint32_t bind_bo_offset
;
622 uint32_t surf_offset
[BRW_MAX_SURFACES
];
624 /** SAMPLER_STATE count and table offset */
625 uint32_t sampler_count
;
626 uint32_t sampler_offset
;
629 enum brw_predicate_state
{
630 /* The first two states are used if we can determine whether to draw
631 * without having to look at the values in the query object buffer. This
632 * will happen if there is no conditional render in progress, if the query
633 * object is already completed or if something else has already added
634 * samples to the preliminary result such as via a BLT command.
636 BRW_PREDICATE_STATE_RENDER
,
637 BRW_PREDICATE_STATE_DONT_RENDER
,
638 /* In this case whether to draw or not depends on the result of an
639 * MI_PREDICATE command so the predicate enable bit needs to be checked.
641 BRW_PREDICATE_STATE_USE_BIT
646 struct gen_l3_config
;
649 * brw_context is derived from gl_context.
653 struct gl_context ctx
; /**< base class, must be first field */
657 uint32_t (*update_renderbuffer_surface
)(struct brw_context
*brw
,
658 struct gl_renderbuffer
*rb
,
659 uint32_t flags
, unsigned unit
,
660 uint32_t surf_index
);
661 void (*emit_null_surface_state
)(struct brw_context
*brw
,
665 uint32_t *out_offset
);
668 * Send the appropriate state packets to configure depth, stencil, and
669 * HiZ buffers (i965+ only)
671 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
672 struct intel_mipmap_tree
*depth_mt
,
673 uint32_t depth_offset
,
674 uint32_t depthbuffer_format
,
675 uint32_t depth_surface_type
,
676 struct intel_mipmap_tree
*stencil_mt
,
677 bool hiz
, bool separate_stencil
,
678 uint32_t width
, uint32_t height
,
679 uint32_t tile_x
, uint32_t tile_y
);
685 drm_intel_context
*hw_ctx
;
687 /** BO for post-sync nonzero writes for gen6 workaround. */
688 drm_intel_bo
*workaround_bo
;
689 uint8_t pipe_controls_since_last_cs_stall
;
692 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
693 * and would need flushing before being used from another cache domain that
694 * isn't coherent with it (i.e. the sampler).
696 struct set
*render_cache
;
699 * Number of resets observed in the system at context creation.
701 * This is tracked in the context so that we can determine that another
702 * reset has occurred.
704 uint32_t reset_count
;
706 struct intel_batchbuffer batch
;
711 uint32_t next_offset
;
715 * Set if rendering has occurred to the drawable's front buffer.
717 * This is used in the DRI2 case to detect that glFlush should also copy
718 * the contents of the fake front buffer to the real front buffer.
720 bool front_buffer_dirty
;
722 /** Framerate throttling: @{ */
723 drm_intel_bo
*throttle_batch
[2];
725 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
726 * frame of rendering to complete. This gives a very precise cap to the
727 * latency between input and output such that rendering never gets more
728 * than a frame behind the user. (With the caveat that we technically are
729 * not using the SwapBuffers itself as a barrier but the first batch
730 * submitted afterwards, which may be immediately prior to the next
733 bool need_swap_throttle
;
735 /** General throttling, not caught by throttling between SwapBuffers */
736 bool need_flush_throttle
;
746 bool always_flush_batch
;
747 bool always_flush_cache
;
748 bool disable_throttling
;
750 bool dual_color_blend_by_location
;
752 driOptionCache optionCache
;
755 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
757 GLenum reduced_primitive
;
760 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
761 * variable is set, this is the flag indicating to do expensive work that
762 * might lead to a perf_debug() call.
766 uint64_t max_gtt_map_object_size
;
778 bool has_separate_stencil
;
779 bool must_use_separate_stencil
;
782 bool has_surface_tile_offset
;
784 bool has_negative_rhw_bug
;
788 bool use_resource_streamer
;
791 * Some versions of Gen hardware don't do centroid interpolation correctly
792 * on unlit pixels, causing incorrect values for derivatives near triangle
793 * edges. Enabling this flag causes the fragment shader to use
794 * non-centroid interpolation for unlit pixels, at the expense of two extra
795 * fragment shader instructions.
797 bool needs_unlit_centroid_workaround
;
799 struct isl_device isl_dev
;
801 struct blorp_context blorp
;
805 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
808 enum brw_pipeline last_pipeline
;
810 struct brw_cache cache
;
812 /** IDs for meta stencil blit shader programs. */
813 struct gl_shader_program
*meta_stencil_blit_programs
[2];
815 /* Whether a meta-operation is in progress. */
816 bool meta_in_progress
;
818 /* Whether the last depth/stencil packets were both NULL. */
819 bool no_depth_or_stencil
;
821 /* The last PMA stall bits programmed. */
822 uint32_t pma_stall_bits
;
826 /** The value of gl_BaseVertex for the current _mesa_prim. */
829 /** The value of gl_BaseInstance for the current _mesa_prim. */
834 * Buffer and offset used for GL_ARB_shader_draw_parameters
835 * (for now, only gl_BaseVertex).
837 drm_intel_bo
*draw_params_bo
;
838 uint32_t draw_params_offset
;
841 * The value of gl_DrawID for the current _mesa_prim. This always comes
842 * in from it's own vertex buffer since it's not part of the indirect
846 drm_intel_bo
*draw_id_bo
;
847 uint32_t draw_id_offset
;
852 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
853 * an indirect call, and num_work_groups_offset is valid. Otherwise,
854 * num_work_groups is set based on glDispatchCompute.
856 drm_intel_bo
*num_work_groups_bo
;
857 GLintptr num_work_groups_offset
;
858 const GLuint
*num_work_groups
;
862 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
863 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
865 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
869 /* Summary of size and varying of active arrays, so we can check
870 * for changes to this state:
872 bool index_bounds_valid
;
873 unsigned int min_index
, max_index
;
875 /* Offset from start of vertex buffer so we can avoid redefining
876 * the same VB packed over and over again.
878 unsigned int start_vertex_bias
;
881 * Certain vertex attribute formats aren't natively handled by the
882 * hardware and require special VS code to fix up their values.
884 * These bitfields indicate which workarounds are needed.
886 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
891 * Index buffer for this draw_prims call.
893 * Updates are signaled by BRW_NEW_INDICES.
895 const struct _mesa_index_buffer
*ib
;
897 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
902 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
903 * avoid re-uploading the IB packet over and over if we're actually
904 * referencing the same index buffer.
906 unsigned int start_vertex_offset
;
909 /* Active vertex program:
911 const struct gl_program
*vertex_program
;
912 const struct gl_program
*geometry_program
;
913 const struct gl_program
*tess_ctrl_program
;
914 const struct gl_program
*tess_eval_program
;
915 const struct gl_program
*fragment_program
;
916 const struct gl_program
*compute_program
;
919 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
920 * that we don't have to reemit that state every time we change FBOs.
924 /* BRW_NEW_URB_ALLOCATIONS:
927 GLuint vsize
; /* vertex size plus header in urb registers */
928 GLuint gsize
; /* GS output size in urb registers */
929 GLuint hsize
; /* Tessellation control output size in urb registers */
930 GLuint dsize
; /* Tessellation evaluation output size in urb registers */
931 GLuint csize
; /* constant buffer size in urb registers */
932 GLuint sfsize
; /* setup data size in urb registers */
936 GLuint nr_vs_entries
;
937 GLuint nr_hs_entries
;
938 GLuint nr_ds_entries
;
939 GLuint nr_gs_entries
;
940 GLuint nr_clip_entries
;
941 GLuint nr_sf_entries
;
942 GLuint nr_cs_entries
;
952 * URB size in the current configuration. The units this is expressed
953 * in are somewhat inconsistent, see gen_device_info::urb::size.
955 * FINISHME: Represent the URB size consistently in KB on all platforms.
959 /* True if the most recently sent _3DSTATE_URB message allocated
960 * URB space for the GS.
964 /* True if the most recently sent _3DSTATE_URB message allocated
965 * URB space for the HS and DS.
971 /* BRW_NEW_CURBE_OFFSETS:
974 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
975 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
983 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
984 * for upload to the CURBE.
986 drm_intel_bo
*curbe_bo
;
987 /** Offset within curbe_bo of space for current curbe entry */
992 * Layout of vertex data exiting the geometry portion of the pipleine.
993 * This comes from the last enabled shader stage (GS, DS, or VS).
995 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
997 struct brw_vue_map vue_map_geom_out
;
1000 struct brw_stage_state base
;
1004 struct brw_stage_state base
;
1007 * True if the 3DSTATE_HS command most recently emitted to the 3D
1008 * pipeline enabled the HS; false otherwise.
1014 struct brw_stage_state base
;
1017 * True if the 3DSTATE_DS command most recently emitted to the 3D
1018 * pipeline enabled the DS; false otherwise.
1024 struct brw_stage_state base
;
1027 * True if the 3DSTATE_GS command most recently emitted to the 3D
1028 * pipeline enabled the GS; false otherwise.
1034 struct brw_ff_gs_prog_data
*prog_data
;
1037 /** Offset in the program cache to the CLIP program pre-gen6 */
1038 uint32_t prog_offset
;
1039 uint32_t state_offset
;
1041 uint32_t bind_bo_offset
;
1043 * Surface offsets for the binding table. We only need surfaces to
1044 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1045 * need in this case.
1047 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1051 struct brw_clip_prog_data
*prog_data
;
1053 /** Offset in the program cache to the CLIP program pre-gen6 */
1054 uint32_t prog_offset
;
1056 /* Offset in the batch to the CLIP state on pre-gen6. */
1057 uint32_t state_offset
;
1059 /* As of gen6, this is the offset in the batch to the CLIP VP,
1065 * The number of viewports to use. If gl_ViewportIndex is written,
1066 * we can have up to ctx->Const.MaxViewports viewports. If not,
1067 * the viewport index is always 0, so we can only emit one.
1069 uint8_t viewport_count
;
1074 struct brw_sf_prog_data
*prog_data
;
1076 /** Offset in the program cache to the CLIP program pre-gen6 */
1077 uint32_t prog_offset
;
1078 uint32_t state_offset
;
1080 bool viewport_transform_enable
;
1084 struct brw_stage_state base
;
1089 * Buffer object used in place of multisampled null render targets on
1090 * Gen6. See brw_emit_null_surface_state().
1092 drm_intel_bo
*multisampled_null_render_target_bo
;
1093 uint32_t fast_clear_op
;
1099 struct brw_stage_state base
;
1102 /* RS hardware binding table */
1105 uint32_t next_offset
;
1109 uint32_t state_offset
;
1110 uint32_t blend_state_offset
;
1111 uint32_t depth_stencil_state_offset
;
1116 struct brw_query_object
*obj
;
1121 enum brw_predicate_state state
;
1125 int num_atoms
[BRW_NUM_PIPELINES
];
1126 const struct brw_tracked_state render_atoms
[76];
1127 const struct brw_tracked_state compute_atoms
[11];
1129 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1133 enum aub_state_struct_type type
;
1135 } *state_batch_list
;
1136 int state_batch_count
;
1138 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1139 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1141 /* PrimitiveRestart */
1144 bool enable_cut_index
;
1147 /** Computed depth/stencil/hiz state from the current attached
1148 * renderbuffers, valid only during the drawing state upload loop after
1149 * brw_workaround_depthstencil_alignment().
1152 struct intel_mipmap_tree
*depth_mt
;
1153 struct intel_mipmap_tree
*stencil_mt
;
1155 /* Inter-tile (page-aligned) byte offsets. */
1156 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1157 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1158 uint32_t tile_x
, tile_y
;
1161 uint32_t num_instances
;
1166 const struct gen_l3_config
*config
;
1173 enum shader_time_shader_type
*types
;
1174 struct shader_times
*cumulative
;
1180 struct brw_fast_clear_state
*fast_clear_state
;
1182 /* Array of flags telling if auxiliary buffer is disabled for corresponding
1183 * renderbuffer. If draw_aux_buffer_disabled[i] is set then use of
1184 * auxiliary buffer for gl_framebuffer::_ColorDrawBuffers[i] is
1186 * This is needed in case the same underlying buffer is also configured
1187 * to be sampled but with a format that the sampling engine can't treat
1188 * compressed or fast cleared.
1190 bool draw_aux_buffer_disabled
[MAX_DRAW_BUFFERS
];
1192 __DRIcontext
*driContext
;
1193 struct intel_screen
*screen
;
1197 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1199 /*======================================================================
1202 extern const char *const brw_vendor_string
;
1205 brw_get_renderer_string(const struct intel_screen
*screen
);
1208 DRI_CONF_BO_REUSE_DISABLED
,
1209 DRI_CONF_BO_REUSE_ALL
1212 void intel_update_renderbuffers(__DRIcontext
*context
,
1213 __DRIdrawable
*drawable
);
1214 void intel_prepare_render(struct brw_context
*brw
);
1216 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1217 __DRIdrawable
*drawable
);
1219 GLboolean
brwCreateContext(gl_api api
,
1220 const struct gl_config
*mesaVis
,
1221 __DRIcontext
*driContextPriv
,
1222 unsigned major_version
,
1223 unsigned minor_version
,
1227 void *sharedContextPrivate
);
1229 /*======================================================================
1233 brw_meta_resolve_color(struct brw_context
*brw
,
1234 struct intel_mipmap_tree
*mt
);
1236 /*======================================================================
1239 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1240 GLbitfield clear_mask
);
1242 /* brw_object_purgeable.c */
1243 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1245 /*======================================================================
1248 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1249 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1250 void brw_emit_query_begin(struct brw_context
*brw
);
1251 void brw_emit_query_end(struct brw_context
*brw
);
1252 void brw_query_counter(struct gl_context
*ctx
, struct gl_query_object
*q
);
1253 bool brw_is_query_pipelined(struct brw_query_object
*query
);
1255 /** gen6_queryobj.c */
1256 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1257 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1258 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1260 /** hsw_queryobj.c */
1261 void hsw_init_queryobj_functions(struct dd_function_table
*functions
);
1263 /** brw_conditional_render.c */
1264 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1265 bool brw_check_conditional_render(struct brw_context
*brw
);
1267 /** intel_batchbuffer.c */
1268 void brw_load_register_mem(struct brw_context
*brw
,
1271 uint32_t read_domains
, uint32_t write_domain
,
1273 void brw_load_register_mem64(struct brw_context
*brw
,
1276 uint32_t read_domains
, uint32_t write_domain
,
1278 void brw_store_register_mem32(struct brw_context
*brw
,
1279 drm_intel_bo
*bo
, uint32_t reg
, uint32_t offset
);
1280 void brw_store_register_mem64(struct brw_context
*brw
,
1281 drm_intel_bo
*bo
, uint32_t reg
, uint32_t offset
);
1282 void brw_load_register_imm32(struct brw_context
*brw
,
1283 uint32_t reg
, uint32_t imm
);
1284 void brw_load_register_imm64(struct brw_context
*brw
,
1285 uint32_t reg
, uint64_t imm
);
1286 void brw_load_register_reg(struct brw_context
*brw
, uint32_t src
,
1288 void brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
,
1290 void brw_store_data_imm32(struct brw_context
*brw
, drm_intel_bo
*bo
,
1291 uint32_t offset
, uint32_t imm
);
1292 void brw_store_data_imm64(struct brw_context
*brw
, drm_intel_bo
*bo
,
1293 uint32_t offset
, uint64_t imm
);
1295 /*======================================================================
1298 void brw_debug_batch(struct brw_context
*brw
);
1299 void brw_annotate_aub(struct brw_context
*brw
);
1301 /*======================================================================
1302 * intel_tex_validate.c
1304 void brw_validate_textures( struct brw_context
*brw
);
1307 /*======================================================================
1311 key_debug(struct brw_context
*brw
, const char *name
, int a
, int b
)
1314 perf_debug(" %s %d->%d\n", name
, a
, b
);
1320 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1322 /* Per-thread scratch space is a power-of-two multiple of 1KB. */
1324 brw_get_scratch_size(int size
)
1326 return MAX2(1024, util_next_power_of_two(size
));
1328 void brw_get_scratch_bo(struct brw_context
*brw
,
1329 drm_intel_bo
**scratch_bo
, int size
);
1330 void brw_alloc_stage_scratch(struct brw_context
*brw
,
1331 struct brw_stage_state
*stage_state
,
1332 unsigned per_thread_size
,
1333 unsigned thread_count
);
1334 void brw_init_shader_time(struct brw_context
*brw
);
1335 int brw_get_shader_time_index(struct brw_context
*brw
,
1336 struct gl_program
*prog
,
1337 enum shader_time_shader_type type
,
1339 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1340 void brw_destroy_shader_time(struct brw_context
*brw
);
1344 void brw_upload_urb_fence(struct brw_context
*brw
);
1348 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1350 /* brw_fs_reg_allocate.cpp
1352 void brw_fs_alloc_reg_sets(struct brw_compiler
*compiler
);
1354 /* brw_vec4_reg_allocate.cpp */
1355 void brw_vec4_alloc_reg_set(struct brw_compiler
*compiler
);
1358 int brw_disassemble_inst(FILE *file
, const struct gen_device_info
*devinfo
,
1359 struct brw_inst
*inst
, bool is_compacted
);
1362 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1364 /* brw_draw_upload.c */
1365 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1366 const struct gl_vertex_array
*glarray
);
1368 static inline unsigned
1369 brw_get_index_type(GLenum type
)
1371 assert((type
== GL_UNSIGNED_BYTE
)
1372 || (type
== GL_UNSIGNED_SHORT
)
1373 || (type
== GL_UNSIGNED_INT
));
1375 /* The possible values for type are GL_UNSIGNED_BYTE (0x1401),
1376 * GL_UNSIGNED_SHORT (0x1403), and GL_UNSIGNED_INT (0x1405) which we want
1377 * to map to scale factors of 0, 1, and 2, respectively. These scale
1378 * factors are then left-shfited by 8 to be in the correct position in the
1379 * CMD_INDEX_BUFFER packet.
1381 * Subtracting 0x1401 gives 0, 2, and 4. Shifting left by 7 afterwards
1382 * gives 0x00000000, 0x00000100, and 0x00000200. These just happen to be
1383 * the values the need to be written in the CMD_INDEX_BUFFER packet.
1385 return (type
- 0x1401) << 7;
1388 void brw_prepare_vertices(struct brw_context
*brw
);
1390 /* brw_wm_surface_state.c */
1391 void brw_init_surface_formats(struct brw_context
*brw
);
1392 void brw_create_constant_surface(struct brw_context
*brw
,
1396 uint32_t *out_offset
);
1397 void brw_create_buffer_surface(struct brw_context
*brw
,
1401 uint32_t *out_offset
);
1402 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1404 uint32_t *surf_offset
);
1406 brw_update_sol_surface(struct brw_context
*brw
,
1407 struct gl_buffer_object
*buffer_obj
,
1408 uint32_t *out_offset
, unsigned num_vector_components
,
1409 unsigned stride_dwords
, unsigned offset_dwords
);
1410 void brw_upload_ubo_surfaces(struct brw_context
*brw
, struct gl_program
*prog
,
1411 struct brw_stage_state
*stage_state
,
1412 struct brw_stage_prog_data
*prog_data
);
1413 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1414 const struct gl_program
*prog
,
1415 struct brw_stage_state
*stage_state
,
1416 struct brw_stage_prog_data
*prog_data
);
1417 void brw_upload_image_surfaces(struct brw_context
*brw
,
1418 const struct gl_program
*prog
,
1419 struct brw_stage_state
*stage_state
,
1420 struct brw_stage_prog_data
*prog_data
);
1422 /* brw_surface_formats.c */
1423 bool brw_render_target_supported(struct brw_context
*brw
,
1424 struct gl_renderbuffer
*rb
);
1425 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1427 /* intel_buffer_objects.c */
1428 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1429 const char *bo_name
);
1430 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1431 const char *bo_name
);
1433 /* intel_extensions.c */
1434 extern void intelInitExtensions(struct gl_context
*ctx
);
1437 extern int intel_translate_shadow_compare_func(GLenum func
);
1438 extern int intel_translate_compare_func(GLenum func
);
1439 extern int intel_translate_stencil_op(GLenum op
);
1440 extern int intel_translate_logic_op(GLenum opcode
);
1443 void brw_init_syncobj_functions(struct dd_function_table
*functions
);
1446 struct gl_transform_feedback_object
*
1447 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1449 brw_delete_transform_feedback(struct gl_context
*ctx
,
1450 struct gl_transform_feedback_object
*obj
);
1452 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1453 struct gl_transform_feedback_object
*obj
);
1455 brw_end_transform_feedback(struct gl_context
*ctx
,
1456 struct gl_transform_feedback_object
*obj
);
1458 brw_save_primitives_written_counters(struct brw_context
*brw
,
1459 struct brw_transform_feedback_object
*obj
);
1461 brw_compute_xfb_vertices_written(struct brw_context
*brw
,
1462 struct brw_transform_feedback_object
*obj
);
1464 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1465 struct gl_transform_feedback_object
*obj
,
1468 /* gen7_sol_state.c */
1470 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1471 struct gl_transform_feedback_object
*obj
);
1473 gen7_end_transform_feedback(struct gl_context
*ctx
,
1474 struct gl_transform_feedback_object
*obj
);
1476 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1477 struct gl_transform_feedback_object
*obj
);
1479 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1480 struct gl_transform_feedback_object
*obj
);
1484 hsw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1485 struct gl_transform_feedback_object
*obj
);
1487 hsw_end_transform_feedback(struct gl_context
*ctx
,
1488 struct gl_transform_feedback_object
*obj
);
1490 hsw_pause_transform_feedback(struct gl_context
*ctx
,
1491 struct gl_transform_feedback_object
*obj
);
1493 hsw_resume_transform_feedback(struct gl_context
*ctx
,
1494 struct gl_transform_feedback_object
*obj
);
1496 /* brw_blorp_blit.cpp */
1498 brw_blorp_framebuffer(struct brw_context
*brw
,
1499 struct gl_framebuffer
*readFb
,
1500 struct gl_framebuffer
*drawFb
,
1501 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1502 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1503 GLbitfield mask
, GLenum filter
);
1506 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1507 struct gl_renderbuffer
*src_rb
,
1508 struct gl_texture_image
*dst_image
,
1510 int srcX0
, int srcY0
,
1511 int dstX0
, int dstY0
,
1512 int width
, int height
);
1514 /* gen6_multisample_state.c */
1516 gen6_determine_sample_mask(struct brw_context
*brw
);
1519 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1520 unsigned num_samples
);
1522 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1524 gen6_get_sample_position(struct gl_context
*ctx
,
1525 struct gl_framebuffer
*fb
,
1529 gen6_set_sample_maps(struct gl_context
*ctx
);
1531 /* gen8_multisample_state.c */
1532 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1533 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1537 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1538 unsigned hs_size
, unsigned ds_size
,
1539 unsigned gs_size
, unsigned fs_size
);
1542 gen6_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1543 bool gs_present
, unsigned gs_size
);
1545 gen7_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1546 bool gs_present
, bool tess_present
);
1550 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1552 brw_check_for_reset(struct brw_context
*brw
);
1556 brw_init_compute_functions(struct dd_function_table
*functions
);
1558 /*======================================================================
1559 * Inline conversion functions. These are better-typed than the
1560 * macros used previously:
1562 static inline struct brw_context
*
1563 brw_context( struct gl_context
*ctx
)
1565 return (struct brw_context
*)ctx
;
1568 static inline struct brw_program
*
1569 brw_program(struct gl_program
*p
)
1571 return (struct brw_program
*) p
;
1574 static inline const struct brw_program
*
1575 brw_program_const(const struct gl_program
*p
)
1577 return (const struct brw_program
*) p
;
1581 * Pre-gen6, the register file of the EUs was shared between threads,
1582 * and each thread used some subset allocated on a 16-register block
1583 * granularity. The unit states wanted these block counts.
1586 brw_register_blocks(int reg_count
)
1588 return ALIGN(reg_count
, 16) / 16 - 1;
1591 static inline uint32_t
1592 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1593 uint32_t prog_offset
)
1595 if (brw
->gen
>= 5) {
1596 /* Using state base address. */
1600 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1604 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1606 return brw
->cache
.bo
->offset64
+ prog_offset
;
1609 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1611 extern const char * const conditional_modifier
[16];
1612 extern const char *const pred_ctrl_align16
[16];
1615 brw_depth_writes_enabled(const struct brw_context
*brw
)
1617 const struct gl_context
*ctx
= &brw
->ctx
;
1619 /* We consider depth writes disabled if the depth function is GL_EQUAL,
1620 * because it would just overwrite the existing depth value with itself.
1622 * These bonus depth writes not only use bandwidth, but they also can
1623 * prevent early depth processing. For example, if the pixel shader
1624 * discards, the hardware must invoke the to determine whether or not
1625 * to do the depth write. If writes are disabled, we may still be able
1626 * to do the depth test before the shader, and skip the shader execution.
1628 * The Broadwell 3DSTATE_WM_DEPTH_STENCIL documentation also contains
1629 * a programming note saying to disable depth writes for EQUAL.
1631 return ctx
->Depth
.Test
&& ctx
->Depth
.Mask
&& ctx
->Depth
.Func
!= GL_EQUAL
;
1635 brw_emit_depthbuffer(struct brw_context
*brw
);
1638 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1639 struct intel_mipmap_tree
*depth_mt
,
1640 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1641 uint32_t depth_surface_type
,
1642 struct intel_mipmap_tree
*stencil_mt
,
1643 bool hiz
, bool separate_stencil
,
1644 uint32_t width
, uint32_t height
,
1645 uint32_t tile_x
, uint32_t tile_y
);
1648 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1649 struct intel_mipmap_tree
*depth_mt
,
1650 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1651 uint32_t depth_surface_type
,
1652 struct intel_mipmap_tree
*stencil_mt
,
1653 bool hiz
, bool separate_stencil
,
1654 uint32_t width
, uint32_t height
,
1655 uint32_t tile_x
, uint32_t tile_y
);
1658 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1659 struct intel_mipmap_tree
*depth_mt
,
1660 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1661 uint32_t depth_surface_type
,
1662 struct intel_mipmap_tree
*stencil_mt
,
1663 bool hiz
, bool separate_stencil
,
1664 uint32_t width
, uint32_t height
,
1665 uint32_t tile_x
, uint32_t tile_y
);
1667 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1668 struct intel_mipmap_tree
*depth_mt
,
1669 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1670 uint32_t depth_surface_type
,
1671 struct intel_mipmap_tree
*stencil_mt
,
1672 bool hiz
, bool separate_stencil
,
1673 uint32_t width
, uint32_t height
,
1674 uint32_t tile_x
, uint32_t tile_y
);
1676 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1677 unsigned int level
, unsigned int layer
, enum blorp_hiz_op op
);
1679 uint32_t get_hw_prim_for_gl_prim(int mode
);
1682 gen6_upload_push_constants(struct brw_context
*brw
,
1683 const struct gl_program
*prog
,
1684 const struct brw_stage_prog_data
*prog_data
,
1685 struct brw_stage_state
*stage_state
,
1686 enum aub_state_struct_type type
);
1689 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
1690 const struct intel_mipmap_tree
*mt
);
1692 /* brw_pipe_control.c */
1693 int brw_init_pipe_control(struct brw_context
*brw
,
1694 const struct gen_device_info
*info
);
1695 void brw_fini_pipe_control(struct brw_context
*brw
);
1697 void brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
);
1698 void brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
1699 drm_intel_bo
*bo
, uint32_t offset
,
1700 uint32_t imm_lower
, uint32_t imm_upper
);
1701 void brw_emit_mi_flush(struct brw_context
*brw
);
1702 void brw_emit_post_sync_nonzero_flush(struct brw_context
*brw
);
1703 void brw_emit_depth_stall_flushes(struct brw_context
*brw
);
1704 void gen7_emit_vs_workaround_flush(struct brw_context
*brw
);
1705 void gen7_emit_cs_stall_flush(struct brw_context
*brw
);
1707 /* brw_queryformat.c */
1708 void brw_query_internal_format(struct gl_context
*ctx
, GLenum target
,
1709 GLenum internalFormat
, GLenum pname
,