i965: Make upload_sampler_state_table a virtual function.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_context.h
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
35
36 #include "intel_context.h"
37 #include "brw_structs.h"
38 #include "main/imports.h"
39 #include "main/macros.h"
40
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44
45 /* Glossary:
46 *
47 * URB - uniform resource buffer. A mid-sized buffer which is
48 * partitioned between the fixed function units and used for passing
49 * values (vertices, primitives, constants) between them.
50 *
51 * CURBE - constant URB entry. An urb region (entry) used to hold
52 * constant values which the fixed function units can be instructed to
53 * preload into the GRF when spawning a thread.
54 *
55 * VUE - vertex URB entry. An urb entry holding a vertex and usually
56 * a vertex header. The header contains control information and
57 * things like primitive type, Begin/end flags and clip codes.
58 *
59 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
60 * unit holding rasterization and interpolation parameters.
61 *
62 * GRF - general register file. One of several register files
63 * addressable by programmed threads. The inputs (r0, payload, curbe,
64 * urb) of the thread are preloaded to this area before the thread is
65 * spawned. The registers are individually 8 dwords wide and suitable
66 * for general usage. Registers holding thread input values are not
67 * special and may be overwritten.
68 *
69 * MRF - message register file. Threads communicate (and terminate)
70 * by sending messages. Message parameters are placed in contiguous
71 * MRF registers. All program output is via these messages. URB
72 * entries are populated by sending a message to the shared URB
73 * function containing the new data, together with a control word,
74 * often an unmodified copy of R0.
75 *
76 * R0 - GRF register 0. Typically holds control information used when
77 * sending messages to other threads.
78 *
79 * EU or GEN4 EU: The name of the programmable subsystem of the
80 * i965 hardware. Threads are executed by the EU, the registers
81 * described above are part of the EU architecture.
82 *
83 * Fixed function units:
84 *
85 * CS - Command streamer. Notional first unit, little software
86 * interaction. Holds the URB entries used for constant data, ie the
87 * CURBEs.
88 *
89 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
90 * this unit is responsible for pulling vertices out of vertex buffers
91 * in vram and injecting them into the processing pipe as VUEs. If
92 * enabled, it first passes them to a VS thread which is a good place
93 * for the driver to implement any active vertex shader.
94 *
95 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
96 * enabled, incoming strips etc are passed to GS threads in individual
97 * line/triangle/point units. The GS thread may perform arbitary
98 * computation and emit whatever primtives with whatever vertices it
99 * chooses. This makes GS an excellent place to implement GL's
100 * unfilled polygon modes, though of course it is capable of much
101 * more. Additionally, GS is used to translate away primitives not
102 * handled by latter units, including Quads and Lineloops.
103 *
104 * CS - Clipper. Mesa's clipping algorithms are imported to run on
105 * this unit. The fixed function part performs cliptesting against
106 * the 6 fixed clipplanes and makes descisions on whether or not the
107 * incoming primitive needs to be passed to a thread for clipping.
108 * User clip planes are handled via cooperation with the VS thread.
109 *
110 * SF - Strips Fans or Setup: Triangles are prepared for
111 * rasterization. Interpolation coefficients are calculated.
112 * Flatshading and two-side lighting usually performed here.
113 *
114 * WM - Windower. Interpolation of vertex attributes performed here.
115 * Fragment shader implemented here. SIMD aspects of EU taken full
116 * advantage of, as pixels are processed in blocks of 16.
117 *
118 * CC - Color Calculator. No EU threads associated with this unit.
119 * Handles blending and (presumably) depth and stencil testing.
120 */
121
122
123 #define BRW_MAX_CURBE (32*16)
124
125 struct brw_context;
126 struct brw_instruction;
127 struct brw_vs_prog_key;
128 struct brw_wm_prog_key;
129 struct brw_wm_prog_data;
130
131 enum brw_state_id {
132 BRW_STATE_URB_FENCE,
133 BRW_STATE_FRAGMENT_PROGRAM,
134 BRW_STATE_VERTEX_PROGRAM,
135 BRW_STATE_CURBE_OFFSETS,
136 BRW_STATE_REDUCED_PRIMITIVE,
137 BRW_STATE_PRIMITIVE,
138 BRW_STATE_CONTEXT,
139 BRW_STATE_PSP,
140 BRW_STATE_SURFACES,
141 BRW_STATE_VS_BINDING_TABLE,
142 BRW_STATE_GS_BINDING_TABLE,
143 BRW_STATE_PS_BINDING_TABLE,
144 BRW_STATE_INDICES,
145 BRW_STATE_VERTICES,
146 BRW_STATE_BATCH,
147 BRW_STATE_INDEX_BUFFER,
148 BRW_STATE_VS_CONSTBUF,
149 BRW_STATE_PROGRAM_CACHE,
150 BRW_STATE_STATE_BASE_ADDRESS,
151 BRW_STATE_VUE_MAP_GEOM_OUT,
152 BRW_STATE_TRANSFORM_FEEDBACK,
153 BRW_STATE_RASTERIZER_DISCARD,
154 BRW_STATE_STATS_WM,
155 BRW_STATE_UNIFORM_BUFFER,
156 BRW_STATE_META_IN_PROGRESS,
157 BRW_STATE_INTERPOLATION_MAP,
158 BRW_NUM_STATE_BITS
159 };
160
161 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
162 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
163 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
164 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
165 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
166 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
167 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
168 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
169 #define BRW_NEW_SURFACES (1 << BRW_STATE_SURFACES)
170 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
171 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
172 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
173 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
174 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
175 /**
176 * Used for any batch entry with a relocated pointer that will be used
177 * by any 3D rendering.
178 */
179 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
180 /** \see brw.state.depth_region */
181 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
182 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
183 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
184 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
185 #define BRW_NEW_VUE_MAP_GEOM_OUT (1 << BRW_STATE_VUE_MAP_GEOM_OUT)
186 #define BRW_NEW_TRANSFORM_FEEDBACK (1 << BRW_STATE_TRANSFORM_FEEDBACK)
187 #define BRW_NEW_RASTERIZER_DISCARD (1 << BRW_STATE_RASTERIZER_DISCARD)
188 #define BRW_NEW_STATS_WM (1 << BRW_STATE_STATS_WM)
189 #define BRW_NEW_UNIFORM_BUFFER (1 << BRW_STATE_UNIFORM_BUFFER)
190 #define BRW_NEW_META_IN_PROGRESS (1 << BRW_STATE_META_IN_PROGRESS)
191 #define BRW_NEW_INTERPOLATION_MAP (1 << BRW_STATE_INTERPOLATION_MAP)
192
193 struct brw_state_flags {
194 /** State update flags signalled by mesa internals */
195 GLuint mesa;
196 /**
197 * State update flags signalled as the result of brw_tracked_state updates
198 */
199 GLuint brw;
200 /** State update flags signalled by brw_state_cache.c searches */
201 GLuint cache;
202 };
203
204 #define AUB_TRACE_TYPE_MASK 0x0000ff00
205 #define AUB_TRACE_TYPE_NOTYPE (0 << 8)
206 #define AUB_TRACE_TYPE_BATCH (1 << 8)
207 #define AUB_TRACE_TYPE_VERTEX_BUFFER (5 << 8)
208 #define AUB_TRACE_TYPE_2D_MAP (6 << 8)
209 #define AUB_TRACE_TYPE_CUBE_MAP (7 << 8)
210 #define AUB_TRACE_TYPE_VOLUME_MAP (9 << 8)
211 #define AUB_TRACE_TYPE_1D_MAP (10 << 8)
212 #define AUB_TRACE_TYPE_CONSTANT_BUFFER (11 << 8)
213 #define AUB_TRACE_TYPE_CONSTANT_URB (12 << 8)
214 #define AUB_TRACE_TYPE_INDEX_BUFFER (13 << 8)
215 #define AUB_TRACE_TYPE_GENERAL (14 << 8)
216 #define AUB_TRACE_TYPE_SURFACE (15 << 8)
217
218 /**
219 * state_struct_type enum values are encoded with the top 16 bits representing
220 * the type to be delivered to the .aub file, and the bottom 16 bits
221 * representing the subtype. This macro performs the encoding.
222 */
223 #define ENCODE_SS_TYPE(type, subtype) (((type) << 16) | (subtype))
224
225 enum state_struct_type {
226 AUB_TRACE_VS_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 1),
227 AUB_TRACE_GS_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 2),
228 AUB_TRACE_CLIP_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 3),
229 AUB_TRACE_SF_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 4),
230 AUB_TRACE_WM_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 5),
231 AUB_TRACE_CC_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 6),
232 AUB_TRACE_CLIP_VP_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 7),
233 AUB_TRACE_SF_VP_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 8),
234 AUB_TRACE_CC_VP_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0x9),
235 AUB_TRACE_SAMPLER_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0xa),
236 AUB_TRACE_KERNEL_INSTRUCTIONS = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0xb),
237 AUB_TRACE_SCRATCH_SPACE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0xc),
238 AUB_TRACE_SAMPLER_DEFAULT_COLOR = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0xd),
239
240 AUB_TRACE_SCISSOR_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0x15),
241 AUB_TRACE_BLEND_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0x16),
242 AUB_TRACE_DEPTH_STENCIL_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0x17),
243
244 AUB_TRACE_VERTEX_BUFFER = ENCODE_SS_TYPE(AUB_TRACE_TYPE_VERTEX_BUFFER, 0),
245 AUB_TRACE_BINDING_TABLE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE, 0x100),
246 AUB_TRACE_SURFACE_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE, 0x200),
247 AUB_TRACE_VS_CONSTANTS = ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER, 0),
248 AUB_TRACE_WM_CONSTANTS = ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER, 1),
249 };
250
251 /**
252 * Decode a state_struct_type value to determine the type that should be
253 * stored in the .aub file.
254 */
255 static inline uint32_t AUB_TRACE_TYPE(enum state_struct_type ss_type)
256 {
257 return (ss_type & 0xFFFF0000) >> 16;
258 }
259
260 /**
261 * Decode a state_struct_type value to determine the subtype that should be
262 * stored in the .aub file.
263 */
264 static inline uint32_t AUB_TRACE_SUBTYPE(enum state_struct_type ss_type)
265 {
266 return ss_type & 0xFFFF;
267 }
268
269 /** Subclass of Mesa vertex program */
270 struct brw_vertex_program {
271 struct gl_vertex_program program;
272 GLuint id;
273 };
274
275
276 /** Subclass of Mesa fragment program */
277 struct brw_fragment_program {
278 struct gl_fragment_program program;
279 GLuint id; /**< serial no. to identify frag progs, never re-used */
280 };
281
282 struct brw_shader {
283 struct gl_shader base;
284
285 bool compiled_once;
286
287 /** Shader IR transformed for native compile, at link time. */
288 struct exec_list *ir;
289 };
290
291 /* Data about a particular attempt to compile a program. Note that
292 * there can be many of these, each in a different GL state
293 * corresponding to a different brw_wm_prog_key struct, with different
294 * compiled programs.
295 *
296 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
297 * struct!
298 */
299 struct brw_wm_prog_data {
300 GLuint curb_read_length;
301 GLuint urb_read_length;
302
303 GLuint first_curbe_grf;
304 GLuint first_curbe_grf_16;
305 GLuint reg_blocks;
306 GLuint reg_blocks_16;
307 GLuint total_scratch;
308
309 GLuint nr_params; /**< number of float params/constants */
310 GLuint nr_pull_params;
311 bool dual_src_blend;
312 int dispatch_width;
313 uint32_t prog_offset_16;
314
315 /**
316 * Mask of which interpolation modes are required by the fragment shader.
317 * Used in hardware setup on gen6+.
318 */
319 uint32_t barycentric_interp_modes;
320
321 /* Pointers to tracked values (only valid once
322 * _mesa_load_state_parameters has been called at runtime).
323 *
324 * These must be the last fields of the struct (see
325 * brw_wm_prog_data_compare()).
326 */
327 const float **param;
328 const float **pull_param;
329 };
330
331 /**
332 * Enum representing the i965-specific vertex results that don't correspond
333 * exactly to any element of gl_varying_slot. The values of this enum are
334 * assigned such that they don't conflict with gl_varying_slot.
335 */
336 typedef enum
337 {
338 BRW_VARYING_SLOT_NDC = VARYING_SLOT_MAX,
339 BRW_VARYING_SLOT_PAD,
340 /**
341 * Technically this is not a varying but just a placeholder that
342 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
343 * builtin variable to be compiled correctly. see compile_sf_prog() for
344 * more info.
345 */
346 BRW_VARYING_SLOT_PNTC,
347 BRW_VARYING_SLOT_COUNT
348 } brw_varying_slot;
349
350
351 /**
352 * Data structure recording the relationship between the gl_varying_slot enum
353 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
354 * single octaword within the VUE (128 bits).
355 *
356 * Note that each BRW register contains 256 bits (2 octawords), so when
357 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
358 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
359 * in a vertex shader), each register corresponds to a single VUE slot, since
360 * it contains data for two separate vertices.
361 */
362 struct brw_vue_map {
363 /**
364 * Bitfield representing all varying slots that are (a) stored in this VUE
365 * map, and (b) actually written by the shader. Does not include any of
366 * the additional varying slots defined in brw_varying_slot.
367 */
368 GLbitfield64 slots_valid;
369
370 /**
371 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
372 * not stored in a slot (because they are not written, or because
373 * additional processing is applied before storing them in the VUE), the
374 * value is -1.
375 */
376 signed char varying_to_slot[BRW_VARYING_SLOT_COUNT];
377
378 /**
379 * Map from VUE slot to gl_varying_slot value. For slots that do not
380 * directly correspond to a gl_varying_slot, the value comes from
381 * brw_varying_slot.
382 *
383 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
384 * simplifies code that uses the value stored in slot_to_varying to
385 * create a bit mask).
386 */
387 signed char slot_to_varying[BRW_VARYING_SLOT_COUNT];
388
389 /**
390 * Total number of VUE slots in use
391 */
392 int num_slots;
393 };
394
395 /**
396 * Convert a VUE slot number into a byte offset within the VUE.
397 */
398 static inline GLuint brw_vue_slot_to_offset(GLuint slot)
399 {
400 return 16*slot;
401 }
402
403 /**
404 * Convert a vertex output (brw_varying_slot) into a byte offset within the
405 * VUE.
406 */
407 static inline GLuint brw_varying_to_offset(struct brw_vue_map *vue_map,
408 GLuint varying)
409 {
410 return brw_vue_slot_to_offset(vue_map->varying_to_slot[varying]);
411 }
412
413 void brw_compute_vue_map(struct brw_context *brw, struct brw_vue_map *vue_map,
414 GLbitfield64 slots_valid, bool userclip_active);
415
416
417 /*
418 * Mapping of VUE map slots to interpolation modes.
419 */
420 struct interpolation_mode_map {
421 unsigned char mode[BRW_VARYING_SLOT_COUNT];
422 };
423
424 static inline bool brw_any_flat_varyings(struct interpolation_mode_map *map)
425 {
426 for (int i = 0; i < BRW_VARYING_SLOT_COUNT; i++)
427 if (map->mode[i] == INTERP_QUALIFIER_FLAT)
428 return true;
429
430 return false;
431 }
432
433 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map *map)
434 {
435 for (int i = 0; i < BRW_VARYING_SLOT_COUNT; i++)
436 if (map->mode[i] == INTERP_QUALIFIER_NOPERSPECTIVE)
437 return true;
438
439 return false;
440 }
441
442
443 struct brw_sf_prog_data {
444 GLuint urb_read_length;
445 GLuint total_grf;
446
447 /* Each vertex may have upto 12 attributes, 4 components each,
448 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
449 * rows.
450 *
451 * Actually we use 4 for each, so call it 12 rows.
452 */
453 GLuint urb_entry_size;
454 };
455
456 struct brw_clip_prog_data {
457 GLuint curb_read_length; /* user planes? */
458 GLuint clip_mode;
459 GLuint urb_read_length;
460 GLuint total_grf;
461 };
462
463 struct brw_gs_prog_data {
464 GLuint urb_read_length;
465 GLuint total_grf;
466
467 /**
468 * Gen6 transform feedback: Amount by which the streaming vertex buffer
469 * indices should be incremented each time the GS is invoked.
470 */
471 unsigned svbi_postincrement_value;
472 };
473
474
475 /* Note: brw_vec4_prog_data_compare() must be updated when adding fields to
476 * this struct!
477 */
478 struct brw_vec4_prog_data {
479 struct brw_vue_map vue_map;
480
481 GLuint curb_read_length;
482 GLuint urb_read_length;
483 GLuint total_grf;
484 GLuint nr_params; /**< number of float params/constants */
485 GLuint nr_pull_params; /**< number of dwords referenced by pull_param[] */
486 GLuint total_scratch;
487
488 /* Used for calculating urb partitions. In the VS, this is the size of the
489 * URB entry used for both input and output to the thread. In the GS, this
490 * is the size of the URB entry used for output.
491 */
492 GLuint urb_entry_size;
493
494 int num_surfaces;
495
496 /* These pointers must appear last. See brw_vec4_prog_data_compare(). */
497 const float **param;
498 const float **pull_param;
499 };
500
501
502 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
503 * struct!
504 */
505 struct brw_vs_prog_data {
506 struct brw_vec4_prog_data base;
507
508 GLbitfield64 inputs_read;
509
510 bool uses_vertexid;
511 };
512
513 /** Number of texture sampler units */
514 #define BRW_MAX_TEX_UNIT 16
515
516 /** Max number of render targets in a shader */
517 #define BRW_MAX_DRAW_BUFFERS 8
518
519 /**
520 * Max number of binding table entries used for stream output.
521 *
522 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
523 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
524 *
525 * On Gen6, the size of transform feedback data is limited not by the number
526 * of components but by the number of binding table entries we set aside. We
527 * use one binding table entry for a float, one entry for a vector, and one
528 * entry per matrix column. Since the only way we can communicate our
529 * transform feedback capabilities to the client is via
530 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
531 * worst case, in which all the varyings are floats, so we use up one binding
532 * table entry per component. Therefore we need to set aside at least 64
533 * binding table entries for use by transform feedback.
534 *
535 * Note: since we don't currently pack varyings, it is currently impossible
536 * for the client to actually use up all of these binding table entries--if
537 * all of their varyings were floats, they would run out of varying slots and
538 * fail to link. But that's a bug, so it seems prudent to go ahead and
539 * allocate the number of binding table entries we will need once the bug is
540 * fixed.
541 */
542 #define BRW_MAX_SOL_BINDINGS 64
543
544 /** Maximum number of actual buffers used for stream output */
545 #define BRW_MAX_SOL_BUFFERS 4
546
547 #define BRW_MAX_WM_UBOS 12
548 #define BRW_MAX_VS_UBOS 12
549
550 /**
551 * Helpers to create Surface Binding Table indexes for draw buffers,
552 * textures, and constant buffers.
553 *
554 * Shader threads access surfaces via numeric handles, rather than directly
555 * using pointers. The binding table maps these numeric handles to the
556 * address of the actual buffer.
557 *
558 * For example, a shader might ask to sample from "surface 7." In this case,
559 * bind[7] would contain a pointer to a texture.
560 *
561 * Currently, our WM binding tables are (arbitrarily) programmed as follows:
562 *
563 * +-------------------------------+
564 * | 0 | Draw buffer 0 |
565 * | . | . |
566 * | : | : |
567 * | 7 | Draw buffer 7 |
568 * |-----|-------------------------|
569 * | 8 | WM Pull Constant Buffer |
570 * |-----|-------------------------|
571 * | 9 | Texture 0 |
572 * | . | . |
573 * | : | : |
574 * | 24 | Texture 15 |
575 * |-----|-------------------------|
576 * | 25 | UBO 0 |
577 * | . | . |
578 * | : | : |
579 * | 36 | UBO 11 |
580 * +-------------------------------+
581 *
582 * Our VS binding tables are programmed as follows:
583 *
584 * +-----+-------------------------+
585 * | 0 | VS Pull Constant Buffer |
586 * +-----+-------------------------+
587 * | 1 | Texture 0 |
588 * | . | . |
589 * | : | : |
590 * | 16 | Texture 15 |
591 * +-----+-------------------------+
592 * | 17 | UBO 0 |
593 * | . | . |
594 * | : | : |
595 * | 28 | UBO 11 |
596 * +-------------------------------+
597 *
598 * Our (gen6) GS binding tables are programmed as follows:
599 *
600 * +-----+-------------------------+
601 * | 0 | SOL Binding 0 |
602 * | . | . |
603 * | : | : |
604 * | 63 | SOL Binding 63 |
605 * +-----+-------------------------+
606 *
607 * Note that nothing actually uses the SURF_INDEX_DRAW macro, so it has to be
608 * the identity function or things will break. We do want to keep draw buffers
609 * first so we can use headerless render target writes for RT 0.
610 */
611 #define SURF_INDEX_DRAW(d) (d)
612 #define SURF_INDEX_FRAG_CONST_BUFFER (BRW_MAX_DRAW_BUFFERS + 1)
613 #define SURF_INDEX_TEXTURE(t) (BRW_MAX_DRAW_BUFFERS + 2 + (t))
614 #define SURF_INDEX_WM_UBO(u) (SURF_INDEX_TEXTURE(BRW_MAX_TEX_UNIT) + u)
615 #define SURF_INDEX_WM_SHADER_TIME (SURF_INDEX_WM_UBO(12))
616 /** Maximum size of the binding table. */
617 #define BRW_MAX_WM_SURFACES (SURF_INDEX_WM_SHADER_TIME + 1)
618
619 #define SURF_INDEX_VERT_CONST_BUFFER (0)
620 #define SURF_INDEX_VS_TEXTURE(t) (SURF_INDEX_VERT_CONST_BUFFER + 1 + (t))
621 #define SURF_INDEX_VS_UBO(u) (SURF_INDEX_VS_TEXTURE(BRW_MAX_TEX_UNIT) + u)
622 #define SURF_INDEX_VS_SHADER_TIME (SURF_INDEX_VS_UBO(12))
623 #define BRW_MAX_VS_SURFACES (SURF_INDEX_VS_SHADER_TIME + 1)
624
625 #define SURF_INDEX_SOL_BINDING(t) ((t))
626 #define BRW_MAX_GS_SURFACES SURF_INDEX_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
627
628 /**
629 * Stride in bytes between shader_time entries.
630 *
631 * We separate entries by a cacheline to reduce traffic between EUs writing to
632 * different entries.
633 */
634 #define SHADER_TIME_STRIDE 64
635
636 enum brw_cache_id {
637 BRW_CC_VP,
638 BRW_CC_UNIT,
639 BRW_WM_PROG,
640 BRW_BLORP_BLIT_PROG,
641 BRW_BLORP_CONST_COLOR_PROG,
642 BRW_SAMPLER,
643 BRW_WM_UNIT,
644 BRW_SF_PROG,
645 BRW_SF_VP,
646 BRW_SF_UNIT, /* scissor state on gen6 */
647 BRW_VS_UNIT,
648 BRW_VS_PROG,
649 BRW_GS_UNIT,
650 BRW_GS_PROG,
651 BRW_CLIP_VP,
652 BRW_CLIP_UNIT,
653 BRW_CLIP_PROG,
654
655 BRW_MAX_CACHE
656 };
657
658 struct brw_cache_item {
659 /**
660 * Effectively part of the key, cache_id identifies what kind of state
661 * buffer is involved, and also which brw->state.dirty.cache flag should
662 * be set when this cache item is chosen.
663 */
664 enum brw_cache_id cache_id;
665 /** 32-bit hash of the key data */
666 GLuint hash;
667 GLuint key_size; /* for variable-sized keys */
668 GLuint aux_size;
669 const void *key;
670
671 uint32_t offset;
672 uint32_t size;
673
674 struct brw_cache_item *next;
675 };
676
677
678 typedef bool (*cache_aux_compare_func)(const void *a, const void *b,
679 int aux_size, const void *key);
680 typedef void (*cache_aux_free_func)(const void *aux);
681
682 struct brw_cache {
683 struct brw_context *brw;
684
685 struct brw_cache_item **items;
686 drm_intel_bo *bo;
687 GLuint size, n_items;
688
689 uint32_t next_offset;
690 bool bo_used_by_gpu;
691
692 /**
693 * Optional functions used in determining whether the prog_data for a new
694 * cache item matches an existing cache item (in case there's relevant data
695 * outside of the prog_data). If NULL, a plain memcmp is done.
696 */
697 cache_aux_compare_func aux_compare[BRW_MAX_CACHE];
698 /** Optional functions for freeing other pointers attached to a prog_data. */
699 cache_aux_free_func aux_free[BRW_MAX_CACHE];
700 };
701
702
703 /* Considered adding a member to this struct to document which flags
704 * an update might raise so that ordering of the state atoms can be
705 * checked or derived at runtime. Dropped the idea in favor of having
706 * a debug mode where the state is monitored for flags which are
707 * raised that have already been tested against.
708 */
709 struct brw_tracked_state {
710 struct brw_state_flags dirty;
711 void (*emit)( struct brw_context *brw );
712 };
713
714 enum shader_time_shader_type {
715 ST_NONE,
716 ST_VS,
717 ST_VS_WRITTEN,
718 ST_VS_RESET,
719 ST_FS8,
720 ST_FS8_WRITTEN,
721 ST_FS8_RESET,
722 ST_FS16,
723 ST_FS16_WRITTEN,
724 ST_FS16_RESET,
725 };
726
727 /* Flags for brw->state.cache.
728 */
729 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
730 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
731 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
732 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
733 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
734 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
735 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
736 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
737 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
738 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
739 #define CACHE_NEW_GS_UNIT (1<<BRW_GS_UNIT)
740 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
741 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
742 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
743 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
744
745 struct brw_cached_batch_item {
746 struct header *header;
747 GLuint sz;
748 struct brw_cached_batch_item *next;
749 };
750
751
752
753 /* Protect against a future where VERT_ATTRIB_MAX > 32. Wouldn't life
754 * be easier if C allowed arrays of packed elements?
755 */
756 #define ATTRIB_BIT_DWORDS ((VERT_ATTRIB_MAX+31)/32)
757
758 struct brw_vertex_buffer {
759 /** Buffer object containing the uploaded vertex data */
760 drm_intel_bo *bo;
761 uint32_t offset;
762 /** Byte stride between elements in the uploaded array */
763 GLuint stride;
764 GLuint step_rate;
765 };
766 struct brw_vertex_element {
767 const struct gl_client_array *glarray;
768
769 int buffer;
770
771 /** The corresponding Mesa vertex attribute */
772 gl_vert_attrib attrib;
773 /** Offset of the first element within the buffer object */
774 unsigned int offset;
775 };
776
777 struct brw_query_object {
778 struct gl_query_object Base;
779
780 /** Last query BO associated with this query. */
781 drm_intel_bo *bo;
782
783 /** Last index in bo with query data for this object. */
784 int last_index;
785 };
786
787
788 /**
789 * brw_context is derived from gl_context.
790 */
791 struct brw_context
792 {
793 struct gl_context ctx; /**< base class, must be first field */
794
795 struct
796 {
797 void (*destroy) (struct brw_context * brw);
798 void (*finish_batch) (struct brw_context * brw);
799 void (*new_batch) (struct brw_context * brw);
800
801 void (*update_texture_surface)(struct gl_context *ctx,
802 unsigned unit,
803 uint32_t *binding_table,
804 unsigned surf_index);
805 void (*update_renderbuffer_surface)(struct brw_context *brw,
806 struct gl_renderbuffer *rb,
807 bool layered,
808 unsigned unit);
809 void (*update_null_renderbuffer_surface)(struct brw_context *brw,
810 unsigned unit);
811 void (*create_constant_surface)(struct brw_context *brw,
812 drm_intel_bo *bo,
813 uint32_t offset,
814 uint32_t size,
815 uint32_t *out_offset,
816 bool dword_pitch);
817
818 /** Upload a SAMPLER_STATE table. */
819 void (*upload_sampler_state_table)(struct brw_context *brw,
820 uint32_t *sampler_count,
821 uint32_t *sst_offset,
822 uint32_t *sdc_offset);
823
824 /**
825 * Send the appropriate state packets to configure depth, stencil, and
826 * HiZ buffers (i965+ only)
827 */
828 void (*emit_depth_stencil_hiz)(struct brw_context *brw,
829 struct intel_mipmap_tree *depth_mt,
830 uint32_t depth_offset,
831 uint32_t depthbuffer_format,
832 uint32_t depth_surface_type,
833 struct intel_mipmap_tree *stencil_mt,
834 bool hiz, bool separate_stencil,
835 uint32_t width, uint32_t height,
836 uint32_t tile_x, uint32_t tile_y);
837
838 } vtbl;
839
840 dri_bufmgr *bufmgr;
841
842 drm_intel_context *hw_ctx;
843
844 struct intel_batchbuffer batch;
845 bool no_batch_wrap;
846
847 struct {
848 drm_intel_bo *bo;
849 GLuint offset;
850 uint32_t buffer_len;
851 uint32_t buffer_offset;
852 char buffer[4096];
853 } upload;
854
855 /**
856 * Set if rendering has occured to the drawable's front buffer.
857 *
858 * This is used in the DRI2 case to detect that glFlush should also copy
859 * the contents of the fake front buffer to the real front buffer.
860 */
861 bool front_buffer_dirty;
862
863 /**
864 * Track whether front-buffer rendering is currently enabled
865 *
866 * A separate flag is used to track this in order to support MRT more
867 * easily.
868 */
869 bool is_front_buffer_rendering;
870
871 /**
872 * Track whether front-buffer is the current read target.
873 *
874 * This is closely associated with is_front_buffer_rendering, but may
875 * be set separately. The DRI2 fake front buffer must be referenced
876 * either way.
877 */
878 bool is_front_buffer_reading;
879
880 /** Framerate throttling: @{ */
881 drm_intel_bo *first_post_swapbuffers_batch;
882 bool need_throttle;
883 /** @} */
884
885 GLuint stats_wm;
886
887 /**
888 * drirc options:
889 * @{
890 */
891 bool no_rast;
892 bool always_flush_batch;
893 bool always_flush_cache;
894 bool disable_throttling;
895 bool precompile;
896
897 driOptionCache optionCache;
898 /** @} */
899
900 GLuint primitive; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
901
902 GLenum reduced_primitive;
903
904 /**
905 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
906 * variable is set, this is the flag indicating to do expensive work that
907 * might lead to a perf_debug() call.
908 */
909 bool perf_debug;
910
911 uint32_t max_gtt_map_object_size;
912
913 bool emit_state_always;
914
915 int gen;
916 int gt;
917
918 bool is_g4x;
919 bool is_baytrail;
920 bool is_haswell;
921
922 bool has_hiz;
923 bool has_separate_stencil;
924 bool must_use_separate_stencil;
925 bool has_llc;
926 bool has_swizzling;
927 bool has_surface_tile_offset;
928 bool has_compr4;
929 bool has_negative_rhw_bug;
930 bool has_aa_line_parameters;
931 bool has_pln;
932
933 /**
934 * Some versions of Gen hardware don't do centroid interpolation correctly
935 * on unlit pixels, causing incorrect values for derivatives near triangle
936 * edges. Enabling this flag causes the fragment shader to use
937 * non-centroid interpolation for unlit pixels, at the expense of two extra
938 * fragment shader instructions.
939 */
940 bool needs_unlit_centroid_workaround;
941
942 GLuint NewGLState;
943 struct {
944 struct brw_state_flags dirty;
945 } state;
946
947 struct brw_cache cache;
948 struct brw_cached_batch_item *cached_batch_items;
949
950 /* Whether a meta-operation is in progress. */
951 bool meta_in_progress;
952
953 struct {
954 struct brw_vertex_element inputs[VERT_ATTRIB_MAX];
955 struct brw_vertex_buffer buffers[VERT_ATTRIB_MAX];
956
957 struct brw_vertex_element *enabled[VERT_ATTRIB_MAX];
958 GLuint nr_enabled;
959 GLuint nr_buffers;
960
961 /* Summary of size and varying of active arrays, so we can check
962 * for changes to this state:
963 */
964 unsigned int min_index, max_index;
965
966 /* Offset from start of vertex buffer so we can avoid redefining
967 * the same VB packed over and over again.
968 */
969 unsigned int start_vertex_bias;
970 } vb;
971
972 struct {
973 /**
974 * Index buffer for this draw_prims call.
975 *
976 * Updates are signaled by BRW_NEW_INDICES.
977 */
978 const struct _mesa_index_buffer *ib;
979
980 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
981 drm_intel_bo *bo;
982 GLuint type;
983
984 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
985 * avoid re-uploading the IB packet over and over if we're actually
986 * referencing the same index buffer.
987 */
988 unsigned int start_vertex_offset;
989 } ib;
990
991 /* Active vertex program:
992 */
993 const struct gl_vertex_program *vertex_program;
994 const struct gl_fragment_program *fragment_program;
995
996 /* hw-dependent 3DSTATE_VF_STATISTICS opcode */
997 uint32_t CMD_VF_STATISTICS;
998 /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
999 uint32_t CMD_PIPELINE_SELECT;
1000
1001 /**
1002 * Platform specific constants containing the maximum number of threads
1003 * for each pipeline stage.
1004 */
1005 int max_vs_threads;
1006 int max_gs_threads;
1007 int max_wm_threads;
1008
1009 /* BRW_NEW_URB_ALLOCATIONS:
1010 */
1011 struct {
1012 GLuint vsize; /* vertex size plus header in urb registers */
1013 GLuint csize; /* constant buffer size in urb registers */
1014 GLuint sfsize; /* setup data size in urb registers */
1015
1016 bool constrained;
1017
1018 GLuint max_vs_entries; /* Maximum number of VS entries */
1019 GLuint max_gs_entries; /* Maximum number of GS entries */
1020
1021 GLuint nr_vs_entries;
1022 GLuint nr_gs_entries;
1023 GLuint nr_clip_entries;
1024 GLuint nr_sf_entries;
1025 GLuint nr_cs_entries;
1026
1027 GLuint vs_start;
1028 GLuint gs_start;
1029 GLuint clip_start;
1030 GLuint sf_start;
1031 GLuint cs_start;
1032 GLuint size; /* Hardware URB size, in KB. */
1033
1034 /* gen6: True if the most recently sent _3DSTATE_URB message allocated
1035 * URB space for the GS.
1036 */
1037 bool gen6_gs_previously_active;
1038 } urb;
1039
1040
1041 /* BRW_NEW_CURBE_OFFSETS:
1042 */
1043 struct {
1044 GLuint wm_start; /**< pos of first wm const in CURBE buffer */
1045 GLuint wm_size; /**< number of float[4] consts, multiple of 16 */
1046 GLuint clip_start;
1047 GLuint clip_size;
1048 GLuint vs_start;
1049 GLuint vs_size;
1050 GLuint total_size;
1051
1052 drm_intel_bo *curbe_bo;
1053 /** Offset within curbe_bo of space for current curbe entry */
1054 GLuint curbe_offset;
1055 /** Offset within curbe_bo of space for next curbe entry */
1056 GLuint curbe_next_offset;
1057
1058 /**
1059 * Copy of the last set of CURBEs uploaded. Frequently we'll end up
1060 * in brw_curbe.c with the same set of constant data to be uploaded,
1061 * so we'd rather not upload new constants in that case (it can cause
1062 * a pipeline bubble since only up to 4 can be pipelined at a time).
1063 */
1064 GLfloat *last_buf;
1065 /**
1066 * Allocation for where to calculate the next set of CURBEs.
1067 * It's a hot enough path that malloc/free of that data matters.
1068 */
1069 GLfloat *next_buf;
1070 GLuint last_bufsz;
1071 } curbe;
1072
1073 /**
1074 * Layout of vertex data exiting the geometry portion of the pipleine.
1075 * This comes from the geometry shader if one exists, otherwise from the
1076 * vertex shader.
1077 *
1078 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1079 */
1080 struct brw_vue_map vue_map_geom_out;
1081
1082 struct {
1083 struct brw_vs_prog_data *prog_data;
1084
1085 drm_intel_bo *scratch_bo;
1086 drm_intel_bo *const_bo;
1087 /** Offset in the program cache to the VS program */
1088 uint32_t prog_offset;
1089 uint32_t state_offset;
1090
1091 uint32_t push_const_offset; /* Offset in the batchbuffer */
1092 int push_const_size; /* in 256-bit register increments */
1093
1094 /** @{ register allocator */
1095
1096 struct ra_regs *regs;
1097
1098 /**
1099 * Array of the ra classes for the unaligned contiguous register
1100 * block sizes used.
1101 */
1102 int *classes;
1103
1104 /**
1105 * Mapping for register-allocated objects in *regs to the first
1106 * GRF for that object.
1107 */
1108 uint8_t *ra_reg_to_grf;
1109 /** @} */
1110
1111 uint32_t bind_bo_offset;
1112 uint32_t surf_offset[BRW_MAX_VS_SURFACES];
1113
1114 /** SAMPLER_STATE count and table offset */
1115 uint32_t sampler_count;
1116 uint32_t sampler_offset;
1117
1118 /** Offsets in the batch to sampler default colors (texture border color)
1119 */
1120 uint32_t sdc_offset[BRW_MAX_TEX_UNIT];
1121 } vs;
1122
1123 struct {
1124 struct brw_gs_prog_data *prog_data;
1125
1126 bool prog_active;
1127 /** Offset in the program cache to the CLIP program pre-gen6 */
1128 uint32_t prog_offset;
1129 uint32_t state_offset;
1130
1131 uint32_t bind_bo_offset;
1132 uint32_t surf_offset[BRW_MAX_GS_SURFACES];
1133 } gs;
1134
1135 struct {
1136 struct brw_clip_prog_data *prog_data;
1137
1138 /** Offset in the program cache to the CLIP program pre-gen6 */
1139 uint32_t prog_offset;
1140
1141 /* Offset in the batch to the CLIP state on pre-gen6. */
1142 uint32_t state_offset;
1143
1144 /* As of gen6, this is the offset in the batch to the CLIP VP,
1145 * instead of vp_bo.
1146 */
1147 uint32_t vp_offset;
1148 } clip;
1149
1150
1151 struct {
1152 struct brw_sf_prog_data *prog_data;
1153
1154 /** Offset in the program cache to the CLIP program pre-gen6 */
1155 uint32_t prog_offset;
1156 uint32_t state_offset;
1157 uint32_t vp_offset;
1158 } sf;
1159
1160 struct {
1161 struct brw_wm_prog_data *prog_data;
1162
1163 GLuint render_surf;
1164
1165 drm_intel_bo *scratch_bo;
1166
1167 /**
1168 * Buffer object used in place of multisampled null render targets on
1169 * Gen6. See brw_update_null_renderbuffer_surface().
1170 */
1171 drm_intel_bo *multisampled_null_render_target_bo;
1172
1173 /** Offset in the program cache to the WM program */
1174 uint32_t prog_offset;
1175
1176 uint32_t state_offset; /* offset in batchbuffer to pre-gen6 WM state */
1177
1178 drm_intel_bo *const_bo; /* pull constant buffer. */
1179 /**
1180 * This is offset in the batch to the push constants on gen6.
1181 *
1182 * Pre-gen6, push constants live in the CURBE.
1183 */
1184 uint32_t push_const_offset;
1185
1186 /** Binding table of pointers to surf_bo entries */
1187 uint32_t bind_bo_offset;
1188 uint32_t surf_offset[BRW_MAX_WM_SURFACES];
1189
1190 /** SAMPLER_STATE count and table offset */
1191 uint32_t sampler_count;
1192 uint32_t sampler_offset;
1193
1194 /** Offsets in the batch to sampler default colors (texture border color)
1195 */
1196 uint32_t sdc_offset[BRW_MAX_TEX_UNIT];
1197
1198 struct {
1199 struct ra_regs *regs;
1200
1201 /** Array of the ra classes for the unaligned contiguous
1202 * register block sizes used.
1203 */
1204 int *classes;
1205
1206 /**
1207 * Mapping for register-allocated objects in *regs to the first
1208 * GRF for that object.
1209 */
1210 uint8_t *ra_reg_to_grf;
1211
1212 /**
1213 * ra class for the aligned pairs we use for PLN, which doesn't
1214 * appear in *classes.
1215 */
1216 int aligned_pairs_class;
1217 } reg_sets[2];
1218 } wm;
1219
1220
1221 struct {
1222 uint32_t state_offset;
1223 uint32_t blend_state_offset;
1224 uint32_t depth_stencil_state_offset;
1225 uint32_t vp_offset;
1226 } cc;
1227
1228 struct {
1229 struct brw_query_object *obj;
1230 bool begin_emitted;
1231 } query;
1232
1233 int num_atoms;
1234 const struct brw_tracked_state **atoms;
1235
1236 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1237 struct {
1238 uint32_t offset;
1239 uint32_t size;
1240 enum state_struct_type type;
1241 } *state_batch_list;
1242 int state_batch_count;
1243
1244 uint32_t render_target_format[MESA_FORMAT_COUNT];
1245 bool format_supported_as_render_target[MESA_FORMAT_COUNT];
1246
1247 /* Interpolation modes, one byte per vue slot.
1248 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1249 */
1250 struct interpolation_mode_map interpolation_mode;
1251
1252 /* PrimitiveRestart */
1253 struct {
1254 bool in_progress;
1255 bool enable_cut_index;
1256 } prim_restart;
1257
1258 /** Computed depth/stencil/hiz state from the current attached
1259 * renderbuffers, valid only during the drawing state upload loop after
1260 * brw_workaround_depthstencil_alignment().
1261 */
1262 struct {
1263 struct intel_mipmap_tree *depth_mt;
1264 struct intel_mipmap_tree *stencil_mt;
1265
1266 /* Inter-tile (page-aligned) byte offsets. */
1267 uint32_t depth_offset, hiz_offset, stencil_offset;
1268 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1269 uint32_t tile_x, tile_y;
1270 } depthstencil;
1271
1272 uint32_t num_instances;
1273 int basevertex;
1274
1275 struct {
1276 drm_intel_bo *bo;
1277 struct gl_shader_program **shader_programs;
1278 struct gl_program **programs;
1279 enum shader_time_shader_type *types;
1280 uint64_t *cumulative;
1281 int num_entries;
1282 int max_entries;
1283 double report_time;
1284 } shader_time;
1285
1286 __DRIcontext *driContext;
1287 struct intel_screen *intelScreen;
1288 void (*saved_viewport)(struct gl_context *ctx,
1289 GLint x, GLint y, GLsizei width, GLsizei height);
1290 };
1291
1292 /*======================================================================
1293 * brw_vtbl.c
1294 */
1295 void brwInitVtbl( struct brw_context *brw );
1296
1297 /*======================================================================
1298 * brw_context.c
1299 */
1300 bool brwCreateContext(int api,
1301 const struct gl_config *mesaVis,
1302 __DRIcontext *driContextPriv,
1303 unsigned major_version,
1304 unsigned minor_version,
1305 uint32_t flags,
1306 unsigned *error,
1307 void *sharedContextPrivate);
1308
1309 /*======================================================================
1310 * brw_misc_state.c
1311 */
1312 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree *depth_mt,
1313 uint32_t depth_level,
1314 uint32_t depth_layer,
1315 struct intel_mipmap_tree *stencil_mt,
1316 uint32_t *out_tile_mask_x,
1317 uint32_t *out_tile_mask_y);
1318 void brw_workaround_depthstencil_alignment(struct brw_context *brw,
1319 GLbitfield clear_mask);
1320
1321 /* brw_object_purgeable.c */
1322 void brw_init_object_purgeable_functions(struct dd_function_table *functions);
1323
1324 /*======================================================================
1325 * brw_queryobj.c
1326 */
1327 void brw_init_common_queryobj_functions(struct dd_function_table *functions);
1328 void gen4_init_queryobj_functions(struct dd_function_table *functions);
1329 void brw_emit_query_begin(struct brw_context *brw);
1330 void brw_emit_query_end(struct brw_context *brw);
1331
1332 /** gen6_queryobj.c */
1333 void gen6_init_queryobj_functions(struct dd_function_table *functions);
1334
1335 /*======================================================================
1336 * brw_state_dump.c
1337 */
1338 void brw_debug_batch(struct brw_context *brw);
1339 void brw_annotate_aub(struct brw_context *brw);
1340
1341 /*======================================================================
1342 * brw_tex.c
1343 */
1344 void brw_validate_textures( struct brw_context *brw );
1345
1346
1347 /*======================================================================
1348 * brw_program.c
1349 */
1350 void brwInitFragProgFuncs( struct dd_function_table *functions );
1351
1352 int brw_get_scratch_size(int size);
1353 void brw_get_scratch_bo(struct brw_context *brw,
1354 drm_intel_bo **scratch_bo, int size);
1355 void brw_init_shader_time(struct brw_context *brw);
1356 int brw_get_shader_time_index(struct brw_context *brw,
1357 struct gl_shader_program *shader_prog,
1358 struct gl_program *prog,
1359 enum shader_time_shader_type type);
1360 void brw_collect_and_report_shader_time(struct brw_context *brw);
1361 void brw_destroy_shader_time(struct brw_context *brw);
1362
1363 /* brw_urb.c
1364 */
1365 void brw_upload_urb_fence(struct brw_context *brw);
1366
1367 /* brw_curbe.c
1368 */
1369 void brw_upload_cs_urb_state(struct brw_context *brw);
1370
1371 /* brw_fs_reg_allocate.cpp
1372 */
1373 void brw_fs_alloc_reg_sets(struct brw_context *brw);
1374
1375 /* brw_disasm.c */
1376 int brw_disasm (FILE *file, struct brw_instruction *inst, int gen);
1377
1378 /* brw_vs.c */
1379 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx);
1380
1381 /* brw_draw_upload.c */
1382 unsigned brw_get_vertex_surface_type(struct brw_context *brw,
1383 const struct gl_client_array *glarray);
1384 unsigned brw_get_index_type(GLenum type);
1385
1386 /* brw_wm_surface_state.c */
1387 void brw_init_surface_formats(struct brw_context *brw);
1388 void
1389 brw_update_sol_surface(struct brw_context *brw,
1390 struct gl_buffer_object *buffer_obj,
1391 uint32_t *out_offset, unsigned num_vector_components,
1392 unsigned stride_dwords, unsigned offset_dwords);
1393 void brw_upload_ubo_surfaces(struct brw_context *brw,
1394 struct gl_shader *shader,
1395 uint32_t *surf_offsets);
1396
1397 /* brw_surface_formats.c */
1398 bool brw_is_hiz_depth_format(struct brw_context *ctx, gl_format format);
1399 bool brw_render_target_supported(struct brw_context *brw,
1400 struct gl_renderbuffer *rb);
1401
1402 /* gen6_sol.c */
1403 void
1404 brw_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
1405 struct gl_transform_feedback_object *obj);
1406 void
1407 brw_end_transform_feedback(struct gl_context *ctx,
1408 struct gl_transform_feedback_object *obj);
1409
1410 /* gen7_sol_state.c */
1411 void
1412 gen7_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
1413 struct gl_transform_feedback_object *obj);
1414 void
1415 gen7_end_transform_feedback(struct gl_context *ctx,
1416 struct gl_transform_feedback_object *obj);
1417
1418 /* brw_blorp_blit.cpp */
1419 GLbitfield
1420 brw_blorp_framebuffer(struct brw_context *brw,
1421 GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1,
1422 GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1,
1423 GLbitfield mask, GLenum filter);
1424
1425 bool
1426 brw_blorp_copytexsubimage(struct brw_context *brw,
1427 struct gl_renderbuffer *src_rb,
1428 struct gl_texture_image *dst_image,
1429 int slice,
1430 int srcX0, int srcY0,
1431 int dstX0, int dstY0,
1432 int width, int height);
1433
1434 /* gen6_multisample_state.c */
1435 void
1436 gen6_emit_3dstate_multisample(struct brw_context *brw,
1437 unsigned num_samples);
1438 void
1439 gen6_emit_3dstate_sample_mask(struct brw_context *brw,
1440 unsigned num_samples, float coverage,
1441 bool coverage_invert, unsigned sample_mask);
1442 void
1443 gen6_get_sample_position(struct gl_context *ctx,
1444 struct gl_framebuffer *fb,
1445 GLuint index,
1446 GLfloat *result);
1447
1448 /* gen7_urb.c */
1449 void
1450 gen7_allocate_push_constants(struct brw_context *brw);
1451
1452 void
1453 gen7_emit_urb_state(struct brw_context *brw, GLuint nr_vs_entries,
1454 GLuint vs_size, GLuint vs_start);
1455
1456
1457
1458 /*======================================================================
1459 * Inline conversion functions. These are better-typed than the
1460 * macros used previously:
1461 */
1462 static INLINE struct brw_context *
1463 brw_context( struct gl_context *ctx )
1464 {
1465 return (struct brw_context *)ctx;
1466 }
1467
1468 static INLINE struct brw_vertex_program *
1469 brw_vertex_program(struct gl_vertex_program *p)
1470 {
1471 return (struct brw_vertex_program *) p;
1472 }
1473
1474 static INLINE const struct brw_vertex_program *
1475 brw_vertex_program_const(const struct gl_vertex_program *p)
1476 {
1477 return (const struct brw_vertex_program *) p;
1478 }
1479
1480 static INLINE struct brw_fragment_program *
1481 brw_fragment_program(struct gl_fragment_program *p)
1482 {
1483 return (struct brw_fragment_program *) p;
1484 }
1485
1486 static INLINE const struct brw_fragment_program *
1487 brw_fragment_program_const(const struct gl_fragment_program *p)
1488 {
1489 return (const struct brw_fragment_program *) p;
1490 }
1491
1492 /**
1493 * Pre-gen6, the register file of the EUs was shared between threads,
1494 * and each thread used some subset allocated on a 16-register block
1495 * granularity. The unit states wanted these block counts.
1496 */
1497 static inline int
1498 brw_register_blocks(int reg_count)
1499 {
1500 return ALIGN(reg_count, 16) / 16 - 1;
1501 }
1502
1503 static inline uint32_t
1504 brw_program_reloc(struct brw_context *brw, uint32_t state_offset,
1505 uint32_t prog_offset)
1506 {
1507 if (brw->gen >= 5) {
1508 /* Using state base address. */
1509 return prog_offset;
1510 }
1511
1512 drm_intel_bo_emit_reloc(brw->batch.bo,
1513 state_offset,
1514 brw->cache.bo,
1515 prog_offset,
1516 I915_GEM_DOMAIN_INSTRUCTION, 0);
1517
1518 return brw->cache.bo->offset + prog_offset;
1519 }
1520
1521 bool brw_do_cubemap_normalize(struct exec_list *instructions);
1522 bool brw_lower_texture_gradients(struct brw_context *brw,
1523 struct exec_list *instructions);
1524
1525 struct opcode_desc {
1526 char *name;
1527 int nsrc;
1528 int ndst;
1529 };
1530
1531 extern const struct opcode_desc opcode_descs[128];
1532
1533 void
1534 brw_emit_depthbuffer(struct brw_context *brw);
1535
1536 void
1537 brw_emit_depth_stencil_hiz(struct brw_context *brw,
1538 struct intel_mipmap_tree *depth_mt,
1539 uint32_t depth_offset, uint32_t depthbuffer_format,
1540 uint32_t depth_surface_type,
1541 struct intel_mipmap_tree *stencil_mt,
1542 bool hiz, bool separate_stencil,
1543 uint32_t width, uint32_t height,
1544 uint32_t tile_x, uint32_t tile_y);
1545
1546 void
1547 gen7_emit_depth_stencil_hiz(struct brw_context *brw,
1548 struct intel_mipmap_tree *depth_mt,
1549 uint32_t depth_offset, uint32_t depthbuffer_format,
1550 uint32_t depth_surface_type,
1551 struct intel_mipmap_tree *stencil_mt,
1552 bool hiz, bool separate_stencil,
1553 uint32_t width, uint32_t height,
1554 uint32_t tile_x, uint32_t tile_y);
1555
1556 #ifdef __cplusplus
1557 }
1558 #endif
1559
1560 #endif