2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
37 #include "main/macros.h"
38 #include "main/mtypes.h"
39 #include "brw_structs.h"
40 #include "brw_compiler.h"
41 #include "intel_aub.h"
44 #include "blorp/blorp.h"
48 /* Evil hack for using libdrm in a c++ compiler. */
52 #include <intel_bufmgr.h>
61 #include "intel_debug.h"
62 #include "intel_screen.h"
63 #include "intel_tex_obj.h"
64 #include "intel_resolve_map.h"
68 * URB - uniform resource buffer. A mid-sized buffer which is
69 * partitioned between the fixed function units and used for passing
70 * values (vertices, primitives, constants) between them.
72 * CURBE - constant URB entry. An urb region (entry) used to hold
73 * constant values which the fixed function units can be instructed to
74 * preload into the GRF when spawning a thread.
76 * VUE - vertex URB entry. An urb entry holding a vertex and usually
77 * a vertex header. The header contains control information and
78 * things like primitive type, Begin/end flags and clip codes.
80 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
81 * unit holding rasterization and interpolation parameters.
83 * GRF - general register file. One of several register files
84 * addressable by programmed threads. The inputs (r0, payload, curbe,
85 * urb) of the thread are preloaded to this area before the thread is
86 * spawned. The registers are individually 8 dwords wide and suitable
87 * for general usage. Registers holding thread input values are not
88 * special and may be overwritten.
90 * MRF - message register file. Threads communicate (and terminate)
91 * by sending messages. Message parameters are placed in contiguous
92 * MRF registers. All program output is via these messages. URB
93 * entries are populated by sending a message to the shared URB
94 * function containing the new data, together with a control word,
95 * often an unmodified copy of R0.
97 * R0 - GRF register 0. Typically holds control information used when
98 * sending messages to other threads.
100 * EU or GEN4 EU: The name of the programmable subsystem of the
101 * i965 hardware. Threads are executed by the EU, the registers
102 * described above are part of the EU architecture.
104 * Fixed function units:
106 * CS - Command streamer. Notional first unit, little software
107 * interaction. Holds the URB entries used for constant data, ie the
110 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
111 * this unit is responsible for pulling vertices out of vertex buffers
112 * in vram and injecting them into the processing pipe as VUEs. If
113 * enabled, it first passes them to a VS thread which is a good place
114 * for the driver to implement any active vertex shader.
116 * HS - Hull Shader (Tessellation Control Shader)
118 * TE - Tessellation Engine (Tessellation Primitive Generation)
120 * DS - Domain Shader (Tessellation Evaluation Shader)
122 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
123 * enabled, incoming strips etc are passed to GS threads in individual
124 * line/triangle/point units. The GS thread may perform arbitary
125 * computation and emit whatever primtives with whatever vertices it
126 * chooses. This makes GS an excellent place to implement GL's
127 * unfilled polygon modes, though of course it is capable of much
128 * more. Additionally, GS is used to translate away primitives not
129 * handled by latter units, including Quads and Lineloops.
131 * CS - Clipper. Mesa's clipping algorithms are imported to run on
132 * this unit. The fixed function part performs cliptesting against
133 * the 6 fixed clipplanes and makes descisions on whether or not the
134 * incoming primitive needs to be passed to a thread for clipping.
135 * User clip planes are handled via cooperation with the VS thread.
137 * SF - Strips Fans or Setup: Triangles are prepared for
138 * rasterization. Interpolation coefficients are calculated.
139 * Flatshading and two-side lighting usually performed here.
141 * WM - Windower. Interpolation of vertex attributes performed here.
142 * Fragment shader implemented here. SIMD aspects of EU taken full
143 * advantage of, as pixels are processed in blocks of 16.
145 * CC - Color Calculator. No EU threads associated with this unit.
146 * Handles blending and (presumably) depth and stencil testing.
151 struct brw_vs_prog_key
;
152 struct brw_vue_prog_key
;
153 struct brw_wm_prog_key
;
154 struct brw_wm_prog_data
;
155 struct brw_cs_prog_key
;
156 struct brw_cs_prog_data
;
160 BRW_COMPUTE_PIPELINE
,
167 BRW_CACHE_BLORP_PROG
,
170 BRW_CACHE_FF_GS_PROG
,
181 /* brw_cache_ids must come first - see brw_state_cache.c */
182 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
183 BRW_STATE_FRAGMENT_PROGRAM
,
184 BRW_STATE_GEOMETRY_PROGRAM
,
185 BRW_STATE_TESS_PROGRAMS
,
186 BRW_STATE_VERTEX_PROGRAM
,
187 BRW_STATE_CURBE_OFFSETS
,
188 BRW_STATE_REDUCED_PRIMITIVE
,
189 BRW_STATE_PATCH_PRIMITIVE
,
194 BRW_STATE_BINDING_TABLE_POINTERS
,
197 BRW_STATE_DEFAULT_TESS_LEVELS
,
199 BRW_STATE_INDEX_BUFFER
,
200 BRW_STATE_VS_CONSTBUF
,
201 BRW_STATE_TCS_CONSTBUF
,
202 BRW_STATE_TES_CONSTBUF
,
203 BRW_STATE_GS_CONSTBUF
,
204 BRW_STATE_PROGRAM_CACHE
,
205 BRW_STATE_STATE_BASE_ADDRESS
,
206 BRW_STATE_VUE_MAP_GEOM_OUT
,
207 BRW_STATE_TRANSFORM_FEEDBACK
,
208 BRW_STATE_RASTERIZER_DISCARD
,
210 BRW_STATE_UNIFORM_BUFFER
,
211 BRW_STATE_ATOMIC_BUFFER
,
212 BRW_STATE_IMAGE_UNITS
,
213 BRW_STATE_META_IN_PROGRESS
,
214 BRW_STATE_INTERPOLATION_MAP
,
215 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
216 BRW_STATE_NUM_SAMPLES
,
217 BRW_STATE_TEXTURE_BUFFER
,
218 BRW_STATE_GEN4_UNIT_STATE
,
222 BRW_STATE_SAMPLER_STATE_TABLE
,
223 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
224 BRW_STATE_COMPUTE_PROGRAM
,
225 BRW_STATE_CS_WORK_GROUPS
,
233 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
235 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
236 * When the currently bound shader program differs from the previous draw
237 * call, these will be flagged. They cover brw->{stage}_program and
238 * ctx->{Stage}Program->_Current.
240 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
241 * driver perspective. Even if the same shader is bound at the API level,
242 * we may need to switch between multiple versions of that shader to handle
243 * changes in non-orthagonal state.
245 * Additionally, multiple shader programs may have identical vertex shaders
246 * (for example), or compile down to the same code in the backend. We combine
247 * those into a single program cache entry.
249 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
250 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
252 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
253 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
254 * use the normal state upload paths), but the cache is still used. To avoid
255 * polluting the brw_state_cache code with special cases, we retain the dirty
256 * bit for now. It should eventually be removed.
258 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_PROG)
259 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
260 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
261 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
262 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
263 #define BRW_NEW_TCS_PROG_DATA (1ull << BRW_CACHE_TCS_PROG)
264 #define BRW_NEW_TES_PROG_DATA (1ull << BRW_CACHE_TES_PROG)
265 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
266 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
267 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
268 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
269 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
270 #define BRW_NEW_TESS_PROGRAMS (1ull << BRW_STATE_TESS_PROGRAMS)
271 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
272 #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
273 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
274 #define BRW_NEW_PATCH_PRIMITIVE (1ull << BRW_STATE_PATCH_PRIMITIVE)
275 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
276 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
277 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
278 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
279 #define BRW_NEW_BINDING_TABLE_POINTERS (1ull << BRW_STATE_BINDING_TABLE_POINTERS)
280 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
281 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
282 #define BRW_NEW_DEFAULT_TESS_LEVELS (1ull << BRW_STATE_DEFAULT_TESS_LEVELS)
284 * Used for any batch entry with a relocated pointer that will be used
285 * by any 3D rendering.
287 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
288 /** \see brw.state.depth_region */
289 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
290 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
291 #define BRW_NEW_TCS_CONSTBUF (1ull << BRW_STATE_TCS_CONSTBUF)
292 #define BRW_NEW_TES_CONSTBUF (1ull << BRW_STATE_TES_CONSTBUF)
293 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
294 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
295 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
296 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
297 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
298 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
299 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
300 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
301 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
302 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
303 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
304 #define BRW_NEW_INTERPOLATION_MAP (1ull << BRW_STATE_INTERPOLATION_MAP)
305 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
306 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
307 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
308 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
309 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
310 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
311 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
312 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
313 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
314 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
315 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
316 #define BRW_NEW_URB_SIZE (1ull << BRW_STATE_URB_SIZE)
317 #define BRW_NEW_CC_STATE (1ull << BRW_STATE_CC_STATE)
318 #define BRW_NEW_BLORP (1ull << BRW_STATE_BLORP)
320 struct brw_state_flags
{
321 /** State update flags signalled by mesa internals */
324 * State update flags signalled as the result of brw_tracked_state updates
329 /** Subclass of Mesa vertex program */
330 struct brw_vertex_program
{
331 struct gl_vertex_program program
;
336 /** Subclass of Mesa tessellation control program */
337 struct brw_tess_ctrl_program
{
338 struct gl_tess_ctrl_program program
;
339 unsigned id
; /**< serial no. to identify tess ctrl progs, never re-used */
343 /** Subclass of Mesa tessellation evaluation program */
344 struct brw_tess_eval_program
{
345 struct gl_tess_eval_program program
;
346 unsigned id
; /**< serial no. to identify tess eval progs, never re-used */
350 /** Subclass of Mesa geometry program */
351 struct brw_geometry_program
{
352 struct gl_geometry_program program
;
353 unsigned id
; /**< serial no. to identify geom progs, never re-used */
357 /** Subclass of Mesa fragment program */
358 struct brw_fragment_program
{
359 struct gl_fragment_program program
;
360 GLuint id
; /**< serial no. to identify frag progs, never re-used */
364 /** Subclass of Mesa compute program */
365 struct brw_compute_program
{
366 struct gl_compute_program program
;
367 unsigned id
; /**< serial no. to identify compute progs, never re-used */
372 struct gl_linked_shader base
;
378 * Bitmask indicating which fragment shader inputs represent varyings (and
379 * hence have to be delivered to the fragment shader by the SF/SBE stage).
381 #define BRW_FS_VARYING_INPUT_MASK \
382 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
383 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
387 * Mapping of VUE map slots to interpolation modes.
389 struct interpolation_mode_map
{
390 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
393 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
395 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
396 if (map
->mode
[i
] == INTERP_MODE_FLAT
)
402 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
404 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
405 if (map
->mode
[i
] == INTERP_MODE_NOPERSPECTIVE
)
412 struct brw_sf_prog_data
{
413 GLuint urb_read_length
;
416 /* Each vertex may have upto 12 attributes, 4 components each,
417 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
420 * Actually we use 4 for each, so call it 12 rows.
422 GLuint urb_entry_size
;
427 * We always program SF to start reading at an offset of 1 (2 varying slots)
428 * from the start of the vertex URB entry. This causes it to skip:
429 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
430 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
432 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
435 struct brw_clip_prog_data
{
436 GLuint curb_read_length
; /* user planes? */
438 GLuint urb_read_length
;
442 struct brw_ff_gs_prog_data
{
443 GLuint urb_read_length
;
447 * Gen6 transform feedback: Amount by which the streaming vertex buffer
448 * indices should be incremented each time the GS is invoked.
450 unsigned svbi_postincrement_value
;
453 /** Number of texture sampler units */
454 #define BRW_MAX_TEX_UNIT 32
456 /** Max number of render targets in a shader */
457 #define BRW_MAX_DRAW_BUFFERS 8
459 /** Max number of UBOs in a shader */
460 #define BRW_MAX_UBO 14
462 /** Max number of SSBOs in a shader */
463 #define BRW_MAX_SSBO 12
465 /** Max number of atomic counter buffer objects in a shader */
466 #define BRW_MAX_ABO 16
468 /** Max number of image uniforms in a shader */
469 #define BRW_MAX_IMAGES 32
472 * Max number of binding table entries used for stream output.
474 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
475 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
477 * On Gen6, the size of transform feedback data is limited not by the number
478 * of components but by the number of binding table entries we set aside. We
479 * use one binding table entry for a float, one entry for a vector, and one
480 * entry per matrix column. Since the only way we can communicate our
481 * transform feedback capabilities to the client is via
482 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
483 * worst case, in which all the varyings are floats, so we use up one binding
484 * table entry per component. Therefore we need to set aside at least 64
485 * binding table entries for use by transform feedback.
487 * Note: since we don't currently pack varyings, it is currently impossible
488 * for the client to actually use up all of these binding table entries--if
489 * all of their varyings were floats, they would run out of varying slots and
490 * fail to link. But that's a bug, so it seems prudent to go ahead and
491 * allocate the number of binding table entries we will need once the bug is
494 #define BRW_MAX_SOL_BINDINGS 64
496 /** Maximum number of actual buffers used for stream output */
497 #define BRW_MAX_SOL_BUFFERS 4
499 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
500 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
505 2 + /* shader time, pull constants */ \
506 1 /* cs num work groups */)
508 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
511 * Stride in bytes between shader_time entries.
513 * We separate entries by a cacheline to reduce traffic between EUs writing to
516 #define SHADER_TIME_STRIDE 64
518 struct brw_cache_item
{
520 * Effectively part of the key, cache_id identifies what kind of state
521 * buffer is involved, and also which dirty flag should set.
523 enum brw_cache_id cache_id
;
524 /** 32-bit hash of the key data */
526 GLuint key_size
; /* for variable-sized keys */
533 struct brw_cache_item
*next
;
538 struct brw_context
*brw
;
540 struct brw_cache_item
**items
;
542 GLuint size
, n_items
;
544 uint32_t next_offset
;
549 /* Considered adding a member to this struct to document which flags
550 * an update might raise so that ordering of the state atoms can be
551 * checked or derived at runtime. Dropped the idea in favor of having
552 * a debug mode where the state is monitored for flags which are
553 * raised that have already been tested against.
555 struct brw_tracked_state
{
556 struct brw_state_flags dirty
;
557 void (*emit
)( struct brw_context
*brw
);
560 enum shader_time_shader_type
{
571 struct brw_vertex_buffer
{
572 /** Buffer object containing the uploaded vertex data */
576 /** Byte stride between elements in the uploaded array */
580 struct brw_vertex_element
{
581 const struct gl_client_array
*glarray
;
585 /** Offset of the first element within the buffer object */
589 struct brw_query_object
{
590 struct gl_query_object Base
;
592 /** Last query BO associated with this query. */
595 /** Last index in bo with query data for this object. */
598 /** True if we know the batch has been flushed since we ended the query. */
608 struct intel_batchbuffer
{
609 /** Current batchbuffer being queued up. */
611 /** Last BO submitted to the hardware. Used for glFinish(). */
612 drm_intel_bo
*last_bo
;
615 uint16_t emit
, total
;
617 uint16_t reserved_space
;
621 #define BATCH_SZ (8192*sizeof(uint32_t))
623 uint32_t state_batch_offset
;
624 enum brw_gpu_ring ring
;
625 bool needs_sol_reset
;
626 bool state_base_address_emitted
;
634 #define MAX_GS_INPUT_VERTICES 6
636 #define BRW_MAX_XFB_STREAMS 4
638 struct brw_transform_feedback_object
{
639 struct gl_transform_feedback_object base
;
641 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
642 drm_intel_bo
*offset_bo
;
644 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
647 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
648 GLenum primitive_mode
;
651 * Count of primitives generated during this transform feedback operation.
654 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
655 drm_intel_bo
*prim_count_bo
;
656 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
660 * Number of vertices written between last Begin/EndTransformFeedback().
662 * Used to implement DrawTransformFeedback().
664 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
665 bool vertices_written_valid
;
669 * Data shared between each programmable stage in the pipeline (vs, gs, and
672 struct brw_stage_state
674 gl_shader_stage stage
;
675 struct brw_stage_prog_data
*prog_data
;
678 * Optional scratch buffer used to store spilled register values and
679 * variably-indexed GRF arrays.
681 * The contents of this buffer are short-lived so the same memory can be
682 * re-used at will for multiple shader programs (executed by the same fixed
683 * function). However reusing a scratch BO for which shader invocations
684 * are still in flight with a per-thread scratch slot size other than the
685 * original can cause threads with different scratch slot size and FFTID
686 * (which may be executed in parallel depending on the shader stage and
687 * hardware generation) to map to an overlapping region of the scratch
688 * space, which can potentially lead to mutual scratch space corruption.
689 * For that reason if you borrow this scratch buffer you should only be
690 * using the slot size given by the \c per_thread_scratch member below,
691 * unless you're taking additional measures to synchronize thread execution
692 * across slot size changes.
694 drm_intel_bo
*scratch_bo
;
697 * Scratch slot size allocated for each thread in the buffer object given
700 uint32_t per_thread_scratch
;
702 /** Offset in the program cache to the program */
703 uint32_t prog_offset
;
705 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
706 uint32_t state_offset
;
708 uint32_t push_const_offset
; /* Offset in the batchbuffer */
709 int push_const_size
; /* in 256-bit register increments */
711 /* Binding table: pointers to SURFACE_STATE entries. */
712 uint32_t bind_bo_offset
;
713 uint32_t surf_offset
[BRW_MAX_SURFACES
];
715 /** SAMPLER_STATE count and table offset */
716 uint32_t sampler_count
;
717 uint32_t sampler_offset
;
720 enum brw_predicate_state
{
721 /* The first two states are used if we can determine whether to draw
722 * without having to look at the values in the query object buffer. This
723 * will happen if there is no conditional render in progress, if the query
724 * object is already completed or if something else has already added
725 * samples to the preliminary result such as via a BLT command.
727 BRW_PREDICATE_STATE_RENDER
,
728 BRW_PREDICATE_STATE_DONT_RENDER
,
729 /* In this case whether to draw or not depends on the result of an
730 * MI_PREDICATE command so the predicate enable bit needs to be checked.
732 BRW_PREDICATE_STATE_USE_BIT
737 struct brw_l3_config
;
740 * brw_context is derived from gl_context.
744 struct gl_context ctx
; /**< base class, must be first field */
748 uint32_t (*update_renderbuffer_surface
)(struct brw_context
*brw
,
749 struct gl_renderbuffer
*rb
,
750 bool layered
, unsigned unit
,
751 uint32_t surf_index
);
752 void (*emit_null_surface_state
)(struct brw_context
*brw
,
756 uint32_t *out_offset
);
759 * Send the appropriate state packets to configure depth, stencil, and
760 * HiZ buffers (i965+ only)
762 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
763 struct intel_mipmap_tree
*depth_mt
,
764 uint32_t depth_offset
,
765 uint32_t depthbuffer_format
,
766 uint32_t depth_surface_type
,
767 struct intel_mipmap_tree
*stencil_mt
,
768 bool hiz
, bool separate_stencil
,
769 uint32_t width
, uint32_t height
,
770 uint32_t tile_x
, uint32_t tile_y
);
776 drm_intel_context
*hw_ctx
;
778 /** BO for post-sync nonzero writes for gen6 workaround. */
779 drm_intel_bo
*workaround_bo
;
780 uint8_t pipe_controls_since_last_cs_stall
;
783 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
784 * and would need flushing before being used from another cache domain that
785 * isn't coherent with it (i.e. the sampler).
787 struct set
*render_cache
;
790 * Number of resets observed in the system at context creation.
792 * This is tracked in the context so that we can determine that another
793 * reset has occurred.
795 uint32_t reset_count
;
797 struct intel_batchbuffer batch
;
802 uint32_t next_offset
;
806 * Set if rendering has occurred to the drawable's front buffer.
808 * This is used in the DRI2 case to detect that glFlush should also copy
809 * the contents of the fake front buffer to the real front buffer.
811 bool front_buffer_dirty
;
813 /** Framerate throttling: @{ */
814 drm_intel_bo
*throttle_batch
[2];
816 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
817 * frame of rendering to complete. This gives a very precise cap to the
818 * latency between input and output such that rendering never gets more
819 * than a frame behind the user. (With the caveat that we technically are
820 * not using the SwapBuffers itself as a barrier but the first batch
821 * submitted afterwards, which may be immediately prior to the next
824 bool need_swap_throttle
;
826 /** General throttling, not caught by throttling between SwapBuffers */
827 bool need_flush_throttle
;
837 bool always_flush_batch
;
838 bool always_flush_cache
;
839 bool disable_throttling
;
841 bool dual_color_blend_by_location
;
843 driOptionCache optionCache
;
846 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
848 GLenum reduced_primitive
;
851 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
852 * variable is set, this is the flag indicating to do expensive work that
853 * might lead to a perf_debug() call.
857 uint64_t max_gtt_map_object_size
;
869 bool has_separate_stencil
;
870 bool must_use_separate_stencil
;
873 bool has_surface_tile_offset
;
875 bool has_negative_rhw_bug
;
879 bool use_resource_streamer
;
882 * Whether LRI can be used to write register values from the batch buffer.
884 bool can_do_pipelined_register_writes
;
887 * Some versions of Gen hardware don't do centroid interpolation correctly
888 * on unlit pixels, causing incorrect values for derivatives near triangle
889 * edges. Enabling this flag causes the fragment shader to use
890 * non-centroid interpolation for unlit pixels, at the expense of two extra
891 * fragment shader instructions.
893 bool needs_unlit_centroid_workaround
;
895 struct isl_device isl_dev
;
897 struct blorp_context blorp
;
901 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
904 enum brw_pipeline last_pipeline
;
906 struct brw_cache cache
;
908 /** IDs for meta stencil blit shader programs. */
909 struct gl_shader_program
*meta_stencil_blit_programs
[2];
911 /* Whether a meta-operation is in progress. */
912 bool meta_in_progress
;
914 /* Whether the last depth/stencil packets were both NULL. */
915 bool no_depth_or_stencil
;
917 /* The last PMA stall bits programmed. */
918 uint32_t pma_stall_bits
;
922 /** The value of gl_BaseVertex for the current _mesa_prim. */
925 /** The value of gl_BaseInstance for the current _mesa_prim. */
930 * Buffer and offset used for GL_ARB_shader_draw_parameters
931 * (for now, only gl_BaseVertex).
933 drm_intel_bo
*draw_params_bo
;
934 uint32_t draw_params_offset
;
937 * The value of gl_DrawID for the current _mesa_prim. This always comes
938 * in from it's own vertex buffer since it's not part of the indirect
942 drm_intel_bo
*draw_id_bo
;
943 uint32_t draw_id_offset
;
948 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
949 * an indirect call, and num_work_groups_offset is valid. Otherwise,
950 * num_work_groups is set based on glDispatchCompute.
952 drm_intel_bo
*num_work_groups_bo
;
953 GLintptr num_work_groups_offset
;
954 const GLuint
*num_work_groups
;
958 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
959 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
961 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
965 /* Summary of size and varying of active arrays, so we can check
966 * for changes to this state:
968 bool index_bounds_valid
;
969 unsigned int min_index
, max_index
;
971 /* Offset from start of vertex buffer so we can avoid redefining
972 * the same VB packed over and over again.
974 unsigned int start_vertex_bias
;
977 * Certain vertex attribute formats aren't natively handled by the
978 * hardware and require special VS code to fix up their values.
980 * These bitfields indicate which workarounds are needed.
982 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
987 * Index buffer for this draw_prims call.
989 * Updates are signaled by BRW_NEW_INDICES.
991 const struct _mesa_index_buffer
*ib
;
993 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
998 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
999 * avoid re-uploading the IB packet over and over if we're actually
1000 * referencing the same index buffer.
1002 unsigned int start_vertex_offset
;
1005 /* Active vertex program:
1007 const struct gl_vertex_program
*vertex_program
;
1008 const struct gl_geometry_program
*geometry_program
;
1009 const struct gl_tess_ctrl_program
*tess_ctrl_program
;
1010 const struct gl_tess_eval_program
*tess_eval_program
;
1011 const struct gl_fragment_program
*fragment_program
;
1012 const struct gl_compute_program
*compute_program
;
1015 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
1016 * that we don't have to reemit that state every time we change FBOs.
1021 * Platform specific constants containing the maximum number of threads
1022 * for each pipeline stage.
1024 unsigned max_vs_threads
;
1025 unsigned max_hs_threads
;
1026 unsigned max_ds_threads
;
1027 unsigned max_gs_threads
;
1028 unsigned max_wm_threads
;
1029 unsigned max_cs_threads
;
1031 /* BRW_NEW_URB_ALLOCATIONS:
1034 GLuint vsize
; /* vertex size plus header in urb registers */
1035 GLuint gsize
; /* GS output size in urb registers */
1036 GLuint hsize
; /* Tessellation control output size in urb registers */
1037 GLuint dsize
; /* Tessellation evaluation output size in urb registers */
1038 GLuint csize
; /* constant buffer size in urb registers */
1039 GLuint sfsize
; /* setup data size in urb registers */
1043 GLuint min_vs_entries
; /* Minimum number of VS entries */
1044 GLuint max_vs_entries
; /* Maximum number of VS entries */
1045 GLuint max_hs_entries
; /* Maximum number of HS entries */
1046 GLuint max_ds_entries
; /* Maximum number of DS entries */
1047 GLuint max_gs_entries
; /* Maximum number of GS entries */
1049 GLuint nr_vs_entries
;
1050 GLuint nr_hs_entries
;
1051 GLuint nr_ds_entries
;
1052 GLuint nr_gs_entries
;
1053 GLuint nr_clip_entries
;
1054 GLuint nr_sf_entries
;
1055 GLuint nr_cs_entries
;
1065 * URB size in the current configuration. The units this is expressed
1066 * in are somewhat inconsistent, see brw_device_info::urb::size.
1068 * FINISHME: Represent the URB size consistently in KB on all platforms.
1072 /* True if the most recently sent _3DSTATE_URB message allocated
1073 * URB space for the GS.
1077 /* True if the most recently sent _3DSTATE_URB message allocated
1078 * URB space for the HS and DS.
1084 /* BRW_NEW_CURBE_OFFSETS:
1087 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1088 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1096 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1097 * for upload to the CURBE.
1099 drm_intel_bo
*curbe_bo
;
1100 /** Offset within curbe_bo of space for current curbe entry */
1101 GLuint curbe_offset
;
1105 * Layout of vertex data exiting the geometry portion of the pipleine.
1106 * This comes from the last enabled shader stage (GS, DS, or VS).
1108 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1110 struct brw_vue_map vue_map_geom_out
;
1113 struct brw_stage_state base
;
1114 struct brw_vs_prog_data
*prog_data
;
1118 struct brw_stage_state base
;
1119 struct brw_tcs_prog_data
*prog_data
;
1122 * True if the 3DSTATE_HS command most recently emitted to the 3D
1123 * pipeline enabled the HS; false otherwise.
1129 struct brw_stage_state base
;
1130 struct brw_tes_prog_data
*prog_data
;
1133 * True if the 3DSTATE_DS command most recently emitted to the 3D
1134 * pipeline enabled the DS; false otherwise.
1140 struct brw_stage_state base
;
1141 struct brw_gs_prog_data
*prog_data
;
1144 * True if the 3DSTATE_GS command most recently emitted to the 3D
1145 * pipeline enabled the GS; false otherwise.
1151 struct brw_ff_gs_prog_data
*prog_data
;
1154 /** Offset in the program cache to the CLIP program pre-gen6 */
1155 uint32_t prog_offset
;
1156 uint32_t state_offset
;
1158 uint32_t bind_bo_offset
;
1160 * Surface offsets for the binding table. We only need surfaces to
1161 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1162 * need in this case.
1164 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1168 struct brw_clip_prog_data
*prog_data
;
1170 /** Offset in the program cache to the CLIP program pre-gen6 */
1171 uint32_t prog_offset
;
1173 /* Offset in the batch to the CLIP state on pre-gen6. */
1174 uint32_t state_offset
;
1176 /* As of gen6, this is the offset in the batch to the CLIP VP,
1184 struct brw_sf_prog_data
*prog_data
;
1186 /** Offset in the program cache to the CLIP program pre-gen6 */
1187 uint32_t prog_offset
;
1188 uint32_t state_offset
;
1190 bool viewport_transform_enable
;
1194 struct brw_stage_state base
;
1195 struct brw_wm_prog_data
*prog_data
;
1200 * Buffer object used in place of multisampled null render targets on
1201 * Gen6. See brw_emit_null_surface_state().
1203 drm_intel_bo
*multisampled_null_render_target_bo
;
1204 uint32_t fast_clear_op
;
1210 struct brw_stage_state base
;
1211 struct brw_cs_prog_data
*prog_data
;
1214 /* RS hardware binding table */
1217 uint32_t next_offset
;
1221 uint32_t state_offset
;
1222 uint32_t blend_state_offset
;
1223 uint32_t depth_stencil_state_offset
;
1228 struct brw_query_object
*obj
;
1233 enum brw_predicate_state state
;
1238 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1239 const int *statistics_registers
;
1241 /** The number of active monitors using OA counters. */
1245 * A buffer object storing OA counter snapshots taken at the start and
1246 * end of each batch (creating "bookends" around the batch).
1248 drm_intel_bo
*bookend_bo
;
1250 /** The number of snapshots written to bookend_bo. */
1251 int bookend_snapshots
;
1254 * An array of monitors whose results haven't yet been assembled based on
1255 * the data in buffer objects.
1257 * These may be active, or have already ended. However, the results
1258 * have not been requested.
1260 struct brw_perf_monitor_object
**unresolved
;
1261 int unresolved_elements
;
1262 int unresolved_array_size
;
1265 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1266 * the counter which MI_REPORT_PERF_COUNT stores there.
1268 const int *oa_snapshot_layout
;
1270 /** Number of 32-bit entries in a hardware counter snapshot. */
1271 int entries_per_oa_snapshot
;
1274 int num_atoms
[BRW_NUM_PIPELINES
];
1275 const struct brw_tracked_state render_atoms
[76];
1276 const struct brw_tracked_state compute_atoms
[11];
1278 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1282 enum aub_state_struct_type type
;
1284 } *state_batch_list
;
1285 int state_batch_count
;
1287 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1288 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1290 /* Interpolation modes, one byte per vue slot.
1291 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1293 struct interpolation_mode_map interpolation_mode
;
1295 /* PrimitiveRestart */
1298 bool enable_cut_index
;
1301 /** Computed depth/stencil/hiz state from the current attached
1302 * renderbuffers, valid only during the drawing state upload loop after
1303 * brw_workaround_depthstencil_alignment().
1306 struct intel_mipmap_tree
*depth_mt
;
1307 struct intel_mipmap_tree
*stencil_mt
;
1309 /* Inter-tile (page-aligned) byte offsets. */
1310 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1311 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1312 uint32_t tile_x
, tile_y
;
1315 uint32_t num_instances
;
1320 const struct brw_l3_config
*config
;
1327 enum shader_time_shader_type
*types
;
1328 struct shader_times
*cumulative
;
1334 struct brw_fast_clear_state
*fast_clear_state
;
1336 __DRIcontext
*driContext
;
1337 struct intel_screen
*intelScreen
;
1340 /*======================================================================
1343 void brwInitVtbl( struct brw_context
*brw
);
1346 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1348 /*======================================================================
1351 extern const char *const brw_vendor_string
;
1354 brw_get_renderer_string(const struct intel_screen
*intelScreen
);
1357 DRI_CONF_BO_REUSE_DISABLED
,
1358 DRI_CONF_BO_REUSE_ALL
1361 void intel_update_renderbuffers(__DRIcontext
*context
,
1362 __DRIdrawable
*drawable
);
1363 void intel_prepare_render(struct brw_context
*brw
);
1365 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1366 __DRIdrawable
*drawable
);
1368 GLboolean
brwCreateContext(gl_api api
,
1369 const struct gl_config
*mesaVis
,
1370 __DRIcontext
*driContextPriv
,
1371 unsigned major_version
,
1372 unsigned minor_version
,
1376 void *sharedContextPrivate
);
1378 /*======================================================================
1382 brw_meta_resolve_color(struct brw_context
*brw
,
1383 struct intel_mipmap_tree
*mt
);
1385 /*======================================================================
1388 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1389 uint32_t depth_level
,
1390 uint32_t depth_layer
,
1391 struct intel_mipmap_tree
*stencil_mt
,
1392 uint32_t *out_tile_mask_x
,
1393 uint32_t *out_tile_mask_y
);
1394 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1395 GLbitfield clear_mask
);
1397 /* brw_object_purgeable.c */
1398 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1400 /*======================================================================
1403 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1404 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1405 void brw_emit_query_begin(struct brw_context
*brw
);
1406 void brw_emit_query_end(struct brw_context
*brw
);
1407 void brw_query_counter(struct gl_context
*ctx
, struct gl_query_object
*q
);
1408 bool brw_is_query_pipelined(struct brw_query_object
*query
);
1410 /** gen6_queryobj.c */
1411 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1412 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1413 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1415 /** hsw_queryobj.c */
1416 void hsw_init_queryobj_functions(struct dd_function_table
*functions
);
1418 /** brw_conditional_render.c */
1419 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1420 bool brw_check_conditional_render(struct brw_context
*brw
);
1422 /** intel_batchbuffer.c */
1423 void brw_load_register_mem(struct brw_context
*brw
,
1426 uint32_t read_domains
, uint32_t write_domain
,
1428 void brw_load_register_mem64(struct brw_context
*brw
,
1431 uint32_t read_domains
, uint32_t write_domain
,
1433 void brw_store_register_mem32(struct brw_context
*brw
,
1434 drm_intel_bo
*bo
, uint32_t reg
, uint32_t offset
);
1435 void brw_store_register_mem64(struct brw_context
*brw
,
1436 drm_intel_bo
*bo
, uint32_t reg
, uint32_t offset
);
1437 void brw_load_register_imm32(struct brw_context
*brw
,
1438 uint32_t reg
, uint32_t imm
);
1439 void brw_load_register_imm64(struct brw_context
*brw
,
1440 uint32_t reg
, uint64_t imm
);
1441 void brw_load_register_reg(struct brw_context
*brw
, uint32_t src
,
1443 void brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
,
1445 void brw_store_data_imm32(struct brw_context
*brw
, drm_intel_bo
*bo
,
1446 uint32_t offset
, uint32_t imm
);
1447 void brw_store_data_imm64(struct brw_context
*brw
, drm_intel_bo
*bo
,
1448 uint32_t offset
, uint64_t imm
);
1450 /*======================================================================
1453 void brw_debug_batch(struct brw_context
*brw
);
1454 void brw_annotate_aub(struct brw_context
*brw
);
1456 /*======================================================================
1457 * intel_tex_validate.c
1459 void brw_validate_textures( struct brw_context
*brw
);
1462 /*======================================================================
1466 key_debug(struct brw_context
*brw
, const char *name
, int a
, int b
)
1469 perf_debug(" %s %d->%d\n", name
, a
, b
);
1475 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1477 /* Per-thread scratch space is a power-of-two multiple of 1KB. */
1479 brw_get_scratch_size(int size
)
1481 return MAX2(1024, util_next_power_of_two(size
));
1483 void brw_get_scratch_bo(struct brw_context
*brw
,
1484 drm_intel_bo
**scratch_bo
, int size
);
1485 void brw_alloc_stage_scratch(struct brw_context
*brw
,
1486 struct brw_stage_state
*stage_state
,
1487 unsigned per_thread_size
,
1488 unsigned thread_count
);
1489 void brw_init_shader_time(struct brw_context
*brw
);
1490 int brw_get_shader_time_index(struct brw_context
*brw
,
1491 struct gl_shader_program
*shader_prog
,
1492 struct gl_program
*prog
,
1493 enum shader_time_shader_type type
);
1494 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1495 void brw_destroy_shader_time(struct brw_context
*brw
);
1499 void brw_upload_urb_fence(struct brw_context
*brw
);
1503 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1505 /* brw_fs_reg_allocate.cpp
1507 void brw_fs_alloc_reg_sets(struct brw_compiler
*compiler
);
1509 /* brw_vec4_reg_allocate.cpp */
1510 void brw_vec4_alloc_reg_set(struct brw_compiler
*compiler
);
1513 int brw_disassemble_inst(FILE *file
, const struct brw_device_info
*devinfo
,
1514 struct brw_inst
*inst
, bool is_compacted
);
1517 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1519 /* brw_draw_upload.c */
1520 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1521 const struct gl_client_array
*glarray
);
1523 static inline unsigned
1524 brw_get_index_type(GLenum type
)
1526 assert((type
== GL_UNSIGNED_BYTE
)
1527 || (type
== GL_UNSIGNED_SHORT
)
1528 || (type
== GL_UNSIGNED_INT
));
1530 /* The possible values for type are GL_UNSIGNED_BYTE (0x1401),
1531 * GL_UNSIGNED_SHORT (0x1403), and GL_UNSIGNED_INT (0x1405) which we want
1532 * to map to scale factors of 0, 1, and 2, respectively. These scale
1533 * factors are then left-shfited by 8 to be in the correct position in the
1534 * CMD_INDEX_BUFFER packet.
1536 * Subtracting 0x1401 gives 0, 2, and 4. Shifting left by 7 afterwards
1537 * gives 0x00000000, 0x00000100, and 0x00000200. These just happen to be
1538 * the values the need to be written in the CMD_INDEX_BUFFER packet.
1540 return (type
- 0x1401) << 7;
1543 void brw_prepare_vertices(struct brw_context
*brw
);
1545 /* brw_wm_surface_state.c */
1546 void brw_init_surface_formats(struct brw_context
*brw
);
1547 void brw_create_constant_surface(struct brw_context
*brw
,
1551 uint32_t *out_offset
);
1552 void brw_create_buffer_surface(struct brw_context
*brw
,
1556 uint32_t *out_offset
);
1557 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1559 uint32_t *surf_offset
);
1561 brw_update_sol_surface(struct brw_context
*brw
,
1562 struct gl_buffer_object
*buffer_obj
,
1563 uint32_t *out_offset
, unsigned num_vector_components
,
1564 unsigned stride_dwords
, unsigned offset_dwords
);
1565 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1566 struct gl_linked_shader
*shader
,
1567 struct brw_stage_state
*stage_state
,
1568 struct brw_stage_prog_data
*prog_data
);
1569 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1570 struct gl_linked_shader
*shader
,
1571 struct brw_stage_state
*stage_state
,
1572 struct brw_stage_prog_data
*prog_data
);
1573 void brw_upload_image_surfaces(struct brw_context
*brw
,
1574 struct gl_linked_shader
*shader
,
1575 struct brw_stage_state
*stage_state
,
1576 struct brw_stage_prog_data
*prog_data
);
1578 /* brw_surface_formats.c */
1579 bool brw_render_target_supported(struct brw_context
*brw
,
1580 struct gl_renderbuffer
*rb
);
1581 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1583 /* brw_performance_monitor.c */
1584 void brw_init_performance_monitors(struct brw_context
*brw
);
1585 void brw_dump_perf_monitors(struct brw_context
*brw
);
1586 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1587 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1589 /* intel_buffer_objects.c */
1590 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1591 const char *bo_name
);
1592 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1593 const char *bo_name
);
1595 /* intel_extensions.c */
1596 extern void intelInitExtensions(struct gl_context
*ctx
);
1599 extern int intel_translate_shadow_compare_func(GLenum func
);
1600 extern int intel_translate_compare_func(GLenum func
);
1601 extern int intel_translate_stencil_op(GLenum op
);
1602 extern int intel_translate_logic_op(GLenum opcode
);
1604 /* intel_syncobj.c */
1605 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1608 struct gl_transform_feedback_object
*
1609 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1611 brw_delete_transform_feedback(struct gl_context
*ctx
,
1612 struct gl_transform_feedback_object
*obj
);
1614 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1615 struct gl_transform_feedback_object
*obj
);
1617 brw_end_transform_feedback(struct gl_context
*ctx
,
1618 struct gl_transform_feedback_object
*obj
);
1620 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1621 struct gl_transform_feedback_object
*obj
,
1624 /* gen7_sol_state.c */
1626 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1627 struct gl_transform_feedback_object
*obj
);
1629 gen7_end_transform_feedback(struct gl_context
*ctx
,
1630 struct gl_transform_feedback_object
*obj
);
1632 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1633 struct gl_transform_feedback_object
*obj
);
1635 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1636 struct gl_transform_feedback_object
*obj
);
1640 hsw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1641 struct gl_transform_feedback_object
*obj
);
1643 hsw_end_transform_feedback(struct gl_context
*ctx
,
1644 struct gl_transform_feedback_object
*obj
);
1646 hsw_pause_transform_feedback(struct gl_context
*ctx
,
1647 struct gl_transform_feedback_object
*obj
);
1649 hsw_resume_transform_feedback(struct gl_context
*ctx
,
1650 struct gl_transform_feedback_object
*obj
);
1652 /* brw_blorp_blit.cpp */
1654 brw_blorp_framebuffer(struct brw_context
*brw
,
1655 struct gl_framebuffer
*readFb
,
1656 struct gl_framebuffer
*drawFb
,
1657 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1658 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1659 GLbitfield mask
, GLenum filter
);
1662 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1663 struct gl_renderbuffer
*src_rb
,
1664 struct gl_texture_image
*dst_image
,
1666 int srcX0
, int srcY0
,
1667 int dstX0
, int dstY0
,
1668 int width
, int height
);
1670 /* gen6_multisample_state.c */
1672 gen6_determine_sample_mask(struct brw_context
*brw
);
1675 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1676 unsigned num_samples
);
1678 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1680 gen6_get_sample_position(struct gl_context
*ctx
,
1681 struct gl_framebuffer
*fb
,
1685 gen6_set_sample_maps(struct gl_context
*ctx
);
1687 /* gen8_multisample_state.c */
1688 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1689 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1693 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1694 unsigned hs_size
, unsigned ds_size
,
1695 unsigned gs_size
, unsigned fs_size
);
1698 gen6_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1699 bool gs_present
, unsigned gs_size
);
1701 gen7_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1702 bool gs_present
, bool tess_present
);
1706 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1708 brw_check_for_reset(struct brw_context
*brw
);
1712 brw_init_compute_functions(struct dd_function_table
*functions
);
1714 /*======================================================================
1715 * Inline conversion functions. These are better-typed than the
1716 * macros used previously:
1718 static inline struct brw_context
*
1719 brw_context( struct gl_context
*ctx
)
1721 return (struct brw_context
*)ctx
;
1724 static inline struct brw_vertex_program
*
1725 brw_vertex_program(struct gl_vertex_program
*p
)
1727 return (struct brw_vertex_program
*) p
;
1730 static inline const struct brw_vertex_program
*
1731 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1733 return (const struct brw_vertex_program
*) p
;
1736 static inline struct brw_tess_ctrl_program
*
1737 brw_tess_ctrl_program(struct gl_tess_ctrl_program
*p
)
1739 return (struct brw_tess_ctrl_program
*) p
;
1742 static inline struct brw_tess_eval_program
*
1743 brw_tess_eval_program(struct gl_tess_eval_program
*p
)
1745 return (struct brw_tess_eval_program
*) p
;
1748 static inline struct brw_geometry_program
*
1749 brw_geometry_program(struct gl_geometry_program
*p
)
1751 return (struct brw_geometry_program
*) p
;
1754 static inline struct brw_fragment_program
*
1755 brw_fragment_program(struct gl_fragment_program
*p
)
1757 return (struct brw_fragment_program
*) p
;
1760 static inline const struct brw_fragment_program
*
1761 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1763 return (const struct brw_fragment_program
*) p
;
1766 static inline struct brw_compute_program
*
1767 brw_compute_program(struct gl_compute_program
*p
)
1769 return (struct brw_compute_program
*) p
;
1773 * Pre-gen6, the register file of the EUs was shared between threads,
1774 * and each thread used some subset allocated on a 16-register block
1775 * granularity. The unit states wanted these block counts.
1778 brw_register_blocks(int reg_count
)
1780 return ALIGN(reg_count
, 16) / 16 - 1;
1783 static inline uint32_t
1784 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1785 uint32_t prog_offset
)
1787 if (brw
->gen
>= 5) {
1788 /* Using state base address. */
1792 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1796 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1798 return brw
->cache
.bo
->offset64
+ prog_offset
;
1801 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1802 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1803 struct exec_list
*instructions
);
1805 extern const char * const conditional_modifier
[16];
1806 extern const char *const pred_ctrl_align16
[16];
1809 brw_emit_depthbuffer(struct brw_context
*brw
);
1812 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1813 struct intel_mipmap_tree
*depth_mt
,
1814 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1815 uint32_t depth_surface_type
,
1816 struct intel_mipmap_tree
*stencil_mt
,
1817 bool hiz
, bool separate_stencil
,
1818 uint32_t width
, uint32_t height
,
1819 uint32_t tile_x
, uint32_t tile_y
);
1822 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1823 struct intel_mipmap_tree
*depth_mt
,
1824 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1825 uint32_t depth_surface_type
,
1826 struct intel_mipmap_tree
*stencil_mt
,
1827 bool hiz
, bool separate_stencil
,
1828 uint32_t width
, uint32_t height
,
1829 uint32_t tile_x
, uint32_t tile_y
);
1832 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1833 struct intel_mipmap_tree
*depth_mt
,
1834 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1835 uint32_t depth_surface_type
,
1836 struct intel_mipmap_tree
*stencil_mt
,
1837 bool hiz
, bool separate_stencil
,
1838 uint32_t width
, uint32_t height
,
1839 uint32_t tile_x
, uint32_t tile_y
);
1841 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1842 struct intel_mipmap_tree
*depth_mt
,
1843 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1844 uint32_t depth_surface_type
,
1845 struct intel_mipmap_tree
*stencil_mt
,
1846 bool hiz
, bool separate_stencil
,
1847 uint32_t width
, uint32_t height
,
1848 uint32_t tile_x
, uint32_t tile_y
);
1850 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1851 unsigned int level
, unsigned int layer
, enum blorp_hiz_op op
);
1853 uint32_t get_hw_prim_for_gl_prim(int mode
);
1856 gen6_upload_push_constants(struct brw_context
*brw
,
1857 const struct gl_program
*prog
,
1858 const struct brw_stage_prog_data
*prog_data
,
1859 struct brw_stage_state
*stage_state
,
1860 enum aub_state_struct_type type
);
1863 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
1864 const struct intel_mipmap_tree
*mt
);
1866 /* brw_pipe_control.c */
1867 int brw_init_pipe_control(struct brw_context
*brw
,
1868 const struct brw_device_info
*info
);
1869 void brw_fini_pipe_control(struct brw_context
*brw
);
1871 void brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
);
1872 void brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
1873 drm_intel_bo
*bo
, uint32_t offset
,
1874 uint32_t imm_lower
, uint32_t imm_upper
);
1875 void brw_emit_mi_flush(struct brw_context
*brw
);
1876 void brw_emit_post_sync_nonzero_flush(struct brw_context
*brw
);
1877 void brw_emit_depth_stall_flushes(struct brw_context
*brw
);
1878 void gen7_emit_vs_workaround_flush(struct brw_context
*brw
);
1879 void gen7_emit_cs_stall_flush(struct brw_context
*brw
);
1881 /* brw_queryformat.c */
1882 void brw_query_internal_format(struct gl_context
*ctx
, GLenum target
,
1883 GLenum internalFormat
, GLenum pname
,