2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
38 #include "main/imports.h"
39 #include "main/macros.h"
41 #include "main/mtypes.h"
42 #include "brw_structs.h"
46 /* Evil hack for using libdrm in a c++ compiler. */
51 #include <intel_bufmgr.h>
61 #include "intel_debug.h"
62 #include "intel_screen.h"
63 #include "intel_tex_obj.h"
67 * URB - uniform resource buffer. A mid-sized buffer which is
68 * partitioned between the fixed function units and used for passing
69 * values (vertices, primitives, constants) between them.
71 * CURBE - constant URB entry. An urb region (entry) used to hold
72 * constant values which the fixed function units can be instructed to
73 * preload into the GRF when spawning a thread.
75 * VUE - vertex URB entry. An urb entry holding a vertex and usually
76 * a vertex header. The header contains control information and
77 * things like primitive type, Begin/end flags and clip codes.
79 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
80 * unit holding rasterization and interpolation parameters.
82 * GRF - general register file. One of several register files
83 * addressable by programmed threads. The inputs (r0, payload, curbe,
84 * urb) of the thread are preloaded to this area before the thread is
85 * spawned. The registers are individually 8 dwords wide and suitable
86 * for general usage. Registers holding thread input values are not
87 * special and may be overwritten.
89 * MRF - message register file. Threads communicate (and terminate)
90 * by sending messages. Message parameters are placed in contiguous
91 * MRF registers. All program output is via these messages. URB
92 * entries are populated by sending a message to the shared URB
93 * function containing the new data, together with a control word,
94 * often an unmodified copy of R0.
96 * R0 - GRF register 0. Typically holds control information used when
97 * sending messages to other threads.
99 * EU or GEN4 EU: The name of the programmable subsystem of the
100 * i965 hardware. Threads are executed by the EU, the registers
101 * described above are part of the EU architecture.
103 * Fixed function units:
105 * CS - Command streamer. Notional first unit, little software
106 * interaction. Holds the URB entries used for constant data, ie the
109 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
110 * this unit is responsible for pulling vertices out of vertex buffers
111 * in vram and injecting them into the processing pipe as VUEs. If
112 * enabled, it first passes them to a VS thread which is a good place
113 * for the driver to implement any active vertex shader.
115 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
116 * enabled, incoming strips etc are passed to GS threads in individual
117 * line/triangle/point units. The GS thread may perform arbitary
118 * computation and emit whatever primtives with whatever vertices it
119 * chooses. This makes GS an excellent place to implement GL's
120 * unfilled polygon modes, though of course it is capable of much
121 * more. Additionally, GS is used to translate away primitives not
122 * handled by latter units, including Quads and Lineloops.
124 * CS - Clipper. Mesa's clipping algorithms are imported to run on
125 * this unit. The fixed function part performs cliptesting against
126 * the 6 fixed clipplanes and makes descisions on whether or not the
127 * incoming primitive needs to be passed to a thread for clipping.
128 * User clip planes are handled via cooperation with the VS thread.
130 * SF - Strips Fans or Setup: Triangles are prepared for
131 * rasterization. Interpolation coefficients are calculated.
132 * Flatshading and two-side lighting usually performed here.
134 * WM - Windower. Interpolation of vertex attributes performed here.
135 * Fragment shader implemented here. SIMD aspects of EU taken full
136 * advantage of, as pixels are processed in blocks of 16.
138 * CC - Color Calculator. No EU threads associated with this unit.
139 * Handles blending and (presumably) depth and stencil testing.
142 #define BRW_MAX_CURBE (32*16)
145 struct brw_instruction
;
146 struct brw_vs_prog_key
;
147 struct brw_vec4_prog_key
;
148 struct brw_wm_prog_key
;
149 struct brw_wm_prog_data
;
153 BRW_STATE_FRAGMENT_PROGRAM
,
154 BRW_STATE_GEOMETRY_PROGRAM
,
155 BRW_STATE_VERTEX_PROGRAM
,
156 BRW_STATE_CURBE_OFFSETS
,
157 BRW_STATE_REDUCED_PRIMITIVE
,
162 BRW_STATE_VS_BINDING_TABLE
,
163 BRW_STATE_GS_BINDING_TABLE
,
164 BRW_STATE_PS_BINDING_TABLE
,
168 BRW_STATE_INDEX_BUFFER
,
169 BRW_STATE_VS_CONSTBUF
,
170 BRW_STATE_GS_CONSTBUF
,
171 BRW_STATE_PROGRAM_CACHE
,
172 BRW_STATE_STATE_BASE_ADDRESS
,
173 BRW_STATE_VUE_MAP_VS
,
174 BRW_STATE_VUE_MAP_GEOM_OUT
,
175 BRW_STATE_TRANSFORM_FEEDBACK
,
176 BRW_STATE_RASTERIZER_DISCARD
,
178 BRW_STATE_UNIFORM_BUFFER
,
179 BRW_STATE_ATOMIC_BUFFER
,
180 BRW_STATE_META_IN_PROGRESS
,
181 BRW_STATE_INTERPOLATION_MAP
,
182 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
186 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
187 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
188 #define BRW_NEW_GEOMETRY_PROGRAM (1 << BRW_STATE_GEOMETRY_PROGRAM)
189 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
190 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
191 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
192 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
193 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
194 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
195 #define BRW_NEW_SURFACES (1 << BRW_STATE_SURFACES)
196 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
197 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
198 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
199 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
200 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
202 * Used for any batch entry with a relocated pointer that will be used
203 * by any 3D rendering.
205 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
206 /** \see brw.state.depth_region */
207 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
208 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
209 #define BRW_NEW_GS_CONSTBUF (1 << BRW_STATE_GS_CONSTBUF)
210 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
211 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
212 #define BRW_NEW_VUE_MAP_VS (1 << BRW_STATE_VUE_MAP_VS)
213 #define BRW_NEW_VUE_MAP_GEOM_OUT (1 << BRW_STATE_VUE_MAP_GEOM_OUT)
214 #define BRW_NEW_TRANSFORM_FEEDBACK (1 << BRW_STATE_TRANSFORM_FEEDBACK)
215 #define BRW_NEW_RASTERIZER_DISCARD (1 << BRW_STATE_RASTERIZER_DISCARD)
216 #define BRW_NEW_STATS_WM (1 << BRW_STATE_STATS_WM)
217 #define BRW_NEW_UNIFORM_BUFFER (1 << BRW_STATE_UNIFORM_BUFFER)
218 #define BRW_NEW_ATOMIC_BUFFER (1 << BRW_STATE_ATOMIC_BUFFER)
219 #define BRW_NEW_META_IN_PROGRESS (1 << BRW_STATE_META_IN_PROGRESS)
220 #define BRW_NEW_INTERPOLATION_MAP (1 << BRW_STATE_INTERPOLATION_MAP)
221 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1 << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
223 struct brw_state_flags
{
224 /** State update flags signalled by mesa internals */
227 * State update flags signalled as the result of brw_tracked_state updates
230 /** State update flags signalled by brw_state_cache.c searches */
234 #define AUB_TRACE_TYPE_MASK 0x0000ff00
235 #define AUB_TRACE_TYPE_NOTYPE (0 << 8)
236 #define AUB_TRACE_TYPE_BATCH (1 << 8)
237 #define AUB_TRACE_TYPE_VERTEX_BUFFER (5 << 8)
238 #define AUB_TRACE_TYPE_2D_MAP (6 << 8)
239 #define AUB_TRACE_TYPE_CUBE_MAP (7 << 8)
240 #define AUB_TRACE_TYPE_VOLUME_MAP (9 << 8)
241 #define AUB_TRACE_TYPE_1D_MAP (10 << 8)
242 #define AUB_TRACE_TYPE_CONSTANT_BUFFER (11 << 8)
243 #define AUB_TRACE_TYPE_CONSTANT_URB (12 << 8)
244 #define AUB_TRACE_TYPE_INDEX_BUFFER (13 << 8)
245 #define AUB_TRACE_TYPE_GENERAL (14 << 8)
246 #define AUB_TRACE_TYPE_SURFACE (15 << 8)
249 * state_struct_type enum values are encoded with the top 16 bits representing
250 * the type to be delivered to the .aub file, and the bottom 16 bits
251 * representing the subtype. This macro performs the encoding.
253 #define ENCODE_SS_TYPE(type, subtype) (((type) << 16) | (subtype))
255 enum state_struct_type
{
256 AUB_TRACE_VS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 1),
257 AUB_TRACE_GS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 2),
258 AUB_TRACE_CLIP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 3),
259 AUB_TRACE_SF_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 4),
260 AUB_TRACE_WM_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 5),
261 AUB_TRACE_CC_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 6),
262 AUB_TRACE_CLIP_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 7),
263 AUB_TRACE_SF_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 8),
264 AUB_TRACE_CC_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x9),
265 AUB_TRACE_SAMPLER_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xa),
266 AUB_TRACE_KERNEL_INSTRUCTIONS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xb),
267 AUB_TRACE_SCRATCH_SPACE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xc),
268 AUB_TRACE_SAMPLER_DEFAULT_COLOR
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xd),
270 AUB_TRACE_SCISSOR_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x15),
271 AUB_TRACE_BLEND_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x16),
272 AUB_TRACE_DEPTH_STENCIL_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x17),
274 AUB_TRACE_VERTEX_BUFFER
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_VERTEX_BUFFER
, 0),
275 AUB_TRACE_BINDING_TABLE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x100),
276 AUB_TRACE_SURFACE_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x200),
277 AUB_TRACE_VS_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 0),
278 AUB_TRACE_WM_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 1),
282 * Decode a state_struct_type value to determine the type that should be
283 * stored in the .aub file.
285 static inline uint32_t AUB_TRACE_TYPE(enum state_struct_type ss_type
)
287 return (ss_type
& 0xFFFF0000) >> 16;
291 * Decode a state_struct_type value to determine the subtype that should be
292 * stored in the .aub file.
294 static inline uint32_t AUB_TRACE_SUBTYPE(enum state_struct_type ss_type
)
296 return ss_type
& 0xFFFF;
299 /** Subclass of Mesa vertex program */
300 struct brw_vertex_program
{
301 struct gl_vertex_program program
;
306 /** Subclass of Mesa geometry program */
307 struct brw_geometry_program
{
308 struct gl_geometry_program program
;
309 unsigned id
; /**< serial no. to identify geom progs, never re-used */
313 /** Subclass of Mesa fragment program */
314 struct brw_fragment_program
{
315 struct gl_fragment_program program
;
316 GLuint id
; /**< serial no. to identify frag progs, never re-used */
320 /** Subclass of Mesa compute program */
321 struct brw_compute_program
{
322 struct gl_compute_program program
;
323 unsigned id
; /**< serial no. to identify compute progs, never re-used */
328 struct gl_shader base
;
333 /* Note: If adding fields that need anything besides a normal memcmp() for
334 * comparing them, be sure to go fix the the stage-specific
335 * prog_data_compare().
337 struct brw_stage_prog_data
{
339 /** size of our binding table. */
343 * surface indices for the various groups of surfaces
345 uint32_t pull_constants_start
;
346 uint32_t texture_start
;
347 uint32_t gather_texture_start
;
350 uint32_t shader_time_start
;
355 /* Data about a particular attempt to compile a program. Note that
356 * there can be many of these, each in a different GL state
357 * corresponding to a different brw_wm_prog_key struct, with different
360 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
363 struct brw_wm_prog_data
{
364 struct brw_stage_prog_data base
;
366 GLuint curb_read_length
;
367 GLuint num_varying_inputs
;
369 GLuint first_curbe_grf
;
370 GLuint first_curbe_grf_16
;
372 GLuint reg_blocks_16
;
373 GLuint total_scratch
;
377 * surface indices the WM-specific surfaces
379 uint32_t render_target_start
;
383 GLuint nr_params
; /**< number of float params/constants */
384 GLuint nr_pull_params
;
386 bool uses_pos_offset
;
388 uint32_t prog_offset_16
;
391 * Mask of which interpolation modes are required by the fragment shader.
392 * Used in hardware setup on gen6+.
394 uint32_t barycentric_interp_modes
;
397 * Map from gl_varying_slot to the position within the FS setup data
398 * payload where the varying's attribute vertex deltas should be delivered.
399 * For varying slots that are not used by the FS, the value is -1.
401 int urb_setup
[VARYING_SLOT_MAX
];
403 /* Pointers to tracked values (only valid once
404 * _mesa_load_state_parameters has been called at runtime).
406 * These must be the last fields of the struct (see
407 * brw_wm_prog_data_compare()).
410 const float **pull_param
;
414 * Enum representing the i965-specific vertex results that don't correspond
415 * exactly to any element of gl_varying_slot. The values of this enum are
416 * assigned such that they don't conflict with gl_varying_slot.
420 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
421 BRW_VARYING_SLOT_PAD
,
423 * Technically this is not a varying but just a placeholder that
424 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
425 * builtin variable to be compiled correctly. see compile_sf_prog() for
428 BRW_VARYING_SLOT_PNTC
,
429 BRW_VARYING_SLOT_COUNT
434 * Data structure recording the relationship between the gl_varying_slot enum
435 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
436 * single octaword within the VUE (128 bits).
438 * Note that each BRW register contains 256 bits (2 octawords), so when
439 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
440 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
441 * in a vertex shader), each register corresponds to a single VUE slot, since
442 * it contains data for two separate vertices.
446 * Bitfield representing all varying slots that are (a) stored in this VUE
447 * map, and (b) actually written by the shader. Does not include any of
448 * the additional varying slots defined in brw_varying_slot.
450 GLbitfield64 slots_valid
;
453 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
454 * not stored in a slot (because they are not written, or because
455 * additional processing is applied before storing them in the VUE), the
458 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
461 * Map from VUE slot to gl_varying_slot value. For slots that do not
462 * directly correspond to a gl_varying_slot, the value comes from
465 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
466 * simplifies code that uses the value stored in slot_to_varying to
467 * create a bit mask).
469 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
472 * Total number of VUE slots in use
478 * Convert a VUE slot number into a byte offset within the VUE.
480 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
486 * Convert a vertex output (brw_varying_slot) into a byte offset within the
489 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
492 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
495 void brw_compute_vue_map(struct brw_context
*brw
, struct brw_vue_map
*vue_map
,
496 GLbitfield64 slots_valid
);
500 * Bitmask indicating which fragment shader inputs represent varyings (and
501 * hence have to be delivered to the fragment shader by the SF/SBE stage).
503 #define BRW_FS_VARYING_INPUT_MASK \
504 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
505 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
509 * Mapping of VUE map slots to interpolation modes.
511 struct interpolation_mode_map
{
512 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
515 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
517 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
518 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
524 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
526 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
527 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
534 struct brw_sf_prog_data
{
535 GLuint urb_read_length
;
538 /* Each vertex may have upto 12 attributes, 4 components each,
539 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
542 * Actually we use 4 for each, so call it 12 rows.
544 GLuint urb_entry_size
;
549 * We always program SF to start reading at an offset of 1 (2 varying slots)
550 * from the start of the vertex URB entry. This causes it to skip:
551 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
552 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
554 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
557 struct brw_clip_prog_data
{
558 GLuint curb_read_length
; /* user planes? */
560 GLuint urb_read_length
;
564 struct brw_ff_gs_prog_data
{
565 GLuint urb_read_length
;
569 * Gen6 transform feedback: Amount by which the streaming vertex buffer
570 * indices should be incremented each time the GS is invoked.
572 unsigned svbi_postincrement_value
;
576 /* Note: brw_vec4_prog_data_compare() must be updated when adding fields to
579 struct brw_vec4_prog_data
{
580 struct brw_stage_prog_data base
;
581 struct brw_vue_map vue_map
;
584 * Register where the thread expects to find input data from the URB
585 * (typically uniforms, followed by per-vertex inputs).
587 unsigned dispatch_grf_start_reg
;
589 GLuint curb_read_length
;
590 GLuint urb_read_length
;
592 GLuint nr_params
; /**< number of float params/constants */
593 GLuint nr_pull_params
; /**< number of dwords referenced by pull_param[] */
594 GLuint total_scratch
;
596 /* Used for calculating urb partitions. In the VS, this is the size of the
597 * URB entry used for both input and output to the thread. In the GS, this
598 * is the size of the URB entry used for output.
600 GLuint urb_entry_size
;
602 /* These pointers must appear last. See brw_vec4_prog_data_compare(). */
604 const float **pull_param
;
608 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
611 struct brw_vs_prog_data
{
612 struct brw_vec4_prog_data base
;
614 GLbitfield64 inputs_read
;
620 /* Note: brw_gs_prog_data_compare() must be updated when adding fields to
623 struct brw_gs_prog_data
625 struct brw_vec4_prog_data base
;
628 * Size of an output vertex, measured in HWORDS (32 bytes).
630 unsigned output_vertex_size_hwords
;
632 unsigned output_topology
;
635 * Size of the control data (cut bits or StreamID bits), in hwords (32
636 * bytes). 0 if there is no control data.
638 unsigned control_data_header_size_hwords
;
641 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
642 * if the control data is StreamID bits, or
643 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
644 * Ignored if control_data_header_size is 0.
646 unsigned control_data_format
;
648 bool include_primitive_id
;
651 * True if the thread should be dispatched in DUAL_INSTANCE mode, false if
652 * it should be dispatched in DUAL_OBJECT mode.
654 bool dual_instanced_dispatch
;
657 /** Number of texture sampler units */
658 #define BRW_MAX_TEX_UNIT 32
660 /** Max number of render targets in a shader */
661 #define BRW_MAX_DRAW_BUFFERS 8
663 /** Max number of atomic counter buffer objects in a shader */
664 #define BRW_MAX_ABO 16
667 * Max number of binding table entries used for stream output.
669 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
670 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
672 * On Gen6, the size of transform feedback data is limited not by the number
673 * of components but by the number of binding table entries we set aside. We
674 * use one binding table entry for a float, one entry for a vector, and one
675 * entry per matrix column. Since the only way we can communicate our
676 * transform feedback capabilities to the client is via
677 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
678 * worst case, in which all the varyings are floats, so we use up one binding
679 * table entry per component. Therefore we need to set aside at least 64
680 * binding table entries for use by transform feedback.
682 * Note: since we don't currently pack varyings, it is currently impossible
683 * for the client to actually use up all of these binding table entries--if
684 * all of their varyings were floats, they would run out of varying slots and
685 * fail to link. But that's a bug, so it seems prudent to go ahead and
686 * allocate the number of binding table entries we will need once the bug is
689 #define BRW_MAX_SOL_BINDINGS 64
691 /** Maximum number of actual buffers used for stream output */
692 #define BRW_MAX_SOL_BUFFERS 4
694 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
695 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
698 2 /* shader time, pull constants */)
700 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
701 #define BRW_MAX_GEN6_GS_SURFACES SURF_INDEX_GEN6_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
704 * Stride in bytes between shader_time entries.
706 * We separate entries by a cacheline to reduce traffic between EUs writing to
709 #define SHADER_TIME_STRIDE 64
716 BRW_BLORP_CONST_COLOR_PROG
,
721 BRW_SF_UNIT
, /* scissor state on gen6 */
734 struct brw_cache_item
{
736 * Effectively part of the key, cache_id identifies what kind of state
737 * buffer is involved, and also which brw->state.dirty.cache flag should
738 * be set when this cache item is chosen.
740 enum brw_cache_id cache_id
;
741 /** 32-bit hash of the key data */
743 GLuint key_size
; /* for variable-sized keys */
750 struct brw_cache_item
*next
;
754 typedef bool (*cache_aux_compare_func
)(const void *a
, const void *b
);
755 typedef void (*cache_aux_free_func
)(const void *aux
);
758 struct brw_context
*brw
;
760 struct brw_cache_item
**items
;
762 GLuint size
, n_items
;
764 uint32_t next_offset
;
768 * Optional functions used in determining whether the prog_data for a new
769 * cache item matches an existing cache item (in case there's relevant data
770 * outside of the prog_data). If NULL, a plain memcmp is done.
772 cache_aux_compare_func aux_compare
[BRW_MAX_CACHE
];
773 /** Optional functions for freeing other pointers attached to a prog_data. */
774 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
778 /* Considered adding a member to this struct to document which flags
779 * an update might raise so that ordering of the state atoms can be
780 * checked or derived at runtime. Dropped the idea in favor of having
781 * a debug mode where the state is monitored for flags which are
782 * raised that have already been tested against.
784 struct brw_tracked_state
{
785 struct brw_state_flags dirty
;
786 void (*emit
)( struct brw_context
*brw
);
789 enum shader_time_shader_type
{
805 /* Flags for brw->state.cache.
807 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
808 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
809 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
810 #define CACHE_NEW_BLORP_BLIT_PROG (1<<BRW_BLORP_BLIT_PROG)
811 #define CACHE_NEW_BLORP_CONST_COLOR_PROG (1<<BRW_BLORP_CONST_COLOR_PROG)
812 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
813 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
814 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
815 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
816 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
817 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
818 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
819 #define CACHE_NEW_FF_GS_UNIT (1<<BRW_FF_GS_UNIT)
820 #define CACHE_NEW_FF_GS_PROG (1<<BRW_FF_GS_PROG)
821 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
822 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
823 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
824 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
826 struct brw_cached_batch_item
{
827 struct header
*header
;
829 struct brw_cached_batch_item
*next
;
832 struct brw_vertex_buffer
{
833 /** Buffer object containing the uploaded vertex data */
836 /** Byte stride between elements in the uploaded array */
840 struct brw_vertex_element
{
841 const struct gl_client_array
*glarray
;
845 /** The corresponding Mesa vertex attribute */
846 gl_vert_attrib attrib
;
847 /** Offset of the first element within the buffer object */
851 struct brw_query_object
{
852 struct gl_query_object Base
;
854 /** Last query BO associated with this query. */
857 /** Last index in bo with query data for this object. */
861 struct intel_sync_object
{
862 struct gl_sync_object Base
;
864 /** Batch associated with this sync object */
874 struct intel_batchbuffer
{
875 /** Current batchbuffer being queued up. */
877 /** Last BO submitted to the hardware. Used for glFinish(). */
878 drm_intel_bo
*last_bo
;
879 /** BO for post-sync nonzero writes for gen6 workaround. */
880 drm_intel_bo
*workaround_bo
;
881 bool need_workaround_flush
;
883 struct cached_batch_item
*cached_items
;
885 uint16_t emit
, total
;
886 uint16_t used
, reserved_space
;
889 #define BATCH_SZ (8192*sizeof(uint32_t))
891 uint32_t state_batch_offset
;
892 enum brw_gpu_ring ring
;
893 bool needs_sol_reset
;
901 #define BRW_MAX_XFB_STREAMS 4
903 struct brw_transform_feedback_object
{
904 struct gl_transform_feedback_object base
;
906 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
907 drm_intel_bo
*offset_bo
;
909 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
912 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
913 GLenum primitive_mode
;
916 * Count of primitives generated during this transform feedback operation.
919 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
920 drm_intel_bo
*prim_count_bo
;
921 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
925 * Number of vertices written between last Begin/EndTransformFeedback().
927 * Used to implement DrawTransformFeedback().
929 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
930 bool vertices_written_valid
;
934 * Data shared between each programmable stage in the pipeline (vs, gs, and
937 struct brw_stage_state
939 struct brw_stage_prog_data
*prog_data
;
942 * Optional scratch buffer used to store spilled register values and
943 * variably-indexed GRF arrays.
945 drm_intel_bo
*scratch_bo
;
947 /** Pull constant buffer */
948 drm_intel_bo
*const_bo
;
950 /** Offset in the program cache to the program */
951 uint32_t prog_offset
;
953 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
954 uint32_t state_offset
;
956 uint32_t push_const_offset
; /* Offset in the batchbuffer */
957 int push_const_size
; /* in 256-bit register increments */
959 /* Binding table: pointers to SURFACE_STATE entries. */
960 uint32_t bind_bo_offset
;
961 uint32_t surf_offset
[BRW_MAX_SURFACES
];
963 /** SAMPLER_STATE count and table offset */
964 uint32_t sampler_count
;
965 uint32_t sampler_offset
;
967 /** Offsets in the batch to sampler default colors (texture border color) */
968 uint32_t sdc_offset
[BRW_MAX_TEX_UNIT
];
973 * brw_context is derived from gl_context.
977 struct gl_context ctx
; /**< base class, must be first field */
981 void (*update_texture_surface
)(struct gl_context
*ctx
,
983 uint32_t *surf_offset
,
985 void (*update_renderbuffer_surface
)(struct brw_context
*brw
,
986 struct gl_renderbuffer
*rb
,
989 void (*update_null_renderbuffer_surface
)(struct brw_context
*brw
,
992 void (*create_raw_surface
)(struct brw_context
*brw
,
996 uint32_t *out_offset
,
998 void (*emit_buffer_surface_state
)(struct brw_context
*brw
,
999 uint32_t *out_offset
,
1001 unsigned buffer_offset
,
1002 unsigned surface_format
,
1003 unsigned buffer_size
,
1008 /** Upload a SAMPLER_STATE table. */
1009 void (*upload_sampler_state_table
)(struct brw_context
*brw
,
1010 struct gl_program
*prog
,
1011 uint32_t sampler_count
,
1012 uint32_t *sst_offset
,
1013 uint32_t *sdc_offset
);
1016 * Send the appropriate state packets to configure depth, stencil, and
1017 * HiZ buffers (i965+ only)
1019 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
1020 struct intel_mipmap_tree
*depth_mt
,
1021 uint32_t depth_offset
,
1022 uint32_t depthbuffer_format
,
1023 uint32_t depth_surface_type
,
1024 struct intel_mipmap_tree
*stencil_mt
,
1025 bool hiz
, bool separate_stencil
,
1026 uint32_t width
, uint32_t height
,
1027 uint32_t tile_x
, uint32_t tile_y
);
1033 drm_intel_context
*hw_ctx
;
1036 * Number of resets observed in the system at context creation.
1038 * This is tracked in the context so that we can determine that another
1039 * reset has occured.
1041 uint32_t reset_count
;
1043 struct intel_batchbuffer batch
;
1049 uint32_t buffer_len
;
1050 uint32_t buffer_offset
;
1055 * Set if rendering has occured to the drawable's front buffer.
1057 * This is used in the DRI2 case to detect that glFlush should also copy
1058 * the contents of the fake front buffer to the real front buffer.
1060 bool front_buffer_dirty
;
1063 * Track whether front-buffer rendering is currently enabled
1065 * A separate flag is used to track this in order to support MRT more
1068 bool is_front_buffer_rendering
;
1071 * Track whether front-buffer is the current read target.
1073 * This is closely associated with is_front_buffer_rendering, but may
1074 * be set separately. The DRI2 fake front buffer must be referenced
1077 bool is_front_buffer_reading
;
1079 /** Framerate throttling: @{ */
1080 drm_intel_bo
*first_post_swapbuffers_batch
;
1091 bool always_flush_batch
;
1092 bool always_flush_cache
;
1093 bool disable_throttling
;
1095 bool disable_derivative_optimization
;
1097 driOptionCache optionCache
;
1100 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
1102 GLenum reduced_primitive
;
1105 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
1106 * variable is set, this is the flag indicating to do expensive work that
1107 * might lead to a perf_debug() call.
1111 uint32_t max_gtt_map_object_size
;
1121 bool has_separate_stencil
;
1122 bool must_use_separate_stencil
;
1125 bool has_surface_tile_offset
;
1127 bool has_negative_rhw_bug
;
1131 * Some versions of Gen hardware don't do centroid interpolation correctly
1132 * on unlit pixels, causing incorrect values for derivatives near triangle
1133 * edges. Enabling this flag causes the fragment shader to use
1134 * non-centroid interpolation for unlit pixels, at the expense of two extra
1135 * fragment shader instructions.
1137 bool needs_unlit_centroid_workaround
;
1141 struct brw_state_flags dirty
;
1144 struct brw_cache cache
;
1145 struct brw_cached_batch_item
*cached_batch_items
;
1147 /* Whether a meta-operation is in progress. */
1148 bool meta_in_progress
;
1151 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
1152 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
1154 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
1158 /* Summary of size and varying of active arrays, so we can check
1159 * for changes to this state:
1161 unsigned int min_index
, max_index
;
1163 /* Offset from start of vertex buffer so we can avoid redefining
1164 * the same VB packed over and over again.
1166 unsigned int start_vertex_bias
;
1171 * Index buffer for this draw_prims call.
1173 * Updates are signaled by BRW_NEW_INDICES.
1175 const struct _mesa_index_buffer
*ib
;
1177 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
1181 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
1182 * avoid re-uploading the IB packet over and over if we're actually
1183 * referencing the same index buffer.
1185 unsigned int start_vertex_offset
;
1188 /* Active vertex program:
1190 const struct gl_vertex_program
*vertex_program
;
1191 const struct gl_geometry_program
*geometry_program
;
1192 const struct gl_fragment_program
*fragment_program
;
1194 /* hw-dependent 3DSTATE_VF_STATISTICS opcode */
1195 uint32_t CMD_VF_STATISTICS
;
1196 /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
1197 uint32_t CMD_PIPELINE_SELECT
;
1200 * Platform specific constants containing the maximum number of threads
1201 * for each pipeline stage.
1207 /* BRW_NEW_URB_ALLOCATIONS:
1210 GLuint vsize
; /* vertex size plus header in urb registers */
1211 GLuint csize
; /* constant buffer size in urb registers */
1212 GLuint sfsize
; /* setup data size in urb registers */
1216 GLuint min_vs_entries
; /* Minimum number of VS entries */
1217 GLuint max_vs_entries
; /* Maximum number of VS entries */
1218 GLuint max_gs_entries
; /* Maximum number of GS entries */
1220 GLuint nr_vs_entries
;
1221 GLuint nr_gs_entries
;
1222 GLuint nr_clip_entries
;
1223 GLuint nr_sf_entries
;
1224 GLuint nr_cs_entries
;
1231 GLuint size
; /* Hardware URB size, in KB. */
1233 /* gen6: True if the most recently sent _3DSTATE_URB message allocated
1234 * URB space for the GS.
1236 bool gen6_gs_previously_active
;
1240 /* BRW_NEW_CURBE_OFFSETS:
1243 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1244 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1251 drm_intel_bo
*curbe_bo
;
1252 /** Offset within curbe_bo of space for current curbe entry */
1253 GLuint curbe_offset
;
1254 /** Offset within curbe_bo of space for next curbe entry */
1255 GLuint curbe_next_offset
;
1258 * Copy of the last set of CURBEs uploaded. Frequently we'll end up
1259 * in brw_curbe.c with the same set of constant data to be uploaded,
1260 * so we'd rather not upload new constants in that case (it can cause
1261 * a pipeline bubble since only up to 4 can be pipelined at a time).
1265 * Allocation for where to calculate the next set of CURBEs.
1266 * It's a hot enough path that malloc/free of that data matters.
1273 * Layout of vertex data exiting the vertex shader.
1275 * BRW_NEW_VUE_MAP_VS is flagged when this VUE map changes.
1277 struct brw_vue_map vue_map_vs
;
1280 * Layout of vertex data exiting the geometry portion of the pipleine.
1281 * This comes from the geometry shader if one exists, otherwise from the
1284 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1286 struct brw_vue_map vue_map_geom_out
;
1289 * Data structures used by all vec4 program compiles (not specific to any
1290 * particular program).
1293 struct ra_regs
*regs
;
1296 * Array of the ra classes for the unaligned contiguous register
1302 * Mapping for register-allocated objects in *regs to the first
1303 * GRF for that object.
1305 uint8_t *ra_reg_to_grf
;
1309 struct brw_stage_state base
;
1310 struct brw_vs_prog_data
*prog_data
;
1314 struct brw_stage_state base
;
1315 struct brw_gs_prog_data
*prog_data
;
1318 * True if the 3DSTATE_GS command most recently emitted to the 3D
1319 * pipeline enabled the GS; false otherwise.
1325 struct brw_ff_gs_prog_data
*prog_data
;
1328 /** Offset in the program cache to the CLIP program pre-gen6 */
1329 uint32_t prog_offset
;
1330 uint32_t state_offset
;
1332 uint32_t bind_bo_offset
;
1333 uint32_t surf_offset
[BRW_MAX_GEN6_GS_SURFACES
];
1337 struct brw_clip_prog_data
*prog_data
;
1339 /** Offset in the program cache to the CLIP program pre-gen6 */
1340 uint32_t prog_offset
;
1342 /* Offset in the batch to the CLIP state on pre-gen6. */
1343 uint32_t state_offset
;
1345 /* As of gen6, this is the offset in the batch to the CLIP VP,
1353 struct brw_sf_prog_data
*prog_data
;
1355 /** Offset in the program cache to the CLIP program pre-gen6 */
1356 uint32_t prog_offset
;
1357 uint32_t state_offset
;
1362 struct brw_stage_state base
;
1363 struct brw_wm_prog_data
*prog_data
;
1368 * Buffer object used in place of multisampled null render targets on
1369 * Gen6. See brw_update_null_renderbuffer_surface().
1371 drm_intel_bo
*multisampled_null_render_target_bo
;
1374 struct ra_regs
*regs
;
1377 * Array of the ra classes for the unaligned contiguous register
1378 * block sizes used, indexed by register size.
1383 * Mapping for register-allocated objects in *regs to the first
1384 * GRF for that object.
1386 uint8_t *ra_reg_to_grf
;
1389 * ra class for the aligned pairs we use for PLN, which doesn't
1390 * appear in *classes.
1392 int aligned_pairs_class
;
1398 uint32_t state_offset
;
1399 uint32_t blend_state_offset
;
1400 uint32_t depth_stencil_state_offset
;
1405 struct brw_query_object
*obj
;
1410 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1411 const int *statistics_registers
;
1413 /** The number of active monitors using OA counters. */
1417 * A buffer object storing OA counter snapshots taken at the start and
1418 * end of each batch (creating "bookends" around the batch).
1420 drm_intel_bo
*bookend_bo
;
1422 /** The number of snapshots written to bookend_bo. */
1423 int bookend_snapshots
;
1426 * An array of monitors whose results haven't yet been assembled based on
1427 * the data in buffer objects.
1429 * These may be active, or have already ended. However, the results
1430 * have not been requested.
1432 struct brw_perf_monitor_object
**unresolved
;
1433 int unresolved_elements
;
1434 int unresolved_array_size
;
1437 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1438 * the counter which MI_REPORT_PERF_COUNT stores there.
1440 const int *oa_snapshot_layout
;
1442 /** Number of 32-bit entries in a hardware counter snapshot. */
1443 int entries_per_oa_snapshot
;
1447 const struct brw_tracked_state
**atoms
;
1449 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1453 enum state_struct_type type
;
1454 } *state_batch_list
;
1455 int state_batch_count
;
1457 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1458 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1460 /* Interpolation modes, one byte per vue slot.
1461 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1463 struct interpolation_mode_map interpolation_mode
;
1465 /* PrimitiveRestart */
1468 bool enable_cut_index
;
1471 /** Computed depth/stencil/hiz state from the current attached
1472 * renderbuffers, valid only during the drawing state upload loop after
1473 * brw_workaround_depthstencil_alignment().
1476 struct intel_mipmap_tree
*depth_mt
;
1477 struct intel_mipmap_tree
*stencil_mt
;
1479 /* Inter-tile (page-aligned) byte offsets. */
1480 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1481 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1482 uint32_t tile_x
, tile_y
;
1485 uint32_t num_instances
;
1490 struct gl_shader_program
**shader_programs
;
1491 struct gl_program
**programs
;
1492 enum shader_time_shader_type
*types
;
1493 uint64_t *cumulative
;
1499 __DRIcontext
*driContext
;
1500 struct intel_screen
*intelScreen
;
1504 is_power_of_two(uint32_t value
)
1506 return (value
& (value
- 1)) == 0;
1509 /*======================================================================
1512 void brwInitVtbl( struct brw_context
*brw
);
1515 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1517 /*======================================================================
1520 extern const char *const brw_vendor_string
;
1522 extern const char *brw_get_renderer_string(unsigned deviceID
);
1524 extern void intelFinish(struct gl_context
* ctx
);
1527 DRI_CONF_BO_REUSE_DISABLED
,
1528 DRI_CONF_BO_REUSE_ALL
1531 void intel_update_renderbuffers(__DRIcontext
*context
,
1532 __DRIdrawable
*drawable
);
1533 void intel_prepare_render(struct brw_context
*brw
);
1535 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1536 __DRIdrawable
*drawable
);
1538 GLboolean
brwCreateContext(gl_api api
,
1539 const struct gl_config
*mesaVis
,
1540 __DRIcontext
*driContextPriv
,
1541 unsigned major_version
,
1542 unsigned minor_version
,
1546 void *sharedContextPrivate
);
1548 /*======================================================================
1551 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1552 uint32_t depth_level
,
1553 uint32_t depth_layer
,
1554 struct intel_mipmap_tree
*stencil_mt
,
1555 uint32_t *out_tile_mask_x
,
1556 uint32_t *out_tile_mask_y
);
1557 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1558 GLbitfield clear_mask
);
1560 /* brw_object_purgeable.c */
1561 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1563 /*======================================================================
1566 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1567 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1568 void brw_emit_query_begin(struct brw_context
*brw
);
1569 void brw_emit_query_end(struct brw_context
*brw
);
1571 /** gen6_queryobj.c */
1572 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1573 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1574 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1575 void brw_store_register_mem64(struct brw_context
*brw
,
1576 drm_intel_bo
*bo
, uint32_t reg
, int idx
);
1578 /*======================================================================
1581 void brw_debug_batch(struct brw_context
*brw
);
1582 void brw_annotate_aub(struct brw_context
*brw
);
1584 /*======================================================================
1587 void brw_validate_textures( struct brw_context
*brw
);
1590 /*======================================================================
1593 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1595 int brw_get_scratch_size(int size
);
1596 void brw_get_scratch_bo(struct brw_context
*brw
,
1597 drm_intel_bo
**scratch_bo
, int size
);
1598 void brw_init_shader_time(struct brw_context
*brw
);
1599 int brw_get_shader_time_index(struct brw_context
*brw
,
1600 struct gl_shader_program
*shader_prog
,
1601 struct gl_program
*prog
,
1602 enum shader_time_shader_type type
);
1603 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1604 void brw_destroy_shader_time(struct brw_context
*brw
);
1608 void brw_upload_urb_fence(struct brw_context
*brw
);
1612 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1614 /* brw_fs_reg_allocate.cpp
1616 void brw_fs_alloc_reg_sets(struct brw_context
*brw
);
1618 /* brw_vec4_reg_allocate.cpp */
1619 void brw_vec4_alloc_reg_set(struct brw_context
*brw
);
1622 int brw_disasm (FILE *file
, struct brw_instruction
*inst
, int gen
);
1625 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1627 /* brw_draw_upload.c */
1628 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1629 const struct gl_client_array
*glarray
);
1630 unsigned brw_get_index_type(GLenum type
);
1631 void brw_prepare_vertices(struct brw_context
*brw
);
1633 /* brw_wm_surface_state.c */
1634 void brw_init_surface_formats(struct brw_context
*brw
);
1635 void brw_create_constant_surface(struct brw_context
*brw
,
1639 uint32_t *out_offset
,
1641 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1643 uint32_t *surf_offset
);
1645 brw_update_sol_surface(struct brw_context
*brw
,
1646 struct gl_buffer_object
*buffer_obj
,
1647 uint32_t *out_offset
, unsigned num_vector_components
,
1648 unsigned stride_dwords
, unsigned offset_dwords
);
1649 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1650 struct gl_shader
*shader
,
1651 struct brw_stage_state
*stage_state
,
1652 struct brw_stage_prog_data
*prog_data
);
1653 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1654 struct gl_shader_program
*prog
,
1655 struct brw_stage_state
*stage_state
,
1656 struct brw_stage_prog_data
*prog_data
);
1658 /* brw_surface_formats.c */
1659 bool brw_is_hiz_depth_format(struct brw_context
*ctx
, mesa_format format
);
1660 bool brw_render_target_supported(struct brw_context
*brw
,
1661 struct gl_renderbuffer
*rb
);
1663 /* brw_performance_monitor.c */
1664 void brw_init_performance_monitors(struct brw_context
*brw
);
1665 void brw_dump_perf_monitors(struct brw_context
*brw
);
1666 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1667 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1669 /* intel_buffer_objects.c */
1670 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1671 const char *bo_name
);
1672 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1673 const char *bo_name
);
1675 /* intel_extensions.c */
1676 extern void intelInitExtensions(struct gl_context
*ctx
);
1679 extern int intel_translate_shadow_compare_func(GLenum func
);
1680 extern int intel_translate_compare_func(GLenum func
);
1681 extern int intel_translate_stencil_op(GLenum op
);
1682 extern int intel_translate_logic_op(GLenum opcode
);
1684 /* intel_syncobj.c */
1685 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1688 struct gl_transform_feedback_object
*
1689 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1691 brw_delete_transform_feedback(struct gl_context
*ctx
,
1692 struct gl_transform_feedback_object
*obj
);
1694 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1695 struct gl_transform_feedback_object
*obj
);
1697 brw_end_transform_feedback(struct gl_context
*ctx
,
1698 struct gl_transform_feedback_object
*obj
);
1700 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1701 struct gl_transform_feedback_object
*obj
,
1704 /* gen7_sol_state.c */
1706 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1707 struct gl_transform_feedback_object
*obj
);
1709 gen7_end_transform_feedback(struct gl_context
*ctx
,
1710 struct gl_transform_feedback_object
*obj
);
1712 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1713 struct gl_transform_feedback_object
*obj
);
1715 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1716 struct gl_transform_feedback_object
*obj
);
1718 /* brw_blorp_blit.cpp */
1720 brw_blorp_framebuffer(struct brw_context
*brw
,
1721 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1722 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1723 GLbitfield mask
, GLenum filter
);
1726 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1727 struct gl_renderbuffer
*src_rb
,
1728 struct gl_texture_image
*dst_image
,
1730 int srcX0
, int srcY0
,
1731 int dstX0
, int dstY0
,
1732 int width
, int height
);
1734 /* gen6_multisample_state.c */
1736 gen6_determine_sample_mask(struct brw_context
*brw
);
1739 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1740 unsigned num_samples
);
1742 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1744 gen6_get_sample_position(struct gl_context
*ctx
,
1745 struct gl_framebuffer
*fb
,
1749 /* gen8_multisample_state.c */
1750 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1751 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1755 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1756 unsigned gs_size
, unsigned fs_size
);
1759 gen7_emit_urb_state(struct brw_context
*brw
,
1760 unsigned nr_vs_entries
, unsigned vs_size
,
1761 unsigned vs_start
, unsigned nr_gs_entries
,
1762 unsigned gs_size
, unsigned gs_start
);
1767 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1769 /*======================================================================
1770 * Inline conversion functions. These are better-typed than the
1771 * macros used previously:
1773 static inline struct brw_context
*
1774 brw_context( struct gl_context
*ctx
)
1776 return (struct brw_context
*)ctx
;
1779 static inline struct brw_vertex_program
*
1780 brw_vertex_program(struct gl_vertex_program
*p
)
1782 return (struct brw_vertex_program
*) p
;
1785 static inline const struct brw_vertex_program
*
1786 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1788 return (const struct brw_vertex_program
*) p
;
1791 static inline struct brw_geometry_program
*
1792 brw_geometry_program(struct gl_geometry_program
*p
)
1794 return (struct brw_geometry_program
*) p
;
1797 static inline struct brw_fragment_program
*
1798 brw_fragment_program(struct gl_fragment_program
*p
)
1800 return (struct brw_fragment_program
*) p
;
1803 static inline const struct brw_fragment_program
*
1804 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1806 return (const struct brw_fragment_program
*) p
;
1810 * Pre-gen6, the register file of the EUs was shared between threads,
1811 * and each thread used some subset allocated on a 16-register block
1812 * granularity. The unit states wanted these block counts.
1815 brw_register_blocks(int reg_count
)
1817 return ALIGN(reg_count
, 16) / 16 - 1;
1820 static inline uint32_t
1821 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1822 uint32_t prog_offset
)
1824 if (brw
->gen
>= 5) {
1825 /* Using state base address. */
1829 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1833 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1835 return brw
->cache
.bo
->offset64
+ prog_offset
;
1838 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1839 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1840 struct exec_list
*instructions
);
1841 bool brw_do_lower_offset_arrays(struct exec_list
*instructions
);
1842 bool brw_do_lower_unnormalized_offset(struct exec_list
*instructions
);
1844 struct opcode_desc
{
1850 extern const struct opcode_desc opcode_descs
[128];
1851 extern const char * const conditional_modifier
[16];
1852 extern const char * const reg_encoding
[8];
1855 brw_emit_depthbuffer(struct brw_context
*brw
);
1858 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1859 struct intel_mipmap_tree
*depth_mt
,
1860 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1861 uint32_t depth_surface_type
,
1862 struct intel_mipmap_tree
*stencil_mt
,
1863 bool hiz
, bool separate_stencil
,
1864 uint32_t width
, uint32_t height
,
1865 uint32_t tile_x
, uint32_t tile_y
);
1868 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1869 struct intel_mipmap_tree
*depth_mt
,
1870 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1871 uint32_t depth_surface_type
,
1872 struct intel_mipmap_tree
*stencil_mt
,
1873 bool hiz
, bool separate_stencil
,
1874 uint32_t width
, uint32_t height
,
1875 uint32_t tile_x
, uint32_t tile_y
);
1877 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1878 struct intel_mipmap_tree
*depth_mt
,
1879 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1880 uint32_t depth_surface_type
,
1881 struct intel_mipmap_tree
*stencil_mt
,
1882 bool hiz
, bool separate_stencil
,
1883 uint32_t width
, uint32_t height
,
1884 uint32_t tile_x
, uint32_t tile_y
);
1886 extern const GLuint prim_to_hw_prim
[GL_TRIANGLE_STRIP_ADJACENCY
+1];
1889 brw_setup_vec4_key_clip_info(struct brw_context
*brw
,
1890 struct brw_vec4_prog_key
*key
,
1891 bool program_uses_clip_distance
);
1894 gen6_upload_vec4_push_constants(struct brw_context
*brw
,
1895 const struct gl_program
*prog
,
1896 const struct brw_vec4_prog_data
*prog_data
,
1897 struct brw_stage_state
*stage_state
,
1898 enum state_struct_type type
);
1900 /* ================================================================
1901 * From linux kernel i386 header files, copes with odd sizes better
1902 * than COPY_DWORDS would:
1903 * XXX Put this in src/mesa/main/imports.h ???
1905 #if defined(i386) || defined(__i386__)
1906 static inline void * __memcpy(void * to
, const void * from
, size_t n
)
1909 __asm__
__volatile__(
1914 "1:\ttestb $1,%b4\n\t"
1918 : "=&c" (d0
), "=&D" (d1
), "=&S" (d2
)
1919 :"0" (n
/4), "q" (n
),"1" ((long) to
),"2" ((long) from
)
1924 #define __memcpy(a,b,c) memcpy(a,b,c)