2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
36 #include "intel_context.h"
37 #include "brw_structs.h"
38 #include "main/imports.h"
43 * URB - uniform resource buffer. A mid-sized buffer which is
44 * partitioned between the fixed function units and used for passing
45 * values (vertices, primitives, constants) between them.
47 * CURBE - constant URB entry. An urb region (entry) used to hold
48 * constant values which the fixed function units can be instructed to
49 * preload into the GRF when spawning a thread.
51 * VUE - vertex URB entry. An urb entry holding a vertex and usually
52 * a vertex header. The header contains control information and
53 * things like primitive type, Begin/end flags and clip codes.
55 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
56 * unit holding rasterization and interpolation parameters.
58 * GRF - general register file. One of several register files
59 * addressable by programmed threads. The inputs (r0, payload, curbe,
60 * urb) of the thread are preloaded to this area before the thread is
61 * spawned. The registers are individually 8 dwords wide and suitable
62 * for general usage. Registers holding thread input values are not
63 * special and may be overwritten.
65 * MRF - message register file. Threads communicate (and terminate)
66 * by sending messages. Message parameters are placed in contiguous
67 * MRF registers. All program output is via these messages. URB
68 * entries are populated by sending a message to the shared URB
69 * function containing the new data, together with a control word,
70 * often an unmodified copy of R0.
72 * R0 - GRF register 0. Typically holds control information used when
73 * sending messages to other threads.
75 * EU or GEN4 EU: The name of the programmable subsystem of the
76 * i965 hardware. Threads are executed by the EU, the registers
77 * described above are part of the EU architecture.
79 * Fixed function units:
81 * CS - Command streamer. Notional first unit, little software
82 * interaction. Holds the URB entries used for constant data, ie the
85 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
86 * this unit is responsible for pulling vertices out of vertex buffers
87 * in vram and injecting them into the processing pipe as VUEs. If
88 * enabled, it first passes them to a VS thread which is a good place
89 * for the driver to implement any active vertex shader.
91 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
92 * enabled, incoming strips etc are passed to GS threads in individual
93 * line/triangle/point units. The GS thread may perform arbitary
94 * computation and emit whatever primtives with whatever vertices it
95 * chooses. This makes GS an excellent place to implement GL's
96 * unfilled polygon modes, though of course it is capable of much
97 * more. Additionally, GS is used to translate away primitives not
98 * handled by latter units, including Quads and Lineloops.
100 * CS - Clipper. Mesa's clipping algorithms are imported to run on
101 * this unit. The fixed function part performs cliptesting against
102 * the 6 fixed clipplanes and makes descisions on whether or not the
103 * incoming primitive needs to be passed to a thread for clipping.
104 * User clip planes are handled via cooperation with the VS thread.
106 * SF - Strips Fans or Setup: Triangles are prepared for
107 * rasterization. Interpolation coefficients are calculated.
108 * Flatshading and two-side lighting usually performed here.
110 * WM - Windower. Interpolation of vertex attributes performed here.
111 * Fragment shader implemented here. SIMD aspects of EU taken full
112 * advantage of, as pixels are processed in blocks of 16.
114 * CC - Color Calculator. No EU threads associated with this unit.
115 * Handles blending and (presumably) depth and stencil testing.
119 #define BRW_MAX_CURBE (32*16)
122 struct brw_instruction
;
123 struct brw_vs_prog_key
;
124 struct brw_wm_prog_key
;
125 struct brw_wm_prog_data
;
129 BRW_STATE_FRAGMENT_PROGRAM
,
130 BRW_STATE_VERTEX_PROGRAM
,
131 BRW_STATE_INPUT_DIMENSIONS
,
132 BRW_STATE_CURBE_OFFSETS
,
133 BRW_STATE_REDUCED_PRIMITIVE
,
136 BRW_STATE_WM_INPUT_DIMENSIONS
,
139 BRW_STATE_VS_BINDING_TABLE
,
140 BRW_STATE_GS_BINDING_TABLE
,
141 BRW_STATE_PS_BINDING_TABLE
,
145 BRW_STATE_NR_WM_SURFACES
,
146 BRW_STATE_NR_VS_SURFACES
,
147 BRW_STATE_INDEX_BUFFER
,
148 BRW_STATE_VS_CONSTBUF
,
149 BRW_STATE_PROGRAM_CACHE
,
150 BRW_STATE_STATE_BASE_ADDRESS
,
151 BRW_STATE_SOL_INDICES
,
154 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
155 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
156 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
157 #define BRW_NEW_INPUT_DIMENSIONS (1 << BRW_STATE_INPUT_DIMENSIONS)
158 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
159 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
160 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
161 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
162 #define BRW_NEW_WM_INPUT_DIMENSIONS (1 << BRW_STATE_WM_INPUT_DIMENSIONS)
163 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
164 #define BRW_NEW_SURFACES (1 << BRW_STATE_SURFACES)
165 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
166 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
167 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
168 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
169 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
171 * Used for any batch entry with a relocated pointer that will be used
172 * by any 3D rendering.
174 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
175 /** \see brw.state.depth_region */
176 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
177 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
178 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
179 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
180 #define BRW_NEW_SOL_INDICES (1 << BRW_STATE_SOL_INDICES)
182 struct brw_state_flags
{
183 /** State update flags signalled by mesa internals */
186 * State update flags signalled as the result of brw_tracked_state updates
189 /** State update flags signalled by brw_state_cache.c searches */
193 enum state_struct_type
{
194 AUB_TRACE_VS_STATE
= 1,
195 AUB_TRACE_GS_STATE
= 2,
196 AUB_TRACE_CLIP_STATE
= 3,
197 AUB_TRACE_SF_STATE
= 4,
198 AUB_TRACE_WM_STATE
= 5,
199 AUB_TRACE_CC_STATE
= 6,
200 AUB_TRACE_CLIP_VP_STATE
= 7,
201 AUB_TRACE_SF_VP_STATE
= 8,
202 AUB_TRACE_CC_VP_STATE
= 0x9,
203 AUB_TRACE_SAMPLER_STATE
= 0xa,
204 AUB_TRACE_KERNEL_INSTRUCTIONS
= 0xb,
205 AUB_TRACE_SCRATCH_SPACE
= 0xc,
206 AUB_TRACE_SAMPLER_DEFAULT_COLOR
= 0xd,
208 AUB_TRACE_SCISSOR_STATE
= 0x15,
209 AUB_TRACE_BLEND_STATE
= 0x16,
210 AUB_TRACE_DEPTH_STENCIL_STATE
= 0x17,
212 /* Not written to .aub files the same way the structures above are. */
213 AUB_TRACE_NO_TYPE
= 0x100,
214 AUB_TRACE_BINDING_TABLE
= 0x101,
215 AUB_TRACE_SURFACE_STATE
= 0x102,
216 AUB_TRACE_VS_CONSTANTS
= 0x103,
217 AUB_TRACE_WM_CONSTANTS
= 0x104,
220 /** Subclass of Mesa vertex program */
221 struct brw_vertex_program
{
222 struct gl_vertex_program program
;
224 bool use_const_buffer
;
228 /** Subclass of Mesa fragment program */
229 struct brw_fragment_program
{
230 struct gl_fragment_program program
;
231 GLuint id
; /**< serial no. to identify frag progs, never re-used */
235 struct gl_shader base
;
237 /** Shader IR transformed for native compile, at link time. */
238 struct exec_list
*ir
;
241 struct brw_shader_program
{
242 struct gl_shader_program base
;
245 enum param_conversion
{
253 /* Data about a particular attempt to compile a program. Note that
254 * there can be many of these, each in a different GL state
255 * corresponding to a different brw_wm_prog_key struct, with different
258 struct brw_wm_prog_data
{
259 GLuint curb_read_length
;
260 GLuint urb_read_length
;
262 GLuint first_curbe_grf
;
263 GLuint first_curbe_grf_16
;
265 GLuint reg_blocks_16
;
266 GLuint total_scratch
;
268 GLuint nr_params
; /**< number of float params/constants */
269 GLuint nr_pull_params
;
272 uint32_t prog_offset_16
;
275 * Mask of which interpolation modes are required by the fragment shader.
276 * Used in hardware setup on gen6+.
278 uint32_t barycentric_interp_modes
;
280 /* Pointer to tracked values (only valid once
281 * _mesa_load_state_parameters has been called at runtime).
283 const float *param
[MAX_UNIFORMS
* 4]; /* should be: BRW_MAX_CURBE */
284 enum param_conversion param_convert
[MAX_UNIFORMS
* 4];
285 const float *pull_param
[MAX_UNIFORMS
* 4];
286 enum param_conversion pull_param_convert
[MAX_UNIFORMS
* 4];
290 * Enum representing the i965-specific vertex results that don't correspond
291 * exactly to any element of gl_vert_result. The values of this enum are
292 * assigned such that they don't conflict with gl_vert_result.
296 BRW_VERT_RESULT_NDC
= VERT_RESULT_MAX
,
297 BRW_VERT_RESULT_HPOS_DUPLICATE
,
300 * It's actually not a vert_result but just a _mark_ to let sf aware that
301 * he need do something special to handle gl_PointCoord builtin variable
302 * correctly. see compile_sf_prog() for more info.
304 BRW_VERT_RESULT_PNTC
,
310 * Data structure recording the relationship between the gl_vert_result enum
311 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
312 * single octaword within the VUE (128 bits).
314 * Note that each BRW register contains 256 bits (2 octawords), so when
315 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
316 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
317 * in a vertex shader), each register corresponds to a single VUE slot, since
318 * it contains data for two separate vertices.
322 * Map from gl_vert_result value to VUE slot. For gl_vert_results that are
323 * not stored in a slot (because they are not written, or because
324 * additional processing is applied before storing them in the VUE), the
327 int vert_result_to_slot
[BRW_VERT_RESULT_MAX
];
330 * Map from VUE slot to gl_vert_result value. For slots that do not
331 * directly correspond to a gl_vert_result, the value comes from
334 * For slots that are not in use, the value is BRW_VERT_RESULT_MAX (this
335 * simplifies code that uses the value stored in slot_to_vert_result to
336 * create a bit mask).
338 int slot_to_vert_result
[BRW_VERT_RESULT_MAX
];
341 * Total number of VUE slots in use
347 * Convert a VUE slot number into a byte offset within the VUE.
349 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
355 * Convert a vert_result into a byte offset within the VUE.
357 static inline GLuint
brw_vert_result_to_offset(struct brw_vue_map
*vue_map
,
360 return brw_vue_slot_to_offset(vue_map
->vert_result_to_slot
[vert_result
]);
364 struct brw_sf_prog_data
{
365 GLuint urb_read_length
;
368 /* Each vertex may have upto 12 attributes, 4 components each,
369 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
372 * Actually we use 4 for each, so call it 12 rows.
374 GLuint urb_entry_size
;
377 struct brw_clip_prog_data
{
378 GLuint curb_read_length
; /* user planes? */
380 GLuint urb_read_length
;
384 struct brw_gs_prog_data
{
385 GLuint urb_read_length
;
389 * Gen6 transform feedback: Amount by which the streaming vertex buffer
390 * indices should be incremented each time the GS is invoked.
392 unsigned svbi_postincrement_value
;
395 struct brw_vs_prog_data
{
396 struct brw_vue_map vue_map
;
398 GLuint curb_read_length
;
399 GLuint urb_read_length
;
401 GLbitfield64 outputs_written
;
402 GLuint nr_params
; /**< number of float params/constants */
403 GLuint nr_pull_params
; /**< number of dwords referenced by pull_param[] */
404 GLuint total_scratch
;
406 GLbitfield64 inputs_read
;
408 /* Used for calculating urb partitions:
410 GLuint urb_entry_size
;
412 const float *param
[MAX_UNIFORMS
* 4]; /* should be: BRW_MAX_CURBE */
413 const float *pull_param
[MAX_UNIFORMS
* 4];
415 bool uses_new_param_layout
;
423 /* Size == 0 if output either not written, or always [0,0,0,1]
425 struct brw_vs_ouput_sizes
{
426 GLubyte output_size
[VERT_RESULT_MAX
];
430 /** Number of texture sampler units */
431 #define BRW_MAX_TEX_UNIT 16
433 /** Max number of render targets in a shader */
434 #define BRW_MAX_DRAW_BUFFERS 8
437 * Max number of binding table entries used for stream output.
439 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
440 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
442 * On Gen6, the size of transform feedback data is limited not by the number
443 * of components but by the number of binding table entries we set aside. We
444 * use one binding table entry for a float, one entry for a vector, and one
445 * entry per matrix column. Since the only way we can communicate our
446 * transform feedback capabilities to the client is via
447 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
448 * worst case, in which all the varyings are floats, so we use up one binding
449 * table entry per component. Therefore we need to set aside at least 64
450 * binding table entries for use by transform feedback.
452 * Note: since we don't currently pack varyings, it is currently impossible
453 * for the client to actually use up all of these binding table entries--if
454 * all of their varyings were floats, they would run out of varying slots and
455 * fail to link. But that's a bug, so it seems prudent to go ahead and
456 * allocate the number of binding table entries we will need once the bug is
459 #define BRW_MAX_SOL_BINDINGS 64
461 /** Maximum number of actual buffers used for stream output */
462 #define BRW_MAX_SOL_BUFFERS 4
465 * Helpers to create Surface Binding Table indexes for draw buffers,
466 * textures, and constant buffers.
468 * Shader threads access surfaces via numeric handles, rather than directly
469 * using pointers. The binding table maps these numeric handles to the
470 * address of the actual buffer.
472 * For example, a shader might ask to sample from "surface 7." In this case,
473 * bind[7] would contain a pointer to a texture.
475 * Although the hardware supports separate binding tables per pipeline stage
476 * (VS, HS, DS, GS, PS), we currently share a single binding table for all of
477 * them. This is purely for convenience.
479 * Currently our SOL/WM binding tables are (arbitrarily) programmed as follows:
481 * +-------------------------------+
482 * | 0 | Draw buffer 0 | .
484 * | : | : | > Only relevant to the WM.
485 * | 7 | Draw buffer 7 | /
486 * |-----|-------------------------| `
487 * | 8 | WM Pull Constant Buffer |
488 * |-----|-------------------------|
492 * | 24 | Texture 15 |
493 * +-------------------------------+
495 * Our VS binding tables are programmed as follows:
497 * +-----+-------------------------+ `
498 * | 0 | VS Pull Constant Buffer |
499 * +-----+-------------------------+
503 * | 16 | Texture 15 |
504 * +-------------------------------+
506 * Our (gen6) GS binding tables are programmed as follows:
508 * +-----+-------------------------+
509 * | 0 | SOL Binding 0 |
512 * | 63 | SOL Binding 63 |
513 * +-----+-------------------------+
515 * Note that nothing actually uses the SURF_INDEX_DRAW macro, so it has to be
516 * the identity function or things will break. We do want to keep draw buffers
517 * first so we can use headerless render target writes for RT 0.
519 #define SURF_INDEX_DRAW(d) (d)
520 #define SURF_INDEX_FRAG_CONST_BUFFER (BRW_MAX_DRAW_BUFFERS + 1)
521 #define SURF_INDEX_TEXTURE(t) (BRW_MAX_DRAW_BUFFERS + 2 + (t))
523 /** Maximum size of the binding table. */
524 #define BRW_MAX_SURFACES SURF_INDEX_TEXTURE(BRW_MAX_TEX_UNIT)
526 #define SURF_INDEX_VERT_CONST_BUFFER (0)
527 #define SURF_INDEX_VS_TEXTURE(t) (SURF_INDEX_VERT_CONST_BUFFER + 1 + (t))
528 #define BRW_MAX_VS_SURFACES SURF_INDEX_VS_TEXTURE(BRW_MAX_TEX_UNIT)
530 #define SURF_INDEX_SOL_BINDING(t) ((t))
531 #define BRW_MAX_GS_SURFACES SURF_INDEX_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
535 BRW_DEPTH_STENCIL_STATE
,
536 BRW_COLOR_CALC_STATE
,
544 BRW_SF_UNIT
, /* scissor state on gen6 */
556 struct brw_cache_item
{
558 * Effectively part of the key, cache_id identifies what kind of state
559 * buffer is involved, and also which brw->state.dirty.cache flag should
560 * be set when this cache item is chosen.
562 enum brw_cache_id cache_id
;
563 /** 32-bit hash of the key data */
565 GLuint key_size
; /* for variable-sized keys */
572 struct brw_cache_item
*next
;
578 struct brw_context
*brw
;
580 struct brw_cache_item
**items
;
582 GLuint size
, n_items
;
584 uint32_t next_offset
;
589 /* Considered adding a member to this struct to document which flags
590 * an update might raise so that ordering of the state atoms can be
591 * checked or derived at runtime. Dropped the idea in favor of having
592 * a debug mode where the state is monitored for flags which are
593 * raised that have already been tested against.
595 struct brw_tracked_state
{
596 struct brw_state_flags dirty
;
597 void (*emit
)( struct brw_context
*brw
);
600 /* Flags for brw->state.cache.
602 #define CACHE_NEW_BLEND_STATE (1<<BRW_BLEND_STATE)
603 #define CACHE_NEW_DEPTH_STENCIL_STATE (1<<BRW_DEPTH_STENCIL_STATE)
604 #define CACHE_NEW_COLOR_CALC_STATE (1<<BRW_COLOR_CALC_STATE)
605 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
606 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
607 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
608 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
609 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
610 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
611 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
612 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
613 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
614 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
615 #define CACHE_NEW_GS_UNIT (1<<BRW_GS_UNIT)
616 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
617 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
618 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
619 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
621 struct brw_cached_batch_item
{
622 struct header
*header
;
624 struct brw_cached_batch_item
*next
;
629 /* Protect against a future where VERT_ATTRIB_MAX > 32. Wouldn't life
630 * be easier if C allowed arrays of packed elements?
632 #define ATTRIB_BIT_DWORDS ((VERT_ATTRIB_MAX+31)/32)
634 struct brw_vertex_buffer
{
635 /** Buffer object containing the uploaded vertex data */
638 /** Byte stride between elements in the uploaded array */
641 struct brw_vertex_element
{
642 const struct gl_client_array
*glarray
;
646 /** The corresponding Mesa vertex attribute */
647 gl_vert_attrib attrib
;
648 /** Size of a complete element */
650 /** Offset of the first element within the buffer object */
656 struct brw_vertex_info
{
657 GLuint sizes
[ATTRIB_BIT_DWORDS
* 2]; /* sizes:2[VERT_ATTRIB_MAX] */
660 struct brw_query_object
{
661 struct gl_query_object Base
;
663 /** Last query BO associated with this query. */
665 /** First index in bo with query data for this object. */
667 /** Last index in bo with query data for this object. */
673 * brw_context is derived from intel_context.
677 struct intel_context intel
; /**< base class, must be first field */
678 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
680 bool emit_state_always
;
681 bool has_surface_tile_offset
;
683 bool has_negative_rhw_bug
;
684 bool has_aa_line_parameters
;
689 struct brw_state_flags dirty
;
692 struct brw_cache cache
;
693 struct brw_cached_batch_item
*cached_batch_items
;
696 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
697 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
702 } current_buffers
[VERT_ATTRIB_MAX
];
704 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
706 GLuint nr_buffers
, nr_current_buffers
;
708 /* Summary of size and varying of active arrays, so we can check
709 * for changes to this state:
711 struct brw_vertex_info info
;
712 unsigned int min_index
, max_index
;
714 /* Offset from start of vertex buffer so we can avoid redefining
715 * the same VB packed over and over again.
717 unsigned int start_vertex_bias
;
722 * Index buffer for this draw_prims call.
724 * Updates are signaled by BRW_NEW_INDICES.
726 const struct _mesa_index_buffer
*ib
;
728 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
732 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
733 * avoid re-uploading the IB packet over and over if we're actually
734 * referencing the same index buffer.
736 unsigned int start_vertex_offset
;
739 /* Active vertex program:
741 const struct gl_vertex_program
*vertex_program
;
742 const struct gl_fragment_program
*fragment_program
;
744 /* hw-dependent 3DSTATE_VF_STATISTICS opcode */
745 uint32_t CMD_VF_STATISTICS
;
746 /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
747 uint32_t CMD_PIPELINE_SELECT
;
750 * Platform specific constants containing the maximum number of threads
751 * for each pipeline stage.
757 /* BRW_NEW_URB_ALLOCATIONS:
760 GLuint vsize
; /* vertex size plus header in urb registers */
761 GLuint csize
; /* constant buffer size in urb registers */
762 GLuint sfsize
; /* setup data size in urb registers */
766 GLuint max_vs_entries
; /* Maximum number of VS entries */
767 GLuint max_gs_entries
; /* Maximum number of GS entries */
769 GLuint nr_vs_entries
;
770 GLuint nr_gs_entries
;
771 GLuint nr_clip_entries
;
772 GLuint nr_sf_entries
;
773 GLuint nr_cs_entries
;
776 * The length of each URB entry owned by the VS (or GS), as
777 * a number of 1024-bit (128-byte) rows. Should be >= 1.
779 * gen7: Same meaning, but in 512-bit (64-byte) rows.
789 GLuint size
; /* Hardware URB size, in KB. */
791 /* gen6: True if the most recently sent _3DSTATE_URB message allocated
792 * URB space for the GS.
794 bool gen6_gs_previously_active
;
798 /* BRW_NEW_CURBE_OFFSETS:
801 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
802 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
809 drm_intel_bo
*curbe_bo
;
810 /** Offset within curbe_bo of space for current curbe entry */
812 /** Offset within curbe_bo of space for next curbe entry */
813 GLuint curbe_next_offset
;
816 * Copy of the last set of CURBEs uploaded. Frequently we'll end up
817 * in brw_curbe.c with the same set of constant data to be uploaded,
818 * so we'd rather not upload new constants in that case (it can cause
819 * a pipeline bubble since only up to 4 can be pipelined at a time).
823 * Allocation for where to calculate the next set of CURBEs.
824 * It's a hot enough path that malloc/free of that data matters.
830 /** SAMPLER_STATE count and offset */
837 struct brw_vs_prog_data
*prog_data
;
838 int8_t *constant_map
; /* variable array following prog_data */
840 drm_intel_bo
*scratch_bo
;
841 drm_intel_bo
*const_bo
;
842 /** Offset in the program cache to the VS program */
843 uint32_t prog_offset
;
844 uint32_t state_offset
;
846 uint32_t push_const_offset
; /* Offset in the batchbuffer */
847 int push_const_size
; /* in 256-bit register increments */
849 /** @{ register allocator */
851 struct ra_regs
*regs
;
854 * Array of the ra classes for the unaligned contiguous register
860 * Mapping for register-allocated objects in *regs to the first
861 * GRF for that object.
863 uint8_t *ra_reg_to_grf
;
866 uint32_t bind_bo_offset
;
867 uint32_t surf_offset
[BRW_MAX_VS_SURFACES
];
871 struct brw_gs_prog_data
*prog_data
;
874 /** Offset in the program cache to the CLIP program pre-gen6 */
875 uint32_t prog_offset
;
876 uint32_t state_offset
;
878 uint32_t bind_bo_offset
;
879 uint32_t surf_offset
[BRW_MAX_GS_SURFACES
];
883 struct brw_clip_prog_data
*prog_data
;
885 /** Offset in the program cache to the CLIP program pre-gen6 */
886 uint32_t prog_offset
;
888 /* Offset in the batch to the CLIP state on pre-gen6. */
889 uint32_t state_offset
;
891 /* As of gen6, this is the offset in the batch to the CLIP VP,
899 struct brw_sf_prog_data
*prog_data
;
901 /** Offset in the program cache to the CLIP program pre-gen6 */
902 uint32_t prog_offset
;
903 uint32_t state_offset
;
908 struct brw_wm_prog_data
*prog_data
;
909 struct brw_wm_compile
*compile_data
;
911 /** Input sizes, calculated from active vertex program.
912 * One bit per fragment program input attribute.
914 GLbitfield input_size_masks
[4];
916 /** offsets in the batch to sampler default colors (texture border color)
918 uint32_t sdc_offset
[BRW_MAX_TEX_UNIT
];
922 drm_intel_bo
*scratch_bo
;
924 /** Offset in the program cache to the WM program */
925 uint32_t prog_offset
;
927 uint32_t state_offset
; /* offset in batchbuffer to pre-gen6 WM state */
929 drm_intel_bo
*const_bo
; /* pull constant buffer. */
931 * This is offset in the batch to the push constants on gen6.
933 * Pre-gen6, push constants live in the CURBE.
935 uint32_t push_const_offset
;
937 /** Binding table of pointers to surf_bo entries */
938 uint32_t bind_bo_offset
;
939 uint32_t surf_offset
[BRW_MAX_SURFACES
];
941 /** @{ register allocator */
943 struct ra_regs
*regs
;
945 /** Array of the ra classes for the unaligned contiguous
946 * register block sizes used.
951 * Mapping for register-allocated objects in *regs to the first
952 * GRF for that object.
954 uint8_t *ra_reg_to_grf
;
957 * ra class for the aligned pairs we use for PLN, which doesn't
958 * appear in *classes.
960 int aligned_pairs_class
;
967 uint32_t state_offset
;
968 uint32_t blend_state_offset
;
969 uint32_t depth_stencil_state_offset
;
974 struct brw_query_object
*obj
;
979 /* Used to give every program string a unique id
984 const struct brw_tracked_state
**atoms
;
986 /* If (INTEL_DEBUG & DEBUG_BATCH) */
990 enum state_struct_type type
;
992 int state_batch_count
;
994 struct brw_sol_state
{
995 uint32_t svbi_0_starting_index
;
996 uint32_t svbi_0_max_index
;
997 uint32_t offset_0_batch_start
;
998 uint32_t primitives_generated
;
999 uint32_t primitives_written
;
1002 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1003 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1008 #define BRW_PACKCOLOR8888(r,g,b,a) ((r<<24) | (g<<16) | (b<<8) | a)
1010 struct brw_instruction_info
{
1016 extern const struct brw_instruction_info brw_opcodes
[128];
1018 /*======================================================================
1021 void brwInitVtbl( struct brw_context
*brw
);
1023 /*======================================================================
1026 bool brwCreateContext(int api
,
1027 const struct gl_config
*mesaVis
,
1028 __DRIcontext
*driContextPriv
,
1029 void *sharedContextPrivate
);
1031 /*======================================================================
1034 void brw_init_queryobj_functions(struct dd_function_table
*functions
);
1035 void brw_prepare_query_begin(struct brw_context
*brw
);
1036 void brw_emit_query_begin(struct brw_context
*brw
);
1037 void brw_emit_query_end(struct brw_context
*brw
);
1039 /*======================================================================
1042 void brw_debug_batch(struct intel_context
*intel
);
1044 /*======================================================================
1047 void brw_validate_textures( struct brw_context
*brw
);
1050 /*======================================================================
1053 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1055 int brw_get_scratch_size(int size
);
1056 void brw_get_scratch_bo(struct intel_context
*intel
,
1057 drm_intel_bo
**scratch_bo
, int size
);
1062 void brw_upload_urb_fence(struct brw_context
*brw
);
1066 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1069 int brw_disasm (FILE *file
, struct brw_instruction
*inst
, int gen
);
1072 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1074 /* brw_wm_surface_state.c */
1075 void brw_init_surface_formats(struct brw_context
*brw
);
1077 brw_update_sol_surface(struct brw_context
*brw
,
1078 struct gl_buffer_object
*buffer_obj
,
1079 uint32_t *out_offset
, unsigned num_vector_components
,
1080 unsigned stride_dwords
, unsigned offset_dwords
);
1084 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1085 struct gl_transform_feedback_object
*obj
);
1087 brw_end_transform_feedback(struct gl_context
*ctx
,
1088 struct gl_transform_feedback_object
*obj
);
1090 /* gen7_sol_state.c */
1092 gen7_end_transform_feedback(struct gl_context
*ctx
,
1093 struct gl_transform_feedback_object
*obj
);
1097 /*======================================================================
1098 * Inline conversion functions. These are better-typed than the
1099 * macros used previously:
1101 static INLINE
struct brw_context
*
1102 brw_context( struct gl_context
*ctx
)
1104 return (struct brw_context
*)ctx
;
1107 static INLINE
struct brw_vertex_program
*
1108 brw_vertex_program(struct gl_vertex_program
*p
)
1110 return (struct brw_vertex_program
*) p
;
1113 static INLINE
const struct brw_vertex_program
*
1114 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1116 return (const struct brw_vertex_program
*) p
;
1119 static INLINE
struct brw_fragment_program
*
1120 brw_fragment_program(struct gl_fragment_program
*p
)
1122 return (struct brw_fragment_program
*) p
;
1125 static INLINE
const struct brw_fragment_program
*
1126 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1128 return (const struct brw_fragment_program
*) p
;
1132 float convert_param(enum param_conversion conversion
, const float *param
)
1140 switch (conversion
) {
1141 case PARAM_NO_CONVERT
:
1143 case PARAM_CONVERT_F2I
:
1146 case PARAM_CONVERT_F2U
:
1149 case PARAM_CONVERT_F2B
:
1155 case PARAM_CONVERT_ZERO
:
1163 * Pre-gen6, the register file of the EUs was shared between threads,
1164 * and each thread used some subset allocated on a 16-register block
1165 * granularity. The unit states wanted these block counts.
1168 brw_register_blocks(int reg_count
)
1170 return ALIGN(reg_count
, 16) / 16 - 1;
1173 static inline uint32_t
1174 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1175 uint32_t prog_offset
)
1177 struct intel_context
*intel
= &brw
->intel
;
1179 if (intel
->gen
>= 5) {
1180 /* Using state base address. */
1184 drm_intel_bo_emit_reloc(intel
->batch
.bo
,
1188 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1190 return brw
->cache
.bo
->offset
+ prog_offset
;
1193 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);